arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 ethernet0 = &fec;
  21                 can0 = &can1;
  22                 can1 = &can2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 ipu0 = &ipu1;
  34                 mmc0 = &usdhc1;
  35                 mmc1 = &usdhc2;
  36                 mmc2 = &usdhc3;
  37                 mmc3 = &usdhc4;
  38                 serial0 = &uart1;
  39                 serial1 = &uart2;
  40                 serial2 = &uart3;
  41                 serial3 = &uart4;
  42                 serial4 = &uart5;
  43                 spi0 = &ecspi1;
  44                 spi1 = &ecspi2;
  45                 spi2 = &ecspi3;
  46                 spi3 = &ecspi4;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         clocks {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 ckil {
  56                         compatible = "fsl,imx-ckil", "fixed-clock";
  57                         #clock-cells = <0>;
  58                         clock-frequency = <32768>;
  59                 };
  60
  61                 ckih1 {
  62                         compatible = "fsl,imx-ckih1", "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <0>;
  65                 };
  66
  67                 osc {
  68                         compatible = "fsl,imx-osc", "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <24000000>;
  71                 };
  72         };
  73
  74         soc {
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 compatible = "simple-bus";
  78                 interrupt-parent = <&gpc>;
  79                 ranges;
  80
  81                 dma_apbh: dma-apbh@00110000 {
  82                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  83                         reg = <0x00110000 0x2000>;
  84                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  88                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  89                         #dma-cells = <1>;
  90                         dma-channels = <4>;
  91                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
  92                 };
  93
  94                 gpmi: gpmi-nand@00112000 {
  95                         compatible = "fsl,imx6q-gpmi-nand";
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  99                         reg-names = "gpmi-nand", "bch";
 100                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 101                         interrupt-names = "bch";
 102                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 103                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 104                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 105                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 106                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 107                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 108                                       "gpmi_bch_apb", "per1_bch";
 109                         dmas = <&dma_apbh 0>;
 110                         dma-names = "rx-tx";
 111                         status = "disabled";
 112                 };
 113
 114                 hdmi: hdmi@0120000 {
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                         reg = <0x00120000 0x9000>;
 118                         interrupts = <0 115 0x04>;
 119                         gpr = <&gpr>;
 120                         clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 121                                  <&clks IMX6QDL_CLK_HDMI_ISFR>;
 122                         clock-names = "iahb", "isfr";
 123                         status = "disabled";
 124
 125                         port@0 {
 126                                 reg = <0>;
 127
 128                                 hdmi_mux_0: endpoint {
 129                                         remote-endpoint = <&ipu1_di0_hdmi>;
 130                                 };
 131                         };
 132
 133                         port@1 {
 134                                 reg = <1>;
 135
 136                                 hdmi_mux_1: endpoint {
 137                                         remote-endpoint = <&ipu1_di1_hdmi>;
 138                                 };
 139                         };
 140                 };
 141
 142                 gpu_3d: gpu@00130000 {
 143                         compatible = "vivante,gc";
 144                         reg = <0x00130000 0x4000>;
 145                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 146                         clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
 147                                  <&clks IMX6QDL_CLK_GPU3D_CORE>,
 148                                  <&clks IMX6QDL_CLK_GPU3D_SHADER>;
 149                         clock-names = "bus", "core", "shader";
 150                         power-domains = <&gpc 1>;
 151                 };
 152
 153                 gpu_2d: gpu@00134000 {
 154                         compatible = "vivante,gc";
 155                         reg = <0x00134000 0x4000>;
 156                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 157                         clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
 158                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 159                         clock-names = "bus", "core";
 160                         power-domains = <&gpc 1>;
 161                 };
 162
 163                 timer@00a00600 {
 164                         compatible = "arm,cortex-a9-twd-timer";
 165                         reg = <0x00a00600 0x20>;
 166                         interrupts = <1 13 0xf01>;
 167                         interrupt-parent = <&intc>;
 168                         clocks = <&clks IMX6QDL_CLK_TWD>;
 169                 };
 170
 171                 intc: interrupt-controller@00a01000 {
 172                         compatible = "arm,cortex-a9-gic";
 173                         #interrupt-cells = <3>;
 174                         interrupt-controller;
 175                         reg = <0x00a01000 0x1000>,
 176                               <0x00a00100 0x100>;
 177                         interrupt-parent = <&intc>;
 178                 };
 179
 180                 L2: l2-cache@00a02000 {
 181                         compatible = "arm,pl310-cache";
 182                         reg = <0x00a02000 0x1000>;
 183                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 184                         cache-unified;
 185                         cache-level = <2>;
 186                         arm,tag-latency = <4 2 3>;
 187                         arm,data-latency = <4 2 3>;
 188                         arm,shared-override;
 189                 };
 190
 191                 pcie: pcie@0x01000000 {
 192                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 193                         reg = <0x01ffc000 0x04000>,
 194                               <0x01f00000 0x80000>;
 195                         reg-names = "dbi", "config";
 196                         #address-cells = <3>;
 197                         #size-cells = <2>;
 198                         device_type = "pci";
 199                         ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 200                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 201                         num-lanes = <1>;
 202                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 203                         interrupt-names = "msi";
 204                         #interrupt-cells = <1>;
 205                         interrupt-map-mask = <0 0 0 0x7>;
 206                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 207                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 208                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 209                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 211                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 212                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 213                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 214                         status = "disabled";
 215                 };
 216
 217                 pmu {
 218                         compatible = "arm,cortex-a9-pmu";
 219                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 220                 };
 221
 222                 aips-bus@02000000 { /* AIPS1 */
 223                         compatible = "fsl,aips-bus", "simple-bus";
 224                         #address-cells = <1>;
 225                         #size-cells = <1>;
 226                         reg = <0x02000000 0x100000>;
 227                         ranges;
 228
 229                         spba-bus@02000000 {
 230                                 compatible = "fsl,spba-bus", "simple-bus";
 231                                 #address-cells = <1>;
 232                                 #size-cells = <1>;
 233                                 reg = <0x02000000 0x40000>;
 234                                 ranges;
 235
 236                                 spdif: spdif@02004000 {
 237                                         compatible = "fsl,imx35-spdif";
 238                                         reg = <0x02004000 0x4000>;
 239                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 240                                         dmas = <&sdma 14 18 0>,
 241                                                <&sdma 15 18 0>;
 242                                         dma-names = "rx", "tx";
 243                                         clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 244                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 245                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 246                                                  <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
 247                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 248                                         clock-names = "core",  "rxtx0",
 249                                                       "rxtx1", "rxtx2",
 250                                                       "rxtx3", "rxtx4",
 251                                                       "rxtx5", "rxtx6",
 252                                                       "rxtx7", "spba";
 253                                         status = "disabled";
 254                                 };
 255
 256                                 ecspi1: ecspi@02008000 {
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 260                                         reg = <0x02008000 0x4000>;
 261                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 262                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 263                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 264                                         clock-names = "ipg", "per";
 265                                         dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
 266                                         dma-names = "rx", "tx";
 267                                         status = "disabled";
 268                                 };
 269
 270                                 ecspi2: ecspi@0200c000 {
 271                                         #address-cells = <1>;
 272                                         #size-cells = <0>;
 273                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 274                                         reg = <0x0200c000 0x4000>;
 275                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 276                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 277                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 278                                         clock-names = "ipg", "per";
 279                                         dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
 280                                         dma-names = "rx", "tx";
 281                                         status = "disabled";
 282                                 };
 283
 284                                 ecspi3: ecspi@02010000 {
 285                                         #address-cells = <1>;
 286                                         #size-cells = <0>;
 287                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 288                                         reg = <0x02010000 0x4000>;
 289                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 290                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 291                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 292                                         clock-names = "ipg", "per";
 293                                         dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
 294                                         dma-names = "rx", "tx";
 295                                         status = "disabled";
 296                                 };
 297
 298                                 ecspi4: ecspi@02014000 {
 299                                         #address-cells = <1>;
 300                                         #size-cells = <0>;
 301                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 302                                         reg = <0x02014000 0x4000>;
 303                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 304                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 305                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 306                                         clock-names = "ipg", "per";
 307                                         dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
 308                                         dma-names = "rx", "tx";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 uart1: serial@02020000 {
 313                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 314                                         reg = <0x02020000 0x4000>;
 315                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 316                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 317                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 318                                         clock-names = "ipg", "per";
 319                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 320                                         dma-names = "rx", "tx";
 321                                         status = "disabled";
 322                                 };
 323
 324                                 esai: esai@02024000 {
 325                                         #sound-dai-cells = <0>;
 326                                         compatible = "fsl,imx35-esai";
 327                                         reg = <0x02024000 0x4000>;
 328                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 329                                         clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
 330                                                  <&clks IMX6QDL_CLK_ESAI_MEM>,
 331                                                  <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 332                                                  <&clks IMX6QDL_CLK_ESAI_IPG>,
 333                                                  <&clks IMX6QDL_CLK_SPBA>;
 334                                         clock-names = "core", "mem", "extal", "fsys", "spba";
 335                                         dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
 336                                         dma-names = "rx", "tx";
 337                                         status = "disabled";
 338                                 };
 339
 340                                 ssi1: ssi@02028000 {
 341                                         #sound-dai-cells = <0>;
 342                                         compatible = "fsl,imx6q-ssi",
 343                                                         "fsl,imx51-ssi";
 344                                         reg = <0x02028000 0x4000>;
 345                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 346                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 347                                                  <&clks IMX6QDL_CLK_SSI1>;
 348                                         clock-names = "ipg", "baud";
 349                                         dmas = <&sdma 37 1 0>,
 350                                                <&sdma 38 1 0>;
 351                                         dma-names = "rx", "tx";
 352                                         fsl,fifo-depth = <15>;
 353                                         status = "disabled";
 354                                 };
 355
 356                                 ssi2: ssi@0202c000 {
 357                                         #sound-dai-cells = <0>;
 358                                         compatible = "fsl,imx6q-ssi",
 359                                                         "fsl,imx51-ssi";
 360                                         reg = <0x0202c000 0x4000>;
 361                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 362                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 363                                                  <&clks IMX6QDL_CLK_SSI2>;
 364                                         clock-names = "ipg", "baud";
 365                                         dmas = <&sdma 41 1 0>,
 366                                                <&sdma 42 1 0>;
 367                                         dma-names = "rx", "tx";
 368                                         fsl,fifo-depth = <15>;
 369                                         status = "disabled";
 370                                 };
 371
 372                                 ssi3: ssi@02030000 {
 373                                         #sound-dai-cells = <0>;
 374                                         compatible = "fsl,imx6q-ssi",
 375                                                         "fsl,imx51-ssi";
 376                                         reg = <0x02030000 0x4000>;
 377                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 378                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 379                                                  <&clks IMX6QDL_CLK_SSI3>;
 380                                         clock-names = "ipg", "baud";
 381                                         dmas = <&sdma 45 1 0>,
 382                                                <&sdma 46 1 0>;
 383                                         dma-names = "rx", "tx";
 384                                         fsl,fifo-depth = <15>;
 385                                         status = "disabled";
 386                                 };
 387
 388                                 asrc: asrc@02034000 {
 389                                         compatible = "fsl,imx53-asrc";
 390                                         reg = <0x02034000 0x4000>;
 391                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 392                                         clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
 393                                                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
 394                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 395                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 396                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 397                                                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
 398                                                 <&clks IMX6QDL_CLK_SPBA>;
 399                                         clock-names = "mem", "ipg", "asrck_0",
 400                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 401                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 402                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 403                                                 "asrck_d", "asrck_e", "asrck_f", "spba";
 404                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 405                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 406                                         dma-names = "rxa", "rxb", "rxc",
 407                                                         "txa", "txb", "txc";
 408                                         fsl,asrc-rate  = <48000>;
 409                                         fsl,asrc-width = <16>;
 410                                         status = "okay";
 411                                 };
 412
 413                                 spba@0203c000 {
 414                                         reg = <0x0203c000 0x4000>;
 415                                 };
 416                         };
 417
 418                         vpu: vpu@02040000 {
 419                                 compatible = "cnm,coda960";
 420                                 reg = <0x02040000 0x3c000>;
 421                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 423                                 interrupt-names = "bit", "jpeg";
 424                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 425                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 426                                 clock-names = "per", "ahb";
 427                                 power-domains = <&gpc 1>;
 428                                 resets = <&src 1>;
 429                                 iram = <&ocram>;
 430                         };
 431
 432                         aipstz@0207c000 { /* AIPSTZ1 */
 433                                 reg = <0x0207c000 0x4000>;
 434                         };
 435
 436                         pwm1: pwm@02080000 {
 437                                 #pwm-cells = <2>;
 438                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 439                                 reg = <0x02080000 0x4000>;
 440                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 442                                          <&clks IMX6QDL_CLK_PWM1>;
 443                                 clock-names = "ipg", "per";
 444                                 status = "disabled";
 445                         };
 446
 447                         pwm2: pwm@02084000 {
 448                                 #pwm-cells = <2>;
 449                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 450                                 reg = <0x02084000 0x4000>;
 451                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 452                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 453                                          <&clks IMX6QDL_CLK_PWM2>;
 454                                 clock-names = "ipg", "per";
 455                                 status = "disabled";
 456                         };
 457
 458                         pwm3: pwm@02088000 {
 459                                 #pwm-cells = <2>;
 460                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 461                                 reg = <0x02088000 0x4000>;
 462                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 463                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 464                                          <&clks IMX6QDL_CLK_PWM3>;
 465                                 clock-names = "ipg", "per";
 466                                 status = "disabled";
 467                         };
 468
 469                         pwm4: pwm@0208c000 {
 470                                 #pwm-cells = <2>;
 471                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 472                                 reg = <0x0208c000 0x4000>;
 473                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 474                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 475                                          <&clks IMX6QDL_CLK_PWM4>;
 476                                 clock-names = "ipg", "per";
 477                                 status = "disabled";
 478                         };
 479
 480                         can1: flexcan@02090000 {
 481                                 compatible = "fsl,imx6q-flexcan";
 482                                 reg = <0x02090000 0x4000>;
 483                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 484                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 485                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 486                                 clock-names = "ipg", "per";
 487                                 status = "disabled";
 488                         };
 489
 490                         can2: flexcan@02094000 {
 491                                 compatible = "fsl,imx6q-flexcan";
 492                                 reg = <0x02094000 0x4000>;
 493                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 495                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 496                                 clock-names = "ipg", "per";
 497                                 status = "disabled";
 498                         };
 499
 500                         gpt: gpt@02098000 {
 501                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 502                                 reg = <0x02098000 0x4000>;
 503                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 505                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 506                                          <&clks IMX6QDL_CLK_GPT_3M>;
 507                                 clock-names = "ipg", "per", "osc_per";
 508                         };
 509
 510                         gpio1: gpio@0209c000 {
 511                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 512                                 reg = <0x0209c000 0x4000>;
 513                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 514                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 515                                 gpio-controller;
 516                                 #gpio-cells = <2>;
 517                                 interrupt-controller;
 518                                 #interrupt-cells = <2>;
 519                         };
 520
 521                         gpio2: gpio@020a0000 {
 522                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 523                                 reg = <0x020a0000 0x4000>;
 524                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 525                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 526                                 gpio-controller;
 527                                 #gpio-cells = <2>;
 528                                 interrupt-controller;
 529                                 #interrupt-cells = <2>;
 530                         };
 531
 532                         gpio3: gpio@020a4000 {
 533                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 534                                 reg = <0x020a4000 0x4000>;
 535                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 536                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 537                                 gpio-controller;
 538                                 #gpio-cells = <2>;
 539                                 interrupt-controller;
 540                                 #interrupt-cells = <2>;
 541                         };
 542
 543                         gpio4: gpio@020a8000 {
 544                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 545                                 reg = <0x020a8000 0x4000>;
 546                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 547                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 548                                 gpio-controller;
 549                                 #gpio-cells = <2>;
 550                                 interrupt-controller;
 551                                 #interrupt-cells = <2>;
 552                         };
 553
 554                         gpio5: gpio@020ac000 {
 555                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 556                                 reg = <0x020ac000 0x4000>;
 557                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 558                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 559                                 gpio-controller;
 560                                 #gpio-cells = <2>;
 561                                 interrupt-controller;
 562                                 #interrupt-cells = <2>;
 563                         };
 564
 565                         gpio6: gpio@020b0000 {
 566                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 567                                 reg = <0x020b0000 0x4000>;
 568                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 569                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 570                                 gpio-controller;
 571                                 #gpio-cells = <2>;
 572                                 interrupt-controller;
 573                                 #interrupt-cells = <2>;
 574                         };
 575
 576                         gpio7: gpio@020b4000 {
 577                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 578                                 reg = <0x020b4000 0x4000>;
 579                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 580                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 581                                 gpio-controller;
 582                                 #gpio-cells = <2>;
 583                                 interrupt-controller;
 584                                 #interrupt-cells = <2>;
 585                         };
 586
 587                         kpp: kpp@020b8000 {
 588                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 589                                 reg = <0x020b8000 0x4000>;
 590                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 591                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 592                                 status = "disabled";
 593                         };
 594
 595                         wdog1: wdog@020bc000 {
 596                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 597                                 reg = <0x020bc000 0x4000>;
 598                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 599                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 600                         };
 601
 602                         wdog2: wdog@020c0000 {
 603                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 604                                 reg = <0x020c0000 0x4000>;
 605                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 606                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 607                                 status = "disabled";
 608                         };
 609
 610                         clks: ccm@020c4000 {
 611                                 compatible = "fsl,imx6q-ccm";
 612                                 reg = <0x020c4000 0x4000>;
 613                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 614                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 615                                 #clock-cells = <1>;
 616                         };
 617
 618                         anatop: anatop@020c8000 {
 619                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 620                                 reg = <0x020c8000 0x1000>;
 621                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 622                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 623                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 624
 625                                 regulator-1p1 {
 626                                         compatible = "fsl,anatop-regulator";
 627                                         regulator-name = "vdd1p1";
 628                                         regulator-min-microvolt = <800000>;
 629                                         regulator-max-microvolt = <1375000>;
 630                                         regulator-always-on;
 631                                         anatop-reg-offset = <0x110>;
 632                                         anatop-vol-bit-shift = <8>;
 633                                         anatop-vol-bit-width = <5>;
 634                                         anatop-min-bit-val = <4>;
 635                                         anatop-min-voltage = <800000>;
 636                                         anatop-max-voltage = <1375000>;
 637                                 };
 638
 639                                 regulator-3p0 {
 640                                         compatible = "fsl,anatop-regulator";
 641                                         regulator-name = "vdd3p0";
 642                                         regulator-min-microvolt = <2800000>;
 643                                         regulator-max-microvolt = <3150000>;
 644                                         regulator-always-on;
 645                                         anatop-reg-offset = <0x120>;
 646                                         anatop-vol-bit-shift = <8>;
 647                                         anatop-vol-bit-width = <5>;
 648                                         anatop-min-bit-val = <0>;
 649                                         anatop-min-voltage = <2625000>;
 650                                         anatop-max-voltage = <3400000>;
 651                                 };
 652
 653                                 regulator-2p5 {
 654                                         compatible = "fsl,anatop-regulator";
 655                                         regulator-name = "vdd2p5";
 656                                         regulator-min-microvolt = <2000000>;
 657                                         regulator-max-microvolt = <2750000>;
 658                                         regulator-always-on;
 659                                         anatop-reg-offset = <0x130>;
 660                                         anatop-vol-bit-shift = <8>;
 661                                         anatop-vol-bit-width = <5>;
 662                                         anatop-min-bit-val = <0>;
 663                                         anatop-min-voltage = <2000000>;
 664                                         anatop-max-voltage = <2750000>;
 665                                 };
 666
 667                                 reg_arm: regulator-vddcore {
 668                                         compatible = "fsl,anatop-regulator";
 669                                         regulator-name = "vddarm";
 670                                         regulator-min-microvolt = <725000>;
 671                                         regulator-max-microvolt = <1450000>;
 672                                         regulator-always-on;
 673                                         anatop-reg-offset = <0x140>;
 674                                         anatop-vol-bit-shift = <0>;
 675                                         anatop-vol-bit-width = <5>;
 676                                         anatop-delay-reg-offset = <0x170>;
 677                                         anatop-delay-bit-shift = <24>;
 678                                         anatop-delay-bit-width = <2>;
 679                                         anatop-min-bit-val = <1>;
 680                                         anatop-min-voltage = <725000>;
 681                                         anatop-max-voltage = <1450000>;
 682                                 };
 683
 684                                 reg_pu: regulator-vddpu {
 685                                         compatible = "fsl,anatop-regulator";
 686                                         regulator-name = "vddpu";
 687                                         regulator-min-microvolt = <725000>;
 688                                         regulator-max-microvolt = <1450000>;
 689                                         regulator-enable-ramp-delay = <150>;
 690                                         anatop-reg-offset = <0x140>;
 691                                         anatop-vol-bit-shift = <9>;
 692                                         anatop-vol-bit-width = <5>;
 693                                         anatop-delay-reg-offset = <0x170>;
 694                                         anatop-delay-bit-shift = <26>;
 695                                         anatop-delay-bit-width = <2>;
 696                                         anatop-min-bit-val = <1>;
 697                                         anatop-min-voltage = <725000>;
 698                                         anatop-max-voltage = <1450000>;
 699                                 };
 700
 701                                 reg_soc: regulator-vddsoc {
 702                                         compatible = "fsl,anatop-regulator";
 703                                         regulator-name = "vddsoc";
 704                                         regulator-min-microvolt = <725000>;
 705                                         regulator-max-microvolt = <1450000>;
 706                                         regulator-always-on;
 707                                         anatop-reg-offset = <0x140>;
 708                                         anatop-vol-bit-shift = <18>;
 709                                         anatop-vol-bit-width = <5>;
 710                                         anatop-delay-reg-offset = <0x170>;
 711                                         anatop-delay-bit-shift = <28>;
 712                                         anatop-delay-bit-width = <2>;
 713                                         anatop-min-bit-val = <1>;
 714                                         anatop-min-voltage = <725000>;
 715                                         anatop-max-voltage = <1450000>;
 716                                 };
 717                         };
 718
 719                         tempmon: tempmon {
 720                                 compatible = "fsl,imx6q-tempmon";
 721                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 722                                 fsl,tempmon = <&anatop>;
 723                                 fsl,tempmon-data = <&ocotp>;
 724                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 725                         };
 726
 727                         usbphy1: usbphy@020c9000 {
 728                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 729                                 reg = <0x020c9000 0x1000>;
 730                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 732                                 fsl,anatop = <&anatop>;
 733                         };
 734
 735                         usbphy2: usbphy@020ca000 {
 736                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 737                                 reg = <0x020ca000 0x1000>;
 738                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 739                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 740                                 fsl,anatop = <&anatop>;
 741                         };
 742
 743                         snvs: snvs@020cc000 {
 744                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 745                                 reg = <0x020cc000 0x4000>;
 746
 747                                 snvs_rtc: snvs-rtc-lp {
 748                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 749                                         regmap = <&snvs>;
 750                                         offset = <0x34>;
 751                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 752                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 753                                 };
 754
 755                                 snvs_poweroff: snvs-poweroff {
 756                                         compatible = "syscon-poweroff";
 757                                         regmap = <&snvs>;
 758                                         offset = <0x38>;
 759                                         mask = <0x60>;
 760                                         status = "disabled";
 761                                 };
 762                         };
 763
 764                         epit1: epit@020d0000 { /* EPIT1 */
 765                                 reg = <0x020d0000 0x4000>;
 766                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 767                         };
 768
 769                         epit2: epit@020d4000 { /* EPIT2 */
 770                                 reg = <0x020d4000 0x4000>;
 771                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 772                         };
 773
 774                         src: src@020d8000 {
 775                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 776                                 reg = <0x020d8000 0x4000>;
 777                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 778                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 779                                 #reset-cells = <1>;
 780                         };
 781
 782                         gpc: gpc@020dc000 {
 783                                 compatible = "fsl,imx6q-gpc";
 784                                 reg = <0x020dc000 0x4000>;
 785                                 interrupt-controller;
 786                                 #interrupt-cells = <3>;
 787                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 788                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 789                                 interrupt-parent = <&intc>;
 790                                 pu-supply = <&reg_pu>;
 791                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 792                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 793                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 794                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 795                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 796                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 797                                 #power-domain-cells = <1>;
 798                         };
 799
 800                         gpr: iomuxc-gpr@020e0000 {
 801                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 802                                 reg = <0x020e0000 0x38>;
 803                         };
 804
 805                         iomuxc: iomuxc@020e0000 {
 806                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 807                                 reg = <0x020e0000 0x4000>;
 808                         };
 809
 810                         ldb: ldb@020e0008 {
 811                                 #address-cells = <1>;
 812                                 #size-cells = <0>;
 813                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 814                                 gpr = <&gpr>;
 815                                 status = "disabled";
 816
 817                                 lvds-channel@0 {
 818                                         #address-cells = <1>;
 819                                         #size-cells = <0>;
 820                                         reg = <0>;
 821                                         status = "disabled";
 822
 823                                         port@0 {
 824                                                 reg = <0>;
 825
 826                                                 lvds0_mux_0: endpoint {
 827                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 828                                                 };
 829                                         };
 830
 831                                         port@1 {
 832                                                 reg = <1>;
 833
 834                                                 lvds0_mux_1: endpoint {
 835                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 836                                                 };
 837                                         };
 838                                 };
 839
 840                                 lvds-channel@1 {
 841                                         #address-cells = <1>;
 842                                         #size-cells = <0>;
 843                                         reg = <1>;
 844                                         status = "disabled";
 845
 846                                         port@0 {
 847                                                 reg = <0>;
 848
 849                                                 lvds1_mux_0: endpoint {
 850                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 851                                                 };
 852                                         };
 853
 854                                         port@1 {
 855                                                 reg = <1>;
 856
 857                                                 lvds1_mux_1: endpoint {
 858                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 859                                                 };
 860                                         };
 861                                 };
 862                         };
 863
 864                         dcic1: dcic@020e4000 {
 865                                 reg = <0x020e4000 0x4000>;
 866                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 867                         };
 868
 869                         dcic2: dcic@020e8000 {
 870                                 reg = <0x020e8000 0x4000>;
 871                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 872                         };
 873
 874                         sdma: sdma@020ec000 {
 875                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 876                                 reg = <0x020ec000 0x4000>;
 877                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 878                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 879                                          <&clks IMX6QDL_CLK_SDMA>;
 880                                 clock-names = "ipg", "ahb";
 881                                 #dma-cells = <3>;
 882                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 883                         };
 884                 };
 885
 886                 aips-bus@02100000 { /* AIPS2 */
 887                         compatible = "fsl,aips-bus", "simple-bus";
 888                         #address-cells = <1>;
 889                         #size-cells = <1>;
 890                         reg = <0x02100000 0x100000>;
 891                         ranges;
 892
 893                         crypto: caam@2100000 {
 894                                 compatible = "fsl,sec-v4.0";
 895                                 fsl,sec-era = <4>;
 896                                 #address-cells = <1>;
 897                                 #size-cells = <1>;
 898                                 reg = <0x2100000 0x10000>;
 899                                 ranges = <0 0x2100000 0x10000>;
 900                                 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
 901                                          <&clks IMX6QDL_CLK_CAAM_ACLK>,
 902                                          <&clks IMX6QDL_CLK_CAAM_IPG>,
 903                                          <&clks IMX6QDL_CLK_EIM_SLOW>;
 904                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 905
 906                                 sec_jr0: jr0@1000 {
 907                                         compatible = "fsl,sec-v4.0-job-ring";
 908                                         reg = <0x1000 0x1000>;
 909                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 910                                 };
 911
 912                                 sec_jr1: jr1@2000 {
 913                                         compatible = "fsl,sec-v4.0-job-ring";
 914                                         reg = <0x2000 0x1000>;
 915                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 916                                 };
 917                         };
 918
 919                         aipstz@0217c000 { /* AIPSTZ2 */
 920                                 reg = <0x0217c000 0x4000>;
 921                         };
 922
 923                         usbotg: usb@02184000 {
 924                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 925                                 reg = <0x02184000 0x200>;
 926                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 928                                 fsl,usbphy = <&usbphy1>;
 929                                 fsl,usbmisc = <&usbmisc 0>;
 930                                 ahb-burst-config = <0x0>;
 931                                 tx-burst-size-dword = <0x10>;
 932                                 rx-burst-size-dword = <0x10>;
 933                                 status = "disabled";
 934                         };
 935
 936                         usbh1: usb@02184200 {
 937                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 938                                 reg = <0x02184200 0x200>;
 939                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 940                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 941                                 fsl,usbphy = <&usbphy2>;
 942                                 fsl,usbmisc = <&usbmisc 1>;
 943                                 dr_mode = "host";
 944                                 ahb-burst-config = <0x0>;
 945                                 tx-burst-size-dword = <0x10>;
 946                                 rx-burst-size-dword = <0x10>;
 947                                 status = "disabled";
 948                         };
 949
 950                         usbh2: usb@02184400 {
 951                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 952                                 reg = <0x02184400 0x200>;
 953                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 954                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 955                                 fsl,usbmisc = <&usbmisc 2>;
 956                                 dr_mode = "host";
 957                                 ahb-burst-config = <0x0>;
 958                                 tx-burst-size-dword = <0x10>;
 959                                 rx-burst-size-dword = <0x10>;
 960                                 status = "disabled";
 961                         };
 962
 963                         usbh3: usb@02184600 {
 964                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 965                                 reg = <0x02184600 0x200>;
 966                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 968                                 fsl,usbmisc = <&usbmisc 3>;
 969                                 dr_mode = "host";
 970                                 ahb-burst-config = <0x0>;
 971                                 tx-burst-size-dword = <0x10>;
 972                                 rx-burst-size-dword = <0x10>;
 973                                 status = "disabled";
 974                         };
 975
 976                         usbmisc: usbmisc@02184800 {
 977                                 #index-cells = <1>;
 978                                 compatible = "fsl,imx6q-usbmisc";
 979                                 reg = <0x02184800 0x200>;
 980                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 981                         };
 982
 983                         fec: ethernet@02188000 {
 984                                 compatible = "fsl,imx6q-fec";
 985                                 reg = <0x02188000 0x4000>;
 986                                 interrupts-extended =
 987                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 988                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 989                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 990                                          <&clks IMX6QDL_CLK_ENET>,
 991                                          <&clks IMX6QDL_CLK_ENET_REF>;
 992                                 clock-names = "ipg", "ahb", "ptp";
 993                                 status = "disabled";
 994                         };
 995
 996                         mlb@0218c000 {
 997                                 reg = <0x0218c000 0x4000>;
 998                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 999                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1000                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
1001                         };
1002
1003                         usdhc1: usdhc@02190000 {
1004                                 compatible = "fsl,imx6q-usdhc";
1005                                 reg = <0x02190000 0x4000>;
1006                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1007                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1008                                          <&clks IMX6QDL_CLK_USDHC1>,
1009                                          <&clks IMX6QDL_CLK_USDHC1>;
1010                                 clock-names = "ipg", "ahb", "per";
1011                                 bus-width = <4>;
1012                                 status = "disabled";
1013                         };
1014
1015                         usdhc2: usdhc@02194000 {
1016                                 compatible = "fsl,imx6q-usdhc";
1017                                 reg = <0x02194000 0x4000>;
1018                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1019                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1020                                          <&clks IMX6QDL_CLK_USDHC2>,
1021                                          <&clks IMX6QDL_CLK_USDHC2>;
1022                                 clock-names = "ipg", "ahb", "per";
1023                                 bus-width = <4>;
1024                                 status = "disabled";
1025                         };
1026
1027                         usdhc3: usdhc@02198000 {
1028                                 compatible = "fsl,imx6q-usdhc";
1029                                 reg = <0x02198000 0x4000>;
1030                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1031                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1032                                          <&clks IMX6QDL_CLK_USDHC3>,
1033                                          <&clks IMX6QDL_CLK_USDHC3>;
1034                                 clock-names = "ipg", "ahb", "per";
1035                                 bus-width = <4>;
1036                                 status = "disabled";
1037                         };
1038
1039                         usdhc4: usdhc@0219c000 {
1040                                 compatible = "fsl,imx6q-usdhc";
1041                                 reg = <0x0219c000 0x4000>;
1042                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1043                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1044                                          <&clks IMX6QDL_CLK_USDHC4>,
1045                                          <&clks IMX6QDL_CLK_USDHC4>;
1046                                 clock-names = "ipg", "ahb", "per";
1047                                 bus-width = <4>;
1048                                 status = "disabled";
1049                         };
1050
1051                         i2c1: i2c@021a0000 {
1052                                 #address-cells = <1>;
1053                                 #size-cells = <0>;
1054                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1055                                 reg = <0x021a0000 0x4000>;
1056                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1057                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
1058                                 status = "disabled";
1059                         };
1060
1061                         i2c2: i2c@021a4000 {
1062                                 #address-cells = <1>;
1063                                 #size-cells = <0>;
1064                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1065                                 reg = <0x021a4000 0x4000>;
1066                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1067                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
1068                                 status = "disabled";
1069                         };
1070
1071                         i2c3: i2c@021a8000 {
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1075                                 reg = <0x021a8000 0x4000>;
1076                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1077                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
1078                                 status = "disabled";
1079                         };
1080
1081                         romcp@021ac000 {
1082                                 reg = <0x021ac000 0x4000>;
1083                         };
1084
1085                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1086                                 compatible = "fsl,imx6q-mmdc";
1087                                 reg = <0x021b0000 0x4000>;
1088                         };
1089
1090                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1091                                 reg = <0x021b4000 0x4000>;
1092                         };
1093
1094                         weim: weim@021b8000 {
1095                                 compatible = "fsl,imx6q-weim";
1096                                 reg = <0x021b8000 0x4000>;
1097                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1098                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1099                         };
1100
1101                         ocotp: ocotp@021bc000 {
1102                                 compatible = "fsl,imx6q-ocotp", "syscon";
1103                                 reg = <0x021bc000 0x4000>;
1104                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1105                         };
1106
1107                         tzasc@021d0000 { /* TZASC1 */
1108                                 reg = <0x021d0000 0x4000>;
1109                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1110                         };
1111
1112                         tzasc@021d4000 { /* TZASC2 */
1113                                 reg = <0x021d4000 0x4000>;
1114                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1115                         };
1116
1117                         audmux: audmux@021d8000 {
1118                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1119                                 reg = <0x021d8000 0x4000>;
1120                                 status = "disabled";
1121                         };
1122
1123                         mipi_csi: mipi@021dc000 {
1124                                 reg = <0x021dc000 0x4000>;
1125                         };
1126
1127                         mipi_dsi: mipi@021e0000 {
1128                                 #address-cells = <1>;
1129                                 #size-cells = <0>;
1130                                 reg = <0x021e0000 0x4000>;
1131                                 status = "disabled";
1132
1133                                 ports {
1134                                         #address-cells = <1>;
1135                                         #size-cells = <0>;
1136
1137                                         port@0 {
1138                                                 reg = <0>;
1139
1140                                                 mipi_mux_0: endpoint {
1141                                                         remote-endpoint = <&ipu1_di0_mipi>;
1142                                                 };
1143                                         };
1144
1145                                         port@1 {
1146                                                 reg = <1>;
1147
1148                                                 mipi_mux_1: endpoint {
1149                                                         remote-endpoint = <&ipu1_di1_mipi>;
1150                                                 };
1151                                         };
1152                                 };
1153                         };
1154
1155                         vdoa@021e4000 {
1156                                 reg = <0x021e4000 0x4000>;
1157                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1158                         };
1159
1160                         uart2: serial@021e8000 {
1161                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1162                                 reg = <0x021e8000 0x4000>;
1163                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1164                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1165                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1166                                 clock-names = "ipg", "per";
1167                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1168                                 dma-names = "rx", "tx";
1169                                 status = "disabled";
1170                         };
1171
1172                         uart3: serial@021ec000 {
1173                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1174                                 reg = <0x021ec000 0x4000>;
1175                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1176                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1177                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1178                                 clock-names = "ipg", "per";
1179                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1180                                 dma-names = "rx", "tx";
1181                                 status = "disabled";
1182                         };
1183
1184                         uart4: serial@021f0000 {
1185                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1186                                 reg = <0x021f0000 0x4000>;
1187                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1188                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1189                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1190                                 clock-names = "ipg", "per";
1191                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1192                                 dma-names = "rx", "tx";
1193                                 status = "disabled";
1194                         };
1195
1196                         uart5: serial@021f4000 {
1197                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1198                                 reg = <0x021f4000 0x4000>;
1199                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1200                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1201                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1202                                 clock-names = "ipg", "per";
1203                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1204                                 dma-names = "rx", "tx";
1205                                 status = "disabled";
1206                         };
1207                 };
1208
1209                 ipu1: ipu@02400000 {
1210                         #address-cells = <1>;
1211                         #size-cells = <0>;
1212                         compatible = "fsl,imx6q-ipu";
1213                         reg = <0x02400000 0x400000>;
1214                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1216                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1217                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1218                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1219                         clock-names = "bus", "di0", "di1";
1220                         resets = <&src 2>;
1221
1222                         ipu1_csi0: port@0 {
1223                                 reg = <0>;
1224                         };
1225
1226                         ipu1_csi1: port@1 {
1227                                 reg = <1>;
1228                         };
1229
1230                         ipu1_di0: port@2 {
1231                                 #address-cells = <1>;
1232                                 #size-cells = <0>;
1233                                 reg = <2>;
1234
1235                                 ipu1_di0_disp0: disp0-endpoint {
1236                                 };
1237
1238                                 ipu1_di0_hdmi: hdmi-endpoint {
1239                                         remote-endpoint = <&hdmi_mux_0>;
1240                                 };
1241
1242                                 ipu1_di0_mipi: mipi-endpoint {
1243                                         remote-endpoint = <&mipi_mux_0>;
1244                                 };
1245
1246                                 ipu1_di0_lvds0: lvds0-endpoint {
1247                                         remote-endpoint = <&lvds0_mux_0>;
1248                                 };
1249
1250                                 ipu1_di0_lvds1: lvds1-endpoint {
1251                                         remote-endpoint = <&lvds1_mux_0>;
1252                                 };
1253                         };
1254
1255                         ipu1_di1: port@3 {
1256                                 #address-cells = <1>;
1257                                 #size-cells = <0>;
1258                                 reg = <3>;
1259
1260                                 ipu1_di1_disp1: disp1-endpoint {
1261                                 };
1262
1263                                 ipu1_di1_hdmi: hdmi-endpoint {
1264                                         remote-endpoint = <&hdmi_mux_1>;
1265                                 };
1266
1267                                 ipu1_di1_mipi: mipi-endpoint {
1268                                         remote-endpoint = <&mipi_mux_1>;
1269                                 };
1270
1271                                 ipu1_di1_lvds0: lvds0-endpoint {
1272                                         remote-endpoint = <&lvds0_mux_1>;
1273                                 };
1274
1275                                 ipu1_di1_lvds1: lvds1-endpoint {
1276                                         remote-endpoint = <&lvds1_mux_1>;
1277                                 };
1278                         };
1279                 };
1280         };
1281 };