arch/arm/boot/dts/imx6ul-geam.dtsi

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/input/input.h>
  45 #include "imx6ul.dtsi"
  46
  47 / {
  48         memory {
  49                 reg = <0x80000000 0x08000000>;
  50         };
  51
  52         chosen {
  53                 stdout-path = &uart1;
  54         };
  55
  56         reg_1p8v: regulator-1p8v {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "1P8V";
  59                 regulator-min-microvolt = <1800000>;
  60                 regulator-max-microvolt = <1800000>;
  61                 regulator-always-on;
  62                 regulator-boot-on;
  63         };
  64
  65         reg_3p3v: regulator-3p3v {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "3P3V";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70                 regulator-always-on;
  71                 regulator-boot-on;
  72         };
  73 };
  74
  75 &can1 {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_flexcan1>;
  78         xceiver-supply = <&reg_3p3v>;
  79 };
  80
  81 &can2 {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_flexcan2>;
  84         xceiver-supply = <&reg_3p3v>;
  85 };
  86
  87 &fec1 {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_enet1>;
  90         phy-mode = "rmii";
  91         phy-handle = <&ethphy0>;
  92         status = "okay";
  93 };
  94
  95 &fec2 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_enet2>;
  98         phy-mode = "rmii";
  99         phy-handle = <&ethphy1>;
 100         status = "okay";
 101
 102         mdio {
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105
 106                 ethphy0: ethernet-phy@0 {
 107                         compatible = "ethernet-phy-ieee802.3-c22";
 108                         reg = <0>;
 109                 };
 110
 111                 ethphy1: ethernet-phy@1 {
 112                         compatible = "ethernet-phy-ieee802.3-c22";
 113                         reg = <1>;
 114                 };
 115         };
 116 };
 117
 118 &gpmi {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_gpmi_nand>;
 121         nand-on-flash-bbt;
 122         status = "okay";
 123 };
 124
 125 &i2c1 {
 126         clock-frequency = <100000>;
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_i2c1>;
 129         status = "okay";
 130 };
 131
 132 &i2c2 {
 133         clock_frequency = <100000>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_i2c2>;
 136         status = "okay";
 137 };
 138
 139 &lcdif {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_lcdif_dat
 142                      &pinctrl_lcdif_ctrl>;
 143         display = <&display0>;
 144 };
 145
 146 &tsc {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_tsc>;
 149         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 150 };
 151
 152 &uart1 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_uart1>;
 155         status = "okay";
 156 };
 157
 158 &uart2 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_uart2>;
 161         status = "okay";
 162 };
 163
 164 &usbotg1 {
 165         dr_mode = "peripheral";
 166         status = "okay";
 167 };
 168
 169 &usbotg2 {
 170         dr_mode = "host";
 171         status = "okay";
 172 };
 173
 174 &usdhc1 {
 175         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 176         pinctrl-0 = <&pinctrl_usdhc1>;
 177         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 178         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 179         bus-width = <4>;
 180         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 181         no-1-8-v;
 182         status = "okay";
 183 };
 184
 185 &iomuxc {
 186         pinctrl_enet1: enet1grp {
 187                 fsl,pins = <
 188                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 189                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 190                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 191                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 192                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 193                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 194                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 195                 >;
 196         };
 197
 198         pinctrl_enet2: enet2grp {
 199                 fsl,pins = <
 200                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 201                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 202                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 203                         MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15       0x1b0b0         /* ENET_nRST */
 204                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 205                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 206                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 207                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 208                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 209                         MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2    0x4001b031
 210                 >;
 211         };
 212
 213         pinctrl_flexcan1: flexcan1grp {
 214                 fsl,pins = <
 215                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 216                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 217                 >;
 218         };
 219
 220         pinctrl_flexcan2: flexcan2grp {
 221                 fsl,pins = <
 222                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 223                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 224                 >;
 225         };
 226
 227         pinctrl_gpmi_nand: gpmi-nand {
 228                 fsl,pins = <
 229                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
 230                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
 231                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
 232                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
 233                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
 234                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
 235                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
 236                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
 237                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
 238                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
 239                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
 240                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
 241                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
 242                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
 243                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
 244                 >;
 245         };
 246
 247         pinctrl_i2c1: i2c1grp {
 248                 fsl,pins = <
 249                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 250                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 251                 >;
 252         };
 253
 254         pinctrl_i2c2: i2c2grp {
 255                         fsl,pins = <
 256                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 257                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 258                 >;
 259         };
 260
 261         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 262                 fsl,pins = <
 263                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 264                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 265                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 266                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 267                 >;
 268         };
 269
 270         pinctrl_lcdif_dat: lcdifdatgrp {
 271                 fsl,pins = <
 272                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 273                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 274                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 275                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 276                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 277                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 278                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 279                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 280                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 281                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 282                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 283                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 284                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 285                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 286                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 287                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 288                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 289                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 290                 >;
 291         };
 292
 293         pinctrl_tsc: tscgrp {
 294                 fsl,pin = <
 295                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
 296                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0xb0
 297                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
 298                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
 299                 >;
 300         };
 301
 302         pinctrl_uart1: uart1grp {
 303                 fsl,pins = <
 304                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 305                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 306                 >;
 307         };
 308
 309         pinctrl_uart2: uart2grp {
 310                 fsl,pins = <
 311                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 312                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 313                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 314                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 315                 >;
 316         };
 317
 318         pinctrl_usdhc1: usdhc1grp {
 319                 fsl,pins = <
 320                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 321                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
 322                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
 323                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
 324                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
 325                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 326                 >;
 327         };
 328
 329         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 330                 fsl,pins = <
 331                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 332                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 333                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 334                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 335                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 336                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 337                 >;
 338         };
 339
 340         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 341                 fsl,pins = <
 342                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 343                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 344                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 345                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 346                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 347                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 348                 >;
 349         };
 350
 351         pinctrl_usdhc2: usdhc2grp {
 352                 fsl,pins = <
 353                         MX6UL_PAD_CSI_VSYNC__USDHC2_CLK     0x17070
 354                         MX6UL_PAD_CSI_HSYNC__USDHC2_CMD     0x10070
 355                         MX6UL_PAD_CSI_DATA00__USDHC2_DATA0  0x17070
 356                         MX6UL_PAD_CSI_DATA01__USDHC2_DATA1  0x17070
 357                         MX6UL_PAD_CSI_DATA02__USDHC2_DATA2  0x17070
 358                         MX6UL_PAD_CSI_DATA03__USDHC2_DATA3  0x17070
 359                 >;
 360         };
 361 };