arch/arm/boot/dts/imx6ul-pico-hobbit.dts

   1 /*
   2  * Copyright 2015 Technexion Ltd.
   3  *
   4  * Author: Wig Cheng  <wig.cheng@technexion.com>
   5  *         Richard Hu <richard.hu@technexion.com>
   6  *         Tapani Utriainen <tapani@technexion.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License
  15  *     version 2 as published by the Free Software Foundation.
  16  *
  17  *     This file is distributed in the hope that it will be useful
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /dts-v1/;
  47
  48 #include "imx6ul.dtsi"
  49
  50 / {
  51         model = "Technexion Pico i.MX6UL Board";
  52         compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
  53
  54         memory {
  55                 reg = <0x80000000 0x10000000>;
  56         };
  57
  58         chosen {
  59                 stdout-path = &uart6;
  60         };
  61
  62         backlight {
  63                 compatible = "pwm-backlight";
  64                 pwms = <&pwm3 0 5000000>;
  65                 brightness-levels = <0 4 8 16 32 64 128 255>;
  66                 default-brightness-level = <6>;
  67                 status = "okay";
  68         };
  69
  70         reg_2p5v: regulator-2p5v {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "2P5V";
  73                 regulator-min-microvolt = <2500000>;
  74                 regulator-max-microvolt = <2500000>;
  75         };
  76
  77         reg_3p3v: regulator-3p3v {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "3P3V";
  80                 regulator-min-microvolt = <3300000>;
  81                 regulator-max-microvolt = <3300000>;
  82         };
  83
  84         reg_sd1_vmmc: regulator-sd1-vmmc {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "VSD_3V3";
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  90                 enable-active-high;
  91         };
  92
  93         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  94                 compatible = "regulator-fixed";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_usb_otg1>;
  97                 regulator-name = "usb_otg_vbus";
  98                 regulator-min-microvolt = <5000000>;
  99                 regulator-max-microvolt = <5000000>;
 100                 gpio = <&gpio1 6 0>;
 101         };
 102
 103         reg_brcm: regulator-brcm {
 104                 compatible = "regulator-fixed";
 105                 enable-active-high;
 106                 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
 107                 pinctrl-names = "default";
 108                 pinctrl-0 = <&pinctrl_brcm_reg>;
 109                 regulator-name = "brcm_reg";
 110                 regulator-min-microvolt = <3300000>;
 111                 regulator-max-microvolt = <3300000>;
 112                 startup-delay-us = <200000>;
 113         };
 114
 115         sound {
 116                 compatible = "fsl,imx-audio-sgtl5000";
 117                 model = "imx6ul-sgtl5000";
 118                 audio-cpu = <&sai1>;
 119                 audio-codec = <&codec>;
 120                 audio-routing =
 121                         "LINE_IN", "Line In Jack",
 122                         "MIC_IN", "Mic Jack",
 123                         "Mic Jack", "Mic Bias",
 124                         "Headphone Jack", "HP_OUT";
 125         };
 126
 127         sys_mclk: clock-sys-mclk {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <24576000>;
 131         };
 132
 133         leds {
 134                 compatible = "gpio-leds";
 135
 136                 hobbitled {
 137                         label = "hobbitled";
 138                         gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
 139                 };
 140         };
 141 };
 142
 143 &can1 {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_flexcan1>;
 146         status = "okay";
 147 };
 148
 149 &can2 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_flexcan2>;
 152         status = "okay";
 153 };
 154
 155 &clks {
 156         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 157         assigned-clock-rates = <786432000>;
 158 };
 159
 160 &fec2 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_enet2>;
 163         phy-mode = "rmii";
 164         phy-handle = <&ethphy1>;
 165         status = "okay";
 166         phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
 167         phy-reset-duration = <1>;
 168
 169         mdio {
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172
 173                 ethphy1: ethernet-phy@1 {
 174                         compatible = "ethernet-phy-ieee802.3-c22";
 175                         reg = <1>;
 176                         max-speed = <100>;
 177                         interrupt-parent = <&gpio5>;
 178                         interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>;
 179                 };
 180         };
 181 };
 182
 183 &i2c1 {
 184         clock-frequency = <100000>;
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_i2c1>;
 187         status = "okay";
 188
 189         pmic: pfuze3000@08 {
 190                 compatible = "fsl,pfuze3000";
 191                 reg = <0x08>;
 192
 193                 regulators {
 194                         /* VDD_ARM_SOC_IN*/
 195                         sw1b_reg: sw1b {
 196                                 regulator-min-microvolt = <700000>;
 197                                 regulator-max-microvolt = <1475000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                                 regulator-ramp-delay = <6250>;
 201                         };
 202
 203                         /* DRAM */
 204                         sw3a_reg: sw3 {
 205                                 regulator-min-microvolt = <900000>;
 206                                 regulator-max-microvolt = <1650000>;
 207                                 regulator-boot-on;
 208                                 regulator-always-on;
 209                         };
 210
 211                         /* DRAM */
 212                         vref_reg: vrefddr {
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216                 };
 217         };
 218 };
 219
 220 &i2c2 {
 221         clock_frequency = <100000>;
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_i2c2>;
 224         status = "okay";
 225
 226         codec: sgtl5000@0a {
 227                 reg = <0x0a>;
 228                 compatible = "fsl,sgtl5000";
 229                 clocks = <&sys_mclk>;
 230                 VDDA-supply = <&reg_2p5v>;
 231                 VDDIO-supply = <&reg_3p3v>;
 232         };
 233 };
 234
 235 &i2c3 {
 236         clock_frequency = <100000>;
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&pinctrl_i2c3>;
 239         status = "okay";
 240 };
 241
 242 &lcdif {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
 245         display = <&display0>;
 246         status = "okay";
 247
 248         display0: display0 {
 249                 bits-per-pixel = <32>;
 250                 bus-width = <24>;
 251
 252                 display-timings {
 253                         native-mode = <&timing0>;
 254
 255                         timing0: timing0 {
 256                                 clock-frequency = <33200000>;
 257                                 hactive = <800>;
 258                                 vactive = <480>;
 259                                 hfront-porch = <210>;
 260                                 hback-porch = <46>;
 261                                 hsync-len = <1>;
 262                                 vback-porch = <22>;
 263                                 vfront-porch = <23>;
 264                                 vsync-len = <1>;
 265                                 hsync-active = <0>;
 266                                 vsync-active = <0>;
 267                                 de-active = <1>;
 268                                 pixelclk-active = <0>;
 269                         };
 270                 };
 271         };
 272 };
 273
 274 &pwm3 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_pwm3>;
 277         status = "okay";
 278 };
 279
 280 &pwm7 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_pwm7>;
 283         status = "okay";
 284 };
 285
 286 &pwm8 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_pwm8>;
 289         status = "okay";
 290 };
 291
 292 &sai1 {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&pinctrl_sai1>;
 295         status = "okay";
 296 };
 297
 298 &uart3 {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_uart3>;
 301         uart-has-rtscts;
 302         status = "okay";
 303 };
 304
 305 &uart6 {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_uart6>;
 308         status = "okay";
 309 };
 310
 311 &usbotg1 {
 312         vbus-supply = <&reg_usb_otg_vbus>;
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 315         dr_mode = "otg";
 316         disable-over-current;
 317         status = "okay";
 318 };
 319
 320 &usbotg2 {
 321         dr_mode = "host";
 322         disable-over-current;
 323         status = "okay";
 324 };
 325
 326 &usdhc1 {
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&pinctrl_usdhc1>;
 329         bus-width = <8>;
 330         no-1-8-v;
 331         non-removable;
 332         keep-power-in-suspend;
 333         status = "okay";
 334 };
 335
 336 &usdhc2 {  /* Wifi SDIO */
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_usdhc2>;
 339         no-1-8-v;
 340         non-removable;
 341         keep-power-in-suspend;
 342         wakeup-source;
 343         vmmc-supply = <&reg_brcm>;
 344         status = "okay";
 345 };
 346
 347 &wdog1 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&pinctrl_wdog>;
 350         fsl,ext-reset-output;
 351 };
 352
 353 &iomuxc {
 354         pinctrl_brcm_reg: brcmreggrp {
 355                 fsl,pins = <
 356                         MX6UL_PAD_NAND_DATA06__GPIO4_IO08       0x10b0  /* WL_REG_ON */
 357                         MX6UL_PAD_NAND_DATA04__GPIO4_IO06       0x10b0  /* WL_HOST_WAKE */
 358                 >;
 359         };
 360
 361         pinctrl_enet2: enet2grp {
 362                 fsl,pins = <
 363                         MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO    0x1b0b0
 364                         MX6UL_PAD_ENET1_TX_EN__ENET2_MDC        0x1b0b0
 365                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 366                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 367                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 368                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 369                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 370                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 371                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 372                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 373                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x800
 374                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x79
 375                 >;
 376         };
 377
 378         pinctrl_flexcan1: flexcan1grp {
 379                 fsl,pins = <
 380                         MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
 381                         MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
 382                 >;
 383         };
 384
 385         pinctrl_flexcan2: flexcan2grp {
 386                 fsl,pins = <
 387                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 388                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
 389                 >;
 390         };
 391
 392         pinctrl_i2c1: i2c1grp {
 393                 fsl,pins = <
 394                         MX6UL_PAD_GPIO1_IO02__I2C1_SCL          0x4001b8b0
 395                         MX6UL_PAD_GPIO1_IO03__I2C1_SDA          0x4001b8b0
 396                 >;
 397         };
 398
 399         pinctrl_i2c2: i2c2grp {
 400                 fsl,pins = <
 401                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
 402                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
 403                 >;
 404         };
 405
 406         pinctrl_i2c3: i2c3grp {
 407                 fsl,pins = <
 408                         MX6UL_PAD_UART1_TX_DATA__I2C3_SCL       0x4001b8b0
 409                         MX6UL_PAD_UART1_RX_DATA__I2C3_SDA       0x4001b8b0
 410                         >;
 411         };
 412
 413         pinctrl_lcdif_dat: lcdifdatgrp {
 414                 fsl,pins = <
 415                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
 416                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
 417                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x79
 418                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x79
 419                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x79
 420                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x79
 421                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x79
 422                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x79
 423                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x79
 424                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x79
 425                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x79
 426                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x79
 427                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x79
 428                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x79
 429                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x79
 430                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x79
 431                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x79
 432                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x79
 433                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x79
 434                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x79
 435                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x79
 436                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x79
 437                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x79
 438                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x79
 439                 >;
 440         };
 441
 442         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 443                 fsl,pins = <
 444                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x79
 445                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
 446                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
 447                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
 448                         /* LCD reset */
 449                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x79
 450                 >;
 451         };
 452
 453         pinctrl_pwm3: pwm3grp {
 454                 fsl,pins = <
 455                         MX6UL_PAD_NAND_ALE__PWM3_OUT            0x110b0
 456                 >;
 457         };
 458
 459         pinctrl_pwm7: pwm7grp {
 460                 fsl,pins = <
 461                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x110b0
 462                 >;
 463         };
 464
 465         pinctrl_pwm8: pwm8grp {
 466                 fsl,pins = <
 467                         MX6UL_PAD_ENET1_RX_ER__PWM8_OUT         0x110b0
 468                 >;
 469         };
 470
 471         pinctrl_sai1: sai1grp {
 472                 fsl,pins = <
 473                         MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC      0x1b0b0
 474                         MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK      0x1b0b0
 475                         MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA      0x110b0
 476                         MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA      0x1f0b8
 477                 >;
 478         };
 479
 480         pinctrl_uart3: uart3grp {
 481                 fsl,pins = <
 482                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b0
 483                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b0
 484                         MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS    0x1b0b0
 485                         MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b0
 486                 >;
 487         };
 488
 489         pinctrl_uart5: uart5grp {
 490                 fsl,pins = <
 491                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x1b0b1
 492                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x1b0b1
 493                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
 494                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
 495                 >;
 496         };
 497
 498         pinctrl_uart6: uart6grp {
 499                 fsl,pins = <
 500                         MX6UL_PAD_CSI_MCLK__UART6_DCE_TX        0x1b0b1
 501                         MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX      0x1b0b1
 502                 >;
 503         };
 504
 505         pinctrl_usb_otg1: usbotg1grp {
 506                 fsl,pins = <
 507                         MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x10b0
 508                         >;
 509         };
 510
 511         pinctrl_usb_otg1_id: usbotg1idgrp {
 512                 fsl,pins = <
 513                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 514                 >;
 515         };
 516
 517         pinctrl_usdhc1: usdhc1grp {
 518                 fsl,pins = <
 519                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 520                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10071
 521                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 522                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 523                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 524                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 525                         MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B      0x03029
 526                         MX6UL_PAD_NAND_READY_B__USDHC1_DATA4    0x17059
 527                         MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5      0x17059
 528                         MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6      0x17059
 529                         MX6UL_PAD_NAND_CLE__USDHC1_DATA7        0x17059
 530                 >;
 531         };
 532
 533         pinctrl_usdhc2: usdhc2grp {
 534                 fsl,pins = <
 535                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
 536                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10059
 537                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
 538                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
 539                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
 540                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
 541                 >;
 542         };
 543
 544         pinctrl_wdog: wdoggrp {
 545                 fsl,pins = <
 546                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 547                 >;
 548         };
 549 };