arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         aliases {
  18                 ethernet0 = &fec1;
  19                 ethernet1 = &fec2;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 sai1 = &sai1;
  40                 sai2 = &sai2;
  41                 sai3 = &sai3;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu0: cpu@0 {
  55                         compatible = "arm,cortex-a7";
  56                         device_type = "cpu";
  57                         reg = <0>;
  58                         clock-latency = <61036>; /* two CLK32 periods */
  59                         operating-points = <
  60                                 /* kHz  uV */
  61                                 528000  1175000
  62                                 396000  1025000
  63                                 198000  950000
  64                         >;
  65                         fsl,soc-operating-points = <
  66                                 /* KHz  uV */
  67                                 528000  1175000
  68                                 396000  1175000
  69                                 198000  1175000
  70                         >;
  71                         clocks = <&clks IMX6UL_CLK_ARM>,
  72                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  73                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  74                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  75                                  <&clks IMX6UL_CLK_STEP>,
  76                                  <&clks IMX6UL_CLK_PLL1_SW>,
  77                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  78                                  <&clks IMX6UL_PLL1_BYPASS>,
  79                                  <&clks IMX6UL_CLK_PLL1>,
  80                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  81                                  <&clks IMX6UL_CLK_OSC>;
  82                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  83                                       "secondary_sel", "step", "pll1_sw",
  84                                       "pll1_sys", "pll1_bypass", "pll1",
  85                                       "pll1_bypass_src", "osc";
  86                         arm-supply = <&reg_arm>;
  87                         soc-supply = <&reg_soc>;
  88                 };
  89         };
  90
  91         intc: interrupt-controller@00a01000 {
  92                 compatible = "arm,cortex-a7-gic";
  93                 #interrupt-cells = <3>;
  94                 interrupt-controller;
  95                 reg = <0x00a01000 0x1000>,
  96                       <0x00a02000 0x1000>,
  97                       <0x00a04000 0x2000>,
  98                       <0x00a06000 0x2000>;
  99         };
 100
 101         ckil: clock-cli {
 102                 compatible = "fixed-clock";
 103                 #clock-cells = <0>;
 104                 clock-frequency = <32768>;
 105                 clock-output-names = "ckil";
 106         };
 107
 108         osc: clock-osc {
 109                 compatible = "fixed-clock";
 110                 #clock-cells = <0>;
 111                 clock-frequency = <24000000>;
 112                 clock-output-names = "osc";
 113         };
 114
 115         ipp_di0: clock-di0 {
 116                 compatible = "fixed-clock";
 117                 #clock-cells = <0>;
 118                 clock-frequency = <0>;
 119                 clock-output-names = "ipp_di0";
 120         };
 121
 122         ipp_di1: clock-di1 {
 123                 compatible = "fixed-clock";
 124                 #clock-cells = <0>;
 125                 clock-frequency = <0>;
 126                 clock-output-names = "ipp_di1";
 127         };
 128
 129         soc {
 130                 #address-cells = <1>;
 131                 #size-cells = <1>;
 132                 compatible = "simple-bus";
 133                 interrupt-parent = <&gpc>;
 134                 ranges;
 135
 136                 pmu {
 137                         compatible = "arm,cortex-a7-pmu";
 138                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 139                         status = "disabled";
 140                 };
 141
 142                 ocram: sram@00900000 {
 143                         compatible = "mmio-sram";
 144                         reg = <0x00900000 0x20000>;
 145                 };
 146
 147                 dma_apbh: dma-apbh@01804000 {
 148                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 149                         reg = <0x01804000 0x2000>;
 150                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 151                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 152                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 153                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 154                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 155                         #dma-cells = <1>;
 156                         dma-channels = <4>;
 157                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 158                 };
 159
 160                 gpmi: gpmi-nand@01806000         {
 161                         compatible = "fsl,imx6q-gpmi-nand";
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 165                         reg-names = "gpmi-nand", "bch";
 166                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 167                         interrupt-names = "bch";
 168                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 169                                  <&clks IMX6UL_CLK_GPMI_APB>,
 170                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 171                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 172                                  <&clks IMX6UL_CLK_PER_BCH>;
 173                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 174                                       "gpmi_bch_apb", "per1_bch";
 175                         dmas = <&dma_apbh 0>;
 176                         dma-names = "rx-tx";
 177                         status = "disabled";
 178                 };
 179
 180                 aips1: aips-bus@02000000 {
 181                         compatible = "fsl,aips-bus", "simple-bus";
 182                         #address-cells = <1>;
 183                         #size-cells = <1>;
 184                         reg = <0x02000000 0x100000>;
 185                         ranges;
 186
 187                         spba-bus@02000000 {
 188                                 compatible = "fsl,spba-bus", "simple-bus";
 189                                 #address-cells = <1>;
 190                                 #size-cells = <1>;
 191                                 reg = <0x02000000 0x40000>;
 192                                 ranges;
 193
 194                                 ecspi1: ecspi@02008000 {
 195                                         #address-cells = <1>;
 196                                         #size-cells = <0>;
 197                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 198                                         reg = <0x02008000 0x4000>;
 199                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 200                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 201                                                  <&clks IMX6UL_CLK_ECSPI1>;
 202                                         clock-names = "ipg", "per";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 ecspi2: ecspi@0200c000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x0200c000 0x4000>;
 211                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 212                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 213                                                  <&clks IMX6UL_CLK_ECSPI2>;
 214                                         clock-names = "ipg", "per";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ecspi3: ecspi@02010000 {
 219                                         #address-cells = <1>;
 220                                         #size-cells = <0>;
 221                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 222                                         reg = <0x02010000 0x4000>;
 223                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 224                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 225                                                  <&clks IMX6UL_CLK_ECSPI3>;
 226                                         clock-names = "ipg", "per";
 227                                         status = "disabled";
 228                                 };
 229
 230                                 ecspi4: ecspi@02014000 {
 231                                         #address-cells = <1>;
 232                                         #size-cells = <0>;
 233                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 234                                         reg = <0x02014000 0x4000>;
 235                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 236                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 237                                                  <&clks IMX6UL_CLK_ECSPI4>;
 238                                         clock-names = "ipg", "per";
 239                                         status = "disabled";
 240                                 };
 241
 242                                 uart7: serial@02018000 {
 243                                         compatible = "fsl,imx6ul-uart",
 244                                                      "fsl,imx6q-uart";
 245                                         reg = <0x02018000 0x4000>;
 246                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 248                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 249                                         clock-names = "ipg", "per";
 250                                         status = "disabled";
 251                                 };
 252
 253                                 uart1: serial@02020000 {
 254                                         compatible = "fsl,imx6ul-uart",
 255                                                      "fsl,imx6q-uart";
 256                                         reg = <0x02020000 0x4000>;
 257                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 258                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 259                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 260                                         clock-names = "ipg", "per";
 261                                         status = "disabled";
 262                                 };
 263
 264                                 uart8: serial@02024000 {
 265                                         compatible = "fsl,imx6ul-uart",
 266                                                      "fsl,imx6q-uart";
 267                                         reg = <0x02024000 0x4000>;
 268                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 270                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 271                                         clock-names = "ipg", "per";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 sai1: sai@02028000 {
 276                                         #sound-dai-cells = <0>;
 277                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 278                                         reg = <0x02028000 0x4000>;
 279                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 280                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 281                                                  <&clks IMX6UL_CLK_SAI1>,
 282                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 283                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 284                                         dmas = <&sdma 35 24 0>,
 285                                                <&sdma 36 24 0>;
 286                                         dma-names = "rx", "tx";
 287                                         status = "disabled";
 288                                 };
 289
 290                                 sai2: sai@0202c000 {
 291                                         #sound-dai-cells = <0>;
 292                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 293                                         reg = <0x0202c000 0x4000>;
 294                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 295                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 296                                                  <&clks IMX6UL_CLK_SAI2>,
 297                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 298                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 299                                         dmas = <&sdma 37 24 0>,
 300                                                <&sdma 38 24 0>;
 301                                         dma-names = "rx", "tx";
 302                                         status = "disabled";
 303                                 };
 304
 305                                 sai3: sai@02030000 {
 306                                         #sound-dai-cells = <0>;
 307                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 308                                         reg = <0x02030000 0x4000>;
 309                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 310                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 311                                                  <&clks IMX6UL_CLK_SAI3>,
 312                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 313                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 314                                         dmas = <&sdma 39 24 0>,
 315                                                <&sdma 40 24 0>;
 316                                         dma-names = "rx", "tx";
 317                                         status = "disabled";
 318                                 };
 319                         };
 320
 321                         tsc: tsc@02040000 {
 322                                 compatible = "fsl,imx6ul-tsc";
 323                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 324                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 325                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 326                                 clocks = <&clks IMX6UL_CLK_IPG>,
 327                                          <&clks IMX6UL_CLK_ADC2>;
 328                                 clock-names = "tsc", "adc";
 329                                 status = "disabled";
 330                         };
 331
 332                         pwm1: pwm@02080000 {
 333                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 334                                 reg = <0x02080000 0x4000>;
 335                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 336                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 337                                          <&clks IMX6UL_CLK_PWM1>;
 338                                 clock-names = "ipg", "per";
 339                                 #pwm-cells = <2>;
 340                                 status = "disabled";
 341                         };
 342
 343                         pwm2: pwm@02084000 {
 344                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 345                                 reg = <0x02084000 0x4000>;
 346                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 348                                          <&clks IMX6UL_CLK_PWM2>;
 349                                 clock-names = "ipg", "per";
 350                                 #pwm-cells = <2>;
 351                                 status = "disabled";
 352                         };
 353
 354                         pwm3: pwm@02088000 {
 355                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 356                                 reg = <0x02088000 0x4000>;
 357                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 358                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 359                                          <&clks IMX6UL_CLK_PWM3>;
 360                                 clock-names = "ipg", "per";
 361                                 #pwm-cells = <2>;
 362                                 status = "disabled";
 363                         };
 364
 365                         pwm4: pwm@0208c000 {
 366                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 367                                 reg = <0x0208c000 0x4000>;
 368                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 369                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 370                                          <&clks IMX6UL_CLK_PWM4>;
 371                                 clock-names = "ipg", "per";
 372                                 #pwm-cells = <2>;
 373                                 status = "disabled";
 374                         };
 375
 376                         can1: flexcan@02090000 {
 377                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 378                                 reg = <0x02090000 0x4000>;
 379                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 380                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 381                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 382                                 clock-names = "ipg", "per";
 383                                 status = "disabled";
 384                         };
 385
 386                         can2: flexcan@02094000 {
 387                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 388                                 reg = <0x02094000 0x4000>;
 389                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 390                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 391                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 392                                 clock-names = "ipg", "per";
 393                                 status = "disabled";
 394                         };
 395
 396                         gpt1: gpt@02098000 {
 397                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 398                                 reg = <0x02098000 0x4000>;
 399                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 400                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 401                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 402                                 clock-names = "ipg", "per";
 403                         };
 404
 405                         gpio1: gpio@0209c000 {
 406                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 407                                 reg = <0x0209c000 0x4000>;
 408                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 409                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 410                                 gpio-controller;
 411                                 #gpio-cells = <2>;
 412                                 interrupt-controller;
 413                                 #interrupt-cells = <2>;
 414                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 415                                               <&iomuxc 16 33 16>;
 416                         };
 417
 418                         gpio2: gpio@020a0000 {
 419                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 420                                 reg = <0x020a0000 0x4000>;
 421                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 423                                 gpio-controller;
 424                                 #gpio-cells = <2>;
 425                                 interrupt-controller;
 426                                 #interrupt-cells = <2>;
 427                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 428                         };
 429
 430                         gpio3: gpio@020a4000 {
 431                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 432                                 reg = <0x020a4000 0x4000>;
 433                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 435                                 gpio-controller;
 436                                 #gpio-cells = <2>;
 437                                 interrupt-controller;
 438                                 #interrupt-cells = <2>;
 439                                 gpio-ranges = <&iomuxc 0 65 29>;
 440                         };
 441
 442                         gpio4: gpio@020a8000 {
 443                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 444                                 reg = <0x020a8000 0x4000>;
 445                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 446                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 447                                 gpio-controller;
 448                                 #gpio-cells = <2>;
 449                                 interrupt-controller;
 450                                 #interrupt-cells = <2>;
 451                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 452                         };
 453
 454                         gpio5: gpio@020ac000 {
 455                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 456                                 reg = <0x020ac000 0x4000>;
 457                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 458                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 459                                 gpio-controller;
 460                                 #gpio-cells = <2>;
 461                                 interrupt-controller;
 462                                 #interrupt-cells = <2>;
 463                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 464                         };
 465
 466                         fec2: ethernet@020b4000 {
 467                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 468                                 reg = <0x020b4000 0x4000>;
 469                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 470                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 471                                 clocks = <&clks IMX6UL_CLK_ENET>,
 472                                          <&clks IMX6UL_CLK_ENET_AHB>,
 473                                          <&clks IMX6UL_CLK_ENET_PTP>,
 474                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 475                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 476                                 clock-names = "ipg", "ahb", "ptp",
 477                                               "enet_clk_ref", "enet_out";
 478                                 fsl,num-tx-queues=<1>;
 479                                 fsl,num-rx-queues=<1>;
 480                                 status = "disabled";
 481                         };
 482
 483                         kpp: kpp@020b8000 {
 484                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 485                                 reg = <0x020b8000 0x4000>;
 486                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 487                                 clocks = <&clks IMX6UL_CLK_KPP>;
 488                                 status = "disabled";
 489                         };
 490
 491                         wdog1: wdog@020bc000 {
 492                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 493                                 reg = <0x020bc000 0x4000>;
 494                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 496                         };
 497
 498                         wdog2: wdog@020c0000 {
 499                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 500                                 reg = <0x020c0000 0x4000>;
 501                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 502                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 503                                 status = "disabled";
 504                         };
 505
 506                         clks: ccm@020c4000 {
 507                                 compatible = "fsl,imx6ul-ccm";
 508                                 reg = <0x020c4000 0x4000>;
 509                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 510                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 511                                 #clock-cells = <1>;
 512                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 513                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 514                         };
 515
 516                         anatop: anatop@020c8000 {
 517                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 518                                              "syscon", "simple-bus";
 519                                 reg = <0x020c8000 0x1000>;
 520                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 521                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 522                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 523
 524                                 reg_3p0: regulator-3p0 {
 525                                         compatible = "fsl,anatop-regulator";
 526                                         regulator-name = "vdd3p0";
 527                                         regulator-min-microvolt = <2625000>;
 528                                         regulator-max-microvolt = <3400000>;
 529                                         anatop-reg-offset = <0x120>;
 530                                         anatop-vol-bit-shift = <8>;
 531                                         anatop-vol-bit-width = <5>;
 532                                         anatop-min-bit-val = <0>;
 533                                         anatop-min-voltage = <2625000>;
 534                                         anatop-max-voltage = <3400000>;
 535                                         anatop-enable-bit = <0>;
 536                                 };
 537
 538                                 reg_arm: regulator-vddcore {
 539                                         compatible = "fsl,anatop-regulator";
 540                                         regulator-name = "cpu";
 541                                         regulator-min-microvolt = <725000>;
 542                                         regulator-max-microvolt = <1450000>;
 543                                         regulator-always-on;
 544                                         anatop-reg-offset = <0x140>;
 545                                         anatop-vol-bit-shift = <0>;
 546                                         anatop-vol-bit-width = <5>;
 547                                         anatop-delay-reg-offset = <0x170>;
 548                                         anatop-delay-bit-shift = <24>;
 549                                         anatop-delay-bit-width = <2>;
 550                                         anatop-min-bit-val = <1>;
 551                                         anatop-min-voltage = <725000>;
 552                                         anatop-max-voltage = <1450000>;
 553                                 };
 554
 555                                 reg_soc: regulator-vddsoc {
 556                                         compatible = "fsl,anatop-regulator";
 557                                         regulator-name = "vddsoc";
 558                                         regulator-min-microvolt = <725000>;
 559                                         regulator-max-microvolt = <1450000>;
 560                                         regulator-always-on;
 561                                         anatop-reg-offset = <0x140>;
 562                                         anatop-vol-bit-shift = <18>;
 563                                         anatop-vol-bit-width = <5>;
 564                                         anatop-delay-reg-offset = <0x170>;
 565                                         anatop-delay-bit-shift = <28>;
 566                                         anatop-delay-bit-width = <2>;
 567                                         anatop-min-bit-val = <1>;
 568                                         anatop-min-voltage = <725000>;
 569                                         anatop-max-voltage = <1450000>;
 570                                 };
 571                         };
 572
 573                         usbphy1: usbphy@020c9000 {
 574                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 575                                 reg = <0x020c9000 0x1000>;
 576                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 577                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 578                                 phy-3p0-supply = <&reg_3p0>;
 579                                 fsl,anatop = <&anatop>;
 580                         };
 581
 582                         usbphy2: usbphy@020ca000 {
 583                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 584                                 reg = <0x020ca000 0x1000>;
 585                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 586                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 587                                 phy-3p0-supply = <&reg_3p0>;
 588                                 fsl,anatop = <&anatop>;
 589                         };
 590
 591                         snvs: snvs@020cc000 {
 592                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 593                                 reg = <0x020cc000 0x4000>;
 594
 595                                 snvs_rtc: snvs-rtc-lp {
 596                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 597                                         regmap = <&snvs>;
 598                                         offset = <0x34>;
 599                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 600                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 601                                 };
 602
 603                                 snvs_poweroff: snvs-poweroff {
 604                                         compatible = "syscon-poweroff";
 605                                         regmap = <&snvs>;
 606                                         offset = <0x38>;
 607                                         mask = <0x60>;
 608                                         status = "disabled";
 609                                 };
 610
 611                                 snvs_pwrkey: snvs-powerkey {
 612                                         compatible = "fsl,sec-v4.0-pwrkey";
 613                                         regmap = <&snvs>;
 614                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 615                                         linux,keycode = <KEY_POWER>;
 616                                         wakeup-source;
 617                                 };
 618                         };
 619
 620                         epit1: epit@020d0000 {
 621                                 reg = <0x020d0000 0x4000>;
 622                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 623                         };
 624
 625                         epit2: epit@020d4000 {
 626                                 reg = <0x020d4000 0x4000>;
 627                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 628                         };
 629
 630                         src: src@020d8000 {
 631                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 632                                 reg = <0x020d8000 0x4000>;
 633                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 634                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 635                                 #reset-cells = <1>;
 636                         };
 637
 638                         gpc: gpc@020dc000 {
 639                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 640                                 reg = <0x020dc000 0x4000>;
 641                                 interrupt-controller;
 642                                 #interrupt-cells = <3>;
 643                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 644                                 interrupt-parent = <&intc>;
 645                         };
 646
 647                         iomuxc: iomuxc@020e0000 {
 648                                 compatible = "fsl,imx6ul-iomuxc";
 649                                 reg = <0x020e0000 0x4000>;
 650                         };
 651
 652                         gpr: iomuxc-gpr@020e4000 {
 653                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 654                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 655                                 reg = <0x020e4000 0x4000>;
 656                         };
 657
 658                         gpt2: gpt@020e8000 {
 659                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 660                                 reg = <0x020e8000 0x4000>;
 661                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 662                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 663                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 664                                 clock-names = "ipg", "per";
 665                         };
 666
 667                         sdma: sdma@020ec000 {
 668                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 669                                              "fsl,imx35-sdma";
 670                                 reg = <0x020ec000 0x4000>;
 671                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 672                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 673                                          <&clks IMX6UL_CLK_SDMA>;
 674                                 clock-names = "ipg", "ahb";
 675                                 #dma-cells = <3>;
 676                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 677                         };
 678
 679                         pwm5: pwm@020f0000 {
 680                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 681                                 reg = <0x020f0000 0x4000>;
 682                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 683                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 684                                          <&clks IMX6UL_CLK_PWM5>;
 685                                 clock-names = "ipg", "per";
 686                                 #pwm-cells = <2>;
 687                                 status = "disabled";
 688                         };
 689
 690                         pwm6: pwm@020f4000 {
 691                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 692                                 reg = <0x020f4000 0x4000>;
 693                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 695                                          <&clks IMX6UL_CLK_PWM6>;
 696                                 clock-names = "ipg", "per";
 697                                 #pwm-cells = <2>;
 698                                 status = "disabled";
 699                         };
 700
 701                         pwm7: pwm@020f8000 {
 702                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 703                                 reg = <0x020f8000 0x4000>;
 704                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 706                                          <&clks IMX6UL_CLK_PWM7>;
 707                                 clock-names = "ipg", "per";
 708                                 #pwm-cells = <2>;
 709                                 status = "disabled";
 710                         };
 711
 712                         pwm8: pwm@020fc000 {
 713                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 714                                 reg = <0x020fc000 0x4000>;
 715                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 716                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 717                                          <&clks IMX6UL_CLK_PWM8>;
 718                                 clock-names = "ipg", "per";
 719                                 #pwm-cells = <2>;
 720                                 status = "disabled";
 721                         };
 722                 };
 723
 724                 aips2: aips-bus@02100000 {
 725                         compatible = "fsl,aips-bus", "simple-bus";
 726                         #address-cells = <1>;
 727                         #size-cells = <1>;
 728                         reg = <0x02100000 0x100000>;
 729                         ranges;
 730
 731                         usbotg1: usb@02184000 {
 732                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 733                                 reg = <0x02184000 0x200>;
 734                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 736                                 fsl,usbphy = <&usbphy1>;
 737                                 fsl,usbmisc = <&usbmisc 0>;
 738                                 fsl,anatop = <&anatop>;
 739                                 ahb-burst-config = <0x0>;
 740                                 tx-burst-size-dword = <0x10>;
 741                                 rx-burst-size-dword = <0x10>;
 742                                 status = "disabled";
 743                         };
 744
 745                         usbotg2: usb@02184200 {
 746                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 747                                 reg = <0x02184200 0x200>;
 748                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 749                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 750                                 fsl,usbphy = <&usbphy2>;
 751                                 fsl,usbmisc = <&usbmisc 1>;
 752                                 ahb-burst-config = <0x0>;
 753                                 tx-burst-size-dword = <0x10>;
 754                                 rx-burst-size-dword = <0x10>;
 755                                 status = "disabled";
 756                         };
 757
 758                         usbmisc: usbmisc@02184800 {
 759                                 #index-cells = <1>;
 760                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 761                                 reg = <0x02184800 0x200>;
 762                         };
 763
 764                         fec1: ethernet@02188000 {
 765                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 766                                 reg = <0x02188000 0x4000>;
 767                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 768                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 769                                 clocks = <&clks IMX6UL_CLK_ENET>,
 770                                          <&clks IMX6UL_CLK_ENET_AHB>,
 771                                          <&clks IMX6UL_CLK_ENET_PTP>,
 772                                          <&clks IMX6UL_CLK_ENET_REF>,
 773                                          <&clks IMX6UL_CLK_ENET_REF>;
 774                                 clock-names = "ipg", "ahb", "ptp",
 775                                               "enet_clk_ref", "enet_out";
 776                                 fsl,num-tx-queues=<1>;
 777                                 fsl,num-rx-queues=<1>;
 778                                 status = "disabled";
 779                         };
 780
 781                         usdhc1: usdhc@02190000 {
 782                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 783                                 reg = <0x02190000 0x4000>;
 784                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 785                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 786                                          <&clks IMX6UL_CLK_USDHC1>,
 787                                          <&clks IMX6UL_CLK_USDHC1>;
 788                                 clock-names = "ipg", "ahb", "per";
 789                                 bus-width = <4>;
 790                                 status = "disabled";
 791                         };
 792
 793                         usdhc2: usdhc@02194000 {
 794                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 795                                 reg = <0x02194000 0x4000>;
 796                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 797                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 798                                          <&clks IMX6UL_CLK_USDHC2>,
 799                                          <&clks IMX6UL_CLK_USDHC2>;
 800                                 clock-names = "ipg", "ahb", "per";
 801                                 bus-width = <4>;
 802                                 status = "disabled";
 803                         };
 804
 805                         adc1: adc@02198000 {
 806                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 807                                 reg = <0x02198000 0x4000>;
 808                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 809                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 810                                 num-channels = <2>;
 811                                 clock-names = "adc";
 812                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 813                                                          <20000000>;
 814                                 status = "disabled";
 815                         };
 816
 817                         i2c1: i2c@021a0000 {
 818                                 #address-cells = <1>;
 819                                 #size-cells = <0>;
 820                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 821                                 reg = <0x021a0000 0x4000>;
 822                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 823                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 824                                 status = "disabled";
 825                         };
 826
 827                         i2c2: i2c@021a4000 {
 828                                 #address-cells = <1>;
 829                                 #size-cells = <0>;
 830                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 831                                 reg = <0x021a4000 0x4000>;
 832                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 834                                 status = "disabled";
 835                         };
 836
 837                         i2c3: i2c@021a8000 {
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 841                                 reg = <0x021a8000 0x4000>;
 842                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 843                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 844                                 status = "disabled";
 845                         };
 846
 847                         mmdc: mmdc@021b0000 {
 848                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 849                                 reg = <0x021b0000 0x4000>;
 850                         };
 851
 852                         lcdif: lcdif@021c8000 {
 853                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 854                                 reg = <0x021c8000 0x4000>;
 855                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 856                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 857                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 858                                          <&clks IMX6UL_CLK_DUMMY>;
 859                                 clock-names = "pix", "axi", "disp_axi";
 860                                 status = "disabled";
 861                         };
 862
 863                         qspi: qspi@021e0000 {
 864                                 #address-cells = <1>;
 865                                 #size-cells = <0>;
 866                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 867                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 868                                 reg-names = "QuadSPI", "QuadSPI-memory";
 869                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 870                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 871                                          <&clks IMX6UL_CLK_QSPI>;
 872                                 clock-names = "qspi_en", "qspi";
 873                                 status = "disabled";
 874                         };
 875
 876                         uart2: serial@021e8000 {
 877                                 compatible = "fsl,imx6ul-uart",
 878                                              "fsl,imx6q-uart";
 879                                 reg = <0x021e8000 0x4000>;
 880                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 881                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 882                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 883                                 clock-names = "ipg", "per";
 884                                 status = "disabled";
 885                         };
 886
 887                         uart3: serial@021ec000 {
 888                                 compatible = "fsl,imx6ul-uart",
 889                                              "fsl,imx6q-uart";
 890                                 reg = <0x021ec000 0x4000>;
 891                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 892                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 893                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 894                                 clock-names = "ipg", "per";
 895                                 status = "disabled";
 896                         };
 897
 898                         uart4: serial@021f0000 {
 899                                 compatible = "fsl,imx6ul-uart",
 900                                              "fsl,imx6q-uart";
 901                                 reg = <0x021f0000 0x4000>;
 902                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 903                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 904                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 905                                 clock-names = "ipg", "per";
 906                                 status = "disabled";
 907                         };
 908
 909                         uart5: serial@021f4000 {
 910                                 compatible = "fsl,imx6ul-uart",
 911                                              "fsl,imx6q-uart";
 912                                 reg = <0x021f4000 0x4000>;
 913                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 915                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 916                                 clock-names = "ipg", "per";
 917                                 status = "disabled";
 918                         };
 919
 920                         i2c4: i2c@021f8000 {
 921                                 #address-cells = <1>;
 922                                 #size-cells = <0>;
 923                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 924                                 reg = <0x021f8000 0x4000>;
 925                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 926                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 927                                 status = "disabled";
 928                         };
 929
 930                         uart6: serial@021fc000 {
 931                                 compatible = "fsl,imx6ul-uart",
 932                                              "fsl,imx6q-uart";
 933                                 reg = <0x021fc000 0x4000>;
 934                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 936                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 937                                 clock-names = "ipg", "per";
 938                                 status = "disabled";
 939                         };
 940                 };
 941         };
 942 };