arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 / {
  14         compatible = "ti,omap4430", "ti,omap4";
  15         interrupt-parent = <&wakeupgen>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59                 interrupt-parent = <&gic>;
  60         };
  61
  62         L2: l2-cache-controller@48242000 {
  63                 compatible = "arm,pl310-cache";
  64                 reg = <0x48242000 0x1000>;
  65                 cache-unified;
  66                 cache-level = <2>;
  67         };
  68
  69         local-timer@48240600 {
  70                 compatible = "arm,cortex-a9-twd-timer";
  71                 clocks = <&mpu_periphclk>;
  72                 reg = <0x48240600 0x20>;
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  74                 interrupt-parent = <&gic>;
  75         };
  76
  77         wakeupgen: interrupt-controller@48281000 {
  78                 compatible = "ti,omap4-wugen-mpu";
  79                 interrupt-controller;
  80                 #interrupt-cells = <3>;
  81                 reg = <0x48281000 0x1000>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         /*
  86          * The soc node represents the soc top level view. It is used for IPs
  87          * that are not memory mapped in the MPU view or for the MPU itself.
  88          */
  89         soc {
  90                 compatible = "ti,omap-infra";
  91                 mpu {
  92                         compatible = "ti,omap4-mpu";
  93                         ti,hwmods = "mpu";
  94                         sram = <&ocmcram>;
  95                 };
  96
  97                 dsp {
  98                         compatible = "ti,omap3-c64";
  99                         ti,hwmods = "dsp";
 100                 };
 101
 102                 iva {
 103                         compatible = "ti,ivahd";
 104                         ti,hwmods = "iva";
 105                 };
 106         };
 107
 108         /*
 109          * XXX: Use a flat representation of the OMAP4 interconnect.
 110          * The real OMAP interconnect network is quite complex.
 111          * Since it will not bring real advantage to represent that in DT for
 112          * the moment, just use a fake OCP bus entry to represent the whole bus
 113          * hierarchy.
 114          */
 115         ocp {
 116                 compatible = "ti,omap4-l3-noc", "simple-bus";
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges;
 120                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 121                 reg = <0x44000000 0x1000>,
 122                       <0x44800000 0x2000>,
 123                       <0x45000000 0x1000>;
 124                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 126
 127                 l4_cfg: l4@4a000000 {
 128                         compatible = "ti,omap4-l4-cfg", "simple-bus";
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131                         ranges = <0 0x4a000000 0x1000000>;
 132
 133                         cm1: cm1@4000 {
 134                                 compatible = "ti,omap4-cm1";
 135                                 reg = <0x4000 0x2000>;
 136
 137                                 cm1_clocks: clocks {
 138                                         #address-cells = <1>;
 139                                         #size-cells = <0>;
 140                                 };
 141
 142                                 cm1_clockdomains: clockdomains {
 143                                 };
 144                         };
 145
 146                         cm2: cm2@8000 {
 147                                 compatible = "ti,omap4-cm2";
 148                                 reg = <0x8000 0x3000>;
 149
 150                                 cm2_clocks: clocks {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                 };
 154
 155                                 cm2_clockdomains: clockdomains {
 156                                 };
 157                         };
 158
 159                         omap4_scm_core: scm@2000 {
 160                                 compatible = "ti,omap4-scm-core", "simple-bus";
 161                                 reg = <0x2000 0x1000>;
 162                                 #address-cells = <1>;
 163                                 #size-cells = <1>;
 164                                 ranges = <0 0x2000 0x1000>;
 165
 166                                 scm_conf: scm_conf@0 {
 167                                         compatible = "syscon";
 168                                         reg = <0x0 0x800>;
 169                                         #address-cells = <1>;
 170                                         #size-cells = <1>;
 171                                 };
 172                         };
 173
 174                         omap4_padconf_core: scm@100000 {
 175                                 compatible = "ti,omap4-scm-padconf-core",
 176                                              "simple-bus";
 177                                 #address-cells = <1>;
 178                                 #size-cells = <1>;
 179                                 ranges = <0 0x100000 0x1000>;
 180
 181                                 omap4_pmx_core: pinmux@40 {
 182                                         compatible = "ti,omap4-padconf",
 183                                                      "pinctrl-single";
 184                                         reg = <0x40 0x0196>;
 185                                         #address-cells = <1>;
 186                                         #size-cells = <0>;
 187                                         #interrupt-cells = <1>;
 188                                         interrupt-controller;
 189                                         pinctrl-single,register-width = <16>;
 190                                         pinctrl-single,function-mask = <0x7fff>;
 191                                 };
 192
 193                                 omap4_padconf_global: omap4_padconf_global@5a0 {
 194                                         compatible = "syscon",
 195                                                      "simple-bus";
 196                                         reg = <0x5a0 0x170>;
 197                                         #address-cells = <1>;
 198                                         #size-cells = <1>;
 199                                         ranges = <0 0x5a0 0x170>;
 200
 201                                         pbias_regulator: pbias_regulator@60 {
 202                                                 compatible = "ti,pbias-omap4", "ti,pbias-omap";
 203                                                 reg = <0x60 0x4>;
 204                                                 syscon = <&omap4_padconf_global>;
 205                                                 pbias_mmc_reg: pbias_mmc_omap4 {
 206                                                         regulator-name = "pbias_mmc_omap4";
 207                                                         regulator-min-microvolt = <1800000>;
 208                                                         regulator-max-microvolt = <3000000>;
 209                                                 };
 210                                         };
 211                                 };
 212                         };
 213
 214                         l4_wkup: l4@300000 {
 215                                 compatible = "ti,omap4-l4-wkup", "simple-bus";
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 ranges = <0 0x300000 0x40000>;
 219
 220                                 counter32k: counter@4000 {
 221                                         compatible = "ti,omap-counter32k";
 222                                         reg = <0x4000 0x20>;
 223                                         ti,hwmods = "counter_32k";
 224                                 };
 225
 226                                 prm: prm@6000 {
 227                                         compatible = "ti,omap4-prm";
 228                                         reg = <0x6000 0x3000>;
 229                                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 230
 231                                         prm_clocks: clocks {
 232                                                 #address-cells = <1>;
 233                                                 #size-cells = <0>;
 234                                         };
 235
 236                                         prm_clockdomains: clockdomains {
 237                                         };
 238                                 };
 239
 240                                 scrm: scrm@a000 {
 241                                         compatible = "ti,omap4-scrm";
 242                                         reg = <0xa000 0x2000>;
 243
 244                                         scrm_clocks: clocks {
 245                                                 #address-cells = <1>;
 246                                                 #size-cells = <0>;
 247                                         };
 248
 249                                         scrm_clockdomains: clockdomains {
 250                                         };
 251                                 };
 252
 253                                 omap4_pmx_wkup: pinmux@1e040 {
 254                                         compatible = "ti,omap4-padconf",
 255                                                      "pinctrl-single";
 256                                         reg = <0x1e040 0x0038>;
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                         #interrupt-cells = <1>;
 260                                         interrupt-controller;
 261                                         pinctrl-single,register-width = <16>;
 262                                         pinctrl-single,function-mask = <0x7fff>;
 263                                 };
 264                         };
 265                 };
 266
 267                 ocmcram: ocmcram@40304000 {
 268                         compatible = "mmio-sram";
 269                         reg = <0x40304000 0xa000>; /* 40k */
 270                 };
 271
 272                 sdma: dma-controller@4a056000 {
 273                         compatible = "ti,omap4430-sdma";
 274                         reg = <0x4a056000 0x1000>;
 275                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 279                         #dma-cells = <1>;
 280                         dma-channels = <32>;
 281                         dma-requests = <127>;
 282                 };
 283
 284                 gpio1: gpio@4a310000 {
 285                         compatible = "ti,omap4-gpio";
 286                         reg = <0x4a310000 0x200>;
 287                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 288                         ti,hwmods = "gpio1";
 289                         ti,gpio-always-on;
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpio2: gpio@48055000 {
 297                         compatible = "ti,omap4-gpio";
 298                         reg = <0x48055000 0x200>;
 299                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 300                         ti,hwmods = "gpio2";
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306
 307                 gpio3: gpio@48057000 {
 308                         compatible = "ti,omap4-gpio";
 309                         reg = <0x48057000 0x200>;
 310                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 311                         ti,hwmods = "gpio3";
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                         interrupt-controller;
 315                         #interrupt-cells = <2>;
 316                 };
 317
 318                 gpio4: gpio@48059000 {
 319                         compatible = "ti,omap4-gpio";
 320                         reg = <0x48059000 0x200>;
 321                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 322                         ti,hwmods = "gpio4";
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                 };
 328
 329                 gpio5: gpio@4805b000 {
 330                         compatible = "ti,omap4-gpio";
 331                         reg = <0x4805b000 0x200>;
 332                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 333                         ti,hwmods = "gpio5";
 334                         gpio-controller;
 335                         #gpio-cells = <2>;
 336                         interrupt-controller;
 337                         #interrupt-cells = <2>;
 338                 };
 339
 340                 gpio6: gpio@4805d000 {
 341                         compatible = "ti,omap4-gpio";
 342                         reg = <0x4805d000 0x200>;
 343                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 344                         ti,hwmods = "gpio6";
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349                 };
 350
 351                 elm: elm@48078000 {
 352                         compatible = "ti,am3352-elm";
 353                         reg = <0x48078000 0x2000>;
 354                         interrupts = <4>;
 355                         ti,hwmods = "elm";
 356                         status = "disabled";
 357                 };
 358
 359                 gpmc: gpmc@50000000 {
 360                         compatible = "ti,omap4430-gpmc";
 361                         reg = <0x50000000 0x1000>;
 362                         #address-cells = <2>;
 363                         #size-cells = <1>;
 364                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 365                         dmas = <&sdma 4>;
 366                         dma-names = "rxtx";
 367                         gpmc,num-cs = <8>;
 368                         gpmc,num-waitpins = <4>;
 369                         ti,hwmods = "gpmc";
 370                         ti,no-idle-on-init;
 371                         clocks = <&l3_div_ck>;
 372                         clock-names = "fck";
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                         gpio-controller;
 376                         #gpio-cells = <2>;
 377                 };
 378
 379                 uart1: serial@4806a000 {
 380                         compatible = "ti,omap4-uart";
 381                         reg = <0x4806a000 0x100>;
 382                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 383                         ti,hwmods = "uart1";
 384                         clock-frequency = <48000000>;
 385                 };
 386
 387                 uart2: serial@4806c000 {
 388                         compatible = "ti,omap4-uart";
 389                         reg = <0x4806c000 0x100>;
 390                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 391                         ti,hwmods = "uart2";
 392                         clock-frequency = <48000000>;
 393                 };
 394
 395                 uart3: serial@48020000 {
 396                         compatible = "ti,omap4-uart";
 397                         reg = <0x48020000 0x100>;
 398                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 399                         ti,hwmods = "uart3";
 400                         clock-frequency = <48000000>;
 401                 };
 402
 403                 uart4: serial@4806e000 {
 404                         compatible = "ti,omap4-uart";
 405                         reg = <0x4806e000 0x100>;
 406                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 407                         ti,hwmods = "uart4";
 408                         clock-frequency = <48000000>;
 409                 };
 410
 411                 hwspinlock: spinlock@4a0f6000 {
 412                         compatible = "ti,omap4-hwspinlock";
 413                         reg = <0x4a0f6000 0x1000>;
 414                         ti,hwmods = "spinlock";
 415                         #hwlock-cells = <1>;
 416                 };
 417
 418                 i2c1: i2c@48070000 {
 419                         compatible = "ti,omap4-i2c";
 420                         reg = <0x48070000 0x100>;
 421                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         ti,hwmods = "i2c1";
 425                 };
 426
 427                 i2c2: i2c@48072000 {
 428                         compatible = "ti,omap4-i2c";
 429                         reg = <0x48072000 0x100>;
 430                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         ti,hwmods = "i2c2";
 434                 };
 435
 436                 i2c3: i2c@48060000 {
 437                         compatible = "ti,omap4-i2c";
 438                         reg = <0x48060000 0x100>;
 439                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         ti,hwmods = "i2c3";
 443                 };
 444
 445                 i2c4: i2c@48350000 {
 446                         compatible = "ti,omap4-i2c";
 447                         reg = <0x48350000 0x100>;
 448                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         ti,hwmods = "i2c4";
 452                 };
 453
 454                 mcspi1: spi@48098000 {
 455                         compatible = "ti,omap4-mcspi";
 456                         reg = <0x48098000 0x200>;
 457                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         ti,hwmods = "mcspi1";
 461                         ti,spi-num-cs = <4>;
 462                         dmas = <&sdma 35>,
 463                                <&sdma 36>,
 464                                <&sdma 37>,
 465                                <&sdma 38>,
 466                                <&sdma 39>,
 467                                <&sdma 40>,
 468                                <&sdma 41>,
 469                                <&sdma 42>;
 470                         dma-names = "tx0", "rx0", "tx1", "rx1",
 471                                     "tx2", "rx2", "tx3", "rx3";
 472                 };
 473
 474                 mcspi2: spi@4809a000 {
 475                         compatible = "ti,omap4-mcspi";
 476                         reg = <0x4809a000 0x200>;
 477                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         ti,hwmods = "mcspi2";
 481                         ti,spi-num-cs = <2>;
 482                         dmas = <&sdma 43>,
 483                                <&sdma 44>,
 484                                <&sdma 45>,
 485                                <&sdma 46>;
 486                         dma-names = "tx0", "rx0", "tx1", "rx1";
 487                 };
 488
 489                 mcspi3: spi@480b8000 {
 490                         compatible = "ti,omap4-mcspi";
 491                         reg = <0x480b8000 0x200>;
 492                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 493                         #address-cells = <1>;
 494                         #size-cells = <0>;
 495                         ti,hwmods = "mcspi3";
 496                         ti,spi-num-cs = <2>;
 497                         dmas = <&sdma 15>, <&sdma 16>;
 498                         dma-names = "tx0", "rx0";
 499                 };
 500
 501                 mcspi4: spi@480ba000 {
 502                         compatible = "ti,omap4-mcspi";
 503                         reg = <0x480ba000 0x200>;
 504                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         ti,hwmods = "mcspi4";
 508                         ti,spi-num-cs = <1>;
 509                         dmas = <&sdma 70>, <&sdma 71>;
 510                         dma-names = "tx0", "rx0";
 511                 };
 512
 513                 mmc1: mmc@4809c000 {
 514                         compatible = "ti,omap4-hsmmc";
 515                         reg = <0x4809c000 0x400>;
 516                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 517                         ti,hwmods = "mmc1";
 518                         ti,dual-volt;
 519                         ti,needs-special-reset;
 520                         dmas = <&sdma 61>, <&sdma 62>;
 521                         dma-names = "tx", "rx";
 522                         pbias-supply = <&pbias_mmc_reg>;
 523                 };
 524
 525                 mmc2: mmc@480b4000 {
 526                         compatible = "ti,omap4-hsmmc";
 527                         reg = <0x480b4000 0x400>;
 528                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 529                         ti,hwmods = "mmc2";
 530                         ti,needs-special-reset;
 531                         dmas = <&sdma 47>, <&sdma 48>;
 532                         dma-names = "tx", "rx";
 533                 };
 534
 535                 mmc3: mmc@480ad000 {
 536                         compatible = "ti,omap4-hsmmc";
 537                         reg = <0x480ad000 0x400>;
 538                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "mmc3";
 540                         ti,needs-special-reset;
 541                         dmas = <&sdma 77>, <&sdma 78>;
 542                         dma-names = "tx", "rx";
 543                 };
 544
 545                 mmc4: mmc@480d1000 {
 546                         compatible = "ti,omap4-hsmmc";
 547                         reg = <0x480d1000 0x400>;
 548                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 549                         ti,hwmods = "mmc4";
 550                         ti,needs-special-reset;
 551                         dmas = <&sdma 57>, <&sdma 58>;
 552                         dma-names = "tx", "rx";
 553                 };
 554
 555                 mmc5: mmc@480d5000 {
 556                         compatible = "ti,omap4-hsmmc";
 557                         reg = <0x480d5000 0x400>;
 558                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 559                         ti,hwmods = "mmc5";
 560                         ti,needs-special-reset;
 561                         dmas = <&sdma 59>, <&sdma 60>;
 562                         dma-names = "tx", "rx";
 563                 };
 564
 565                 mmu_dsp: mmu@4a066000 {
 566                         compatible = "ti,omap4-iommu";
 567                         reg = <0x4a066000 0x100>;
 568                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "mmu_dsp";
 570                         #iommu-cells = <0>;
 571                 };
 572
 573                 mmu_ipu: mmu@55082000 {
 574                         compatible = "ti,omap4-iommu";
 575                         reg = <0x55082000 0x100>;
 576                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 577                         ti,hwmods = "mmu_ipu";
 578                         #iommu-cells = <0>;
 579                         ti,iommu-bus-err-back;
 580                 };
 581
 582                 wdt2: wdt@4a314000 {
 583                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 584                         reg = <0x4a314000 0x80>;
 585                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 586                         ti,hwmods = "wd_timer2";
 587                 };
 588
 589                 mcpdm: mcpdm@40132000 {
 590                         compatible = "ti,omap4-mcpdm";
 591                         reg = <0x40132000 0x7f>, /* MPU private access */
 592                               <0x49032000 0x7f>; /* L3 Interconnect */
 593                         reg-names = "mpu", "dma";
 594                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "mcpdm";
 596                         dmas = <&sdma 65>,
 597                                <&sdma 66>;
 598                         dma-names = "up_link", "dn_link";
 599                         status = "disabled";
 600                 };
 601
 602                 dmic: dmic@4012e000 {
 603                         compatible = "ti,omap4-dmic";
 604                         reg = <0x4012e000 0x7f>, /* MPU private access */
 605                               <0x4902e000 0x7f>; /* L3 Interconnect */
 606                         reg-names = "mpu", "dma";
 607                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 608                         ti,hwmods = "dmic";
 609                         dmas = <&sdma 67>;
 610                         dma-names = "up_link";
 611                         status = "disabled";
 612                 };
 613
 614                 mcbsp1: mcbsp@40122000 {
 615                         compatible = "ti,omap4-mcbsp";
 616                         reg = <0x40122000 0xff>, /* MPU private access */
 617                               <0x49022000 0xff>; /* L3 Interconnect */
 618                         reg-names = "mpu", "dma";
 619                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 620                         interrupt-names = "common";
 621                         ti,buffer-size = <128>;
 622                         ti,hwmods = "mcbsp1";
 623                         dmas = <&sdma 33>,
 624                                <&sdma 34>;
 625                         dma-names = "tx", "rx";
 626                         status = "disabled";
 627                 };
 628
 629                 mcbsp2: mcbsp@40124000 {
 630                         compatible = "ti,omap4-mcbsp";
 631                         reg = <0x40124000 0xff>, /* MPU private access */
 632                               <0x49024000 0xff>; /* L3 Interconnect */
 633                         reg-names = "mpu", "dma";
 634                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 635                         interrupt-names = "common";
 636                         ti,buffer-size = <128>;
 637                         ti,hwmods = "mcbsp2";
 638                         dmas = <&sdma 17>,
 639                                <&sdma 18>;
 640                         dma-names = "tx", "rx";
 641                         status = "disabled";
 642                 };
 643
 644                 mcbsp3: mcbsp@40126000 {
 645                         compatible = "ti,omap4-mcbsp";
 646                         reg = <0x40126000 0xff>, /* MPU private access */
 647                               <0x49026000 0xff>; /* L3 Interconnect */
 648                         reg-names = "mpu", "dma";
 649                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 650                         interrupt-names = "common";
 651                         ti,buffer-size = <128>;
 652                         ti,hwmods = "mcbsp3";
 653                         dmas = <&sdma 19>,
 654                                <&sdma 20>;
 655                         dma-names = "tx", "rx";
 656                         status = "disabled";
 657                 };
 658
 659                 mcbsp4: mcbsp@48096000 {
 660                         compatible = "ti,omap4-mcbsp";
 661                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 662                         reg-names = "mpu";
 663                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 664                         interrupt-names = "common";
 665                         ti,buffer-size = <128>;
 666                         ti,hwmods = "mcbsp4";
 667                         dmas = <&sdma 31>,
 668                                <&sdma 32>;
 669                         dma-names = "tx", "rx";
 670                         status = "disabled";
 671                 };
 672
 673                 keypad: keypad@4a31c000 {
 674                         compatible = "ti,omap4-keypad";
 675                         reg = <0x4a31c000 0x80>;
 676                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 677                         reg-names = "mpu";
 678                         ti,hwmods = "kbd";
 679                 };
 680
 681                 dmm@4e000000 {
 682                         compatible = "ti,omap4-dmm";
 683                         reg = <0x4e000000 0x800>;
 684                         interrupts = <0 113 0x4>;
 685                         ti,hwmods = "dmm";
 686                 };
 687
 688                 emif1: emif@4c000000 {
 689                         compatible = "ti,emif-4d";
 690                         reg = <0x4c000000 0x100>;
 691                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 692                         ti,hwmods = "emif1";
 693                         ti,no-idle-on-init;
 694                         phy-type = <1>;
 695                         hw-caps-read-idle-ctrl;
 696                         hw-caps-ll-interface;
 697                         hw-caps-temp-alert;
 698                 };
 699
 700                 emif2: emif@4d000000 {
 701                         compatible = "ti,emif-4d";
 702                         reg = <0x4d000000 0x100>;
 703                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 704                         ti,hwmods = "emif2";
 705                         ti,no-idle-on-init;
 706                         phy-type = <1>;
 707                         hw-caps-read-idle-ctrl;
 708                         hw-caps-ll-interface;
 709                         hw-caps-temp-alert;
 710                 };
 711
 712                 ocp2scp@4a0ad000 {
 713                         compatible = "ti,omap-ocp2scp";
 714                         reg = <0x4a0ad000 0x1f>;
 715                         #address-cells = <1>;
 716                         #size-cells = <1>;
 717                         ranges;
 718                         ti,hwmods = "ocp2scp_usb_phy";
 719                         usb2_phy: usb2phy@4a0ad080 {
 720                                 compatible = "ti,omap-usb2";
 721                                 reg = <0x4a0ad080 0x58>;
 722                                 ctrl-module = <&omap_control_usb2phy>;
 723                                 clocks = <&usb_phy_cm_clk32k>;
 724                                 clock-names = "wkupclk";
 725                                 #phy-cells = <0>;
 726                         };
 727                 };
 728
 729                 mailbox: mailbox@4a0f4000 {
 730                         compatible = "ti,omap4-mailbox";
 731                         reg = <0x4a0f4000 0x200>;
 732                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 733                         ti,hwmods = "mailbox";
 734                         #mbox-cells = <1>;
 735                         ti,mbox-num-users = <3>;
 736                         ti,mbox-num-fifos = <8>;
 737                         mbox_ipu: mbox_ipu {
 738                                 ti,mbox-tx = <0 0 0>;
 739                                 ti,mbox-rx = <1 0 0>;
 740                         };
 741                         mbox_dsp: mbox_dsp {
 742                                 ti,mbox-tx = <3 0 0>;
 743                                 ti,mbox-rx = <2 0 0>;
 744                         };
 745                 };
 746
 747                 timer1: timer@4a318000 {
 748                         compatible = "ti,omap3430-timer";
 749                         reg = <0x4a318000 0x80>;
 750                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 751                         ti,hwmods = "timer1";
 752                         ti,timer-alwon;
 753                 };
 754
 755                 timer2: timer@48032000 {
 756                         compatible = "ti,omap3430-timer";
 757                         reg = <0x48032000 0x80>;
 758                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 759                         ti,hwmods = "timer2";
 760                 };
 761
 762                 timer3: timer@48034000 {
 763                         compatible = "ti,omap4430-timer";
 764                         reg = <0x48034000 0x80>;
 765                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 766                         ti,hwmods = "timer3";
 767                 };
 768
 769                 timer4: timer@48036000 {
 770                         compatible = "ti,omap4430-timer";
 771                         reg = <0x48036000 0x80>;
 772                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 773                         ti,hwmods = "timer4";
 774                 };
 775
 776                 timer5: timer@40138000 {
 777                         compatible = "ti,omap4430-timer";
 778                         reg = <0x40138000 0x80>,
 779                               <0x49038000 0x80>;
 780                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 781                         ti,hwmods = "timer5";
 782                         ti,timer-dsp;
 783                 };
 784
 785                 timer6: timer@4013a000 {
 786                         compatible = "ti,omap4430-timer";
 787                         reg = <0x4013a000 0x80>,
 788                               <0x4903a000 0x80>;
 789                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "timer6";
 791                         ti,timer-dsp;
 792                 };
 793
 794                 timer7: timer@4013c000 {
 795                         compatible = "ti,omap4430-timer";
 796                         reg = <0x4013c000 0x80>,
 797                               <0x4903c000 0x80>;
 798                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 799                         ti,hwmods = "timer7";
 800                         ti,timer-dsp;
 801                 };
 802
 803                 timer8: timer@4013e000 {
 804                         compatible = "ti,omap4430-timer";
 805                         reg = <0x4013e000 0x80>,
 806                               <0x4903e000 0x80>;
 807                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 808                         ti,hwmods = "timer8";
 809                         ti,timer-pwm;
 810                         ti,timer-dsp;
 811                 };
 812
 813                 timer9: timer@4803e000 {
 814                         compatible = "ti,omap4430-timer";
 815                         reg = <0x4803e000 0x80>;
 816                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 817                         ti,hwmods = "timer9";
 818                         ti,timer-pwm;
 819                 };
 820
 821                 timer10: timer@48086000 {
 822                         compatible = "ti,omap3430-timer";
 823                         reg = <0x48086000 0x80>;
 824                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 825                         ti,hwmods = "timer10";
 826                         ti,timer-pwm;
 827                 };
 828
 829                 timer11: timer@48088000 {
 830                         compatible = "ti,omap4430-timer";
 831                         reg = <0x48088000 0x80>;
 832                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 833                         ti,hwmods = "timer11";
 834                         ti,timer-pwm;
 835                 };
 836
 837                 usbhstll: usbhstll@4a062000 {
 838                         compatible = "ti,usbhs-tll";
 839                         reg = <0x4a062000 0x1000>;
 840                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 841                         ti,hwmods = "usb_tll_hs";
 842                 };
 843
 844                 usbhshost: usbhshost@4a064000 {
 845                         compatible = "ti,usbhs-host";
 846                         reg = <0x4a064000 0x800>;
 847                         ti,hwmods = "usb_host_hs";
 848                         #address-cells = <1>;
 849                         #size-cells = <1>;
 850                         ranges;
 851                         clocks = <&init_60m_fclk>,
 852                                  <&xclk60mhsp1_ck>,
 853                                  <&xclk60mhsp2_ck>;
 854                         clock-names = "refclk_60m_int",
 855                                       "refclk_60m_ext_p1",
 856                                       "refclk_60m_ext_p2";
 857
 858                         usbhsohci: ohci@4a064800 {
 859                                 compatible = "ti,ohci-omap3";
 860                                 reg = <0x4a064800 0x400>;
 861                                 interrupt-parent = <&gic>;
 862                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 863                         };
 864
 865                         usbhsehci: ehci@4a064c00 {
 866                                 compatible = "ti,ehci-omap";
 867                                 reg = <0x4a064c00 0x400>;
 868                                 interrupt-parent = <&gic>;
 869                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 870                         };
 871                 };
 872
 873                 omap_control_usb2phy: control-phy@4a002300 {
 874                         compatible = "ti,control-phy-usb2";
 875                         reg = <0x4a002300 0x4>;
 876                         reg-names = "power";
 877                 };
 878
 879                 omap_control_usbotg: control-phy@4a00233c {
 880                         compatible = "ti,control-phy-otghs";
 881                         reg = <0x4a00233c 0x4>;
 882                         reg-names = "otghs_control";
 883                 };
 884
 885                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 886                         compatible = "ti,omap4-musb";
 887                         reg = <0x4a0ab000 0x7ff>;
 888                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 889                         interrupt-names = "mc", "dma";
 890                         ti,hwmods = "usb_otg_hs";
 891                         usb-phy = <&usb2_phy>;
 892                         phys = <&usb2_phy>;
 893                         phy-names = "usb2-phy";
 894                         multipoint = <1>;
 895                         num-eps = <16>;
 896                         ram-bits = <12>;
 897                         ctrl-module = <&omap_control_usbotg>;
 898                 };
 899
 900                 aes: aes@4b501000 {
 901                         compatible = "ti,omap4-aes";
 902                         ti,hwmods = "aes";
 903                         reg = <0x4b501000 0xa0>;
 904                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 905                         dmas = <&sdma 111>, <&sdma 110>;
 906                         dma-names = "tx", "rx";
 907                 };
 908
 909                 des: des@480a5000 {
 910                         compatible = "ti,omap4-des";
 911                         ti,hwmods = "des";
 912                         reg = <0x480a5000 0xa0>;
 913                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 914                         dmas = <&sdma 117>, <&sdma 116>;
 915                         dma-names = "tx", "rx";
 916                 };
 917
 918                 abb_mpu: regulator-abb-mpu {
 919                         compatible = "ti,abb-v2";
 920                         regulator-name = "abb_mpu";
 921                         #address-cells = <0>;
 922                         #size-cells = <0>;
 923                         ti,tranxdone-status-mask = <0x80>;
 924                         clocks = <&sys_clkin_ck>;
 925                         ti,settling-time = <50>;
 926                         ti,clock-cycles = <16>;
 927
 928                         status = "disabled";
 929                 };
 930
 931                 abb_iva: regulator-abb-iva {
 932                         compatible = "ti,abb-v2";
 933                         regulator-name = "abb_iva";
 934                         #address-cells = <0>;
 935                         #size-cells = <0>;
 936                         ti,tranxdone-status-mask = <0x80000000>;
 937                         clocks = <&sys_clkin_ck>;
 938                         ti,settling-time = <50>;
 939                         ti,clock-cycles = <16>;
 940
 941                         status = "disabled";
 942                 };
 943
 944                 dss: dss@58000000 {
 945                         compatible = "ti,omap4-dss";
 946                         reg = <0x58000000 0x80>;
 947                         status = "disabled";
 948                         ti,hwmods = "dss_core";
 949                         clocks = <&dss_dss_clk>;
 950                         clock-names = "fck";
 951                         #address-cells = <1>;
 952                         #size-cells = <1>;
 953                         ranges;
 954
 955                         dispc@58001000 {
 956                                 compatible = "ti,omap4-dispc";
 957                                 reg = <0x58001000 0x1000>;
 958                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 959                                 ti,hwmods = "dss_dispc";
 960                                 clocks = <&dss_dss_clk>;
 961                                 clock-names = "fck";
 962                         };
 963
 964                         rfbi: encoder@58002000  {
 965                                 compatible = "ti,omap4-rfbi";
 966                                 reg = <0x58002000 0x1000>;
 967                                 status = "disabled";
 968                                 ti,hwmods = "dss_rfbi";
 969                                 clocks = <&dss_dss_clk>, <&l3_div_ck>;
 970                                 clock-names = "fck", "ick";
 971                         };
 972
 973                         venc: encoder@58003000 {
 974                                 compatible = "ti,omap4-venc";
 975                                 reg = <0x58003000 0x1000>;
 976                                 status = "disabled";
 977                                 ti,hwmods = "dss_venc";
 978                                 clocks = <&dss_tv_clk>;
 979                                 clock-names = "fck";
 980                         };
 981
 982                         dsi1: encoder@58004000 {
 983                                 compatible = "ti,omap4-dsi";
 984                                 reg = <0x58004000 0x200>,
 985                                       <0x58004200 0x40>,
 986                                       <0x58004300 0x20>;
 987                                 reg-names = "proto", "phy", "pll";
 988                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 989                                 status = "disabled";
 990                                 ti,hwmods = "dss_dsi1";
 991                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 992                                 clock-names = "fck", "sys_clk";
 993                         };
 994
 995                         dsi2: encoder@58005000 {
 996                                 compatible = "ti,omap4-dsi";
 997                                 reg = <0x58005000 0x200>,
 998                                       <0x58005200 0x40>,
 999                                       <0x58005300 0x20>;
1000                                 reg-names = "proto", "phy", "pll";
1001                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1002                                 status = "disabled";
1003                                 ti,hwmods = "dss_dsi2";
1004                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1005                                 clock-names = "fck", "sys_clk";
1006                         };
1007
1008                         hdmi: encoder@58006000 {
1009                                 compatible = "ti,omap4-hdmi";
1010                                 reg = <0x58006000 0x200>,
1011                                       <0x58006200 0x100>,
1012                                       <0x58006300 0x100>,
1013                                       <0x58006400 0x1000>;
1014                                 reg-names = "wp", "pll", "phy", "core";
1015                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1016                                 status = "disabled";
1017                                 ti,hwmods = "dss_hdmi";
1018                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1019                                 clock-names = "fck", "sys_clk";
1020                                 dmas = <&sdma 76>;
1021                                 dma-names = "audio_tx";
1022                         };
1023                 };
1024         };
1025 };
1026
1027 /include/ "omap44xx-clocks.dtsi"