arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 / {
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         compatible = "ti,omap5";
  19         interrupt-parent = <&wakeupgen>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 i2c3 = &i2c4;
  26                 i2c4 = &i2c5;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 serial5 = &uart6;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <0x0>;
  43
  44                         operating-points = <
  45                                 /* kHz    uV */
  46                                 1000000 1060000
  47                                 1500000 1250000
  48                         >;
  49
  50                         clocks = <&dpll_mpu_ck>;
  51                         clock-names = "cpu";
  52
  53                         clock-latency = <300000>; /* From omap-cpufreq driver */
  54
  55                         /* cooling options */
  56                         cooling-min-level = <0>;
  57                         cooling-max-level = <2>;
  58                         #cooling-cells = <2>; /* min followed by max */
  59                 };
  60                 cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <0x1>;
  64                 };
  65         };
  66
  67         thermal-zones {
  68                 #include "omap4-cpu-thermal.dtsi"
  69                 #include "omap5-gpu-thermal.dtsi"
  70                 #include "omap5-core-thermal.dtsi"
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 /* PPI secure/nonsecure IRQ */
  76                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  78                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  80                 interrupt-parent = <&gic>;
  81         };
  82
  83         pmu {
  84                 compatible = "arm,cortex-a15-pmu";
  85                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  87         };
  88
  89         gic: interrupt-controller@48211000 {
  90                 compatible = "arm,cortex-a15-gic";
  91                 interrupt-controller;
  92                 #interrupt-cells = <3>;
  93                 reg = <0 0x48211000 0 0x1000>,
  94                       <0 0x48212000 0 0x1000>,
  95                       <0 0x48214000 0 0x2000>,
  96                       <0 0x48216000 0 0x2000>;
  97                 interrupt-parent = <&gic>;
  98         };
  99
 100         wakeupgen: interrupt-controller@48281000 {
 101                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 102                 interrupt-controller;
 103                 #interrupt-cells = <3>;
 104                 reg = <0 0x48281000 0 0x1000>;
 105                 interrupt-parent = <&gic>;
 106         };
 107
 108         /*
 109          * The soc node represents the soc top level view. It is used for IPs
 110          * that are not memory mapped in the MPU view or for the MPU itself.
 111          */
 112         soc {
 113                 compatible = "ti,omap-infra";
 114                 mpu {
 115                         compatible = "ti,omap4-mpu";
 116                         ti,hwmods = "mpu";
 117                         sram = <&ocmcram>;
 118                 };
 119         };
 120
 121         /*
 122          * XXX: Use a flat representation of the OMAP3 interconnect.
 123          * The real OMAP interconnect network is quite complex.
 124          * Since it will not bring real advantage to represent that in DT for
 125          * the moment, just use a fake OCP bus entry to represent the whole bus
 126          * hierarchy.
 127          */
 128         ocp {
 129                 compatible = "ti,omap5-l3-noc", "simple-bus";
 130                 #address-cells = <1>;
 131                 #size-cells = <1>;
 132                 ranges = <0 0 0 0xc0000000>;
 133                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 134                 reg = <0 0x44000000 0 0x2000>,
 135                       <0 0x44800000 0 0x3000>,
 136                       <0 0x45000000 0 0x4000>;
 137                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 139
 140                 l4_cfg: l4@4a000000 {
 141                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         ranges = <0 0x4a000000 0x22a000>;
 145
 146                         scm_core: scm@2000 {
 147                                 compatible = "ti,omap5-scm-core", "simple-bus";
 148                                 reg = <0x2000 0x1000>;
 149                                 #address-cells = <1>;
 150                                 #size-cells = <1>;
 151                                 ranges = <0 0x2000 0x800>;
 152
 153                                 scm_conf: scm_conf@0 {
 154                                         compatible = "syscon";
 155                                         reg = <0x0 0x800>;
 156                                         #address-cells = <1>;
 157                                         #size-cells = <1>;
 158                                 };
 159                         };
 160
 161                         scm_padconf_core: scm@2800 {
 162                                 compatible = "ti,omap5-scm-padconf-core",
 163                                              "simple-bus";
 164                                 #address-cells = <1>;
 165                                 #size-cells = <1>;
 166                                 ranges = <0 0x2800 0x800>;
 167
 168                                 omap5_pmx_core: pinmux@40 {
 169                                         compatible = "ti,omap5-padconf",
 170                                                      "pinctrl-single";
 171                                         reg = <0x40 0x01b6>;
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                         #interrupt-cells = <1>;
 175                                         interrupt-controller;
 176                                         pinctrl-single,register-width = <16>;
 177                                         pinctrl-single,function-mask = <0x7fff>;
 178                                 };
 179
 180                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 181                                         compatible = "syscon",
 182                                                      "simple-bus";
 183                                         reg = <0x5a0 0xec>;
 184                                         #address-cells = <1>;
 185                                         #size-cells = <1>;
 186                                         ranges = <0 0x5a0 0xec>;
 187
 188                                         pbias_regulator: pbias_regulator@60 {
 189                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 190                                                 reg = <0x60 0x4>;
 191                                                 syscon = <&omap5_padconf_global>;
 192                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 193                                                         regulator-name = "pbias_mmc_omap5";
 194                                                         regulator-min-microvolt = <1800000>;
 195                                                         regulator-max-microvolt = <3000000>;
 196                                                 };
 197                                         };
 198                                 };
 199                         };
 200
 201                         cm_core_aon: cm_core_aon@4000 {
 202                                 compatible = "ti,omap5-cm-core-aon";
 203                                 reg = <0x4000 0x2000>;
 204
 205                                 cm_core_aon_clocks: clocks {
 206                                         #address-cells = <1>;
 207                                         #size-cells = <0>;
 208                                 };
 209
 210                                 cm_core_aon_clockdomains: clockdomains {
 211                                 };
 212                         };
 213
 214                         cm_core: cm_core@8000 {
 215                                 compatible = "ti,omap5-cm-core";
 216                                 reg = <0x8000 0x3000>;
 217
 218                                 cm_core_clocks: clocks {
 219                                         #address-cells = <1>;
 220                                         #size-cells = <0>;
 221                                 };
 222
 223                                 cm_core_clockdomains: clockdomains {
 224                                 };
 225                         };
 226                 };
 227
 228                 l4_wkup: l4@4ae00000 {
 229                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         ranges = <0 0x4ae00000 0x2b000>;
 233
 234                         counter32k: counter@4000 {
 235                                 compatible = "ti,omap-counter32k";
 236                                 reg = <0x4000 0x40>;
 237                                 ti,hwmods = "counter_32k";
 238                         };
 239
 240                         prm: prm@6000 {
 241                                 compatible = "ti,omap5-prm";
 242                                 reg = <0x6000 0x3000>;
 243                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 244
 245                                 prm_clocks: clocks {
 246                                         #address-cells = <1>;
 247                                         #size-cells = <0>;
 248                                 };
 249
 250                                 prm_clockdomains: clockdomains {
 251                                 };
 252                         };
 253
 254                         scrm: scrm@a000 {
 255                                 compatible = "ti,omap5-scrm";
 256                                 reg = <0xa000 0x2000>;
 257
 258                                 scrm_clocks: clocks {
 259                                         #address-cells = <1>;
 260                                         #size-cells = <0>;
 261                                 };
 262
 263                                 scrm_clockdomains: clockdomains {
 264                                 };
 265                         };
 266
 267                         omap5_pmx_wkup: pinmux@c840 {
 268                                 compatible = "ti,omap5-padconf",
 269                                              "pinctrl-single";
 270                                 reg = <0xc840 0x003c>;
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273                                 #interrupt-cells = <1>;
 274                                 interrupt-controller;
 275                                 pinctrl-single,register-width = <16>;
 276                                 pinctrl-single,function-mask = <0x7fff>;
 277                         };
 278                 };
 279
 280                 ocmcram: ocmcram@40300000 {
 281                         compatible = "mmio-sram";
 282                         reg = <0x40300000 0x20000>; /* 128k */
 283                 };
 284
 285                 sdma: dma-controller@4a056000 {
 286                         compatible = "ti,omap4430-sdma";
 287                         reg = <0x4a056000 0x1000>;
 288                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 292                         #dma-cells = <1>;
 293                         dma-channels = <32>;
 294                         dma-requests = <127>;
 295                 };
 296
 297                 gpio1: gpio@4ae10000 {
 298                         compatible = "ti,omap4-gpio";
 299                         reg = <0x4ae10000 0x200>;
 300                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 301                         ti,hwmods = "gpio1";
 302                         ti,gpio-always-on;
 303                         gpio-controller;
 304                         #gpio-cells = <2>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 gpio2: gpio@48055000 {
 310                         compatible = "ti,omap4-gpio";
 311                         reg = <0x48055000 0x200>;
 312                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 313                         ti,hwmods = "gpio2";
 314                         gpio-controller;
 315                         #gpio-cells = <2>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319
 320                 gpio3: gpio@48057000 {
 321                         compatible = "ti,omap4-gpio";
 322                         reg = <0x48057000 0x200>;
 323                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 324                         ti,hwmods = "gpio3";
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                         interrupt-controller;
 328                         #interrupt-cells = <2>;
 329                 };
 330
 331                 gpio4: gpio@48059000 {
 332                         compatible = "ti,omap4-gpio";
 333                         reg = <0x48059000 0x200>;
 334                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 335                         ti,hwmods = "gpio4";
 336                         gpio-controller;
 337                         #gpio-cells = <2>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                 };
 341
 342                 gpio5: gpio@4805b000 {
 343                         compatible = "ti,omap4-gpio";
 344                         reg = <0x4805b000 0x200>;
 345                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 346                         ti,hwmods = "gpio5";
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349                         interrupt-controller;
 350                         #interrupt-cells = <2>;
 351                 };
 352
 353                 gpio6: gpio@4805d000 {
 354                         compatible = "ti,omap4-gpio";
 355                         reg = <0x4805d000 0x200>;
 356                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 357                         ti,hwmods = "gpio6";
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360                         interrupt-controller;
 361                         #interrupt-cells = <2>;
 362                 };
 363
 364                 gpio7: gpio@48051000 {
 365                         compatible = "ti,omap4-gpio";
 366                         reg = <0x48051000 0x200>;
 367                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "gpio7";
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         interrupt-controller;
 372                         #interrupt-cells = <2>;
 373                 };
 374
 375                 gpio8: gpio@48053000 {
 376                         compatible = "ti,omap4-gpio";
 377                         reg = <0x48053000 0x200>;
 378                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "gpio8";
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385
 386                 gpmc: gpmc@50000000 {
 387                         compatible = "ti,omap4430-gpmc";
 388                         reg = <0x50000000 0x1000>;
 389                         #address-cells = <2>;
 390                         #size-cells = <1>;
 391                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 392                         dmas = <&sdma 4>;
 393                         dma-names = "rxtx";
 394                         gpmc,num-cs = <8>;
 395                         gpmc,num-waitpins = <4>;
 396                         ti,hwmods = "gpmc";
 397                         clocks = <&l3_iclk_div>;
 398                         clock-names = "fck";
 399                         interrupt-controller;
 400                         #interrupt-cells = <2>;
 401                         gpio-controller;
 402                         #gpio-cells = <2>;
 403                 };
 404
 405                 i2c1: i2c@48070000 {
 406                         compatible = "ti,omap4-i2c";
 407                         reg = <0x48070000 0x100>;
 408                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         ti,hwmods = "i2c1";
 412                 };
 413
 414                 i2c2: i2c@48072000 {
 415                         compatible = "ti,omap4-i2c";
 416                         reg = <0x48072000 0x100>;
 417                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         ti,hwmods = "i2c2";
 421                 };
 422
 423                 i2c3: i2c@48060000 {
 424                         compatible = "ti,omap4-i2c";
 425                         reg = <0x48060000 0x100>;
 426                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         ti,hwmods = "i2c3";
 430                 };
 431
 432                 i2c4: i2c@4807a000 {
 433                         compatible = "ti,omap4-i2c";
 434                         reg = <0x4807a000 0x100>;
 435                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         ti,hwmods = "i2c4";
 439                 };
 440
 441                 i2c5: i2c@4807c000 {
 442                         compatible = "ti,omap4-i2c";
 443                         reg = <0x4807c000 0x100>;
 444                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         ti,hwmods = "i2c5";
 448                 };
 449
 450                 hwspinlock: spinlock@4a0f6000 {
 451                         compatible = "ti,omap4-hwspinlock";
 452                         reg = <0x4a0f6000 0x1000>;
 453                         ti,hwmods = "spinlock";
 454                         #hwlock-cells = <1>;
 455                 };
 456
 457                 mcspi1: spi@48098000 {
 458                         compatible = "ti,omap4-mcspi";
 459                         reg = <0x48098000 0x200>;
 460                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         ti,hwmods = "mcspi1";
 464                         ti,spi-num-cs = <4>;
 465                         dmas = <&sdma 35>,
 466                                <&sdma 36>,
 467                                <&sdma 37>,
 468                                <&sdma 38>,
 469                                <&sdma 39>,
 470                                <&sdma 40>,
 471                                <&sdma 41>,
 472                                <&sdma 42>;
 473                         dma-names = "tx0", "rx0", "tx1", "rx1",
 474                                     "tx2", "rx2", "tx3", "rx3";
 475                 };
 476
 477                 mcspi2: spi@4809a000 {
 478                         compatible = "ti,omap4-mcspi";
 479                         reg = <0x4809a000 0x200>;
 480                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         ti,hwmods = "mcspi2";
 484                         ti,spi-num-cs = <2>;
 485                         dmas = <&sdma 43>,
 486                                <&sdma 44>,
 487                                <&sdma 45>,
 488                                <&sdma 46>;
 489                         dma-names = "tx0", "rx0", "tx1", "rx1";
 490                 };
 491
 492                 mcspi3: spi@480b8000 {
 493                         compatible = "ti,omap4-mcspi";
 494                         reg = <0x480b8000 0x200>;
 495                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         ti,hwmods = "mcspi3";
 499                         ti,spi-num-cs = <2>;
 500                         dmas = <&sdma 15>, <&sdma 16>;
 501                         dma-names = "tx0", "rx0";
 502                 };
 503
 504                 mcspi4: spi@480ba000 {
 505                         compatible = "ti,omap4-mcspi";
 506                         reg = <0x480ba000 0x200>;
 507                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         ti,hwmods = "mcspi4";
 511                         ti,spi-num-cs = <1>;
 512                         dmas = <&sdma 70>, <&sdma 71>;
 513                         dma-names = "tx0", "rx0";
 514                 };
 515
 516                 uart1: serial@4806a000 {
 517                         compatible = "ti,omap4-uart";
 518                         reg = <0x4806a000 0x100>;
 519                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "uart1";
 521                         clock-frequency = <48000000>;
 522                 };
 523
 524                 uart2: serial@4806c000 {
 525                         compatible = "ti,omap4-uart";
 526                         reg = <0x4806c000 0x100>;
 527                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 528                         ti,hwmods = "uart2";
 529                         clock-frequency = <48000000>;
 530                 };
 531
 532                 uart3: serial@48020000 {
 533                         compatible = "ti,omap4-uart";
 534                         reg = <0x48020000 0x100>;
 535                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "uart3";
 537                         clock-frequency = <48000000>;
 538                 };
 539
 540                 uart4: serial@4806e000 {
 541                         compatible = "ti,omap4-uart";
 542                         reg = <0x4806e000 0x100>;
 543                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 544                         ti,hwmods = "uart4";
 545                         clock-frequency = <48000000>;
 546                 };
 547
 548                 uart5: serial@48066000 {
 549                         compatible = "ti,omap4-uart";
 550                         reg = <0x48066000 0x100>;
 551                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 552                         ti,hwmods = "uart5";
 553                         clock-frequency = <48000000>;
 554                 };
 555
 556                 uart6: serial@48068000 {
 557                         compatible = "ti,omap4-uart";
 558                         reg = <0x48068000 0x100>;
 559                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 560                         ti,hwmods = "uart6";
 561                         clock-frequency = <48000000>;
 562                 };
 563
 564                 mmc1: mmc@4809c000 {
 565                         compatible = "ti,omap4-hsmmc";
 566                         reg = <0x4809c000 0x400>;
 567                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 568                         ti,hwmods = "mmc1";
 569                         ti,dual-volt;
 570                         ti,needs-special-reset;
 571                         dmas = <&sdma 61>, <&sdma 62>;
 572                         dma-names = "tx", "rx";
 573                         pbias-supply = <&pbias_mmc_reg>;
 574                 };
 575
 576                 mmc2: mmc@480b4000 {
 577                         compatible = "ti,omap4-hsmmc";
 578                         reg = <0x480b4000 0x400>;
 579                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 580                         ti,hwmods = "mmc2";
 581                         ti,needs-special-reset;
 582                         dmas = <&sdma 47>, <&sdma 48>;
 583                         dma-names = "tx", "rx";
 584                 };
 585
 586                 mmc3: mmc@480ad000 {
 587                         compatible = "ti,omap4-hsmmc";
 588                         reg = <0x480ad000 0x400>;
 589                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 590                         ti,hwmods = "mmc3";
 591                         ti,needs-special-reset;
 592                         dmas = <&sdma 77>, <&sdma 78>;
 593                         dma-names = "tx", "rx";
 594                 };
 595
 596                 mmc4: mmc@480d1000 {
 597                         compatible = "ti,omap4-hsmmc";
 598                         reg = <0x480d1000 0x400>;
 599                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 600                         ti,hwmods = "mmc4";
 601                         ti,needs-special-reset;
 602                         dmas = <&sdma 57>, <&sdma 58>;
 603                         dma-names = "tx", "rx";
 604                 };
 605
 606                 mmc5: mmc@480d5000 {
 607                         compatible = "ti,omap4-hsmmc";
 608                         reg = <0x480d5000 0x400>;
 609                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 610                         ti,hwmods = "mmc5";
 611                         ti,needs-special-reset;
 612                         dmas = <&sdma 59>, <&sdma 60>;
 613                         dma-names = "tx", "rx";
 614                 };
 615
 616                 mmu_dsp: mmu@4a066000 {
 617                         compatible = "ti,omap4-iommu";
 618                         reg = <0x4a066000 0x100>;
 619                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 620                         ti,hwmods = "mmu_dsp";
 621                         #iommu-cells = <0>;
 622                 };
 623
 624                 mmu_ipu: mmu@55082000 {
 625                         compatible = "ti,omap4-iommu";
 626                         reg = <0x55082000 0x100>;
 627                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 628                         ti,hwmods = "mmu_ipu";
 629                         #iommu-cells = <0>;
 630                         ti,iommu-bus-err-back;
 631                 };
 632
 633                 keypad: keypad@4ae1c000 {
 634                         compatible = "ti,omap4-keypad";
 635                         reg = <0x4ae1c000 0x400>;
 636                         ti,hwmods = "kbd";
 637                 };
 638
 639                 mcpdm: mcpdm@40132000 {
 640                         compatible = "ti,omap4-mcpdm";
 641                         reg = <0x40132000 0x7f>, /* MPU private access */
 642                               <0x49032000 0x7f>; /* L3 Interconnect */
 643                         reg-names = "mpu", "dma";
 644                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 645                         ti,hwmods = "mcpdm";
 646                         dmas = <&sdma 65>,
 647                                <&sdma 66>;
 648                         dma-names = "up_link", "dn_link";
 649                         status = "disabled";
 650                 };
 651
 652                 dmic: dmic@4012e000 {
 653                         compatible = "ti,omap4-dmic";
 654                         reg = <0x4012e000 0x7f>, /* MPU private access */
 655                               <0x4902e000 0x7f>; /* L3 Interconnect */
 656                         reg-names = "mpu", "dma";
 657                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "dmic";
 659                         dmas = <&sdma 67>;
 660                         dma-names = "up_link";
 661                         status = "disabled";
 662                 };
 663
 664                 mcbsp1: mcbsp@40122000 {
 665                         compatible = "ti,omap4-mcbsp";
 666                         reg = <0x40122000 0xff>, /* MPU private access */
 667                               <0x49022000 0xff>; /* L3 Interconnect */
 668                         reg-names = "mpu", "dma";
 669                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 670                         interrupt-names = "common";
 671                         ti,buffer-size = <128>;
 672                         ti,hwmods = "mcbsp1";
 673                         dmas = <&sdma 33>,
 674                                <&sdma 34>;
 675                         dma-names = "tx", "rx";
 676                         status = "disabled";
 677                 };
 678
 679                 mcbsp2: mcbsp@40124000 {
 680                         compatible = "ti,omap4-mcbsp";
 681                         reg = <0x40124000 0xff>, /* MPU private access */
 682                               <0x49024000 0xff>; /* L3 Interconnect */
 683                         reg-names = "mpu", "dma";
 684                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 685                         interrupt-names = "common";
 686                         ti,buffer-size = <128>;
 687                         ti,hwmods = "mcbsp2";
 688                         dmas = <&sdma 17>,
 689                                <&sdma 18>;
 690                         dma-names = "tx", "rx";
 691                         status = "disabled";
 692                 };
 693
 694                 mcbsp3: mcbsp@40126000 {
 695                         compatible = "ti,omap4-mcbsp";
 696                         reg = <0x40126000 0xff>, /* MPU private access */
 697                               <0x49026000 0xff>; /* L3 Interconnect */
 698                         reg-names = "mpu", "dma";
 699                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 700                         interrupt-names = "common";
 701                         ti,buffer-size = <128>;
 702                         ti,hwmods = "mcbsp3";
 703                         dmas = <&sdma 19>,
 704                                <&sdma 20>;
 705                         dma-names = "tx", "rx";
 706                         status = "disabled";
 707                 };
 708
 709                 mailbox: mailbox@4a0f4000 {
 710                         compatible = "ti,omap4-mailbox";
 711                         reg = <0x4a0f4000 0x200>;
 712                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "mailbox";
 714                         #mbox-cells = <1>;
 715                         ti,mbox-num-users = <3>;
 716                         ti,mbox-num-fifos = <8>;
 717                         mbox_ipu: mbox_ipu {
 718                                 ti,mbox-tx = <0 0 0>;
 719                                 ti,mbox-rx = <1 0 0>;
 720                         };
 721                         mbox_dsp: mbox_dsp {
 722                                 ti,mbox-tx = <3 0 0>;
 723                                 ti,mbox-rx = <2 0 0>;
 724                         };
 725                 };
 726
 727                 timer1: timer@4ae18000 {
 728                         compatible = "ti,omap5430-timer";
 729                         reg = <0x4ae18000 0x80>;
 730                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 731                         ti,hwmods = "timer1";
 732                         ti,timer-alwon;
 733                 };
 734
 735                 timer2: timer@48032000 {
 736                         compatible = "ti,omap5430-timer";
 737                         reg = <0x48032000 0x80>;
 738                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 739                         ti,hwmods = "timer2";
 740                 };
 741
 742                 timer3: timer@48034000 {
 743                         compatible = "ti,omap5430-timer";
 744                         reg = <0x48034000 0x80>;
 745                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "timer3";
 747                 };
 748
 749                 timer4: timer@48036000 {
 750                         compatible = "ti,omap5430-timer";
 751                         reg = <0x48036000 0x80>;
 752                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 753                         ti,hwmods = "timer4";
 754                 };
 755
 756                 timer5: timer@40138000 {
 757                         compatible = "ti,omap5430-timer";
 758                         reg = <0x40138000 0x80>,
 759                               <0x49038000 0x80>;
 760                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 761                         ti,hwmods = "timer5";
 762                         ti,timer-dsp;
 763                         ti,timer-pwm;
 764                 };
 765
 766                 timer6: timer@4013a000 {
 767                         compatible = "ti,omap5430-timer";
 768                         reg = <0x4013a000 0x80>,
 769                               <0x4903a000 0x80>;
 770                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 771                         ti,hwmods = "timer6";
 772                         ti,timer-dsp;
 773                         ti,timer-pwm;
 774                 };
 775
 776                 timer7: timer@4013c000 {
 777                         compatible = "ti,omap5430-timer";
 778                         reg = <0x4013c000 0x80>,
 779                               <0x4903c000 0x80>;
 780                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 781                         ti,hwmods = "timer7";
 782                         ti,timer-dsp;
 783                 };
 784
 785                 timer8: timer@4013e000 {
 786                         compatible = "ti,omap5430-timer";
 787                         reg = <0x4013e000 0x80>,
 788                               <0x4903e000 0x80>;
 789                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "timer8";
 791                         ti,timer-dsp;
 792                         ti,timer-pwm;
 793                 };
 794
 795                 timer9: timer@4803e000 {
 796                         compatible = "ti,omap5430-timer";
 797                         reg = <0x4803e000 0x80>;
 798                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 799                         ti,hwmods = "timer9";
 800                         ti,timer-pwm;
 801                 };
 802
 803                 timer10: timer@48086000 {
 804                         compatible = "ti,omap5430-timer";
 805                         reg = <0x48086000 0x80>;
 806                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 807                         ti,hwmods = "timer10";
 808                         ti,timer-pwm;
 809                 };
 810
 811                 timer11: timer@48088000 {
 812                         compatible = "ti,omap5430-timer";
 813                         reg = <0x48088000 0x80>;
 814                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 815                         ti,hwmods = "timer11";
 816                         ti,timer-pwm;
 817                 };
 818
 819                 wdt2: wdt@4ae14000 {
 820                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 821                         reg = <0x4ae14000 0x80>;
 822                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 823                         ti,hwmods = "wd_timer2";
 824                 };
 825
 826                 dmm@4e000000 {
 827                         compatible = "ti,omap5-dmm";
 828                         reg = <0x4e000000 0x800>;
 829                         interrupts = <0 113 0x4>;
 830                         ti,hwmods = "dmm";
 831                 };
 832
 833                 emif1: emif@4c000000 {
 834                         compatible      = "ti,emif-4d5";
 835                         ti,hwmods       = "emif1";
 836                         ti,no-idle-on-init;
 837                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 838                         reg = <0x4c000000 0x400>;
 839                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 840                         hw-caps-read-idle-ctrl;
 841                         hw-caps-ll-interface;
 842                         hw-caps-temp-alert;
 843                 };
 844
 845                 emif2: emif@4d000000 {
 846                         compatible      = "ti,emif-4d5";
 847                         ti,hwmods       = "emif2";
 848                         ti,no-idle-on-init;
 849                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 850                         reg = <0x4d000000 0x400>;
 851                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 852                         hw-caps-read-idle-ctrl;
 853                         hw-caps-ll-interface;
 854                         hw-caps-temp-alert;
 855                 };
 856
 857                 usb3: omap_dwc3@4a020000 {
 858                         compatible = "ti,dwc3";
 859                         ti,hwmods = "usb_otg_ss";
 860                         reg = <0x4a020000 0x10000>;
 861                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 862                         #address-cells = <1>;
 863                         #size-cells = <1>;
 864                         utmi-mode = <2>;
 865                         ranges;
 866                         dwc3: dwc3@4a030000 {
 867                                 compatible = "snps,dwc3";
 868                                 reg = <0x4a030000 0x10000>;
 869                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 870                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 871                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 872                                 interrupt-names = "peripheral",
 873                                                   "host",
 874                                                   "otg";
 875                                 phys = <&usb2_phy>, <&usb3_phy>;
 876                                 phy-names = "usb2-phy", "usb3-phy";
 877                                 dr_mode = "peripheral";
 878                         };
 879                 };
 880
 881                 ocp2scp@4a080000 {
 882                         compatible = "ti,omap-ocp2scp";
 883                         #address-cells = <1>;
 884                         #size-cells = <1>;
 885                         reg = <0x4a080000 0x20>;
 886                         ranges;
 887                         ti,hwmods = "ocp2scp1";
 888                         usb2_phy: usb2phy@4a084000 {
 889                                 compatible = "ti,omap-usb2";
 890                                 reg = <0x4a084000 0x7c>;
 891                                 syscon-phy-power = <&scm_conf 0x300>;
 892                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 893                                 clock-names = "wkupclk", "refclk";
 894                                 #phy-cells = <0>;
 895                         };
 896
 897                         usb3_phy: usb3phy@4a084400 {
 898                                 compatible = "ti,omap-usb3";
 899                                 reg = <0x4a084400 0x80>,
 900                                       <0x4a084800 0x64>,
 901                                       <0x4a084c00 0x40>;
 902                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 903                                 syscon-phy-power = <&scm_conf 0x370>;
 904                                 clocks = <&usb_phy_cm_clk32k>,
 905                                          <&sys_clkin>,
 906                                          <&usb_otg_ss_refclk960m>;
 907                                 clock-names =   "wkupclk",
 908                                                 "sysclk",
 909                                                 "refclk";
 910                                 #phy-cells = <0>;
 911                         };
 912                 };
 913
 914                 usbhstll: usbhstll@4a062000 {
 915                         compatible = "ti,usbhs-tll";
 916                         reg = <0x4a062000 0x1000>;
 917                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 918                         ti,hwmods = "usb_tll_hs";
 919                 };
 920
 921                 usbhshost: usbhshost@4a064000 {
 922                         compatible = "ti,usbhs-host";
 923                         reg = <0x4a064000 0x800>;
 924                         ti,hwmods = "usb_host_hs";
 925                         #address-cells = <1>;
 926                         #size-cells = <1>;
 927                         ranges;
 928                         clocks = <&l3init_60m_fclk>,
 929                                  <&xclk60mhsp1_ck>,
 930                                  <&xclk60mhsp2_ck>;
 931                         clock-names = "refclk_60m_int",
 932                                       "refclk_60m_ext_p1",
 933                                       "refclk_60m_ext_p2";
 934
 935                         usbhsohci: ohci@4a064800 {
 936                                 compatible = "ti,ohci-omap3";
 937                                 reg = <0x4a064800 0x400>;
 938                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 939                         };
 940
 941                         usbhsehci: ehci@4a064c00 {
 942                                 compatible = "ti,ehci-omap";
 943                                 reg = <0x4a064c00 0x400>;
 944                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 945                         };
 946                 };
 947
 948                 bandgap: bandgap@4a0021e0 {
 949                         reg = <0x4a0021e0 0xc
 950                                0x4a00232c 0xc
 951                                0x4a002380 0x2c
 952                                0x4a0023C0 0x3c>;
 953                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 954                         compatible = "ti,omap5430-bandgap";
 955
 956                         #thermal-sensor-cells = <1>;
 957                 };
 958
 959                 /* OCP2SCP3 */
 960                 ocp2scp@4a090000 {
 961                         compatible = "ti,omap-ocp2scp";
 962                         #address-cells = <1>;
 963                         #size-cells = <1>;
 964                         reg = <0x4a090000 0x20>;
 965                         ranges;
 966                         ti,hwmods = "ocp2scp3";
 967                         sata_phy: phy@4a096000 {
 968                                 compatible = "ti,phy-pipe3-sata";
 969                                 reg = <0x4A096000 0x80>, /* phy_rx */
 970                                       <0x4A096400 0x64>, /* phy_tx */
 971                                       <0x4A096800 0x40>; /* pll_ctrl */
 972                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 973                                 syscon-phy-power = <&scm_conf 0x374>;
 974                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 975                                 clock-names = "sysclk", "refclk";
 976                                 #phy-cells = <0>;
 977                         };
 978                 };
 979
 980                 sata: sata@4a141100 {
 981                         compatible = "snps,dwc-ahci";
 982                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 983                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 984                         phys = <&sata_phy>;
 985                         phy-names = "sata-phy";
 986                         clocks = <&sata_ref_clk>;
 987                         ti,hwmods = "sata";
 988                 };
 989
 990                 dss: dss@58000000 {
 991                         compatible = "ti,omap5-dss";
 992                         reg = <0x58000000 0x80>;
 993                         status = "disabled";
 994                         ti,hwmods = "dss_core";
 995                         clocks = <&dss_dss_clk>;
 996                         clock-names = "fck";
 997                         #address-cells = <1>;
 998                         #size-cells = <1>;
 999                         ranges;
1000
1001                         dispc@58001000 {
1002                                 compatible = "ti,omap5-dispc";
1003                                 reg = <0x58001000 0x1000>;
1004                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1005                                 ti,hwmods = "dss_dispc";
1006                                 clocks = <&dss_dss_clk>;
1007                                 clock-names = "fck";
1008                         };
1009
1010                         rfbi: encoder@58002000  {
1011                                 compatible = "ti,omap5-rfbi";
1012                                 reg = <0x58002000 0x100>;
1013                                 status = "disabled";
1014                                 ti,hwmods = "dss_rfbi";
1015                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1016                                 clock-names = "fck", "ick";
1017                         };
1018
1019                         dsi1: encoder@58004000 {
1020                                 compatible = "ti,omap5-dsi";
1021                                 reg = <0x58004000 0x200>,
1022                                       <0x58004200 0x40>,
1023                                       <0x58004300 0x40>;
1024                                 reg-names = "proto", "phy", "pll";
1025                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026                                 status = "disabled";
1027                                 ti,hwmods = "dss_dsi1";
1028                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1029                                 clock-names = "fck", "sys_clk";
1030                         };
1031
1032                         dsi2: encoder@58005000 {
1033                                 compatible = "ti,omap5-dsi";
1034                                 reg = <0x58009000 0x200>,
1035                                       <0x58009200 0x40>,
1036                                       <0x58009300 0x40>;
1037                                 reg-names = "proto", "phy", "pll";
1038                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1039                                 status = "disabled";
1040                                 ti,hwmods = "dss_dsi2";
1041                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1042                                 clock-names = "fck", "sys_clk";
1043                         };
1044
1045                         hdmi: encoder@58060000 {
1046                                 compatible = "ti,omap5-hdmi";
1047                                 reg = <0x58040000 0x200>,
1048                                       <0x58040200 0x80>,
1049                                       <0x58040300 0x80>,
1050                                       <0x58060000 0x19000>;
1051                                 reg-names = "wp", "pll", "phy", "core";
1052                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1053                                 status = "disabled";
1054                                 ti,hwmods = "dss_hdmi";
1055                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1056                                 clock-names = "fck", "sys_clk";
1057                                 dmas = <&sdma 76>;
1058                                 dma-names = "audio_tx";
1059                         };
1060                 };
1061
1062                 abb_mpu: regulator-abb-mpu {
1063                         compatible = "ti,abb-v2";
1064                         regulator-name = "abb_mpu";
1065                         #address-cells = <0>;
1066                         #size-cells = <0>;
1067                         clocks = <&sys_clkin>;
1068                         ti,settling-time = <50>;
1069                         ti,clock-cycles = <16>;
1070
1071                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1072                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1073                         reg-names = "base-address", "int-address",
1074                                     "efuse-address", "ldo-address";
1075                         ti,tranxdone-status-mask = <0x80>;
1076                         /* LDOVBBMPU_MUX_CTRL */
1077                         ti,ldovbb-override-mask = <0x400>;
1078                         /* LDOVBBMPU_VSET_OUT */
1079                         ti,ldovbb-vset-mask = <0x1F>;
1080
1081                         /*
1082                          * NOTE: only FBB mode used but actual vset will
1083                          * determine final biasing
1084                          */
1085                         ti,abb_info = <
1086                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1087                         1060000         0       0x0     0 0x02000000 0x01F00000
1088                         1250000         0       0x4     0 0x02000000 0x01F00000
1089                         >;
1090                 };
1091
1092                 abb_mm: regulator-abb-mm {
1093                         compatible = "ti,abb-v2";
1094                         regulator-name = "abb_mm";
1095                         #address-cells = <0>;
1096                         #size-cells = <0>;
1097                         clocks = <&sys_clkin>;
1098                         ti,settling-time = <50>;
1099                         ti,clock-cycles = <16>;
1100
1101                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1102                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1103                         reg-names = "base-address", "int-address",
1104                                     "efuse-address", "ldo-address";
1105                         ti,tranxdone-status-mask = <0x80000000>;
1106                         /* LDOVBBMM_MUX_CTRL */
1107                         ti,ldovbb-override-mask = <0x400>;
1108                         /* LDOVBBMM_VSET_OUT */
1109                         ti,ldovbb-vset-mask = <0x1F>;
1110
1111                         /*
1112                          * NOTE: only FBB mode used but actual vset will
1113                          * determine final biasing
1114                          */
1115                         ti,abb_info = <
1116                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1117                         1025000         0       0x0     0 0x02000000 0x01F00000
1118                         1120000         0       0x4     0 0x02000000 0x01F00000
1119                         >;
1120                 };
1121         };
1122 };
1123
1124 &cpu_thermal {
1125         polling-delay = <500>; /* milliseconds */
1126 };
1127
1128 /include/ "omap54xx-clocks.dtsi"