arch/arm/boot/dts/qcom-apq8084.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4
   5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         model = "Qualcomm APQ 8084";
  10         compatible = "qcom,apq8084";
  11         interrupt-parent = <&intc>;
  12
  13         reserved-memory {
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges;
  17
  18                 smem_mem: smem_region@fa00000 {
  19                         reg = <0xfa00000 0x200000>;
  20                         no-map;
  21                 };
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "qcom,krait";
  31                         reg = <0>;
  32                         enable-method = "qcom,kpss-acc-v2";
  33                         next-level-cache = <&L2>;
  34                         qcom,acc = <&acc0>;
  35                         qcom,saw = <&saw0>;
  36                         cpu-idle-states = <&CPU_SPC>;
  37                 };
  38
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "qcom,krait";
  42                         reg = <1>;
  43                         enable-method = "qcom,kpss-acc-v2";
  44                         next-level-cache = <&L2>;
  45                         qcom,acc = <&acc1>;
  46                         qcom,saw = <&saw1>;
  47                         cpu-idle-states = <&CPU_SPC>;
  48                 };
  49
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "qcom,krait";
  53                         reg = <2>;
  54                         enable-method = "qcom,kpss-acc-v2";
  55                         next-level-cache = <&L2>;
  56                         qcom,acc = <&acc2>;
  57                         qcom,saw = <&saw2>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 cpu@3 {
  62                         device_type = "cpu";
  63                         compatible = "qcom,krait";
  64                         reg = <3>;
  65                         enable-method = "qcom,kpss-acc-v2";
  66                         next-level-cache = <&L2>;
  67                         qcom,acc = <&acc3>;
  68                         qcom,saw = <&saw3>;
  69                         cpu-idle-states = <&CPU_SPC>;
  70                 };
  71
  72                 L2: l2-cache {
  73                         compatible = "qcom,arch-cache";
  74                         cache-level = <2>;
  75                         qcom,saw = <&saw_l2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <150>;
  83                                 exit-latency-us = <200>;
  84                                 min-residency-us = <2000>;
  85                         };
  86                 };
  87         };
  88
  89         firmware {
  90                 scm {
  91                         compatible = "qcom,scm";
  92                         clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
  93                         clock-names = "core", "bus", "iface";
  94                 };
  95         };
  96
  97         thermal-zones {
  98                 cpu-thermal0 {
  99                         polling-delay-passive = <250>;
 100                         polling-delay = <1000>;
 101
 102                         thermal-sensors = <&tsens 5>;
 103
 104                         trips {
 105                                 cpu_alert0: trip0 {
 106                                         temperature = <75000>;
 107                                         hysteresis = <2000>;
 108                                         type = "passive";
 109                                 };
 110                                 cpu_crit0: trip1 {
 111                                         temperature = <110000>;
 112                                         hysteresis = <2000>;
 113                                         type = "critical";
 114                                 };
 115                         };
 116                 };
 117
 118                 cpu-thermal1 {
 119                         polling-delay-passive = <250>;
 120                         polling-delay = <1000>;
 121
 122                         thermal-sensors = <&tsens 6>;
 123
 124                         trips {
 125                                 cpu_alert1: trip0 {
 126                                         temperature = <75000>;
 127                                         hysteresis = <2000>;
 128                                         type = "passive";
 129                                 };
 130                                 cpu_crit1: trip1 {
 131                                         temperature = <110000>;
 132                                         hysteresis = <2000>;
 133                                         type = "critical";
 134                                 };
 135                         };
 136                 };
 137
 138                 cpu-thermal2 {
 139                         polling-delay-passive = <250>;
 140                         polling-delay = <1000>;
 141
 142                         thermal-sensors = <&tsens 7>;
 143
 144                         trips {
 145                                 cpu_alert2: trip0 {
 146                                         temperature = <75000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150                                 cpu_crit2: trip1 {
 151                                         temperature = <110000>;
 152                                         hysteresis = <2000>;
 153                                         type = "critical";
 154                                 };
 155                         };
 156                 };
 157
 158                 cpu-thermal3 {
 159                         polling-delay-passive = <250>;
 160                         polling-delay = <1000>;
 161
 162                         thermal-sensors = <&tsens 8>;
 163
 164                         trips {
 165                                 cpu_alert3: trip0 {
 166                                         temperature = <75000>;
 167                                         hysteresis = <2000>;
 168                                         type = "passive";
 169                                 };
 170                                 cpu_crit3: trip1 {
 171                                         temperature = <110000>;
 172                                         hysteresis = <2000>;
 173                                         type = "critical";
 174                                 };
 175                         };
 176                 };
 177         };
 178
 179         cpu-pmu {
 180                 compatible = "qcom,krait-pmu";
 181                 interrupts = <1 7 0xf04>;
 182         };
 183
 184         clocks {
 185                 xo_board {
 186                         compatible = "fixed-clock";
 187                         #clock-cells = <0>;
 188                         clock-frequency = <19200000>;
 189                 };
 190
 191                 sleep_clk {
 192                         compatible = "fixed-clock";
 193                         #clock-cells = <0>;
 194                         clock-frequency = <32768>;
 195                 };
 196         };
 197
 198         timer {
 199                 compatible = "arm,armv7-timer";
 200                 interrupts = <1 2 0xf08>,
 201                              <1 3 0xf08>,
 202                              <1 4 0xf08>,
 203                              <1 1 0xf08>;
 204                 clock-frequency = <19200000>;
 205         };
 206
 207         smem {
 208                 compatible = "qcom,smem";
 209
 210                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 211                 memory-region = <&smem_mem>;
 212
 213                 hwlocks = <&tcsr_mutex 3>;
 214         };
 215
 216         soc: soc {
 217                 #address-cells = <1>;
 218                 #size-cells = <1>;
 219                 ranges;
 220                 compatible = "simple-bus";
 221
 222                 intc: interrupt-controller@f9000000 {
 223                         compatible = "qcom,msm-qgic2";
 224                         interrupt-controller;
 225                         #interrupt-cells = <3>;
 226                         reg = <0xf9000000 0x1000>,
 227                               <0xf9002000 0x1000>;
 228                 };
 229
 230                 apcs: syscon@f9011000 {
 231                         compatible = "syscon";
 232                         reg = <0xf9011000 0x1000>;
 233                 };
 234
 235                 qfprom: qfprom@fc4bc000 {
 236                         #address-cells = <1>;
 237                         #size-cells = <1>;
 238                         compatible = "qcom,qfprom";
 239                         reg = <0xfc4bc000 0x1000>;
 240                         tsens_calib: calib@d0 {
 241                                 reg = <0xd0 0x18>;
 242                         };
 243                         tsens_backup: backup@440 {
 244                                 reg = <0x440 0x10>;
 245                         };
 246                 };
 247
 248                 tsens: thermal-sensor@fc4a8000 {
 249                         compatible = "qcom,msm8974-tsens";
 250                         reg = <0xfc4a8000 0x2000>;
 251                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 252                         nvmem-cell-names = "calib", "calib_backup";
 253                         #thermal-sensor-cells = <1>;
 254                 };
 255
 256                 timer@f9020000 {
 257                         #address-cells = <1>;
 258                         #size-cells = <1>;
 259                         ranges;
 260                         compatible = "arm,armv7-timer-mem";
 261                         reg = <0xf9020000 0x1000>;
 262                         clock-frequency = <19200000>;
 263
 264                         frame@f9021000 {
 265                                 frame-number = <0>;
 266                                 interrupts = <0 8 0x4>,
 267                                              <0 7 0x4>;
 268                                 reg = <0xf9021000 0x1000>,
 269                                       <0xf9022000 0x1000>;
 270                         };
 271
 272                         frame@f9023000 {
 273                                 frame-number = <1>;
 274                                 interrupts = <0 9 0x4>;
 275                                 reg = <0xf9023000 0x1000>;
 276                                 status = "disabled";
 277                         };
 278
 279                         frame@f9024000 {
 280                                 frame-number = <2>;
 281                                 interrupts = <0 10 0x4>;
 282                                 reg = <0xf9024000 0x1000>;
 283                                 status = "disabled";
 284                         };
 285
 286                         frame@f9025000 {
 287                                 frame-number = <3>;
 288                                 interrupts = <0 11 0x4>;
 289                                 reg = <0xf9025000 0x1000>;
 290                                 status = "disabled";
 291                         };
 292
 293                         frame@f9026000 {
 294                                 frame-number = <4>;
 295                                 interrupts = <0 12 0x4>;
 296                                 reg = <0xf9026000 0x1000>;
 297                                 status = "disabled";
 298                         };
 299
 300                         frame@f9027000 {
 301                                 frame-number = <5>;
 302                                 interrupts = <0 13 0x4>;
 303                                 reg = <0xf9027000 0x1000>;
 304                                 status = "disabled";
 305                         };
 306
 307                         frame@f9028000 {
 308                                 frame-number = <6>;
 309                                 interrupts = <0 14 0x4>;
 310                                 reg = <0xf9028000 0x1000>;
 311                                 status = "disabled";
 312                         };
 313                 };
 314
 315                 saw0: power-controller@f9089000 {
 316                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 317                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 318                 };
 319
 320                 saw1: power-controller@f9099000 {
 321                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 322                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 323                 };
 324
 325                 saw2: power-controller@f90a9000 {
 326                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 327                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 328                 };
 329
 330                 saw3: power-controller@f90b9000 {
 331                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 332                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 333                 };
 334
 335                 saw_l2: power-controller@f9012000 {
 336                         compatible = "qcom,saw2";
 337                         reg = <0xf9012000 0x1000>;
 338                         regulator;
 339                 };
 340
 341                 acc0: clock-controller@f9088000 {
 342                         compatible = "qcom,kpss-acc-v2";
 343                         reg = <0xf9088000 0x1000>,
 344                               <0xf9008000 0x1000>;
 345                 };
 346
 347                 acc1: clock-controller@f9098000 {
 348                         compatible = "qcom,kpss-acc-v2";
 349                         reg = <0xf9098000 0x1000>,
 350                               <0xf9008000 0x1000>;
 351                 };
 352
 353                 acc2: clock-controller@f90a8000 {
 354                         compatible = "qcom,kpss-acc-v2";
 355                         reg = <0xf90a8000 0x1000>,
 356                               <0xf9008000 0x1000>;
 357                 };
 358
 359                 acc3: clock-controller@f90b8000 {
 360                         compatible = "qcom,kpss-acc-v2";
 361                         reg = <0xf90b8000 0x1000>,
 362                               <0xf9008000 0x1000>;
 363                 };
 364
 365                 restart@fc4ab000 {
 366                         compatible = "qcom,pshold";
 367                         reg = <0xfc4ab000 0x4>;
 368                 };
 369
 370                 gcc: clock-controller@fc400000 {
 371                         compatible = "qcom,gcc-apq8084";
 372                         #clock-cells = <1>;
 373                         #reset-cells = <1>;
 374                         #power-domain-cells = <1>;
 375                         reg = <0xfc400000 0x4000>;
 376                 };
 377
 378                 tcsr_mutex_regs: syscon@fd484000 {
 379                         compatible = "syscon";
 380                         reg = <0xfd484000 0x2000>;
 381                 };
 382
 383                 tcsr_mutex: hwlock {
 384                         compatible = "qcom,tcsr-mutex";
 385                         syscon = <&tcsr_mutex_regs 0 0x80>;
 386                         #hwlock-cells = <1>;
 387                 };
 388
 389                 rpm_msg_ram: memory@fc428000 {
 390                         compatible = "qcom,rpm-msg-ram";
 391                         reg = <0xfc428000 0x4000>;
 392                 };
 393
 394                 tlmm: pinctrl@fd510000 {
 395                         compatible = "qcom,apq8084-pinctrl";
 396                         reg = <0xfd510000 0x4000>;
 397                         gpio-controller;
 398                         #gpio-cells = <2>;
 399                         interrupt-controller;
 400                         #interrupt-cells = <2>;
 401                         interrupts = <0 208 0>;
 402                 };
 403
 404                 blsp2_uart2: serial@f995e000 {
 405                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 406                         reg = <0xf995e000 0x1000>;
 407                         interrupts = <0 114 0x0>;
 408                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 409                         clock-names = "core", "iface";
 410                         status = "disabled";
 411                 };
 412
 413                 sdhci@f9824900 {
 414                         compatible = "qcom,sdhci-msm-v4";
 415                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 416                         reg-names = "hc_mem", "core_mem";
 417                         interrupts = <0 123 0>, <0 138 0>;
 418                         interrupt-names = "hc_irq", "pwr_irq";
 419                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 420                         clock-names = "core", "iface";
 421                         status = "disabled";
 422                 };
 423
 424                 sdhci@f98a4900 {
 425                         compatible = "qcom,sdhci-msm-v4";
 426                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 427                         reg-names = "hc_mem", "core_mem";
 428                         interrupts = <0 125 0>, <0 221 0>;
 429                         interrupt-names = "hc_irq", "pwr_irq";
 430                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 431                         clock-names = "core", "iface";
 432                         status = "disabled";
 433                 };
 434
 435                 spmi_bus: spmi@fc4cf000 {
 436                         compatible = "qcom,spmi-pmic-arb";
 437                         reg-names = "core", "intr", "cnfg";
 438                         reg = <0xfc4cf000 0x1000>,
 439                               <0xfc4cb000 0x1000>,
 440                               <0xfc4ca000 0x1000>;
 441                         interrupt-names = "periph_irq";
 442                         interrupts = <0 190 0>;
 443                         qcom,ee = <0>;
 444                         qcom,channel = <0>;
 445                         #address-cells = <2>;
 446                         #size-cells = <0>;
 447                         interrupt-controller;
 448                         #interrupt-cells = <4>;
 449                 };
 450         };
 451
 452         smd {
 453                 compatible = "qcom,smd";
 454
 455                 rpm {
 456                         interrupts = <0 168 1>;
 457                         qcom,ipc = <&apcs 8 0>;
 458                         qcom,smd-edge = <15>;
 459
 460                         rpm_requests {
 461                                 compatible = "qcom,rpm-apq8084";
 462                                 qcom,smd-channels = "rpm_requests";
 463
 464                                 pma8084-regulators {
 465                                         compatible = "qcom,rpm-pma8084-regulators";
 466
 467                                         pma8084_s1: s1 {};
 468                                         pma8084_s2: s2 {};
 469                                         pma8084_s3: s3 {};
 470                                         pma8084_s4: s4 {};
 471                                         pma8084_s5: s5 {};
 472                                         pma8084_s6: s6 {};
 473                                         pma8084_s7: s7 {};
 474                                         pma8084_s8: s8 {};
 475                                         pma8084_s9: s9 {};
 476                                         pma8084_s10: s10 {};
 477                                         pma8084_s11: s11 {};
 478                                         pma8084_s12: s12 {};
 479
 480                                         pma8084_l1: l1 {};
 481                                         pma8084_l2: l2 {};
 482                                         pma8084_l3: l3 {};
 483                                         pma8084_l4: l4 {};
 484                                         pma8084_l5: l5 {};
 485                                         pma8084_l6: l6 {};
 486                                         pma8084_l7: l7 {};
 487                                         pma8084_l8: l8 {};
 488                                         pma8084_l9: l9 {};
 489                                         pma8084_l10: l10 {};
 490                                         pma8084_l11: l11 {};
 491                                         pma8084_l12: l12 {};
 492                                         pma8084_l13: l13 {};
 493                                         pma8084_l14: l14 {};
 494                                         pma8084_l15: l15 {};
 495                                         pma8084_l16: l16 {};
 496                                         pma8084_l17: l17 {};
 497                                         pma8084_l18: l18 {};
 498                                         pma8084_l19: l19 {};
 499                                         pma8084_l20: l20 {};
 500                                         pma8084_l21: l21 {};
 501                                         pma8084_l22: l22 {};
 502                                         pma8084_l23: l23 {};
 503                                         pma8084_l24: l24 {};
 504                                         pma8084_l25: l25 {};
 505                                         pma8084_l26: l26 {};
 506                                         pma8084_l27: l27 {};
 507
 508                                         pma8084_lvs1: lvs1 {};
 509                                         pma8084_lvs2: lvs2 {};
 510                                         pma8084_lvs3: lvs3 {};
 511                                         pma8084_lvs4: lvs4 {};
 512
 513                                         pma8084_5vs1: 5vs1 {};
 514                                 };
 515                         };
 516                 };
 517         };
 518 };