arch/arm/boot/dts/r8a7792.dtsi

   1 /*
   2  * Device Tree Source for the r8a7792 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7792-clock.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a7792-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7792";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 spi0 = &qspi;
  29                 vin0 = &vin0;
  30                 vin1 = &vin1;
  31                 vin2 = &vin2;
  32                 vin3 = &vin3;
  33                 vin4 = &vin4;
  34                 vin5 = &vin5;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40                 enable-method = "renesas,apmu";
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0>;
  46                         clock-frequency = <1000000000>;
  47                         clocks = <&cpg_clocks R8A7792_CLK_Z>;
  48                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  49                         next-level-cache = <&L2_CA15>;
  50                 };
  51
  52                 cpu1: cpu@1 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <1>;
  56                         clock-frequency = <1000000000>;
  57                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  58                         next-level-cache = <&L2_CA15>;
  59                 };
  60
  61                 L2_CA15: cache-controller@0 {
  62                         compatible = "cache";
  63                         reg = <0>;
  64                         cache-unified;
  65                         cache-level = <2>;
  66                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  67                 };
  68         };
  69
  70         soc {
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&gic>;
  73
  74                 #address-cells = <2>;
  75                 #size-cells = <2>;
  76                 ranges;
  77
  78                 apmu@e6152000 {
  79                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
  80                         reg = <0 0xe6152000 0 0x188>;
  81                         cpus = <&cpu0 &cpu1>;
  82                 };
  83
  84                 gic: interrupt-controller@f1001000 {
  85                         compatible = "arm,gic-400";
  86                         #interrupt-cells = <3>;
  87                         interrupt-controller;
  88                         reg = <0 0xf1001000 0 0x1000>,
  89                               <0 0xf1002000 0 0x1000>,
  90                               <0 0xf1004000 0 0x2000>,
  91                               <0 0xf1006000 0 0x2000>;
  92                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  93                                       IRQ_TYPE_LEVEL_HIGH)>;
  94                 };
  95
  96                 irqc: interrupt-controller@e61c0000 {
  97                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
  98                         #interrupt-cells = <2>;
  99                         interrupt-controller;
 100                         reg = <0 0xe61c0000 0 0x200>;
 101                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
 106                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 107                 };
 108
 109                 timer {
 110                         compatible = "arm,armv7-timer";
 111                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 112                                       IRQ_TYPE_LEVEL_LOW)>,
 113                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 114                                       IRQ_TYPE_LEVEL_LOW)>,
 115                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 116                                       IRQ_TYPE_LEVEL_LOW)>,
 117                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 118                                       IRQ_TYPE_LEVEL_LOW)>;
 119                 };
 120
 121                 sysc: system-controller@e6180000 {
 122                         compatible = "renesas,r8a7792-sysc";
 123                         reg = <0 0xe6180000 0 0x0200>;
 124                         #power-domain-cells = <1>;
 125                 };
 126
 127                 pfc: pin-controller@e6060000 {
 128                         compatible = "renesas,pfc-r8a7792";
 129                         reg = <0 0xe6060000 0 0x144>;
 130                 };
 131
 132                 gpio0: gpio@e6050000 {
 133                         compatible = "renesas,gpio-r8a7792",
 134                                      "renesas,gpio-rcar";
 135                         reg = <0 0xe6050000 0 0x50>;
 136                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 137                         #gpio-cells = <2>;
 138                         gpio-controller;
 139                         gpio-ranges = <&pfc 0 0 29>;
 140                         #interrupt-cells = <2>;
 141                         interrupt-controller;
 142                         clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
 143                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 144                 };
 145
 146                 gpio1: gpio@e6051000 {
 147                         compatible = "renesas,gpio-r8a7792",
 148                                      "renesas,gpio-rcar";
 149                         reg = <0 0xe6051000 0 0x50>;
 150                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 151                         #gpio-cells = <2>;
 152                         gpio-controller;
 153                         gpio-ranges = <&pfc 0 32 23>;
 154                         #interrupt-cells = <2>;
 155                         interrupt-controller;
 156                         clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
 157                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 158                 };
 159
 160                 gpio2: gpio@e6052000 {
 161                         compatible = "renesas,gpio-r8a7792",
 162                                      "renesas,gpio-rcar";
 163                         reg = <0 0xe6052000 0 0x50>;
 164                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 165                         #gpio-cells = <2>;
 166                         gpio-controller;
 167                         gpio-ranges = <&pfc 0 64 32>;
 168                         #interrupt-cells = <2>;
 169                         interrupt-controller;
 170                         clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
 171                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 172                 };
 173
 174                 gpio3: gpio@e6053000 {
 175                         compatible = "renesas,gpio-r8a7792",
 176                                      "renesas,gpio-rcar";
 177                         reg = <0 0xe6053000 0 0x50>;
 178                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 179                         #gpio-cells = <2>;
 180                         gpio-controller;
 181                         gpio-ranges = <&pfc 0 96 28>;
 182                         #interrupt-cells = <2>;
 183                         interrupt-controller;
 184                         clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
 185                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 186                 };
 187
 188                 gpio4: gpio@e6054000 {
 189                         compatible = "renesas,gpio-r8a7792",
 190                                      "renesas,gpio-rcar";
 191                         reg = <0 0xe6054000 0 0x50>;
 192                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 193                         #gpio-cells = <2>;
 194                         gpio-controller;
 195                         gpio-ranges = <&pfc 0 128 17>;
 196                         #interrupt-cells = <2>;
 197                         interrupt-controller;
 198                         clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
 199                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 200                 };
 201
 202                 gpio5: gpio@e6055000 {
 203                         compatible = "renesas,gpio-r8a7792",
 204                                      "renesas,gpio-rcar";
 205                         reg = <0 0xe6055000 0 0x50>;
 206                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 207                         #gpio-cells = <2>;
 208                         gpio-controller;
 209                         gpio-ranges = <&pfc 0 160 17>;
 210                         #interrupt-cells = <2>;
 211                         interrupt-controller;
 212                         clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
 213                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 214                 };
 215
 216                 gpio6: gpio@e6055100 {
 217                         compatible = "renesas,gpio-r8a7792",
 218                                      "renesas,gpio-rcar";
 219                         reg = <0 0xe6055100 0 0x50>;
 220                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 221                         #gpio-cells = <2>;
 222                         gpio-controller;
 223                         gpio-ranges = <&pfc 0 192 17>;
 224                         #interrupt-cells = <2>;
 225                         interrupt-controller;
 226                         clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
 227                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 228                 };
 229
 230                 gpio7: gpio@e6055200 {
 231                         compatible = "renesas,gpio-r8a7792",
 232                                      "renesas,gpio-rcar";
 233                         reg = <0 0xe6055200 0 0x50>;
 234                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 235                         #gpio-cells = <2>;
 236                         gpio-controller;
 237                         gpio-ranges = <&pfc 0 224 17>;
 238                         #interrupt-cells = <2>;
 239                         interrupt-controller;
 240                         clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
 241                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 242                 };
 243
 244                 gpio8: gpio@e6055300 {
 245                         compatible = "renesas,gpio-r8a7792",
 246                                      "renesas,gpio-rcar";
 247                         reg = <0 0xe6055300 0 0x50>;
 248                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 249                         #gpio-cells = <2>;
 250                         gpio-controller;
 251                         gpio-ranges = <&pfc 0 256 17>;
 252                         #interrupt-cells = <2>;
 253                         interrupt-controller;
 254                         clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
 255                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 256                 };
 257
 258                 gpio9: gpio@e6055400 {
 259                         compatible = "renesas,gpio-r8a7792",
 260                                      "renesas,gpio-rcar";
 261                         reg = <0 0xe6055400 0 0x50>;
 262                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 263                         #gpio-cells = <2>;
 264                         gpio-controller;
 265                         gpio-ranges = <&pfc 0 288 17>;
 266                         #interrupt-cells = <2>;
 267                         interrupt-controller;
 268                         clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
 269                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 270                 };
 271
 272                 gpio10: gpio@e6055500 {
 273                         compatible = "renesas,gpio-r8a7792",
 274                                      "renesas,gpio-rcar";
 275                         reg = <0 0xe6055500 0 0x50>;
 276                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 277                         #gpio-cells = <2>;
 278                         gpio-controller;
 279                         gpio-ranges = <&pfc 0 320 32>;
 280                         #interrupt-cells = <2>;
 281                         interrupt-controller;
 282                         clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
 283                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 284                 };
 285
 286                 gpio11: gpio@e6055600 {
 287                         compatible = "renesas,gpio-r8a7792",
 288                                      "renesas,gpio-rcar";
 289                         reg = <0 0xe6055600 0 0x50>;
 290                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 291                         #gpio-cells = <2>;
 292                         gpio-controller;
 293                         gpio-ranges = <&pfc 0 352 30>;
 294                         #interrupt-cells = <2>;
 295                         interrupt-controller;
 296                         clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
 297                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 298                 };
 299
 300                 dmac0: dma-controller@e6700000 {
 301                         compatible = "renesas,dmac-r8a7792",
 302                                      "renesas,rcar-dmac";
 303                         reg = <0 0xe6700000 0 0x20000>;
 304                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 305                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 306                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 307                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 308                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 309                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 310                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 311                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 312                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 313                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 314                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 315                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 316                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 317                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 318                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 319                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 320                         interrupt-names = "error",
 321                                           "ch0", "ch1", "ch2", "ch3",
 322                                           "ch4", "ch5", "ch6", "ch7",
 323                                           "ch8", "ch9", "ch10", "ch11",
 324                                           "ch12", "ch13", "ch14";
 325                         clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
 326                         clock-names = "fck";
 327                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 328                         #dma-cells = <1>;
 329                         dma-channels = <15>;
 330                 };
 331
 332                 dmac1: dma-controller@e6720000 {
 333                         compatible = "renesas,dmac-r8a7792",
 334                                      "renesas,rcar-dmac";
 335                         reg = <0 0xe6720000 0 0x20000>;
 336                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 337                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 338                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 339                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 340                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 341                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 342                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 343                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 344                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 345                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 346                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 347                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 348                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 349                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 350                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 351                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 352                         interrupt-names = "error",
 353                                           "ch0", "ch1", "ch2", "ch3",
 354                                           "ch4", "ch5", "ch6", "ch7",
 355                                           "ch8", "ch9", "ch10", "ch11",
 356                                           "ch12", "ch13", "ch14";
 357                         clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
 358                         clock-names = "fck";
 359                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 360                         #dma-cells = <1>;
 361                         dma-channels = <15>;
 362                 };
 363
 364                 scif0: serial@e6e60000 {
 365                         compatible = "renesas,scif-r8a7792",
 366                                      "renesas,rcar-gen2-scif", "renesas,scif";
 367                         reg = <0 0xe6e60000 0 64>;
 368                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
 370                                  <&scif_clk>;
 371                         clock-names = "fck", "brg_int", "scif_clk";
 372                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 373                                <&dmac1 0x29>, <&dmac1 0x2a>;
 374                         dma-names = "tx", "rx", "tx", "rx";
 375                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 376                         status = "disabled";
 377                 };
 378
 379                 scif1: serial@e6e68000 {
 380                         compatible = "renesas,scif-r8a7792",
 381                                      "renesas,rcar-gen2-scif", "renesas,scif";
 382                         reg = <0 0xe6e68000 0 64>;
 383                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
 385                                  <&scif_clk>;
 386                         clock-names = "fck", "brg_int", "scif_clk";
 387                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 388                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 389                         dma-names = "tx", "rx", "tx", "rx";
 390                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 391                         status = "disabled";
 392                 };
 393
 394                 scif2: serial@e6e58000 {
 395                         compatible = "renesas,scif-r8a7792",
 396                                      "renesas,rcar-gen2-scif", "renesas,scif";
 397                         reg = <0 0xe6e58000 0 64>;
 398                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 399                         clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
 400                                  <&scif_clk>;
 401                         clock-names = "fck", "brg_int", "scif_clk";
 402                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 403                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 404                         dma-names = "tx", "rx", "tx", "rx";
 405                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 406                         status = "disabled";
 407                 };
 408
 409                 scif3: serial@e6ea8000 {
 410                         compatible = "renesas,scif-r8a7792",
 411                                      "renesas,rcar-gen2-scif", "renesas,scif";
 412                         reg = <0 0xe6ea8000 0 64>;
 413                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
 415                                  <&scif_clk>;
 416                         clock-names = "fck", "brg_int", "scif_clk";
 417                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 418                                <&dmac1 0x2f>, <&dmac1 0x30>;
 419                         dma-names = "tx", "rx", "tx", "rx";
 420                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 421                         status = "disabled";
 422                 };
 423
 424                 hscif0: serial@e62c0000 {
 425                         compatible = "renesas,hscif-r8a7792",
 426                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 427                         reg = <0 0xe62c0000 0 96>;
 428                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
 430                                  <&scif_clk>;
 431                         clock-names = "fck", "brg_int", "scif_clk";
 432                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 433                                <&dmac1 0x39>, <&dmac1 0x3a>;
 434                         dma-names = "tx", "rx", "tx", "rx";
 435                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 436                         status = "disabled";
 437                 };
 438
 439                 hscif1: serial@e62c8000 {
 440                         compatible = "renesas,hscif-r8a7792",
 441                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 442                         reg = <0 0xe62c8000 0 96>;
 443                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 444                         clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
 445                                  <&scif_clk>;
 446                         clock-names = "fck", "brg_int", "scif_clk";
 447                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 448                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 449                         dma-names = "tx", "rx", "tx", "rx";
 450                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 451                         status = "disabled";
 452                 };
 453
 454                 sdhi0: sd@ee100000 {
 455                         compatible = "renesas,sdhi-r8a7792";
 456                         reg = <0 0xee100000 0 0x328>;
 457                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 458                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 459                                <&dmac1 0xcd>, <&dmac1 0xce>;
 460                         dma-names = "tx", "rx", "tx", "rx";
 461                         clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
 462                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 463                         status = "disabled";
 464                 };
 465
 466                 jpu: jpeg-codec@fe980000 {
 467                         compatible = "renesas,jpu-r8a7792",
 468                                      "renesas,rcar-gen2-jpu";
 469                         reg = <0 0xfe980000 0 0x10300>;
 470                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&mstp1_clks R8A7792_CLK_JPU>;
 472                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 473                 };
 474
 475                 avb: ethernet@e6800000 {
 476                         compatible = "renesas,etheravb-r8a7792",
 477                                      "renesas,etheravb-rcar-gen2";
 478                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 479                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
 481                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         status = "disabled";
 485                 };
 486
 487                 /* I2C doesn't need pinmux */
 488                 i2c0: i2c@e6508000 {
 489                         compatible = "renesas,i2c-r8a7792";
 490                         reg = <0 0xe6508000 0 0x40>;
 491                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
 493                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 494                         i2c-scl-internal-delay-ns = <6>;
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         status = "disabled";
 498                 };
 499
 500                 i2c1: i2c@e6518000 {
 501                         compatible = "renesas,i2c-r8a7792";
 502                         reg = <0 0xe6518000 0 0x40>;
 503                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
 505                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 506                         i2c-scl-internal-delay-ns = <6>;
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c2: i2c@e6530000 {
 513                         compatible = "renesas,i2c-r8a7792";
 514                         reg = <0 0xe6530000 0 0x40>;
 515                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
 517                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 518                         i2c-scl-internal-delay-ns = <6>;
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                         status = "disabled";
 522                 };
 523
 524                 i2c3: i2c@e6540000 {
 525                         compatible = "renesas,i2c-r8a7792";
 526                         reg = <0 0xe6540000 0 0x40>;
 527                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
 529                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 530                         i2c-scl-internal-delay-ns = <6>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         status = "disabled";
 534                 };
 535
 536                 i2c4: i2c@e6520000 {
 537                         compatible = "renesas,i2c-r8a7792";
 538                         reg = <0 0xe6520000 0 0x40>;
 539                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
 541                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 542                         i2c-scl-internal-delay-ns = <6>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         status = "disabled";
 546                 };
 547
 548                 i2c5: i2c@e6528000 {
 549                         compatible = "renesas,i2c-r8a7792";
 550                         reg = <0 0xe6528000 0 0x40>;
 551                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
 553                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 554                         i2c-scl-internal-delay-ns = <110>;
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         status = "disabled";
 558                 };
 559
 560                 qspi: spi@e6b10000 {
 561                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 562                         reg = <0 0xe6b10000 0 0x2c>;
 563                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
 565                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 566                                <&dmac1 0x17>, <&dmac1 0x18>;
 567                         dma-names = "tx", "rx", "tx", "rx";
 568                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 569                         num-cs = <1>;
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         status = "disabled";
 573                 };
 574
 575                 du: display@feb00000 {
 576                         compatible = "renesas,du-r8a7792";
 577                         reg = <0 0xfeb00000 0 0x40000>;
 578                         reg-names = "du";
 579                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 581                         clocks = <&mstp7_clks R8A7792_CLK_DU0>,
 582                                  <&mstp7_clks R8A7792_CLK_DU1>;
 583                         clock-names = "du.0", "du.1";
 584                         status = "disabled";
 585
 586                         ports {
 587                                 #address-cells = <1>;
 588                                 #size-cells = <0>;
 589
 590                                 port@0 {
 591                                         reg = <0>;
 592                                         du_out_rgb0: endpoint {
 593                                         };
 594                                 };
 595                                 port@1 {
 596                                         reg = <1>;
 597                                         du_out_rgb1: endpoint {
 598                                         };
 599                                 };
 600                         };
 601                 };
 602
 603                 can0: can@e6e80000 {
 604                         compatible = "renesas,can-r8a7792",
 605                                      "renesas,rcar-gen2-can";
 606                         reg = <0 0xe6e80000 0 0x1000>;
 607                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
 609                                  <&rcan_clk>, <&can_clk>;
 610                         clock-names = "clkp1", "clkp2", "can_clk";
 611                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 612                         status = "disabled";
 613                 };
 614
 615                 can1: can@e6e88000 {
 616                         compatible = "renesas,can-r8a7792",
 617                                      "renesas,rcar-gen2-can";
 618                         reg = <0 0xe6e88000 0 0x1000>;
 619                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 620                         clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
 621                                  <&rcan_clk>, <&can_clk>;
 622                         clock-names = "clkp1", "clkp2", "can_clk";
 623                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 624                         status = "disabled";
 625                 };
 626
 627                 vin0: video@e6ef0000 {
 628                         compatible = "renesas,vin-r8a7792",
 629                                      "renesas,rcar-gen2-vin";
 630                         reg = <0 0xe6ef0000 0 0x1000>;
 631                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
 633                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 634                         status = "disabled";
 635                 };
 636
 637                 vin1: video@e6ef1000 {
 638                         compatible = "renesas,vin-r8a7792",
 639                                      "renesas,rcar-gen2-vin";
 640                         reg = <0 0xe6ef1000 0 0x1000>;
 641                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 642                         clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
 643                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 644                         status = "disabled";
 645                 };
 646
 647                 vin2: video@e6ef2000 {
 648                         compatible = "renesas,vin-r8a7792",
 649                                      "renesas,rcar-gen2-vin";
 650                         reg = <0 0xe6ef2000 0 0x1000>;
 651                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 652                         clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
 653                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 654                         status = "disabled";
 655                 };
 656
 657                 vin3: video@e6ef3000 {
 658                         compatible = "renesas,vin-r8a7792",
 659                                      "renesas,rcar-gen2-vin";
 660                         reg = <0 0xe6ef3000 0 0x1000>;
 661                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 662                         clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
 663                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 664                         status = "disabled";
 665                 };
 666
 667                 vin4: video@e6ef4000 {
 668                         compatible = "renesas,vin-r8a7792",
 669                                      "renesas,rcar-gen2-vin";
 670                         reg = <0 0xe6ef4000 0 0x1000>;
 671                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 672                         clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
 673                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 674                         status = "disabled";
 675                 };
 676
 677                 vin5: video@e6ef5000 {
 678                         compatible = "renesas,vin-r8a7792",
 679                                      "renesas,rcar-gen2-vin";
 680                         reg = <0 0xe6ef5000 0 0x1000>;
 681                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 682                         clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
 683                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 684                         status = "disabled";
 685                 };
 686
 687                 vsp1@fe928000 {
 688                         compatible = "renesas,vsp1";
 689                         reg = <0 0xfe928000 0 0x8000>;
 690                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
 692                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 693                 };
 694
 695                 vsp1@fe930000 {
 696                         compatible = "renesas,vsp1";
 697                         reg = <0 0xfe930000 0 0x8000>;
 698                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 699                         clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
 700                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 701                 };
 702
 703                 vsp1@fe938000 {
 704                         compatible = "renesas,vsp1";
 705                         reg = <0 0xfe938000 0 0x8000>;
 706                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
 708                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 709                 };
 710
 711                 /* Special CPG clocks */
 712                 cpg_clocks: cpg_clocks@e6150000 {
 713                         compatible = "renesas,r8a7792-cpg-clocks",
 714                                      "renesas,rcar-gen2-cpg-clocks";
 715                         reg = <0 0xe6150000 0 0x1000>;
 716                         clocks = <&extal_clk>;
 717                         #clock-cells = <1>;
 718                         clock-output-names = "main", "pll0", "pll1", "pll3",
 719                                              "lb", "qspi", "z";
 720                         #power-domain-cells = <0>;
 721                 };
 722
 723                 /* Fixed factor clocks */
 724                 pll1_div2_clk: pll1_div2 {
 725                         compatible = "fixed-factor-clock";
 726                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 727                         #clock-cells = <0>;
 728                         clock-div = <2>;
 729                         clock-mult = <1>;
 730                 };
 731                 zx_clk: zx {
 732                         compatible = "fixed-factor-clock";
 733                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 734                         #clock-cells = <0>;
 735                         clock-div = <3>;
 736                         clock-mult = <1>;
 737                 };
 738                 zs_clk: zs {
 739                         compatible = "fixed-factor-clock";
 740                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 741                         #clock-cells = <0>;
 742                         clock-div = <6>;
 743                         clock-mult = <1>;
 744                 };
 745                 hp_clk: hp {
 746                         compatible = "fixed-factor-clock";
 747                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 748                         #clock-cells = <0>;
 749                         clock-div = <12>;
 750                         clock-mult = <1>;
 751                 };
 752                 p_clk: p {
 753                         compatible = "fixed-factor-clock";
 754                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 755                         #clock-cells = <0>;
 756                         clock-div = <24>;
 757                         clock-mult = <1>;
 758                 };
 759                 cp_clk: cp {
 760                         compatible = "fixed-factor-clock";
 761                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 762                         #clock-cells = <0>;
 763                         clock-div = <48>;
 764                         clock-mult = <1>;
 765                 };
 766                 m2_clk: m2 {
 767                         compatible = "fixed-factor-clock";
 768                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 769                         #clock-cells = <0>;
 770                         clock-div = <8>;
 771                         clock-mult = <1>;
 772                 };
 773                 sd_clk: sd {
 774                         compatible = "fixed-factor-clock";
 775                         clocks = <&pll1_div2_clk>;
 776                         #clock-cells = <0>;
 777                         clock-div = <8>;
 778                         clock-mult = <1>;
 779                 };
 780                 rcan_clk: rcan {
 781                         compatible = "fixed-factor-clock";
 782                         clocks = <&pll1_div2_clk>;
 783                         #clock-cells = <0>;
 784                         clock-div = <49>;
 785                         clock-mult = <1>;
 786                 };
 787                 zg_clk: zg {
 788                         compatible = "fixed-factor-clock";
 789                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 790                         #clock-cells = <0>;
 791                         clock-div = <5>;
 792                         clock-mult = <1>;
 793                 };
 794
 795                 /* Gate clocks */
 796                 mstp1_clks: mstp1_clks@e6150134 {
 797                         compatible = "renesas,r8a7792-mstp-clocks",
 798                                      "renesas,cpg-mstp-clocks";
 799                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 800                         clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 801                         #clock-cells = <1>;
 802                         clock-indices = <
 803                                 R8A7792_CLK_JPU
 804                                 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
 805                                 R8A7792_CLK_VSP1_SY
 806                         >;
 807                         clock-output-names = "jpu", "vsp1du1", "vsp1du0",
 808                                              "vsp1-sy";
 809                 };
 810                 mstp2_clks: mstp2_clks@e6150138 {
 811                         compatible = "renesas,r8a7792-mstp-clocks",
 812                                      "renesas,cpg-mstp-clocks";
 813                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 814                         clocks = <&zs_clk>, <&zs_clk>;
 815                         #clock-cells = <1>;
 816                         clock-indices = <
 817                                 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
 818                         >;
 819                         clock-output-names = "sys-dmac1", "sys-dmac0";
 820                 };
 821                 mstp3_clks: mstp3_clks@e615013c {
 822                         compatible = "renesas,r8a7792-mstp-clocks",
 823                                      "renesas,cpg-mstp-clocks";
 824                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 825                         clocks = <&sd_clk>;
 826                         #clock-cells = <1>;
 827                         renesas,clock-indices = <R8A7792_CLK_SDHI0>;
 828                         clock-output-names = "sdhi0";
 829                 };
 830                 mstp4_clks: mstp4_clks@e6150140 {
 831                         compatible = "renesas,r8a7792-mstp-clocks",
 832                                      "renesas,cpg-mstp-clocks";
 833                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 834                         clocks = <&cp_clk>;
 835                         #clock-cells = <1>;
 836                         clock-indices = <R8A7792_CLK_IRQC>;
 837                         clock-output-names = "irqc";
 838                 };
 839                 mstp7_clks: mstp7_clks@e615014c {
 840                         compatible = "renesas,r8a7792-mstp-clocks",
 841                                      "renesas,cpg-mstp-clocks";
 842                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 843                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
 844                                  <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
 845                         #clock-cells = <1>;
 846                         clock-indices = <
 847                                 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
 848                                 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
 849                                 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
 850                                 R8A7792_CLK_DU1 R8A7792_CLK_DU0
 851                         >;
 852                         clock-output-names = "hscif1", "hscif0", "scif3",
 853                                              "scif2", "scif1", "scif0",
 854                                              "du1", "du0";
 855                 };
 856                 mstp8_clks: mstp8_clks@e6150990 {
 857                         compatible = "renesas,r8a7792-mstp-clocks",
 858                                      "renesas,cpg-mstp-clocks";
 859                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 860                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
 861                                  <&zg_clk>, <&zg_clk>, <&hp_clk>;
 862                         #clock-cells = <1>;
 863                         clock-indices = <
 864                                 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
 865                                 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
 866                                 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
 867                                 R8A7792_CLK_ETHERAVB
 868                         >;
 869                         clock-output-names = "vin5", "vin4", "vin3", "vin2",
 870                                              "vin1", "vin0", "etheravb";
 871                 };
 872                 mstp9_clks: mstp9_clks@e6150994 {
 873                         compatible = "renesas,r8a7792-mstp-clocks",
 874                                      "renesas,cpg-mstp-clocks";
 875                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 876                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 877                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 878                                  <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
 879                                  <&cpg_clocks R8A7792_CLK_QSPI>,
 880                                  <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
 881                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 882                         #clock-cells = <1>;
 883                         clock-indices = <
 884                                 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
 885                                 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
 886                                 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
 887                                 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
 888                                 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
 889                                 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
 890                                 R8A7792_CLK_QSPI_MOD
 891                                 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
 892                                 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
 893                                 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
 894                                 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
 895                         >;
 896                         clock-output-names =
 897                                 "gpio7", "gpio6", "gpio5", "gpio4",
 898                                 "gpio3", "gpio2", "gpio1", "gpio0",
 899                                 "gpio11", "gpio10", "can1", "can0",
 900                                 "qspi_mod", "gpio9", "gpio8",
 901                                 "i2c5", "i2c4", "i2c3", "i2c2",
 902                                 "i2c1", "i2c0";
 903                 };
 904         };
 905
 906         /* External root clock */
 907         extal_clk: extal {
 908                 compatible = "fixed-clock";
 909                 #clock-cells = <0>;
 910                 /* This value must be overridden by the board. */
 911                 clock-frequency = <0>;
 912         };
 913
 914         /* External SCIF clock */
 915         scif_clk: scif {
 916                 compatible = "fixed-clock";
 917                 #clock-cells = <0>;
 918                 /* This value must be overridden by the board. */
 919                 clock-frequency = <0>;
 920         };
 921
 922         /* External CAN clock */
 923         can_clk: can {
 924                 compatible = "fixed-clock";
 925                 #clock-cells = <0>;
 926                 /* This value must be overridden by the board. */
 927                 clock-frequency = <0>;
 928         };
 929 };