arch/arm/boot/dts/r8a7794-alt.dts

   1 /*
   2  * Device Tree Source for the Alt board
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12 #include "r8a7794.dtsi"
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         model = "Alt";
  17         compatible = "renesas,alt", "renesas,r8a7794";
  18
  19         aliases {
  20                 serial0 = &scif2;
  21         };
  22
  23         chosen {
  24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         memory@40000000 {
  29                 device_type = "memory";
  30                 reg = <0 0x40000000 0 0x40000000>;
  31         };
  32
  33         d3_3v: regulator-d3-3v {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "D3.3V";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 regulator-boot-on;
  39                 regulator-always-on;
  40         };
  41
  42         vcc_sdhi0: regulator-vcc-sdhi0 {
  43                 compatible = "regulator-fixed";
  44
  45                 regulator-name = "SDHI0 Vcc";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48
  49                 gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  50                 enable-active-high;
  51         };
  52
  53         vccq_sdhi0: regulator-vccq-sdhi0 {
  54                 compatible = "regulator-gpio";
  55
  56                 regulator-name = "SDHI0 VccQ";
  57                 regulator-min-microvolt = <1800000>;
  58                 regulator-max-microvolt = <3300000>;
  59
  60                 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
  61                 gpios-states = <1>;
  62                 states = <3300000 1
  63                           1800000 0>;
  64         };
  65
  66         vcc_sdhi1: regulator-vcc-sdhi1 {
  67                 compatible = "regulator-fixed";
  68
  69                 regulator-name = "SDHI1 Vcc";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72
  73                 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  74                 enable-active-high;
  75         };
  76
  77         vccq_sdhi1: regulator-vccq-sdhi1 {
  78                 compatible = "regulator-gpio";
  79
  80                 regulator-name = "SDHI1 VccQ";
  81                 regulator-min-microvolt = <1800000>;
  82                 regulator-max-microvolt = <3300000>;
  83
  84                 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
  85                 gpios-states = <1>;
  86                 states = <3300000 1
  87                           1800000 0>;
  88         };
  89
  90         lbsc {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93         };
  94
  95         vga-encoder {
  96                 compatible = "adi,adv7123";
  97
  98                 ports {
  99                         #address-cells = <1>;
 100                         #size-cells = <0>;
 101
 102                         port@0 {
 103                                 reg = <0>;
 104                                 adv7123_in: endpoint {
 105                                         remote-endpoint = <&du_out_rgb1>;
 106                                 };
 107                         };
 108                         port@1 {
 109                                 reg = <1>;
 110                                 adv7123_out: endpoint {
 111                                         remote-endpoint = <&vga_in>;
 112                                 };
 113                         };
 114                 };
 115         };
 116
 117         vga {
 118                 compatible = "vga-connector";
 119
 120                 port {
 121                         vga_in: endpoint {
 122                                 remote-endpoint = <&adv7123_out>;
 123                         };
 124                 };
 125         };
 126
 127         x2_clk: x2-clock {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <74250000>;
 131         };
 132
 133         x13_clk: x13-clock {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <148500000>;
 137         };
 138 };
 139
 140 &du {
 141         pinctrl-0 = <&du_pins>;
 142         pinctrl-names = "default";
 143         status = "okay";
 144
 145         clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 146                  <&mstp7_clks R8A7794_CLK_DU0>,
 147                  <&x13_clk>, <&x2_clk>;
 148         clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 149
 150         ports {
 151                 port@1 {
 152                         endpoint {
 153                                 remote-endpoint = <&adv7123_in>;
 154                         };
 155                 };
 156         };
 157 };
 158
 159 &extal_clk {
 160         clock-frequency = <20000000>;
 161 };
 162
 163 &pfc {
 164         pinctrl-0 = <&scif_clk_pins>;
 165         pinctrl-names = "default";
 166
 167         du_pins: du {
 168                 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
 169                 function = "du";
 170         };
 171
 172         scif2_pins: scif2 {
 173                 groups = "scif2_data";
 174                 function = "scif2";
 175         };
 176
 177         scif_clk_pins: scif_clk {
 178                 groups = "scif_clk";
 179                 function = "scif_clk";
 180         };
 181
 182         ether_pins: ether {
 183                 groups = "eth_link", "eth_mdio", "eth_rmii";
 184                 function = "eth";
 185         };
 186
 187         phy1_pins: phy1 {
 188                 groups = "intc_irq8";
 189                 function = "intc";
 190         };
 191
 192         i2c1_pins: i2c1 {
 193                 groups = "i2c1";
 194                 function = "i2c1";
 195         };
 196
 197         vin0_pins: vin0 {
 198                 groups = "vin0_data8", "vin0_clk";
 199                 function = "vin0";
 200         };
 201
 202         mmcif0_pins: mmcif0 {
 203                 groups = "mmc_data8", "mmc_ctrl";
 204                 function = "mmc";
 205         };
 206
 207         sdhi0_pins: sd0 {
 208                 groups = "sdhi0_data4", "sdhi0_ctrl";
 209                 function = "sdhi0";
 210         };
 211
 212         sdhi1_pins: sd1 {
 213                 groups = "sdhi1_data4", "sdhi1_ctrl";
 214                 function = "sdhi1";
 215         };
 216 };
 217
 218 &cmt0 {
 219         status = "okay";
 220 };
 221
 222 &pfc {
 223         qspi_pins: qspi {
 224                 groups = "qspi_ctrl", "qspi_data4";
 225                 function = "qspi";
 226         };
 227 };
 228
 229 &ether {
 230         pinctrl-0 = <&ether_pins &phy1_pins>;
 231         pinctrl-names = "default";
 232
 233         phy-handle = <&phy1>;
 234         renesas,ether-link-active-low;
 235         status = "okay";
 236
 237         phy1: ethernet-phy@1 {
 238                 reg = <1>;
 239                 interrupt-parent = <&irqc0>;
 240                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 241                 micrel,led-mode = <1>;
 242         };
 243 };
 244
 245 &mmcif0 {
 246         pinctrl-0 = <&mmcif0_pins>;
 247         pinctrl-names = "default";
 248
 249         vmmc-supply = <&d3_3v>;
 250         vqmmc-supply = <&d3_3v>;
 251         bus-width = <8>;
 252         non-removable;
 253         status = "okay";
 254 };
 255
 256 &sdhi0 {
 257         pinctrl-0 = <&sdhi0_pins>;
 258         pinctrl-names = "default";
 259
 260         vmmc-supply = <&vcc_sdhi0>;
 261         vqmmc-supply = <&vccq_sdhi0>;
 262         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
 263         wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
 264         status = "okay";
 265 };
 266
 267 &sdhi1 {
 268         pinctrl-0 = <&sdhi1_pins>;
 269         pinctrl-names = "default";
 270
 271         vmmc-supply = <&vcc_sdhi1>;
 272         vqmmc-supply = <&vccq_sdhi1>;
 273         cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 274         wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 275         status = "okay";
 276 };
 277
 278 &i2c1 {
 279         pinctrl-0 = <&i2c1_pins>;
 280         pinctrl-names = "default";
 281
 282         status = "okay";
 283         clock-frequency = <400000>;
 284
 285         composite-in@20 {
 286                 compatible = "adi,adv7180";
 287                 reg = <0x20>;
 288                 remote = <&vin0>;
 289
 290                 port {
 291                         adv7180: endpoint {
 292                                 bus-width = <8>;
 293                                 remote-endpoint = <&vin0ep>;
 294                         };
 295                 };
 296         };
 297 };
 298
 299 &vin0 {
 300         status = "okay";
 301         pinctrl-0 = <&vin0_pins>;
 302         pinctrl-names = "default";
 303
 304         port {
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307
 308                 vin0ep: endpoint {
 309                         remote-endpoint = <&adv7180>;
 310                         bus-width = <8>;
 311                 };
 312         };
 313 };
 314
 315 &scif2 {
 316         pinctrl-0 = <&scif2_pins>;
 317         pinctrl-names = "default";
 318
 319         status = "okay";
 320 };
 321
 322 &scif_clk {
 323         clock-frequency = <14745600>;
 324         status = "okay";
 325 };
 326
 327 &qspi {
 328         pinctrl-0 = <&qspi_pins>;
 329         pinctrl-names = "default";
 330
 331         status = "okay";
 332
 333         flash@0 {
 334                 compatible = "spansion,s25fl512s", "jedec,spi-nor";
 335                 reg = <0>;
 336                 spi-max-frequency = <30000000>;
 337                 spi-tx-bus-width = <4>;
 338                 spi-rx-bus-width = <4>;
 339                 spi-cpol;
 340                 spi-cpha;
 341                 m25p,fast-read;
 342
 343                 partitions {
 344                         compatible = "fixed-partitions";
 345                         #address-cells = <1>;
 346                         #size-cells = <1>;
 347
 348                         partition@0 {
 349                                 label = "loader";
 350                                 reg = <0x00000000 0x00040000>;
 351                                 read-only;
 352                         };
 353                         partition@40000 {
 354                                 label = "system";
 355                                 reg = <0x00040000 0x00040000>;
 356                                 read-only;
 357                         };
 358                         partition@80000 {
 359                                 label = "user";
 360                                 reg = <0x00080000 0x03f80000>;
 361                         };
 362                 };
 363         };
 364 };