arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton.dtsi"
  49 #include "armv7-m.dtsi"
  50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  51
  52 / {
  53         clocks {
  54                 clk_hse: clk-hse {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-clock";
  57                         clock-frequency = <0>;
  58                 };
  59         };
  60
  61         soc {
  62                 dma-ranges = <0xc0000000 0x0 0x10000000>;
  63
  64                 timer2: timer@40000000 {
  65                         compatible = "st,stm32-timer";
  66                         reg = <0x40000000 0x400>;
  67                         interrupts = <28>;
  68                         clocks = <&rcc 0 128>;
  69                         status = "disabled";
  70                 };
  71
  72                 timer3: timer@40000400 {
  73                         compatible = "st,stm32-timer";
  74                         reg = <0x40000400 0x400>;
  75                         interrupts = <29>;
  76                         clocks = <&rcc 0 129>;
  77                         status = "disabled";
  78                 };
  79
  80                 timer4: timer@40000800 {
  81                         compatible = "st,stm32-timer";
  82                         reg = <0x40000800 0x400>;
  83                         interrupts = <30>;
  84                         clocks = <&rcc 0 130>;
  85                         status = "disabled";
  86                 };
  87
  88                 timer5: timer@40000c00 {
  89                         compatible = "st,stm32-timer";
  90                         reg = <0x40000c00 0x400>;
  91                         interrupts = <50>;
  92                         clocks = <&rcc 0 131>;
  93                 };
  94
  95                 timer6: timer@40001000 {
  96                         compatible = "st,stm32-timer";
  97                         reg = <0x40001000 0x400>;
  98                         interrupts = <54>;
  99                         clocks = <&rcc 0 132>;
 100                         status = "disabled";
 101                 };
 102
 103                 timer7: timer@40001400 {
 104                         compatible = "st,stm32-timer";
 105                         reg = <0x40001400 0x400>;
 106                         interrupts = <55>;
 107                         clocks = <&rcc 0 133>;
 108                         status = "disabled";
 109                 };
 110
 111                 usart2: serial@40004400 {
 112                         compatible = "st,stm32-usart", "st,stm32-uart";
 113                         reg = <0x40004400 0x400>;
 114                         interrupts = <38>;
 115                         clocks =  <&rcc 0 145>;
 116                         status = "disabled";
 117                 };
 118
 119                 usart3: serial@40004800 {
 120                         compatible = "st,stm32-usart", "st,stm32-uart";
 121                         reg = <0x40004800 0x400>;
 122                         interrupts = <39>;
 123                         clocks = <&rcc 0 146>;
 124                         status = "disabled";
 125                 };
 126
 127                 usart4: serial@40004c00 {
 128                         compatible = "st,stm32-uart";
 129                         reg = <0x40004c00 0x400>;
 130                         interrupts = <52>;
 131                         clocks = <&rcc 0 147>;
 132                         status = "disabled";
 133                 };
 134
 135                 usart5: serial@40005000 {
 136                         compatible = "st,stm32-uart";
 137                         reg = <0x40005000 0x400>;
 138                         interrupts = <53>;
 139                         clocks = <&rcc 0 148>;
 140                         status = "disabled";
 141                 };
 142
 143                 usart7: serial@40007800 {
 144                         compatible = "st,stm32-usart", "st,stm32-uart";
 145                         reg = <0x40007800 0x400>;
 146                         interrupts = <82>;
 147                         clocks = <&rcc 0 158>;
 148                         status = "disabled";
 149                 };
 150
 151                 usart8: serial@40007c00 {
 152                         compatible = "st,stm32-usart", "st,stm32-uart";
 153                         reg = <0x40007c00 0x400>;
 154                         interrupts = <83>;
 155                         clocks = <&rcc 0 159>;
 156                         status = "disabled";
 157                 };
 158
 159                 usart1: serial@40011000 {
 160                         compatible = "st,stm32-usart", "st,stm32-uart";
 161                         reg = <0x40011000 0x400>;
 162                         interrupts = <37>;
 163                         clocks = <&rcc 0 164>;
 164                         status = "disabled";
 165                 };
 166
 167                 usart6: serial@40011400 {
 168                         compatible = "st,stm32-usart", "st,stm32-uart";
 169                         reg = <0x40011400 0x400>;
 170                         interrupts = <71>;
 171                         clocks = <&rcc 0 165>;
 172                         status = "disabled";
 173                 };
 174
 175                 syscfg: system-config@40013800 {
 176                         compatible = "syscon";
 177                         reg = <0x40013800 0x400>;
 178                 };
 179
 180                 exti: interrupt-controller@40013c00 {
 181                         compatible = "st,stm32-exti";
 182                         interrupt-controller;
 183                         #interrupt-cells = <2>;
 184                         reg = <0x40013C00 0x400>;
 185                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 186                 };
 187
 188                 pin-controller {
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         compatible = "st,stm32f429-pinctrl";
 192                         ranges = <0 0x40020000 0x3000>;
 193                         pins-are-numbered;
 194
 195                         gpioa: gpio@40020000 {
 196                                 gpio-controller;
 197                                 #gpio-cells = <2>;
 198                                 reg = <0x0 0x400>;
 199                                 clocks = <&rcc 0 0>;
 200                                 st,bank-name = "GPIOA";
 201                         };
 202
 203                         gpiob: gpio@40020400 {
 204                                 gpio-controller;
 205                                 #gpio-cells = <2>;
 206                                 reg = <0x400 0x400>;
 207                                 clocks = <&rcc 0 1>;
 208                                 st,bank-name = "GPIOB";
 209                         };
 210
 211                         gpioc: gpio@40020800 {
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 reg = <0x800 0x400>;
 215                                 clocks = <&rcc 0 2>;
 216                                 st,bank-name = "GPIOC";
 217                         };
 218
 219                         gpiod: gpio@40020c00 {
 220                                 gpio-controller;
 221                                 #gpio-cells = <2>;
 222                                 reg = <0xc00 0x400>;
 223                                 clocks = <&rcc 0 3>;
 224                                 st,bank-name = "GPIOD";
 225                         };
 226
 227                         gpioe: gpio@40021000 {
 228                                 gpio-controller;
 229                                 #gpio-cells = <2>;
 230                                 reg = <0x1000 0x400>;
 231                                 clocks = <&rcc 0 4>;
 232                                 st,bank-name = "GPIOE";
 233                         };
 234
 235                         gpiof: gpio@40021400 {
 236                                 gpio-controller;
 237                                 #gpio-cells = <2>;
 238                                 reg = <0x1400 0x400>;
 239                                 clocks = <&rcc 0 5>;
 240                                 st,bank-name = "GPIOF";
 241                         };
 242
 243                         gpiog: gpio@40021800 {
 244                                 gpio-controller;
 245                                 #gpio-cells = <2>;
 246                                 reg = <0x1800 0x400>;
 247                                 clocks = <&rcc 0 6>;
 248                                 st,bank-name = "GPIOG";
 249                         };
 250
 251                         gpioh: gpio@40021c00 {
 252                                 gpio-controller;
 253                                 #gpio-cells = <2>;
 254                                 reg = <0x1c00 0x400>;
 255                                 clocks = <&rcc 0 7>;
 256                                 st,bank-name = "GPIOH";
 257                         };
 258
 259                         gpioi: gpio@40022000 {
 260                                 gpio-controller;
 261                                 #gpio-cells = <2>;
 262                                 reg = <0x2000 0x400>;
 263                                 clocks = <&rcc 0 8>;
 264                                 st,bank-name = "GPIOI";
 265                         };
 266
 267                         gpioj: gpio@40022400 {
 268                                 gpio-controller;
 269                                 #gpio-cells = <2>;
 270                                 reg = <0x2400 0x400>;
 271                                 clocks = <&rcc 0 9>;
 272                                 st,bank-name = "GPIOJ";
 273                         };
 274
 275                         gpiok: gpio@40022800 {
 276                                 gpio-controller;
 277                                 #gpio-cells = <2>;
 278                                 reg = <0x2800 0x400>;
 279                                 clocks = <&rcc 0 10>;
 280                                 st,bank-name = "GPIOK";
 281                         };
 282
 283                         usart1_pins_a: usart1@0 {
 284                                 pins1 {
 285                                         pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
 286                                         bias-disable;
 287                                         drive-push-pull;
 288                                         slew-rate = <0>;
 289                                 };
 290                                 pins2 {
 291                                         pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
 292                                         bias-disable;
 293                                 };
 294                         };
 295
 296                         usbotg_hs_pins_a: usbotg_hs@0 {
 297                                 pins {
 298                                         pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
 299                                                  <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
 300                                                  <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
 301                                                  <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
 302                                                  <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
 303                                                  <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
 304                                                  <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
 305                                                  <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
 306                                                  <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
 307                                                  <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
 308                                                  <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
 309                                                  <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
 310                                         bias-disable;
 311                                         drive-push-pull;
 312                                         slew-rate = <2>;
 313                                 };
 314                         };
 315
 316                         ethernet0_mii: mii@0 {
 317                                 pins {
 318                                         pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
 319                                                  <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
 320                                                  <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
 321                                                  <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
 322                                                  <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
 323                                                  <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
 324                                                  <STM32F429_PA2_FUNC_ETH_MDIO>,
 325                                                  <STM32F429_PC1_FUNC_ETH_MDC>,
 326                                                  <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
 327                                                  <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
 328                                                  <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
 329                                                  <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
 330                                                  <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
 331                                                  <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
 332                                         slew-rate = <2>;
 333                                 };
 334                         };
 335                 };
 336
 337                 rcc: rcc@40023810 {
 338                         #reset-cells = <1>;
 339                         #clock-cells = <2>;
 340                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 341                         reg = <0x40023800 0x400>;
 342                         clocks = <&clk_hse>;
 343                 };
 344
 345                 dma1: dma-controller@40026000 {
 346                         compatible = "st,stm32-dma";
 347                         reg = <0x40026000 0x400>;
 348                         interrupts = <11>,
 349                                      <12>,
 350                                      <13>,
 351                                      <14>,
 352                                      <15>,
 353                                      <16>,
 354                                      <17>,
 355                                      <47>;
 356                         clocks = <&rcc 0 21>;
 357                         #dma-cells = <4>;
 358                 };
 359
 360                 dma2: dma-controller@40026400 {
 361                         compatible = "st,stm32-dma";
 362                         reg = <0x40026400 0x400>;
 363                         interrupts = <56>,
 364                                      <57>,
 365                                      <58>,
 366                                      <59>,
 367                                      <60>,
 368                                      <68>,
 369                                      <69>,
 370                                      <70>;
 371                         clocks = <&rcc 0 22>;
 372                         #dma-cells = <4>;
 373                         st,mem2mem;
 374                 };
 375
 376                 ethernet0: dwmac@40028000 {
 377                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 378                         reg = <0x40028000 0x8000>;
 379                         reg-names = "stmmaceth";
 380                         interrupts = <61>, <62>;
 381                         interrupt-names = "macirq", "eth_wake_irq";
 382                         clock-names = "stmmaceth", "tx-clk", "rx-clk";
 383                         clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
 384                         st,syscon = <&syscfg 0x4>;
 385                         snps,pbl = <8>;
 386                         snps,mixed-burst;
 387                         dma-ranges;
 388                         status = "disabled";
 389                 };
 390
 391                 usbotg_hs: usb@40040000 {
 392                         compatible = "snps,dwc2";
 393                         dma-ranges;
 394                         reg = <0x40040000 0x40000>;
 395                         interrupts = <77>;
 396                         clocks = <&rcc 0 29>;
 397                         clock-names = "otg";
 398                         status = "disabled";
 399                 };
 400
 401                 rng: rng@50060800 {
 402                         compatible = "st,stm32-rng";
 403                         reg = <0x50060800 0x400>;
 404                         interrupts = <80>;
 405                         clocks = <&rcc 0 38>;
 406                 };
 407         };
 408 };
 409
 410 &systick {
 411         clocks = <&rcc 1 0>;
 412         status = "okay";
 413 };