arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  51 #include <dt-bindings/pinctrl/sun4i-a10.h>
  52 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 simplefb_hdmi: framebuffer@0 {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  71                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  72                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  73                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  74                         status = "disabled";
  75                 };
  76
  77                 simplefb_lcd: framebuffer@1 {
  78                         compatible = "allwinner,simple-framebuffer",
  79                                      "simple-framebuffer";
  80                         allwinner,pipeline = "de_be0-lcd0";
  81                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  82                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  83                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  84                         status = "disabled";
  85                 };
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv7-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  93                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  94                 clock-frequency = <24000000>;
  95                 arm,cpu-registers-not-fw-configured;
  96         };
  97
  98         cpus {
  99                 enable-method = "allwinner,sun6i-a31";
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102
 103                 cpu0: cpu@0 {
 104                         compatible = "arm,cortex-a7";
 105                         device_type = "cpu";
 106                         reg = <0>;
 107                         clocks = <&ccu CLK_CPU>;
 108                         clock-latency = <244144>; /* 8 32k periods */
 109                         operating-points = <
 110                                 /* kHz    uV */
 111                                 1008000 1200000
 112                                 864000  1200000
 113                                 720000  1100000
 114                                 480000  1000000
 115                                 >;
 116                         #cooling-cells = <2>;
 117                         cooling-min-level = <0>;
 118                         cooling-max-level = <3>;
 119                 };
 120
 121                 cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                 };
 126
 127                 cpu@2 {
 128                         compatible = "arm,cortex-a7";
 129                         device_type = "cpu";
 130                         reg = <2>;
 131                 };
 132
 133                 cpu@3 {
 134                         compatible = "arm,cortex-a7";
 135                         device_type = "cpu";
 136                         reg = <3>;
 137                 };
 138         };
 139
 140         thermal-zones {
 141                 cpu_thermal {
 142                         /* milliseconds */
 143                         polling-delay-passive = <250>;
 144                         polling-delay = <1000>;
 145                         thermal-sensors = <&rtp>;
 146
 147                         cooling-maps {
 148                                 map0 {
 149                                         trip = <&cpu_alert0>;
 150                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 151                                 };
 152                         };
 153
 154                         trips {
 155                                 cpu_alert0: cpu_alert0 {
 156                                         /* milliCelsius */
 157                                         temperature = <70000>;
 158                                         hysteresis = <2000>;
 159                                         type = "passive";
 160                                 };
 161
 162                                 cpu_crit: cpu_crit {
 163                                         /* milliCelsius */
 164                                         temperature = <100000>;
 165                                         hysteresis = <2000>;
 166                                         type = "critical";
 167                                 };
 168                         };
 169                 };
 170         };
 171
 172         memory {
 173                 reg = <0x40000000 0x80000000>;
 174         };
 175
 176         pmu {
 177                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 178                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 182         };
 183
 184         clocks {
 185                 #address-cells = <1>;
 186                 #size-cells = <1>;
 187                 ranges;
 188
 189                 osc24M: osc24M {
 190                         #clock-cells = <0>;
 191                         compatible = "fixed-clock";
 192                         clock-frequency = <24000000>;
 193                 };
 194
 195                 osc32k: clk@0 {
 196                         #clock-cells = <0>;
 197                         compatible = "fixed-clock";
 198                         clock-frequency = <32768>;
 199                         clock-output-names = "osc32k";
 200                 };
 201
 202                 /*
 203                  * The following two are dummy clocks, placeholders
 204                  * used in the gmac_tx clock. The gmac driver will
 205                  * choose one parent depending on the PHY interface
 206                  * mode, using clk_set_rate auto-reparenting.
 207                  *
 208                  * The actual TX clock rate is not controlled by the
 209                  * gmac_tx clock.
 210                  */
 211                 mii_phy_tx_clk: clk@1 {
 212                         #clock-cells = <0>;
 213                         compatible = "fixed-clock";
 214                         clock-frequency = <25000000>;
 215                         clock-output-names = "mii_phy_tx";
 216                 };
 217
 218                 gmac_int_tx_clk: clk@2 {
 219                         #clock-cells = <0>;
 220                         compatible = "fixed-clock";
 221                         clock-frequency = <125000000>;
 222                         clock-output-names = "gmac_int_tx";
 223                 };
 224
 225                 gmac_tx_clk: clk@01c200d0 {
 226                         #clock-cells = <0>;
 227                         compatible = "allwinner,sun7i-a20-gmac-clk";
 228                         reg = <0x01c200d0 0x4>;
 229                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 230                         clock-output-names = "gmac_tx";
 231                 };
 232         };
 233
 234         soc@01c00000 {
 235                 compatible = "simple-bus";
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238                 ranges;
 239
 240                 dma: dma-controller@01c02000 {
 241                         compatible = "allwinner,sun6i-a31-dma";
 242                         reg = <0x01c02000 0x1000>;
 243                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 244                         clocks = <&ccu CLK_AHB1_DMA>;
 245                         resets = <&ccu RST_AHB1_DMA>;
 246                         #dma-cells = <1>;
 247                 };
 248
 249                 mmc0: mmc@01c0f000 {
 250                         compatible = "allwinner,sun7i-a20-mmc";
 251                         reg = <0x01c0f000 0x1000>;
 252                         clocks = <&ccu CLK_AHB1_MMC0>,
 253                                  <&ccu CLK_MMC0>,
 254                                  <&ccu CLK_MMC0_OUTPUT>,
 255                                  <&ccu CLK_MMC0_SAMPLE>;
 256                         clock-names = "ahb",
 257                                       "mmc",
 258                                       "output",
 259                                       "sample";
 260                         resets = <&ccu RST_AHB1_MMC0>;
 261                         reset-names = "ahb";
 262                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 263                         status = "disabled";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                 };
 267
 268                 mmc1: mmc@01c10000 {
 269                         compatible = "allwinner,sun7i-a20-mmc";
 270                         reg = <0x01c10000 0x1000>;
 271                         clocks = <&ccu CLK_AHB1_MMC1>,
 272                                  <&ccu CLK_MMC1>,
 273                                  <&ccu CLK_MMC1_OUTPUT>,
 274                                  <&ccu CLK_MMC1_SAMPLE>;
 275                         clock-names = "ahb",
 276                                       "mmc",
 277                                       "output",
 278                                       "sample";
 279                         resets = <&ccu RST_AHB1_MMC1>;
 280                         reset-names = "ahb";
 281                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 282                         status = "disabled";
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                 };
 286
 287                 mmc2: mmc@01c11000 {
 288                         compatible = "allwinner,sun7i-a20-mmc";
 289                         reg = <0x01c11000 0x1000>;
 290                         clocks = <&ccu CLK_AHB1_MMC2>,
 291                                  <&ccu CLK_MMC2>,
 292                                  <&ccu CLK_MMC2_OUTPUT>,
 293                                  <&ccu CLK_MMC2_SAMPLE>;
 294                         clock-names = "ahb",
 295                                       "mmc",
 296                                       "output",
 297                                       "sample";
 298                         resets = <&ccu RST_AHB1_MMC2>;
 299                         reset-names = "ahb";
 300                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 301                         status = "disabled";
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                 };
 305
 306                 mmc3: mmc@01c12000 {
 307                         compatible = "allwinner,sun7i-a20-mmc";
 308                         reg = <0x01c12000 0x1000>;
 309                         clocks = <&ccu CLK_AHB1_MMC3>,
 310                                  <&ccu CLK_MMC3>,
 311                                  <&ccu CLK_MMC3_OUTPUT>,
 312                                  <&ccu CLK_MMC3_SAMPLE>;
 313                         clock-names = "ahb",
 314                                       "mmc",
 315                                       "output",
 316                                       "sample";
 317                         resets = <&ccu RST_AHB1_MMC3>;
 318                         reset-names = "ahb";
 319                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 320                         status = "disabled";
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                 };
 324
 325                 usb_otg: usb@01c19000 {
 326                         compatible = "allwinner,sun6i-a31-musb";
 327                         reg = <0x01c19000 0x0400>;
 328                         clocks = <&ccu CLK_AHB1_OTG>;
 329                         resets = <&ccu RST_AHB1_OTG>;
 330                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 331                         interrupt-names = "mc";
 332                         phys = <&usbphy 0>;
 333                         phy-names = "usb";
 334                         extcon = <&usbphy 0>;
 335                         status = "disabled";
 336                 };
 337
 338                 usbphy: phy@01c19400 {
 339                         compatible = "allwinner,sun6i-a31-usb-phy";
 340                         reg = <0x01c19400 0x10>,
 341                               <0x01c1a800 0x4>,
 342                               <0x01c1b800 0x4>;
 343                         reg-names = "phy_ctrl",
 344                                     "pmu1",
 345                                     "pmu2";
 346                         clocks = <&ccu CLK_USB_PHY0>,
 347                                  <&ccu CLK_USB_PHY1>,
 348                                  <&ccu CLK_USB_PHY2>;
 349                         clock-names = "usb0_phy",
 350                                       "usb1_phy",
 351                                       "usb2_phy";
 352                         resets = <&ccu RST_USB_PHY0>,
 353                                  <&ccu RST_USB_PHY1>,
 354                                  <&ccu RST_USB_PHY2>;
 355                         reset-names = "usb0_reset",
 356                                       "usb1_reset",
 357                                       "usb2_reset";
 358                         status = "disabled";
 359                         #phy-cells = <1>;
 360                 };
 361
 362                 ehci0: usb@01c1a000 {
 363                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 364                         reg = <0x01c1a000 0x100>;
 365                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&ccu CLK_AHB1_EHCI0>;
 367                         resets = <&ccu RST_AHB1_EHCI0>;
 368                         phys = <&usbphy 1>;
 369                         phy-names = "usb";
 370                         status = "disabled";
 371                 };
 372
 373                 ohci0: usb@01c1a400 {
 374                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 375                         reg = <0x01c1a400 0x100>;
 376                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 377                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 378                         resets = <&ccu RST_AHB1_OHCI0>;
 379                         phys = <&usbphy 1>;
 380                         phy-names = "usb";
 381                         status = "disabled";
 382                 };
 383
 384                 ehci1: usb@01c1b000 {
 385                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 386                         reg = <0x01c1b000 0x100>;
 387                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&ccu CLK_AHB1_EHCI1>;
 389                         resets = <&ccu RST_AHB1_EHCI1>;
 390                         phys = <&usbphy 2>;
 391                         phy-names = "usb";
 392                         status = "disabled";
 393                 };
 394
 395                 ohci1: usb@01c1b400 {
 396                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 397                         reg = <0x01c1b400 0x100>;
 398                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 399                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 400                         resets = <&ccu RST_AHB1_OHCI1>;
 401                         phys = <&usbphy 2>;
 402                         phy-names = "usb";
 403                         status = "disabled";
 404                 };
 405
 406                 ohci2: usb@01c1c400 {
 407                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 408                         reg = <0x01c1c400 0x100>;
 409                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 411                         resets = <&ccu RST_AHB1_OHCI2>;
 412                         status = "disabled";
 413                 };
 414
 415                 ccu: clock@01c20000 {
 416                         compatible = "allwinner,sun6i-a31-ccu";
 417                         reg = <0x01c20000 0x400>;
 418                         clocks = <&osc24M>, <&osc32k>;
 419                         clock-names = "hosc", "losc";
 420                         #clock-cells = <1>;
 421                         #reset-cells = <1>;
 422                 };
 423
 424                 pio: pinctrl@01c20800 {
 425                         compatible = "allwinner,sun6i-a31-pinctrl";
 426                         reg = <0x01c20800 0x400>;
 427                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 428                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 429                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 430                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&ccu CLK_APB1_PIO>;
 432                         gpio-controller;
 433                         interrupt-controller;
 434                         #interrupt-cells = <3>;
 435                         #gpio-cells = <3>;
 436
 437                         uart0_pins_a: uart0@0 {
 438                                 allwinner,pins = "PH20", "PH21";
 439                                 allwinner,function = "uart0";
 440                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 441                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 442                         };
 443
 444                         i2c0_pins_a: i2c0@0 {
 445                                 allwinner,pins = "PH14", "PH15";
 446                                 allwinner,function = "i2c0";
 447                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 448                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 449                         };
 450
 451                         i2c1_pins_a: i2c1@0 {
 452                                 allwinner,pins = "PH16", "PH17";
 453                                 allwinner,function = "i2c1";
 454                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 455                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 456                         };
 457
 458                         i2c2_pins_a: i2c2@0 {
 459                                 allwinner,pins = "PH18", "PH19";
 460                                 allwinner,function = "i2c2";
 461                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 462                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 463                         };
 464
 465                         mmc0_pins_a: mmc0@0 {
 466                                 allwinner,pins = "PF0", "PF1", "PF2",
 467                                                  "PF3", "PF4", "PF5";
 468                                 allwinner,function = "mmc0";
 469                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 470                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 471                         };
 472
 473                         mmc1_pins_a: mmc1@0 {
 474                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 475                                                  "PG4", "PG5";
 476                                 allwinner,function = "mmc1";
 477                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 478                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 479                         };
 480
 481                         mmc2_pins_a: mmc2@0 {
 482                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 483                                                  "PC10", "PC11";
 484                                 allwinner,function = "mmc2";
 485                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 486                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 487                         };
 488
 489                         mmc2_8bit_emmc_pins: mmc2@1 {
 490                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 491                                                  "PC10", "PC11", "PC12",
 492                                                  "PC13", "PC14", "PC15",
 493                                                  "PC24";
 494                                 allwinner,function = "mmc2";
 495                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 496                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 497                         };
 498
 499                         mmc3_8bit_emmc_pins: mmc3@1 {
 500                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 501                                                  "PC10", "PC11", "PC12",
 502                                                  "PC13", "PC14", "PC15",
 503                                                  "PC24";
 504                                 allwinner,function = "mmc3";
 505                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 506                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 507                         };
 508
 509                         gmac_pins_mii_a: gmac_mii@0 {
 510                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 511                                                 "PA8", "PA9", "PA11",
 512                                                 "PA12", "PA13", "PA14", "PA19",
 513                                                 "PA20", "PA21", "PA22", "PA23",
 514                                                 "PA24", "PA26", "PA27";
 515                                 allwinner,function = "gmac";
 516                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 517                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 518                         };
 519
 520                         gmac_pins_gmii_a: gmac_gmii@0 {
 521                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 522                                                 "PA4", "PA5", "PA6", "PA7",
 523                                                 "PA8", "PA9", "PA10", "PA11",
 524                                                 "PA12", "PA13", "PA14", "PA15",
 525                                                 "PA16", "PA17", "PA18", "PA19",
 526                                                 "PA20", "PA21", "PA22", "PA23",
 527                                                 "PA24", "PA25", "PA26", "PA27";
 528                                 allwinner,function = "gmac";
 529                                 /*
 530                                  * data lines in GMII mode run at 125MHz and
 531                                  * might need a higher signal drive strength
 532                                  */
 533                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 534                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 535                         };
 536
 537                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 538                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 539                                                 "PA9", "PA10", "PA11",
 540                                                 "PA12", "PA13", "PA14", "PA19",
 541                                                 "PA20", "PA25", "PA26", "PA27";
 542                                 allwinner,function = "gmac";
 543                                 /*
 544                                  * data lines in RGMII mode use DDR mode
 545                                  * and need a higher signal drive strength
 546                                  */
 547                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 548                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 549                         };
 550                 };
 551
 552                 timer@01c20c00 {
 553                         compatible = "allwinner,sun4i-a10-timer";
 554                         reg = <0x01c20c00 0xa0>;
 555                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 556                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 558                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&osc24M>;
 561                 };
 562
 563                 wdt1: watchdog@01c20ca0 {
 564                         compatible = "allwinner,sun6i-a31-wdt";
 565                         reg = <0x01c20ca0 0x20>;
 566                 };
 567
 568                 lradc: lradc@01c22800 {
 569                         compatible = "allwinner,sun4i-a10-lradc-keys";
 570                         reg = <0x01c22800 0x100>;
 571                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 572                         status = "disabled";
 573                 };
 574
 575                 rtp: rtp@01c25000 {
 576                         compatible = "allwinner,sun6i-a31-ts";
 577                         reg = <0x01c25000 0x100>;
 578                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 579                         #thermal-sensor-cells = <0>;
 580                 };
 581
 582                 uart0: serial@01c28000 {
 583                         compatible = "snps,dw-apb-uart";
 584                         reg = <0x01c28000 0x400>;
 585                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 586                         reg-shift = <2>;
 587                         reg-io-width = <4>;
 588                         clocks = <&ccu CLK_APB2_UART0>;
 589                         resets = <&ccu RST_APB2_UART0>;
 590                         dmas = <&dma 6>, <&dma 6>;
 591                         dma-names = "rx", "tx";
 592                         status = "disabled";
 593                 };
 594
 595                 uart1: serial@01c28400 {
 596                         compatible = "snps,dw-apb-uart";
 597                         reg = <0x01c28400 0x400>;
 598                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 599                         reg-shift = <2>;
 600                         reg-io-width = <4>;
 601                         clocks = <&ccu CLK_APB2_UART1>;
 602                         resets = <&ccu RST_APB2_UART1>;
 603                         dmas = <&dma 7>, <&dma 7>;
 604                         dma-names = "rx", "tx";
 605                         status = "disabled";
 606                 };
 607
 608                 uart2: serial@01c28800 {
 609                         compatible = "snps,dw-apb-uart";
 610                         reg = <0x01c28800 0x400>;
 611                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 612                         reg-shift = <2>;
 613                         reg-io-width = <4>;
 614                         clocks = <&ccu CLK_APB2_UART2>;
 615                         resets = <&ccu RST_APB2_UART2>;
 616                         dmas = <&dma 8>, <&dma 8>;
 617                         dma-names = "rx", "tx";
 618                         status = "disabled";
 619                 };
 620
 621                 uart3: serial@01c28c00 {
 622                         compatible = "snps,dw-apb-uart";
 623                         reg = <0x01c28c00 0x400>;
 624                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 625                         reg-shift = <2>;
 626                         reg-io-width = <4>;
 627                         clocks = <&ccu CLK_APB2_UART3>;
 628                         resets = <&ccu RST_APB2_UART3>;
 629                         dmas = <&dma 9>, <&dma 9>;
 630                         dma-names = "rx", "tx";
 631                         status = "disabled";
 632                 };
 633
 634                 uart4: serial@01c29000 {
 635                         compatible = "snps,dw-apb-uart";
 636                         reg = <0x01c29000 0x400>;
 637                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 638                         reg-shift = <2>;
 639                         reg-io-width = <4>;
 640                         clocks = <&ccu CLK_APB2_UART4>;
 641                         resets = <&ccu RST_APB2_UART4>;
 642                         dmas = <&dma 10>, <&dma 10>;
 643                         dma-names = "rx", "tx";
 644                         status = "disabled";
 645                 };
 646
 647                 uart5: serial@01c29400 {
 648                         compatible = "snps,dw-apb-uart";
 649                         reg = <0x01c29400 0x400>;
 650                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 651                         reg-shift = <2>;
 652                         reg-io-width = <4>;
 653                         clocks = <&ccu CLK_APB2_UART5>;
 654                         resets = <&ccu RST_APB2_UART5>;
 655                         dmas = <&dma 22>, <&dma 22>;
 656                         dma-names = "rx", "tx";
 657                         status = "disabled";
 658                 };
 659
 660                 i2c0: i2c@01c2ac00 {
 661                         compatible = "allwinner,sun6i-a31-i2c";
 662                         reg = <0x01c2ac00 0x400>;
 663                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 664                         clocks = <&ccu CLK_APB2_I2C0>;
 665                         resets = <&ccu RST_APB2_I2C0>;
 666                         status = "disabled";
 667                         #address-cells = <1>;
 668                         #size-cells = <0>;
 669                 };
 670
 671                 i2c1: i2c@01c2b000 {
 672                         compatible = "allwinner,sun6i-a31-i2c";
 673                         reg = <0x01c2b000 0x400>;
 674                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 675                         clocks = <&ccu CLK_APB2_I2C1>;
 676                         resets = <&ccu RST_APB2_I2C1>;
 677                         status = "disabled";
 678                         #address-cells = <1>;
 679                         #size-cells = <0>;
 680                 };
 681
 682                 i2c2: i2c@01c2b400 {
 683                         compatible = "allwinner,sun6i-a31-i2c";
 684                         reg = <0x01c2b400 0x400>;
 685                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 686                         clocks = <&ccu CLK_APB2_I2C2>;
 687                         resets = <&ccu RST_APB2_I2C2>;
 688                         status = "disabled";
 689                         #address-cells = <1>;
 690                         #size-cells = <0>;
 691                 };
 692
 693                 i2c3: i2c@01c2b800 {
 694                         compatible = "allwinner,sun6i-a31-i2c";
 695                         reg = <0x01c2b800 0x400>;
 696                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&ccu CLK_APB2_I2C3>;
 698                         resets = <&ccu RST_APB2_I2C3>;
 699                         status = "disabled";
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                 };
 703
 704                 gmac: ethernet@01c30000 {
 705                         compatible = "allwinner,sun7i-a20-gmac";
 706                         reg = <0x01c30000 0x1054>;
 707                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 708                         interrupt-names = "macirq";
 709                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 710                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 711                         resets = <&ccu RST_AHB1_EMAC>;
 712                         reset-names = "stmmaceth";
 713                         snps,pbl = <2>;
 714                         snps,fixed-burst;
 715                         snps,force_sf_dma_mode;
 716                         status = "disabled";
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719                 };
 720
 721                 crypto: crypto-engine@01c15000 {
 722                         compatible = "allwinner,sun4i-a10-crypto";
 723                         reg = <0x01c15000 0x1000>;
 724                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 726                         clock-names = "ahb", "mod";
 727                         resets = <&ccu RST_AHB1_SS>;
 728                         reset-names = "ahb";
 729                 };
 730
 731                 timer@01c60000 {
 732                         compatible = "allwinner,sun6i-a31-hstimer",
 733                                      "allwinner,sun7i-a20-hstimer";
 734                         reg = <0x01c60000 0x1000>;
 735                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 739                         clocks = <&ccu CLK_AHB1_HSTIMER>;
 740                         resets = <&ccu RST_AHB1_HSTIMER>;
 741                 };
 742
 743                 spi0: spi@01c68000 {
 744                         compatible = "allwinner,sun6i-a31-spi";
 745                         reg = <0x01c68000 0x1000>;
 746                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 747                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
 748                         clock-names = "ahb", "mod";
 749                         dmas = <&dma 23>, <&dma 23>;
 750                         dma-names = "rx", "tx";
 751                         resets = <&ccu RST_AHB1_SPI0>;
 752                         status = "disabled";
 753                 };
 754
 755                 spi1: spi@01c69000 {
 756                         compatible = "allwinner,sun6i-a31-spi";
 757                         reg = <0x01c69000 0x1000>;
 758                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 759                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
 760                         clock-names = "ahb", "mod";
 761                         dmas = <&dma 24>, <&dma 24>;
 762                         dma-names = "rx", "tx";
 763                         resets = <&ccu RST_AHB1_SPI1>;
 764                         status = "disabled";
 765                 };
 766
 767                 spi2: spi@01c6a000 {
 768                         compatible = "allwinner,sun6i-a31-spi";
 769                         reg = <0x01c6a000 0x1000>;
 770                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 771                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
 772                         clock-names = "ahb", "mod";
 773                         dmas = <&dma 25>, <&dma 25>;
 774                         dma-names = "rx", "tx";
 775                         resets = <&ccu RST_AHB1_SPI2>;
 776                         status = "disabled";
 777                 };
 778
 779                 spi3: spi@01c6b000 {
 780                         compatible = "allwinner,sun6i-a31-spi";
 781                         reg = <0x01c6b000 0x1000>;
 782                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
 784                         clock-names = "ahb", "mod";
 785                         dmas = <&dma 26>, <&dma 26>;
 786                         dma-names = "rx", "tx";
 787                         resets = <&ccu RST_AHB1_SPI3>;
 788                         status = "disabled";
 789                 };
 790
 791                 gic: interrupt-controller@01c81000 {
 792                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 793                         reg = <0x01c81000 0x1000>,
 794                               <0x01c82000 0x1000>,
 795                               <0x01c84000 0x2000>,
 796                               <0x01c86000 0x2000>;
 797                         interrupt-controller;
 798                         #interrupt-cells = <3>;
 799                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 800                 };
 801
 802                 rtc: rtc@01f00000 {
 803                         compatible = "allwinner,sun6i-a31-rtc";
 804                         reg = <0x01f00000 0x54>;
 805                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 806                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 807                 };
 808
 809                 nmi_intc: interrupt-controller@01f00c0c {
 810                         compatible = "allwinner,sun6i-a31-sc-nmi";
 811                         interrupt-controller;
 812                         #interrupt-cells = <2>;
 813                         reg = <0x01f00c0c 0x38>;
 814                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 815                 };
 816
 817                 prcm@01f01400 {
 818                         compatible = "allwinner,sun6i-a31-prcm";
 819                         reg = <0x01f01400 0x200>;
 820
 821                         ar100: ar100_clk {
 822                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 823                                 #clock-cells = <0>;
 824                                 clocks = <&osc32k>, <&osc24M>,
 825                                          <&ccu CLK_PLL_PERIPH>,
 826                                          <&ccu CLK_PLL_PERIPH>;
 827                                 clock-output-names = "ar100";
 828                         };
 829
 830                         ahb0: ahb0_clk {
 831                                 compatible = "fixed-factor-clock";
 832                                 #clock-cells = <0>;
 833                                 clock-div = <1>;
 834                                 clock-mult = <1>;
 835                                 clocks = <&ar100>;
 836                                 clock-output-names = "ahb0";
 837                         };
 838
 839                         apb0: apb0_clk {
 840                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 841                                 #clock-cells = <0>;
 842                                 clocks = <&ahb0>;
 843                                 clock-output-names = "apb0";
 844                         };
 845
 846                         apb0_gates: apb0_gates_clk {
 847                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 848                                 #clock-cells = <1>;
 849                                 clocks = <&apb0>;
 850                                 clock-output-names = "apb0_pio", "apb0_ir",
 851                                                 "apb0_timer", "apb0_p2wi",
 852                                                 "apb0_uart", "apb0_1wire",
 853                                                 "apb0_i2c";
 854                         };
 855
 856                         ir_clk: ir_clk {
 857                                 #clock-cells = <0>;
 858                                 compatible = "allwinner,sun4i-a10-mod0-clk";
 859                                 clocks = <&osc32k>, <&osc24M>;
 860                                 clock-output-names = "ir";
 861                         };
 862
 863                         apb0_rst: apb0_rst {
 864                                 compatible = "allwinner,sun6i-a31-clock-reset";
 865                                 #reset-cells = <1>;
 866                         };
 867                 };
 868
 869                 cpucfg@01f01c00 {
 870                         compatible = "allwinner,sun6i-a31-cpuconfig";
 871                         reg = <0x01f01c00 0x300>;
 872                 };
 873
 874                 ir: ir@01f02000 {
 875                         compatible = "allwinner,sun5i-a13-ir";
 876                         clocks = <&apb0_gates 1>, <&ir_clk>;
 877                         clock-names = "apb", "ir";
 878                         resets = <&apb0_rst 1>;
 879                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 880                         reg = <0x01f02000 0x40>;
 881                         status = "disabled";
 882                 };
 883
 884                 r_pio: pinctrl@01f02c00 {
 885                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 886                         reg = <0x01f02c00 0x400>;
 887                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 888                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 889                         clocks = <&apb0_gates 0>;
 890                         resets = <&apb0_rst 0>;
 891                         gpio-controller;
 892                         interrupt-controller;
 893                         #interrupt-cells = <3>;
 894                         #size-cells = <0>;
 895                         #gpio-cells = <3>;
 896
 897                         ir_pins_a: ir@0 {
 898                                 allwinner,pins = "PL4";
 899                                 allwinner,function = "s_ir";
 900                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 901                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 902                         };
 903
 904                         p2wi_pins: p2wi {
 905                                 allwinner,pins = "PL0", "PL1";
 906                                 allwinner,function = "s_p2wi";
 907                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 908                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 909                         };
 910                 };
 911
 912                 p2wi: i2c@01f03400 {
 913                         compatible = "allwinner,sun6i-a31-p2wi";
 914                         reg = <0x01f03400 0x400>;
 915                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 916                         clocks = <&apb0_gates 3>;
 917                         clock-frequency = <100000>;
 918                         resets = <&apb0_rst 3>;
 919                         pinctrl-names = "default";
 920                         pinctrl-0 = <&p2wi_pins>;
 921                         status = "disabled";
 922                         #address-cells = <1>;
 923                         #size-cells = <0>;
 924                 };
 925         };
 926 };