arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton64.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a7";
  60                         device_type = "cpu";
  61                         reg = <0x0>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0x1>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "arm,cortex-a7";
  72                         device_type = "cpu";
  73                         reg = <0x2>;
  74                 };
  75
  76                 cpu3: cpu@3 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <0x3>;
  80                 };
  81
  82                 cpu4: cpu@100 {
  83                         compatible = "arm,cortex-a15";
  84                         device_type = "cpu";
  85                         reg = <0x100>;
  86                 };
  87
  88                 cpu5: cpu@101 {
  89                         compatible = "arm,cortex-a15";
  90                         device_type = "cpu";
  91                         reg = <0x101>;
  92                 };
  93
  94                 cpu6: cpu@102 {
  95                         compatible = "arm,cortex-a15";
  96                         device_type = "cpu";
  97                         reg = <0x102>;
  98                 };
  99
 100                 cpu7: cpu@103 {
 101                         compatible = "arm,cortex-a15";
 102                         device_type = "cpu";
 103                         reg = <0x103>;
 104                 };
 105         };
 106
 107         memory {
 108                 /* 8GB max. with LPAE */
 109                 reg = <0 0x20000000 0x02 0>;
 110         };
 111
 112         timer {
 113                 compatible = "arm,armv7-timer";
 114                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 115                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 118                 clock-frequency = <24000000>;
 119                 arm,cpu-registers-not-fw-configured;
 120         };
 121
 122         clocks {
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 /*
 126                  * map 64 bit address range down to 32 bits,
 127                  * as the peripherals are all under 512MB.
 128                  */
 129                 ranges = <0 0 0 0x20000000>;
 130
 131                 /*
 132                  * This clock is actually configurable from the PRCM address
 133                  * space. The external 24M oscillator can be turned off, and
 134                  * the clock switched to an internal 16M RC oscillator. Under
 135                  * normal operation there's no reason to do this, and the
 136                  * default is to use the external good one, so just model this
 137                  * as a fixed clock. Also it is not entirely clear if the
 138                  * osc24M mux in the PRCM affects the entire clock tree, which
 139                  * would also throw all the PLL clock rates off, or just the
 140                  * downstream clocks in the PRCM.
 141                  */
 142                 osc24M: osc24M_clk {
 143                         #clock-cells = <0>;
 144                         compatible = "fixed-clock";
 145                         clock-frequency = <24000000>;
 146                         clock-output-names = "osc24M";
 147                 };
 148
 149                 /*
 150                  * The 32k clock is from an external source, normally the
 151                  * AC100 codec/RTC chip. This serves as a placeholder for
 152                  * board dts files to specify the source.
 153                  */
 154                 osc32k: osc32k_clk {
 155                         #clock-cells = <0>;
 156                         compatible = "fixed-factor-clock";
 157                         clock-div = <1>;
 158                         clock-mult = <1>;
 159                         clock-output-names = "osc32k";
 160                 };
 161
 162                 usb_mod_clk: clk@00a08000 {
 163                         #clock-cells = <1>;
 164                         #reset-cells = <1>;
 165                         compatible = "allwinner,sun9i-a80-usb-mod-clk";
 166                         reg = <0x00a08000 0x4>;
 167                         clocks = <&ahb1_gates 1>;
 168                         clock-output-names = "usb0_ahb", "usb_ohci0",
 169                                              "usb1_ahb", "usb_ohci1",
 170                                              "usb2_ahb", "usb_ohci2";
 171                 };
 172
 173                 usb_phy_clk: clk@00a08004 {
 174                         #clock-cells = <1>;
 175                         #reset-cells = <1>;
 176                         compatible = "allwinner,sun9i-a80-usb-phy-clk";
 177                         reg = <0x00a08004 0x4>;
 178                         clocks = <&ahb1_gates 1>;
 179                         clock-output-names = "usb_phy0", "usb_hsic1_480M",
 180                                              "usb_phy1", "usb_hsic2_480M",
 181                                              "usb_phy2", "usb_hsic_12M";
 182                 };
 183
 184                 pll3: clk@06000008 {
 185                         /* placeholder until implemented */
 186                         #clock-cells = <0>;
 187                         compatible = "fixed-clock";
 188                         clock-rate = <0>;
 189                         clock-output-names = "pll3";
 190                 };
 191
 192                 pll4: clk@0600000c {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun9i-a80-pll4-clk";
 195                         reg = <0x0600000c 0x4>;
 196                         clocks = <&osc24M>;
 197                         clock-output-names = "pll4";
 198                 };
 199
 200                 pll12: clk@0600002c {
 201                         #clock-cells = <0>;
 202                         compatible = "allwinner,sun9i-a80-pll4-clk";
 203                         reg = <0x0600002c 0x4>;
 204                         clocks = <&osc24M>;
 205                         clock-output-names = "pll12";
 206                 };
 207
 208                 gt_clk: clk@0600005c {
 209                         #clock-cells = <0>;
 210                         compatible = "allwinner,sun9i-a80-gt-clk";
 211                         reg = <0x0600005c 0x4>;
 212                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 213                         clock-output-names = "gt";
 214                 };
 215
 216                 ahb0: clk@06000060 {
 217                         #clock-cells = <0>;
 218                         compatible = "allwinner,sun9i-a80-ahb-clk";
 219                         reg = <0x06000060 0x4>;
 220                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 221                         clock-output-names = "ahb0";
 222                 };
 223
 224                 ahb1: clk@06000064 {
 225                         #clock-cells = <0>;
 226                         compatible = "allwinner,sun9i-a80-ahb-clk";
 227                         reg = <0x06000064 0x4>;
 228                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 229                         clock-output-names = "ahb1";
 230                 };
 231
 232                 ahb2: clk@06000068 {
 233                         #clock-cells = <0>;
 234                         compatible = "allwinner,sun9i-a80-ahb-clk";
 235                         reg = <0x06000068 0x4>;
 236                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 237                         clock-output-names = "ahb2";
 238                 };
 239
 240                 apb0: clk@06000070 {
 241                         #clock-cells = <0>;
 242                         compatible = "allwinner,sun9i-a80-apb0-clk";
 243                         reg = <0x06000070 0x4>;
 244                         clocks = <&osc24M>, <&pll4>;
 245                         clock-output-names = "apb0";
 246                 };
 247
 248                 apb1: clk@06000074 {
 249                         #clock-cells = <0>;
 250                         compatible = "allwinner,sun9i-a80-apb1-clk";
 251                         reg = <0x06000074 0x4>;
 252                         clocks = <&osc24M>, <&pll4>;
 253                         clock-output-names = "apb1";
 254                 };
 255
 256                 cci400_clk: clk@06000078 {
 257                         #clock-cells = <0>;
 258                         compatible = "allwinner,sun9i-a80-gt-clk";
 259                         reg = <0x06000078 0x4>;
 260                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 261                         clock-output-names = "cci400";
 262                 };
 263
 264                 mmc0_clk: clk@06000410 {
 265                         #clock-cells = <1>;
 266                         compatible = "allwinner,sun9i-a80-mmc-clk";
 267                         reg = <0x06000410 0x4>;
 268                         clocks = <&osc24M>, <&pll4>;
 269                         clock-output-names = "mmc0", "mmc0_output",
 270                                              "mmc0_sample";
 271                 };
 272
 273                 mmc1_clk: clk@06000414 {
 274                         #clock-cells = <1>;
 275                         compatible = "allwinner,sun9i-a80-mmc-clk";
 276                         reg = <0x06000414 0x4>;
 277                         clocks = <&osc24M>, <&pll4>;
 278                         clock-output-names = "mmc1", "mmc1_output",
 279                                              "mmc1_sample";
 280                 };
 281
 282                 mmc2_clk: clk@06000418 {
 283                         #clock-cells = <1>;
 284                         compatible = "allwinner,sun9i-a80-mmc-clk";
 285                         reg = <0x06000418 0x4>;
 286                         clocks = <&osc24M>, <&pll4>;
 287                         clock-output-names = "mmc2", "mmc2_output",
 288                                              "mmc2_sample";
 289                 };
 290
 291                 mmc3_clk: clk@0600041c {
 292                         #clock-cells = <1>;
 293                         compatible = "allwinner,sun9i-a80-mmc-clk";
 294                         reg = <0x0600041c 0x4>;
 295                         clocks = <&osc24M>, <&pll4>;
 296                         clock-output-names = "mmc3", "mmc3_output",
 297                                              "mmc3_sample";
 298                 };
 299
 300                 ahb0_gates: clk@06000580 {
 301                         #clock-cells = <1>;
 302                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 303                         reg = <0x06000580 0x4>;
 304                         clocks = <&ahb0>;
 305                         clock-indices = <0>, <1>, <3>,
 306                                         <5>, <8>, <12>,
 307                                         <13>, <14>,
 308                                         <15>, <16>, <18>,
 309                                         <20>, <21>, <22>,
 310                                         <23>;
 311                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 312                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
 313                                         "ahb0_nand0", "ahb0_sdram",
 314                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
 315                                         "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
 316                                         "ahb0_spi3";
 317                 };
 318
 319                 ahb1_gates: clk@06000584 {
 320                         #clock-cells = <1>;
 321                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 322                         reg = <0x06000584 0x4>;
 323                         clocks = <&ahb1>;
 324                         clock-indices = <0>, <1>,
 325                                         <17>, <21>,
 326                                         <22>, <23>,
 327                                         <24>;
 328                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 329                                         "ahb1_gmac", "ahb1_msgbox",
 330                                         "ahb1_spinlock", "ahb1_hstimer",
 331                                         "ahb1_dma";
 332                 };
 333
 334                 ahb2_gates: clk@06000588 {
 335                         #clock-cells = <1>;
 336                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 337                         reg = <0x06000588 0x4>;
 338                         clocks = <&ahb2>;
 339                         clock-indices = <0>, <1>,
 340                                         <2>, <4>, <5>,
 341                                         <7>, <8>, <11>;
 342                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 343                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 344                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
 345                 };
 346
 347                 apb0_gates: clk@06000590 {
 348                         #clock-cells = <1>;
 349                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 350                         reg = <0x06000590 0x4>;
 351                         clocks = <&apb0>;
 352                         clock-indices = <1>, <5>,
 353                                         <11>, <12>, <13>,
 354                                         <15>, <17>, <18>,
 355                                         <19>;
 356                         clock-output-names = "apb0_spdif", "apb0_pio",
 357                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 358                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
 359                                         "apb0_cirtx";
 360                 };
 361
 362                 apb1_gates: clk@06000594 {
 363                         #clock-cells = <1>;
 364                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 365                         reg = <0x06000594 0x4>;
 366                         clocks = <&apb1>;
 367                         clock-indices = <0>, <1>,
 368                                         <2>, <3>, <4>,
 369                                         <16>, <17>,
 370                                         <18>, <19>,
 371                                         <20>, <21>;
 372                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 373                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 374                                         "apb1_uart0", "apb1_uart1",
 375                                         "apb1_uart2", "apb1_uart3",
 376                                         "apb1_uart4", "apb1_uart5";
 377                 };
 378
 379                 cpus_clk: clk@08001410 {
 380                         compatible = "allwinner,sun9i-a80-cpus-clk";
 381                         reg = <0x08001410 0x4>;
 382                         #clock-cells = <0>;
 383                         clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
 384                         clock-output-names = "cpus";
 385                 };
 386
 387                 ahbs: ahbs_clk {
 388                         compatible = "fixed-factor-clock";
 389                         #clock-cells = <0>;
 390                         clock-div = <1>;
 391                         clock-mult = <1>;
 392                         clocks = <&cpus_clk>;
 393                         clock-output-names = "ahbs";
 394                 };
 395
 396                 apbs: clk@0800141c {
 397                         compatible = "allwinner,sun8i-a23-apb0-clk";
 398                         reg = <0x0800141c 0x4>;
 399                         #clock-cells = <0>;
 400                         clocks = <&ahbs>;
 401                         clock-output-names = "apbs";
 402                 };
 403
 404                 apbs_gates: clk@08001428 {
 405                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 406                         reg = <0x08001428 0x4>;
 407                         #clock-cells = <1>;
 408                         clocks = <&apbs>;
 409                         clock-indices = <0>, <1>,
 410                                         <2>, <3>,
 411                                         <4>, <5>,
 412                                         <6>, <7>,
 413                                         <12>, <13>,
 414                                         <16>, <17>,
 415                                         <18>, <20>;
 416                         clock-output-names = "apbs_pio", "apbs_ir",
 417                                         "apbs_timer", "apbs_rsb",
 418                                         "apbs_uart", "apbs_1wire",
 419                                         "apbs_i2c0", "apbs_i2c1",
 420                                         "apbs_ps2_0", "apbs_ps2_1",
 421                                         "apbs_dma", "apbs_i2s0",
 422                                         "apbs_i2s1", "apbs_twd";
 423                 };
 424
 425                 r_1wire_clk: clk@08001450 {
 426                         reg = <0x08001450 0x4>;
 427                         #clock-cells = <0>;
 428                         compatible = "allwinner,sun4i-a10-mod0-clk";
 429                         clocks = <&osc32k>, <&osc24M>;
 430                         clock-output-names = "r_1wire";
 431                 };
 432
 433                 r_ir_clk: clk@08001454 {
 434                         reg = <0x08001454 0x4>;
 435                         #clock-cells = <0>;
 436                         compatible = "allwinner,sun4i-a10-mod0-clk";
 437                         clocks = <&osc32k>, <&osc24M>;
 438                         clock-output-names = "r_ir";
 439                 };
 440         };
 441
 442         soc {
 443                 compatible = "simple-bus";
 444                 #address-cells = <1>;
 445                 #size-cells = <1>;
 446                 /*
 447                  * map 64 bit address range down to 32 bits,
 448                  * as the peripherals are all under 512MB.
 449                  */
 450                 ranges = <0 0 0 0x20000000>;
 451
 452                 ehci0: usb@00a00000 {
 453                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 454                         reg = <0x00a00000 0x100>;
 455                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&usb_mod_clk 1>;
 457                         resets = <&usb_mod_clk 17>;
 458                         phys = <&usbphy1>;
 459                         phy-names = "usb";
 460                         status = "disabled";
 461                 };
 462
 463                 ohci0: usb@00a00400 {
 464                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 465                         reg = <0x00a00400 0x100>;
 466                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 467                         clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
 468                         resets = <&usb_mod_clk 17>;
 469                         phys = <&usbphy1>;
 470                         phy-names = "usb";
 471                         status = "disabled";
 472                 };
 473
 474                 usbphy1: phy@00a00800 {
 475                         compatible = "allwinner,sun9i-a80-usb-phy";
 476                         reg = <0x00a00800 0x4>;
 477                         clocks = <&usb_phy_clk 1>;
 478                         clock-names = "phy";
 479                         resets = <&usb_phy_clk 17>;
 480                         reset-names = "phy";
 481                         status = "disabled";
 482                         #phy-cells = <0>;
 483                 };
 484
 485                 ehci1: usb@00a01000 {
 486                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 487                         reg = <0x00a01000 0x100>;
 488                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&usb_mod_clk 3>;
 490                         resets = <&usb_mod_clk 18>;
 491                         phys = <&usbphy2>;
 492                         phy-names = "usb";
 493                         status = "disabled";
 494                 };
 495
 496                 usbphy2: phy@00a01800 {
 497                         compatible = "allwinner,sun9i-a80-usb-phy";
 498                         reg = <0x00a01800 0x4>;
 499                         clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
 500                                  <&usb_phy_clk 3>;
 501                         clock-names = "hsic_480M", "hsic_12M", "phy";
 502                         resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
 503                         reset-names = "hsic", "phy";
 504                         status = "disabled";
 505                         #phy-cells = <0>;
 506                         /* usb1 is always used with HSIC */
 507                         phy_type = "hsic";
 508                 };
 509
 510                 ehci2: usb@00a02000 {
 511                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 512                         reg = <0x00a02000 0x100>;
 513                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&usb_mod_clk 5>;
 515                         resets = <&usb_mod_clk 19>;
 516                         phys = <&usbphy3>;
 517                         phy-names = "usb";
 518                         status = "disabled";
 519                 };
 520
 521                 ohci2: usb@00a02400 {
 522                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 523                         reg = <0x00a02400 0x100>;
 524                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
 526                         resets = <&usb_mod_clk 19>;
 527                         phys = <&usbphy3>;
 528                         phy-names = "usb";
 529                         status = "disabled";
 530                 };
 531
 532                 usbphy3: phy@00a02800 {
 533                         compatible = "allwinner,sun9i-a80-usb-phy";
 534                         reg = <0x00a02800 0x4>;
 535                         clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
 536                                  <&usb_phy_clk 5>;
 537                         clock-names = "hsic_480M", "hsic_12M", "phy";
 538                         resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
 539                         reset-names = "hsic", "phy";
 540                         status = "disabled";
 541                         #phy-cells = <0>;
 542                 };
 543
 544                 mmc0: mmc@01c0f000 {
 545                         compatible = "allwinner,sun9i-a80-mmc";
 546                         reg = <0x01c0f000 0x1000>;
 547                         clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 548                                  <&mmc0_clk 1>, <&mmc0_clk 2>;
 549                         clock-names = "ahb", "mmc", "output", "sample";
 550                         resets = <&mmc_config_clk 0>;
 551                         reset-names = "ahb";
 552                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 553                         status = "disabled";
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                 };
 557
 558                 mmc1: mmc@01c10000 {
 559                         compatible = "allwinner,sun9i-a80-mmc";
 560                         reg = <0x01c10000 0x1000>;
 561                         clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 562                                  <&mmc1_clk 1>, <&mmc1_clk 2>;
 563                         clock-names = "ahb", "mmc", "output", "sample";
 564                         resets = <&mmc_config_clk 1>;
 565                         reset-names = "ahb";
 566                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 567                         status = "disabled";
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                 };
 571
 572                 mmc2: mmc@01c11000 {
 573                         compatible = "allwinner,sun9i-a80-mmc";
 574                         reg = <0x01c11000 0x1000>;
 575                         clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 576                                  <&mmc2_clk 1>, <&mmc2_clk 2>;
 577                         clock-names = "ahb", "mmc", "output", "sample";
 578                         resets = <&mmc_config_clk 2>;
 579                         reset-names = "ahb";
 580                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 581                         status = "disabled";
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                 };
 585
 586                 mmc3: mmc@01c12000 {
 587                         compatible = "allwinner,sun9i-a80-mmc";
 588                         reg = <0x01c12000 0x1000>;
 589                         clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 590                                  <&mmc3_clk 1>, <&mmc3_clk 2>;
 591                         clock-names = "ahb", "mmc", "output", "sample";
 592                         resets = <&mmc_config_clk 3>;
 593                         reset-names = "ahb";
 594                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 595                         status = "disabled";
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                 };
 599
 600                 mmc_config_clk: clk@01c13000 {
 601                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 602                         reg = <0x01c13000 0x10>;
 603                         clocks = <&ahb0_gates 8>;
 604                         clock-names = "ahb";
 605                         resets = <&ahb0_resets 8>;
 606                         reset-names = "ahb";
 607                         #clock-cells = <1>;
 608                         #reset-cells = <1>;
 609                         clock-output-names = "mmc0_config", "mmc1_config",
 610                                              "mmc2_config", "mmc3_config";
 611                 };
 612
 613                 gic: interrupt-controller@01c41000 {
 614                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 615                         reg = <0x01c41000 0x1000>,
 616                               <0x01c42000 0x1000>,
 617                               <0x01c44000 0x2000>,
 618                               <0x01c46000 0x2000>;
 619                         interrupt-controller;
 620                         #interrupt-cells = <3>;
 621                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 622                 };
 623
 624                 ahb0_resets: reset@060005a0 {
 625                         #reset-cells = <1>;
 626                         compatible = "allwinner,sun6i-a31-clock-reset";
 627                         reg = <0x060005a0 0x4>;
 628                 };
 629
 630                 ahb1_resets: reset@060005a4 {
 631                         #reset-cells = <1>;
 632                         compatible = "allwinner,sun6i-a31-clock-reset";
 633                         reg = <0x060005a4 0x4>;
 634                 };
 635
 636                 ahb2_resets: reset@060005a8 {
 637                         #reset-cells = <1>;
 638                         compatible = "allwinner,sun6i-a31-clock-reset";
 639                         reg = <0x060005a8 0x4>;
 640                 };
 641
 642                 apb0_resets: reset@060005b0 {
 643                         #reset-cells = <1>;
 644                         compatible = "allwinner,sun6i-a31-clock-reset";
 645                         reg = <0x060005b0 0x4>;
 646                 };
 647
 648                 apb1_resets: reset@060005b4 {
 649                         #reset-cells = <1>;
 650                         compatible = "allwinner,sun6i-a31-clock-reset";
 651                         reg = <0x060005b4 0x4>;
 652                 };
 653
 654                 timer@06000c00 {
 655                         compatible = "allwinner,sun4i-a10-timer";
 656                         reg = <0x06000c00 0xa0>;
 657                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 658                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 663
 664                         clocks = <&osc24M>;
 665                 };
 666
 667                 wdt: watchdog@06000ca0 {
 668                         compatible = "allwinner,sun6i-a31-wdt";
 669                         reg = <0x06000ca0 0x20>;
 670                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 671                 };
 672
 673                 pio: pinctrl@06000800 {
 674                         compatible = "allwinner,sun9i-a80-pinctrl";
 675                         reg = <0x06000800 0x400>;
 676                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&apb0_gates 5>;
 682                         gpio-controller;
 683                         interrupt-controller;
 684                         #interrupt-cells = <3>;
 685                         #size-cells = <0>;
 686                         #gpio-cells = <3>;
 687
 688                         i2c3_pins_a: i2c3@0 {
 689                                 allwinner,pins = "PG10", "PG11";
 690                                 allwinner,function = "i2c3";
 691                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 692                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 693                         };
 694
 695                         mmc0_pins: mmc0 {
 696                                 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
 697                                                  "PF4", "PF5";
 698                                 allwinner,function = "mmc0";
 699                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 700                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 701                         };
 702
 703                         mmc2_8bit_pins: mmc2_8bit {
 704                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 705                                                  "PC10", "PC11", "PC12",
 706                                                  "PC13", "PC14", "PC15",
 707                                                  "PC16";
 708                                 allwinner,function = "mmc2";
 709                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 710                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 711                         };
 712
 713                         uart0_pins_a: uart0@0 {
 714                                 allwinner,pins = "PH12", "PH13";
 715                                 allwinner,function = "uart0";
 716                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 717                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 718                         };
 719
 720                         uart4_pins_a: uart4@0 {
 721                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
 722                                 allwinner,function = "uart4";
 723                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 724                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 725                         };
 726                 };
 727
 728                 uart0: serial@07000000 {
 729                         compatible = "snps,dw-apb-uart";
 730                         reg = <0x07000000 0x400>;
 731                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 732                         reg-shift = <2>;
 733                         reg-io-width = <4>;
 734                         clocks = <&apb1_gates 16>;
 735                         resets = <&apb1_resets 16>;
 736                         status = "disabled";
 737                 };
 738
 739                 uart1: serial@07000400 {
 740                         compatible = "snps,dw-apb-uart";
 741                         reg = <0x07000400 0x400>;
 742                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 743                         reg-shift = <2>;
 744                         reg-io-width = <4>;
 745                         clocks = <&apb1_gates 17>;
 746                         resets = <&apb1_resets 17>;
 747                         status = "disabled";
 748                 };
 749
 750                 uart2: serial@07000800 {
 751                         compatible = "snps,dw-apb-uart";
 752                         reg = <0x07000800 0x400>;
 753                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 754                         reg-shift = <2>;
 755                         reg-io-width = <4>;
 756                         clocks = <&apb1_gates 18>;
 757                         resets = <&apb1_resets 18>;
 758                         status = "disabled";
 759                 };
 760
 761                 uart3: serial@07000c00 {
 762                         compatible = "snps,dw-apb-uart";
 763                         reg = <0x07000c00 0x400>;
 764                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 765                         reg-shift = <2>;
 766                         reg-io-width = <4>;
 767                         clocks = <&apb1_gates 19>;
 768                         resets = <&apb1_resets 19>;
 769                         status = "disabled";
 770                 };
 771
 772                 uart4: serial@07001000 {
 773                         compatible = "snps,dw-apb-uart";
 774                         reg = <0x07001000 0x400>;
 775                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 776                         reg-shift = <2>;
 777                         reg-io-width = <4>;
 778                         clocks = <&apb1_gates 20>;
 779                         resets = <&apb1_resets 20>;
 780                         status = "disabled";
 781                 };
 782
 783                 uart5: serial@07001400 {
 784                         compatible = "snps,dw-apb-uart";
 785                         reg = <0x07001400 0x400>;
 786                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 787                         reg-shift = <2>;
 788                         reg-io-width = <4>;
 789                         clocks = <&apb1_gates 21>;
 790                         resets = <&apb1_resets 21>;
 791                         status = "disabled";
 792                 };
 793
 794                 i2c0: i2c@07002800 {
 795                         compatible = "allwinner,sun6i-a31-i2c";
 796                         reg = <0x07002800 0x400>;
 797                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 798                         clocks = <&apb1_gates 0>;
 799                         resets = <&apb1_resets 0>;
 800                         status = "disabled";
 801                         #address-cells = <1>;
 802                         #size-cells = <0>;
 803                 };
 804
 805                 i2c1: i2c@07002c00 {
 806                         compatible = "allwinner,sun6i-a31-i2c";
 807                         reg = <0x07002c00 0x400>;
 808                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 809                         clocks = <&apb1_gates 1>;
 810                         resets = <&apb1_resets 1>;
 811                         status = "disabled";
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                 };
 815
 816                 i2c2: i2c@07003000 {
 817                         compatible = "allwinner,sun6i-a31-i2c";
 818                         reg = <0x07003000 0x400>;
 819                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 820                         clocks = <&apb1_gates 2>;
 821                         resets = <&apb1_resets 2>;
 822                         status = "disabled";
 823                         #address-cells = <1>;
 824                         #size-cells = <0>;
 825                 };
 826
 827                 i2c3: i2c@07003400 {
 828                         compatible = "allwinner,sun6i-a31-i2c";
 829                         reg = <0x07003400 0x400>;
 830                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 831                         clocks = <&apb1_gates 3>;
 832                         resets = <&apb1_resets 3>;
 833                         status = "disabled";
 834                         #address-cells = <1>;
 835                         #size-cells = <0>;
 836                 };
 837
 838                 i2c4: i2c@07003800 {
 839                         compatible = "allwinner,sun6i-a31-i2c";
 840                         reg = <0x07003800 0x400>;
 841                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 842                         clocks = <&apb1_gates 4>;
 843                         resets = <&apb1_resets 4>;
 844                         status = "disabled";
 845                         #address-cells = <1>;
 846                         #size-cells = <0>;
 847                 };
 848
 849                 r_wdt: watchdog@08001000 {
 850                         compatible = "allwinner,sun6i-a31-wdt";
 851                         reg = <0x08001000 0x20>;
 852                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 853                 };
 854
 855                 apbs_rst: reset@080014b0 {
 856                         reg = <0x080014b0 0x4>;
 857                         compatible = "allwinner,sun6i-a31-clock-reset";
 858                         #reset-cells = <1>;
 859                 };
 860
 861                 nmi_intc: interrupt-controller@080015a0 {
 862                         compatible = "allwinner,sun9i-a80-nmi";
 863                         interrupt-controller;
 864                         #interrupt-cells = <2>;
 865                         reg = <0x080015a0 0xc>;
 866                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 867                 };
 868
 869                 r_ir: ir@08002000 {
 870                         compatible = "allwinner,sun5i-a13-ir";
 871                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 872                         pinctrl-names = "default";
 873                         pinctrl-0 = <&r_ir_pins>;
 874                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
 875                         clock-names = "apb", "ir";
 876                         resets = <&apbs_rst 1>;
 877                         reg = <0x08002000 0x40>;
 878                         status = "disabled";
 879                 };
 880
 881                 r_uart: serial@08002800 {
 882                         compatible = "snps,dw-apb-uart";
 883                         reg = <0x08002800 0x400>;
 884                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 885                         reg-shift = <2>;
 886                         reg-io-width = <4>;
 887                         clocks = <&apbs_gates 4>;
 888                         resets = <&apbs_rst 4>;
 889                         status = "disabled";
 890                 };
 891
 892                 r_pio: pinctrl@08002c00 {
 893                         compatible = "allwinner,sun9i-a80-r-pinctrl";
 894                         reg = <0x08002c00 0x400>;
 895                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 896                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&apbs_gates 0>;
 898                         resets = <&apbs_rst 0>;
 899                         gpio-controller;
 900                         interrupt-controller;
 901                         #interrupt-cells = <3>;
 902                         #gpio-cells = <3>;
 903
 904                         r_ir_pins: r_ir {
 905                                 allwinner,pins = "PL6";
 906                                 allwinner,function = "s_cir_rx";
 907                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 908                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 909                         };
 910
 911                         r_rsb_pins: r_rsb {
 912                                 allwinner,pins = "PN0", "PN1";
 913                                 allwinner,function = "s_rsb";
 914                                 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
 915                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 916                         };
 917                 };
 918
 919                 r_rsb: i2c@08003400 {
 920                         compatible = "allwinner,sun8i-a23-rsb";
 921                         reg = <0x08003400 0x400>;
 922                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 923                         clocks = <&apbs_gates 3>;
 924                         clock-frequency = <3000000>;
 925                         resets = <&apbs_rst 3>;
 926                         pinctrl-names = "default";
 927                         pinctrl-0 = <&r_rsb_pins>;
 928                         status = "disabled";
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931                 };
 932         };
 933 };