arch/arm/boot/dts/uniphier-proxstream2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier ProXstream2 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /include/ "uniphier-common32.dtsi"
  46
  47 / {
  48         compatible = "socionext,proxstream2";
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53                 enable-method = "socionext,uniphier-smp";
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         reg = <0>;
  59                         next-level-cache = <&l2>;
  60                 };
  61
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a9";
  65                         reg = <1>;
  66                         next-level-cache = <&l2>;
  67                 };
  68
  69                 cpu@2 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a9";
  72                         reg = <2>;
  73                         next-level-cache = <&l2>;
  74                 };
  75
  76                 cpu@3 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a9";
  79                         reg = <3>;
  80                         next-level-cache = <&l2>;
  81                 };
  82         };
  83
  84         clocks {
  85                 arm_timer_clk: arm_timer_clk {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <50000000>;
  89                 };
  90
  91                 uart_clk: uart_clk {
  92                         #clock-cells = <0>;
  93                         compatible = "fixed-clock";
  94                         clock-frequency = <88900000>;
  95                 };
  96
  97                 i2c_clk: i2c_clk {
  98                         #clock-cells = <0>;
  99                         compatible = "fixed-clock";
 100                         clock-frequency = <50000000>;
 101                 };
 102         };
 103 };
 104
 105 &soc {
 106         l2: l2-cache@500c0000 {
 107                 compatible = "socionext,uniphier-system-cache";
 108                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
 109                 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 110                 cache-unified;
 111                 cache-size = <(1280 * 1024)>;
 112                 cache-sets = <512>;
 113                 cache-line-size = <128>;
 114                 cache-level = <2>;
 115         };
 116
 117         i2c0: i2c@58780000 {
 118                 compatible = "socionext,uniphier-fi2c";
 119                 status = "disabled";
 120                 reg = <0x58780000 0x80>;
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123                 interrupts = <0 41 4>;
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&pinctrl_i2c0>;
 126                 clocks = <&i2c_clk>;
 127                 clock-frequency = <100000>;
 128         };
 129
 130         i2c1: i2c@58781000 {
 131                 compatible = "socionext,uniphier-fi2c";
 132                 status = "disabled";
 133                 reg = <0x58781000 0x80>;
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 interrupts = <0 42 4>;
 137                 pinctrl-names = "default";
 138                 pinctrl-0 = <&pinctrl_i2c1>;
 139                 clocks = <&i2c_clk>;
 140                 clock-frequency = <100000>;
 141         };
 142
 143         i2c2: i2c@58782000 {
 144                 compatible = "socionext,uniphier-fi2c";
 145                 status = "disabled";
 146                 reg = <0x58782000 0x80>;
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149                 pinctrl-names = "default";
 150                 pinctrl-0 = <&pinctrl_i2c2>;
 151                 interrupts = <0 43 4>;
 152                 clocks = <&i2c_clk>;
 153                 clock-frequency = <100000>;
 154         };
 155
 156         i2c3: i2c@58783000 {
 157                 compatible = "socionext,uniphier-fi2c";
 158                 status = "disabled";
 159                 reg = <0x58783000 0x80>;
 160                 #address-cells = <1>;
 161                 #size-cells = <0>;
 162                 interrupts = <0 44 4>;
 163                 pinctrl-names = "default";
 164                 pinctrl-0 = <&pinctrl_i2c3>;
 165                 clocks = <&i2c_clk>;
 166                 clock-frequency = <100000>;
 167         };
 168
 169         /* chip-internal connection for DMD */
 170         i2c4: i2c@58784000 {
 171                 compatible = "socionext,uniphier-fi2c";
 172                 reg = <0x58784000 0x80>;
 173                 #address-cells = <1>;
 174                 #size-cells = <0>;
 175                 interrupts = <0 45 4>;
 176                 clocks = <&i2c_clk>;
 177                 clock-frequency = <400000>;
 178         };
 179
 180         /* chip-internal connection for STM */
 181         i2c5: i2c@58785000 {
 182                 compatible = "socionext,uniphier-fi2c";
 183                 reg = <0x58785000 0x80>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 interrupts = <0 25 4>;
 187                 clocks = <&i2c_clk>;
 188                 clock-frequency = <400000>;
 189         };
 190
 191         /* chip-internal connection for HDMI */
 192         i2c6: i2c@58786000 {
 193                 compatible = "socionext,uniphier-fi2c";
 194                 reg = <0x58786000 0x80>;
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 interrupts = <0 26 4>;
 198                 clocks = <&i2c_clk>;
 199                 clock-frequency = <400000>;
 200         };
 201 };
 202
 203 &refclk {
 204         clock-frequency = <25000000>;
 205 };
 206
 207 &pinctrl {
 208         compatible = "socionext,uniphier-pxs2-pinctrl";
 209 };