arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPUIR     4
  12 #define CPUID_MPIDR     5
  13 #define CPUID_REVIDR    6
  14
  15 #ifdef CONFIG_CPU_V7M
  16 #define CPUID_EXT_PFR0  0x40
  17 #define CPUID_EXT_PFR1  0x44
  18 #define CPUID_EXT_DFR0  0x48
  19 #define CPUID_EXT_AFR0  0x4c
  20 #define CPUID_EXT_MMFR0 0x50
  21 #define CPUID_EXT_MMFR1 0x54
  22 #define CPUID_EXT_MMFR2 0x58
  23 #define CPUID_EXT_MMFR3 0x5c
  24 #define CPUID_EXT_ISAR0 0x60
  25 #define CPUID_EXT_ISAR1 0x64
  26 #define CPUID_EXT_ISAR2 0x68
  27 #define CPUID_EXT_ISAR3 0x6c
  28 #define CPUID_EXT_ISAR4 0x70
  29 #define CPUID_EXT_ISAR5 0x74
  30 #else
  31 #define CPUID_EXT_PFR0  "c1, 0"
  32 #define CPUID_EXT_PFR1  "c1, 1"
  33 #define CPUID_EXT_DFR0  "c1, 2"
  34 #define CPUID_EXT_AFR0  "c1, 3"
  35 #define CPUID_EXT_MMFR0 "c1, 4"
  36 #define CPUID_EXT_MMFR1 "c1, 5"
  37 #define CPUID_EXT_MMFR2 "c1, 6"
  38 #define CPUID_EXT_MMFR3 "c1, 7"
  39 #define CPUID_EXT_ISAR0 "c2, 0"
  40 #define CPUID_EXT_ISAR1 "c2, 1"
  41 #define CPUID_EXT_ISAR2 "c2, 2"
  42 #define CPUID_EXT_ISAR3 "c2, 3"
  43 #define CPUID_EXT_ISAR4 "c2, 4"
  44 #define CPUID_EXT_ISAR5 "c2, 5"
  45 #endif
  46
  47 #define MPIDR_SMP_BITMASK (0x3 << 30)
  48 #define MPIDR_SMP_VALUE (0x2 << 30)
  49
  50 #define MPIDR_MT_BITMASK (0x1 << 24)
  51
  52 #define MPIDR_HWID_BITMASK 0xFFFFFF
  53
  54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  55
  56 #define MPIDR_LEVEL_BITS 8
  57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  58 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
  59
  60 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  61         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  62
  63 #define ARM_CPU_IMP_ARM                 0x41
  64 #define ARM_CPU_IMP_DEC                 0x44
  65 #define ARM_CPU_IMP_INTEL               0x69
  66
  67 /* ARM implemented processors */
  68 #define ARM_CPU_PART_ARM1136            0x4100b360
  69 #define ARM_CPU_PART_ARM1156            0x4100b560
  70 #define ARM_CPU_PART_ARM1176            0x4100b760
  71 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  72 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  73 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  74 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  75 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  76 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  77 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  78 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  79 #define ARM_CPU_PART_MASK               0xff00fff0
  80
  81 /* DEC implemented cores */
  82 #define ARM_CPU_PART_SA1100             0x4400a110
  83
  84 /* Intel implemented cores */
  85 #define ARM_CPU_PART_SA1110             0x6900b110
  86 #define ARM_CPU_REV_SA1110_A0           0
  87 #define ARM_CPU_REV_SA1110_B0           4
  88 #define ARM_CPU_REV_SA1110_B1           5
  89 #define ARM_CPU_REV_SA1110_B2           6
  90 #define ARM_CPU_REV_SA1110_B4           8
  91
  92 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  93 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  94 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  95 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  96
  97 extern unsigned int processor_id;
  98
  99 #ifdef CONFIG_CPU_CP15
 100 #define read_cpuid(reg)                                                 \
 101         ({                                                              \
 102                 unsigned int __val;                                     \
 103                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
 104                     : "=r" (__val)                                      \
 105                     :                                                   \
 106                     : "cc");                                            \
 107                 __val;                                                  \
 108         })
 109
 110 /*
 111  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 112  * any is_smp() tests, which can cause undefined instruction aborts on
 113  * ARM1136 r0 due to the missing extended CP15 registers.
 114  */
 115 #define read_cpuid_ext(ext_reg)                                         \
 116         ({                                                              \
 117                 unsigned int __val;                                     \
 118                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 119                     : "=r" (__val)                                      \
 120                     :                                                   \
 121                     : "memory");                                        \
 122                 __val;                                                  \
 123         })
 124
 125 #elif defined(CONFIG_CPU_V7M)
 126
 127 #include <asm/io.h>
 128 #include <asm/v7m.h>
 129
 130 #define read_cpuid(reg)                                                 \
 131         ({                                                              \
 132                 WARN_ON_ONCE(1);                                        \
 133                 0;                                                      \
 134         })
 135
 136 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 137 {
 138         return readl(BASEADDR_V7M_SCB + offset);
 139 }
 140
 141 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 142
 143 /*
 144  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 145  * have cp15 so warn on other usages.
 146  */
 147 #define read_cpuid(reg)                                                 \
 148         ({                                                              \
 149                 WARN_ON_ONCE(1);                                        \
 150                 0;                                                      \
 151         })
 152
 153 #define read_cpuid_ext(reg) read_cpuid(reg)
 154
 155 #endif /* ifdef CONFIG_CPU_CP15 / else */
 156
 157 #ifdef CONFIG_CPU_CP15
 158 /*
 159  * The CPU ID never changes at run time, so we might as well tell the
 160  * compiler that it's constant.  Use this function to read the CPU ID
 161  * rather than directly reading processor_id or read_cpuid() directly.
 162  */
 163 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 164 {
 165         return read_cpuid(CPUID_ID);
 166 }
 167
 168 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 169 {
 170         return read_cpuid(CPUID_CACHETYPE);
 171 }
 172
 173 #elif defined(CONFIG_CPU_V7M)
 174
 175 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 176 {
 177         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 178 }
 179
 180 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 181 {
 182         return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
 183 }
 184
 185 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 186
 187 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 188 {
 189         return processor_id;
 190 }
 191
 192 #endif /* ifdef CONFIG_CPU_CP15 / else */
 193
 194 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 195 {
 196         return (read_cpuid_id() & 0xFF000000) >> 24;
 197 }
 198
 199 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
 200 {
 201         return read_cpuid_id() & 0x0000000f;
 202 }
 203
 204 /*
 205  * The CPU part number is meaningless without referring to the CPU
 206  * implementer: implementers are free to define their own part numbers
 207  * which are permitted to clash with other implementer part numbers.
 208  */
 209 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 210 {
 211         return read_cpuid_id() & ARM_CPU_PART_MASK;
 212 }
 213
 214 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 215 {
 216         return read_cpuid_id() & 0xFFF0;
 217 }
 218
 219 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 220 {
 221         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 222 }
 223
 224 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 225 {
 226         return read_cpuid(CPUID_TCM);
 227 }
 228
 229 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 230 {
 231         return read_cpuid(CPUID_MPIDR);
 232 }
 233
 234 /* StrongARM-11x0 CPUs */
 235 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
 236 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
 237
 238 /*
 239  * Intel's XScale3 core supports some v6 features (supersections, L2)
 240  * but advertises itself as v5 as it does not support the v6 ISA.  For
 241  * this reason, we need a way to explicitly test for this type of CPU.
 242  */
 243 #ifndef CONFIG_CPU_XSC3
 244 #define cpu_is_xsc3()   0
 245 #else
 246 static inline int cpu_is_xsc3(void)
 247 {
 248         unsigned int id;
 249         id = read_cpuid_id() & 0xffffe000;
 250         /* It covers both Intel ID and Marvell ID */
 251         if ((id == 0x69056000) || (id == 0x56056000))
 252                 return 1;
 253
 254         return 0;
 255 }
 256 #endif
 257
 258 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
 259     !defined(CONFIG_CPU_MOHAWK)
 260 #define cpu_is_xscale_family() 0
 261 #else
 262 static inline int cpu_is_xscale_family(void)
 263 {
 264         unsigned int id;
 265         id = read_cpuid_id() & 0xffffe000;
 266
 267         switch (id) {
 268         case 0x69052000: /* Intel XScale 1 */
 269         case 0x69054000: /* Intel XScale 2 */
 270         case 0x69056000: /* Intel XScale 3 */
 271         case 0x56056000: /* Marvell XScale 3 */
 272         case 0x56158000: /* Marvell Mohawk */
 273                 return 1;
 274         }
 275
 276         return 0;
 277 }
 278 #endif
 279
 280 /*
 281  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 282  * but require a specical sequence for enabling coprocessors.
 283  * For this reason, we need a way to distinguish them.
 284  */
 285 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 286 static inline int cpu_is_pj4(void)
 287 {
 288         unsigned int id;
 289
 290         id = read_cpuid_id();
 291         if ((id & 0xff0fff00) == 0x560f5800)
 292                 return 1;
 293
 294         return 0;
 295 }
 296 #else
 297 #define cpu_is_pj4()    0
 298 #endif
 299
 300 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 301                                                                   int field)
 302 {
 303         int feature = (features >> field) & 15;
 304
 305         /* feature registers are signed values */
 306         if (feature > 7)
 307                 feature -= 16;
 308
 309         return feature;
 310 }
 311
 312 #define cpuid_feature_extract(reg, field) \
 313         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 314
 315 #endif