arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/hsmmc-omap.h>
  19 #include <linux/platform_data/spi-omap2-mcspi.h>
  20 #include "omap_hwmod.h"
  21 #include "i2c.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27 #include "common.h"
  28
  29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  33
  34 /*
  35  * 'l3' class
  36  * instance(s): l3_main, l3_s, l3_instr
  37  */
  38 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  39         .name           = "l3",
  40 };
  41
  42 struct omap_hwmod am33xx_l3_main_hwmod = {
  43         .name           = "l3_main",
  44         .class          = &am33xx_l3_hwmod_class,
  45         .clkdm_name     = "l3_clkdm",
  46         .flags          = HWMOD_INIT_NO_IDLE,
  47         .main_clk       = "l3_gclk",
  48         .prcm           = {
  49                 .omap4  = {
  50                         .modulemode     = MODULEMODE_SWCTRL,
  51                 },
  52         },
  53 };
  54
  55 /* l3_s */
  56 struct omap_hwmod am33xx_l3_s_hwmod = {
  57         .name           = "l3_s",
  58         .class          = &am33xx_l3_hwmod_class,
  59         .clkdm_name     = "l3s_clkdm",
  60 };
  61
  62 /* l3_instr */
  63 struct omap_hwmod am33xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &am33xx_l3_hwmod_class,
  66         .clkdm_name     = "l3_clkdm",
  67         .flags          = HWMOD_INIT_NO_IDLE,
  68         .main_clk       = "l3_gclk",
  69         .prcm           = {
  70                 .omap4  = {
  71                         .modulemode     = MODULEMODE_SWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /*
  77  * 'l4' class
  78  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  79  */
  80 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  81         .name           = "l4",
  82 };
  83
  84 /* l4_ls */
  85 struct omap_hwmod am33xx_l4_ls_hwmod = {
  86         .name           = "l4_ls",
  87         .class          = &am33xx_l4_hwmod_class,
  88         .clkdm_name     = "l4ls_clkdm",
  89         .flags          = HWMOD_INIT_NO_IDLE,
  90         .main_clk       = "l4ls_gclk",
  91         .prcm           = {
  92                 .omap4  = {
  93                         .modulemode     = MODULEMODE_SWCTRL,
  94                 },
  95         },
  96 };
  97
  98 /* l4_wkup */
  99 struct omap_hwmod am33xx_l4_wkup_hwmod = {
 100         .name           = "l4_wkup",
 101         .class          = &am33xx_l4_hwmod_class,
 102         .clkdm_name     = "l4_wkup_clkdm",
 103         .flags          = HWMOD_INIT_NO_IDLE,
 104         .prcm           = {
 105                 .omap4  = {
 106                         .modulemode     = MODULEMODE_SWCTRL,
 107                 },
 108         },
 109 };
 110
 111 /*
 112  * 'mpu' class
 113  */
 114 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 115         .name   = "mpu",
 116 };
 117
 118 struct omap_hwmod am33xx_mpu_hwmod = {
 119         .name           = "mpu",
 120         .class          = &am33xx_mpu_hwmod_class,
 121         .clkdm_name     = "mpu_clkdm",
 122         .flags          = HWMOD_INIT_NO_IDLE,
 123         .main_clk       = "dpll_mpu_m2_ck",
 124         .prcm           = {
 125                 .omap4  = {
 126                         .modulemode     = MODULEMODE_SWCTRL,
 127                 },
 128         },
 129 };
 130
 131 /*
 132  * 'wakeup m3' class
 133  * Wakeup controller sub-system under wakeup domain
 134  */
 135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 136         .name           = "wkup_m3",
 137 };
 138
 139 /*
 140  * 'pru-icss' class
 141  * Programmable Real-Time Unit and Industrial Communication Subsystem
 142  */
 143 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 144         .name   = "pruss",
 145 };
 146
 147 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 148         { .name = "pruss", .rst_shift = 1 },
 149 };
 150
 151 /* pru-icss */
 152 /* Pseudo hwmod for reset control purpose only */
 153 struct omap_hwmod am33xx_pruss_hwmod = {
 154         .name           = "pruss",
 155         .class          = &am33xx_pruss_hwmod_class,
 156         .clkdm_name     = "pruss_ocp_clkdm",
 157         .main_clk       = "pruss_ocp_gclk",
 158         .prcm           = {
 159                 .omap4  = {
 160                         .modulemode     = MODULEMODE_SWCTRL,
 161                 },
 162         },
 163         .rst_lines      = am33xx_pruss_resets,
 164         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 165 };
 166
 167 /* gfx */
 168 /* Pseudo hwmod for reset control purpose only */
 169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 170         .name   = "gfx",
 171 };
 172
 173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 174         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 175 };
 176
 177 struct omap_hwmod am33xx_gfx_hwmod = {
 178         .name           = "gfx",
 179         .class          = &am33xx_gfx_hwmod_class,
 180         .clkdm_name     = "gfx_l3_clkdm",
 181         .main_clk       = "gfx_fck_div_ck",
 182         .prcm           = {
 183                 .omap4  = {
 184                         .modulemode     = MODULEMODE_SWCTRL,
 185                 },
 186         },
 187         .rst_lines      = am33xx_gfx_resets,
 188         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 189 };
 190
 191 /*
 192  * 'prcm' class
 193  * power and reset manager (whole prcm infrastructure)
 194  */
 195 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 196         .name   = "prcm",
 197 };
 198
 199 /* prcm */
 200 struct omap_hwmod am33xx_prcm_hwmod = {
 201         .name           = "prcm",
 202         .class          = &am33xx_prcm_hwmod_class,
 203         .clkdm_name     = "l4_wkup_clkdm",
 204 };
 205
 206 /*
 207  * 'emif' class
 208  * instance(s): emif
 209  */
 210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 211         .rev_offs       = 0x0000,
 212 };
 213
 214 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 215         .name           = "emif",
 216         .sysc           = &am33xx_emif_sysc,
 217 };
 218
 219 /*
 220  * 'aes0' class
 221  */
 222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 223         .rev_offs       = 0x80,
 224         .sysc_offs      = 0x84,
 225         .syss_offs      = 0x88,
 226         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 227 };
 228
 229 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 230         .name           = "aes0",
 231         .sysc           = &am33xx_aes0_sysc,
 232 };
 233
 234 struct omap_hwmod am33xx_aes0_hwmod = {
 235         .name           = "aes",
 236         .class          = &am33xx_aes0_hwmod_class,
 237         .clkdm_name     = "l3_clkdm",
 238         .main_clk       = "aes0_fck",
 239         .prcm           = {
 240                 .omap4  = {
 241                         .modulemode     = MODULEMODE_SWCTRL,
 242                 },
 243         },
 244 };
 245
 246 /* sha0 HIB2 (the 'P' (public) device) */
 247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 248         .rev_offs       = 0x100,
 249         .sysc_offs      = 0x110,
 250         .syss_offs      = 0x114,
 251         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 252 };
 253
 254 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 255         .name           = "sha0",
 256         .sysc           = &am33xx_sha0_sysc,
 257 };
 258
 259 struct omap_hwmod am33xx_sha0_hwmod = {
 260         .name           = "sham",
 261         .class          = &am33xx_sha0_hwmod_class,
 262         .clkdm_name     = "l3_clkdm",
 263         .main_clk       = "l3_gclk",
 264         .prcm           = {
 265                 .omap4  = {
 266                         .modulemode     = MODULEMODE_SWCTRL,
 267                 },
 268         },
 269 };
 270
 271 /* ocmcram */
 272 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 273         .name = "ocmcram",
 274 };
 275
 276 struct omap_hwmod am33xx_ocmcram_hwmod = {
 277         .name           = "ocmcram",
 278         .class          = &am33xx_ocmcram_hwmod_class,
 279         .clkdm_name     = "l3_clkdm",
 280         .flags          = HWMOD_INIT_NO_IDLE,
 281         .main_clk       = "l3_gclk",
 282         .prcm           = {
 283                 .omap4  = {
 284                         .modulemode     = MODULEMODE_SWCTRL,
 285                 },
 286         },
 287 };
 288
 289 /* 'smartreflex' class */
 290 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 291         .name           = "smartreflex",
 292 };
 293
 294 /* smartreflex0 */
 295 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 296         .name           = "smartreflex0",
 297         .class          = &am33xx_smartreflex_hwmod_class,
 298         .clkdm_name     = "l4_wkup_clkdm",
 299         .main_clk       = "smartreflex0_fck",
 300         .prcm           = {
 301                 .omap4  = {
 302                         .modulemode     = MODULEMODE_SWCTRL,
 303                 },
 304         },
 305 };
 306
 307 /* smartreflex1 */
 308 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 309         .name           = "smartreflex1",
 310         .class          = &am33xx_smartreflex_hwmod_class,
 311         .clkdm_name     = "l4_wkup_clkdm",
 312         .main_clk       = "smartreflex1_fck",
 313         .prcm           = {
 314                 .omap4  = {
 315                         .modulemode     = MODULEMODE_SWCTRL,
 316                 },
 317         },
 318 };
 319
 320 /*
 321  * 'control' module class
 322  */
 323 struct omap_hwmod_class am33xx_control_hwmod_class = {
 324         .name           = "control",
 325 };
 326
 327 /*
 328  * 'cpgmac' class
 329  * cpsw/cpgmac sub system
 330  */
 331 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 332         .rev_offs       = 0x0,
 333         .sysc_offs      = 0x8,
 334         .syss_offs      = 0x4,
 335         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 336                            SYSS_HAS_RESET_STATUS),
 337         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 338                            MSTANDBY_NO),
 339         .sysc_fields    = &omap_hwmod_sysc_type3,
 340 };
 341
 342 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 343         .name           = "cpgmac0",
 344         .sysc           = &am33xx_cpgmac_sysc,
 345 };
 346
 347 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 348         .name           = "cpgmac0",
 349         .class          = &am33xx_cpgmac0_hwmod_class,
 350         .clkdm_name     = "cpsw_125mhz_clkdm",
 351         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 352         .main_clk       = "cpsw_125mhz_gclk",
 353         .mpu_rt_idx     = 1,
 354         .prcm           = {
 355                 .omap4  = {
 356                         .modulemode     = MODULEMODE_SWCTRL,
 357                 },
 358         },
 359 };
 360
 361 /*
 362  * mdio class
 363  */
 364 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 365         .name           = "davinci_mdio",
 366 };
 367
 368 struct omap_hwmod am33xx_mdio_hwmod = {
 369         .name           = "davinci_mdio",
 370         .class          = &am33xx_mdio_hwmod_class,
 371         .clkdm_name     = "cpsw_125mhz_clkdm",
 372         .main_clk       = "cpsw_125mhz_gclk",
 373 };
 374
 375 /*
 376  * dcan class
 377  */
 378 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 379         .name = "d_can",
 380 };
 381
 382 /* dcan0 */
 383 struct omap_hwmod am33xx_dcan0_hwmod = {
 384         .name           = "d_can0",
 385         .class          = &am33xx_dcan_hwmod_class,
 386         .clkdm_name     = "l4ls_clkdm",
 387         .main_clk       = "dcan0_fck",
 388         .prcm           = {
 389                 .omap4  = {
 390                         .modulemode     = MODULEMODE_SWCTRL,
 391                 },
 392         },
 393 };
 394
 395 /* dcan1 */
 396 struct omap_hwmod am33xx_dcan1_hwmod = {
 397         .name           = "d_can1",
 398         .class          = &am33xx_dcan_hwmod_class,
 399         .clkdm_name     = "l4ls_clkdm",
 400         .main_clk       = "dcan1_fck",
 401         .prcm           = {
 402                 .omap4  = {
 403                         .modulemode     = MODULEMODE_SWCTRL,
 404                 },
 405         },
 406 };
 407
 408 /* elm */
 409 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 410         .rev_offs       = 0x0000,
 411         .sysc_offs      = 0x0010,
 412         .syss_offs      = 0x0014,
 413         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 414                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 415                         SYSS_HAS_RESET_STATUS),
 416         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 417         .sysc_fields    = &omap_hwmod_sysc_type1,
 418 };
 419
 420 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 421         .name           = "elm",
 422         .sysc           = &am33xx_elm_sysc,
 423 };
 424
 425 struct omap_hwmod am33xx_elm_hwmod = {
 426         .name           = "elm",
 427         .class          = &am33xx_elm_hwmod_class,
 428         .clkdm_name     = "l4ls_clkdm",
 429         .main_clk       = "l4ls_gclk",
 430         .prcm           = {
 431                 .omap4  = {
 432                         .modulemode     = MODULEMODE_SWCTRL,
 433                 },
 434         },
 435 };
 436
 437 /* pwmss  */
 438 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 439         .rev_offs       = 0x0,
 440         .sysc_offs      = 0x4,
 441         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 442         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 443                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 444                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 445         .sysc_fields    = &omap_hwmod_sysc_type2,
 446 };
 447
 448 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 449         .name           = "epwmss",
 450         .sysc           = &am33xx_epwmss_sysc,
 451 };
 452
 453 /* epwmss0 */
 454 struct omap_hwmod am33xx_epwmss0_hwmod = {
 455         .name           = "epwmss0",
 456         .class          = &am33xx_epwmss_hwmod_class,
 457         .clkdm_name     = "l4ls_clkdm",
 458         .main_clk       = "l4ls_gclk",
 459         .prcm           = {
 460                 .omap4  = {
 461                         .modulemode     = MODULEMODE_SWCTRL,
 462                 },
 463         },
 464 };
 465
 466 /* epwmss1 */
 467 struct omap_hwmod am33xx_epwmss1_hwmod = {
 468         .name           = "epwmss1",
 469         .class          = &am33xx_epwmss_hwmod_class,
 470         .clkdm_name     = "l4ls_clkdm",
 471         .main_clk       = "l4ls_gclk",
 472         .prcm           = {
 473                 .omap4  = {
 474                         .modulemode     = MODULEMODE_SWCTRL,
 475                 },
 476         },
 477 };
 478
 479 /* epwmss2 */
 480 struct omap_hwmod am33xx_epwmss2_hwmod = {
 481         .name           = "epwmss2",
 482         .class          = &am33xx_epwmss_hwmod_class,
 483         .clkdm_name     = "l4ls_clkdm",
 484         .main_clk       = "l4ls_gclk",
 485         .prcm           = {
 486                 .omap4  = {
 487                         .modulemode     = MODULEMODE_SWCTRL,
 488                 },
 489         },
 490 };
 491
 492 /*
 493  * 'gpio' class: for gpio 0,1,2,3
 494  */
 495 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 496         .rev_offs       = 0x0000,
 497         .sysc_offs      = 0x0010,
 498         .syss_offs      = 0x0114,
 499         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 500                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 501                           SYSS_HAS_RESET_STATUS),
 502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 503                           SIDLE_SMART_WKUP),
 504         .sysc_fields    = &omap_hwmod_sysc_type1,
 505 };
 506
 507 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 508         .name           = "gpio",
 509         .sysc           = &am33xx_gpio_sysc,
 510         .rev            = 2,
 511 };
 512
 513 struct omap_gpio_dev_attr gpio_dev_attr = {
 514         .bank_width     = 32,
 515         .dbck_flag      = true,
 516 };
 517
 518 /* gpio1 */
 519 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 520         { .role = "dbclk", .clk = "gpio1_dbclk" },
 521 };
 522
 523 struct omap_hwmod am33xx_gpio1_hwmod = {
 524         .name           = "gpio2",
 525         .class          = &am33xx_gpio_hwmod_class,
 526         .clkdm_name     = "l4ls_clkdm",
 527         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 528         .main_clk       = "l4ls_gclk",
 529         .prcm           = {
 530                 .omap4  = {
 531                         .modulemode     = MODULEMODE_SWCTRL,
 532                 },
 533         },
 534         .opt_clks       = gpio1_opt_clks,
 535         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 536         .dev_attr       = &gpio_dev_attr,
 537 };
 538
 539 /* gpio2 */
 540 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 541         { .role = "dbclk", .clk = "gpio2_dbclk" },
 542 };
 543
 544 struct omap_hwmod am33xx_gpio2_hwmod = {
 545         .name           = "gpio3",
 546         .class          = &am33xx_gpio_hwmod_class,
 547         .clkdm_name     = "l4ls_clkdm",
 548         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 549         .main_clk       = "l4ls_gclk",
 550         .prcm           = {
 551                 .omap4  = {
 552                         .modulemode     = MODULEMODE_SWCTRL,
 553                 },
 554         },
 555         .opt_clks       = gpio2_opt_clks,
 556         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 557         .dev_attr       = &gpio_dev_attr,
 558 };
 559
 560 /* gpio3 */
 561 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 562         { .role = "dbclk", .clk = "gpio3_dbclk" },
 563 };
 564
 565 struct omap_hwmod am33xx_gpio3_hwmod = {
 566         .name           = "gpio4",
 567         .class          = &am33xx_gpio_hwmod_class,
 568         .clkdm_name     = "l4ls_clkdm",
 569         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 570         .main_clk       = "l4ls_gclk",
 571         .prcm           = {
 572                 .omap4  = {
 573                         .modulemode     = MODULEMODE_SWCTRL,
 574                 },
 575         },
 576         .opt_clks       = gpio3_opt_clks,
 577         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 578         .dev_attr       = &gpio_dev_attr,
 579 };
 580
 581 /* gpmc */
 582 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 583         .rev_offs       = 0x0,
 584         .sysc_offs      = 0x10,
 585         .syss_offs      = 0x14,
 586         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 587                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 588         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 589         .sysc_fields    = &omap_hwmod_sysc_type1,
 590 };
 591
 592 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 593         .name           = "gpmc",
 594         .sysc           = &gpmc_sysc,
 595 };
 596
 597 struct omap_hwmod am33xx_gpmc_hwmod = {
 598         .name           = "gpmc",
 599         .class          = &am33xx_gpmc_hwmod_class,
 600         .clkdm_name     = "l3s_clkdm",
 601         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 602         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 603         .main_clk       = "l3s_gclk",
 604         .prcm           = {
 605                 .omap4  = {
 606                         .modulemode     = MODULEMODE_SWCTRL,
 607                 },
 608         },
 609 };
 610
 611 /* 'i2c' class */
 612 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 613         .sysc_offs      = 0x0010,
 614         .syss_offs      = 0x0090,
 615         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 616                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 617                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 618         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 619                           SIDLE_SMART_WKUP),
 620         .sysc_fields    = &omap_hwmod_sysc_type1,
 621 };
 622
 623 static struct omap_hwmod_class i2c_class = {
 624         .name           = "i2c",
 625         .sysc           = &am33xx_i2c_sysc,
 626         .rev            = OMAP_I2C_IP_VERSION_2,
 627         .reset          = &omap_i2c_reset,
 628 };
 629
 630 static struct omap_i2c_dev_attr i2c_dev_attr = {
 631         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 632 };
 633
 634 /* i2c1 */
 635 struct omap_hwmod am33xx_i2c1_hwmod = {
 636         .name           = "i2c1",
 637         .class          = &i2c_class,
 638         .clkdm_name     = "l4_wkup_clkdm",
 639         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 640         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 641         .prcm           = {
 642                 .omap4  = {
 643                         .modulemode     = MODULEMODE_SWCTRL,
 644                 },
 645         },
 646         .dev_attr       = &i2c_dev_attr,
 647 };
 648
 649 /* i2c1 */
 650 struct omap_hwmod am33xx_i2c2_hwmod = {
 651         .name           = "i2c2",
 652         .class          = &i2c_class,
 653         .clkdm_name     = "l4ls_clkdm",
 654         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 655         .main_clk       = "dpll_per_m2_div4_ck",
 656         .prcm           = {
 657                 .omap4 = {
 658                         .modulemode     = MODULEMODE_SWCTRL,
 659                 },
 660         },
 661         .dev_attr       = &i2c_dev_attr,
 662 };
 663
 664 /* i2c3 */
 665 struct omap_hwmod am33xx_i2c3_hwmod = {
 666         .name           = "i2c3",
 667         .class          = &i2c_class,
 668         .clkdm_name     = "l4ls_clkdm",
 669         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 670         .main_clk       = "dpll_per_m2_div4_ck",
 671         .prcm           = {
 672                 .omap4  = {
 673                         .modulemode     = MODULEMODE_SWCTRL,
 674                 },
 675         },
 676         .dev_attr       = &i2c_dev_attr,
 677 };
 678
 679 /*
 680  * 'mailbox' class
 681  * mailbox module allowing communication between the on-chip processors using a
 682  * queued mailbox-interrupt mechanism.
 683  */
 684 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 685         .rev_offs       = 0x0000,
 686         .sysc_offs      = 0x0010,
 687         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 688                           SYSC_HAS_SOFTRESET),
 689         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 690         .sysc_fields    = &omap_hwmod_sysc_type2,
 691 };
 692
 693 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 694         .name   = "mailbox",
 695         .sysc   = &am33xx_mailbox_sysc,
 696 };
 697
 698 struct omap_hwmod am33xx_mailbox_hwmod = {
 699         .name           = "mailbox",
 700         .class          = &am33xx_mailbox_hwmod_class,
 701         .clkdm_name     = "l4ls_clkdm",
 702         .main_clk       = "l4ls_gclk",
 703         .prcm = {
 704                 .omap4 = {
 705                         .modulemode     = MODULEMODE_SWCTRL,
 706                 },
 707         },
 708 };
 709
 710 /*
 711  * 'mcasp' class
 712  */
 713 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 714         .rev_offs       = 0x0,
 715         .sysc_offs      = 0x4,
 716         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 717         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 718         .sysc_fields    = &omap_hwmod_sysc_type3,
 719 };
 720
 721 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 722         .name           = "mcasp",
 723         .sysc           = &am33xx_mcasp_sysc,
 724 };
 725
 726 /* mcasp0 */
 727 struct omap_hwmod am33xx_mcasp0_hwmod = {
 728         .name           = "mcasp0",
 729         .class          = &am33xx_mcasp_hwmod_class,
 730         .clkdm_name     = "l3s_clkdm",
 731         .main_clk       = "mcasp0_fck",
 732         .prcm           = {
 733                 .omap4  = {
 734                         .modulemode     = MODULEMODE_SWCTRL,
 735                 },
 736         },
 737 };
 738
 739 /* mcasp1 */
 740 struct omap_hwmod am33xx_mcasp1_hwmod = {
 741         .name           = "mcasp1",
 742         .class          = &am33xx_mcasp_hwmod_class,
 743         .clkdm_name     = "l3s_clkdm",
 744         .main_clk       = "mcasp1_fck",
 745         .prcm           = {
 746                 .omap4  = {
 747                         .modulemode     = MODULEMODE_SWCTRL,
 748                 },
 749         },
 750 };
 751
 752 /* 'mmc' class */
 753 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 754         .rev_offs       = 0x1fc,
 755         .sysc_offs      = 0x10,
 756         .syss_offs      = 0x14,
 757         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 758                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 759                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 760         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 761         .sysc_fields    = &omap_hwmod_sysc_type1,
 762 };
 763
 764 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 765         .name           = "mmc",
 766         .sysc           = &am33xx_mmc_sysc,
 767 };
 768
 769 /* mmc0 */
 770 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
 771         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 772 };
 773
 774 struct omap_hwmod am33xx_mmc0_hwmod = {
 775         .name           = "mmc1",
 776         .class          = &am33xx_mmc_hwmod_class,
 777         .clkdm_name     = "l4ls_clkdm",
 778         .main_clk       = "mmc_clk",
 779         .prcm           = {
 780                 .omap4  = {
 781                         .modulemode     = MODULEMODE_SWCTRL,
 782                 },
 783         },
 784         .dev_attr       = &am33xx_mmc0_dev_attr,
 785 };
 786
 787 /* mmc1 */
 788 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
 789         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 790 };
 791
 792 struct omap_hwmod am33xx_mmc1_hwmod = {
 793         .name           = "mmc2",
 794         .class          = &am33xx_mmc_hwmod_class,
 795         .clkdm_name     = "l4ls_clkdm",
 796         .main_clk       = "mmc_clk",
 797         .prcm           = {
 798                 .omap4  = {
 799                         .modulemode     = MODULEMODE_SWCTRL,
 800                 },
 801         },
 802         .dev_attr       = &am33xx_mmc1_dev_attr,
 803 };
 804
 805 /* mmc2 */
 806 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
 807         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 808 };
 809 struct omap_hwmod am33xx_mmc2_hwmod = {
 810         .name           = "mmc3",
 811         .class          = &am33xx_mmc_hwmod_class,
 812         .clkdm_name     = "l3s_clkdm",
 813         .main_clk       = "mmc_clk",
 814         .prcm           = {
 815                 .omap4  = {
 816                         .modulemode     = MODULEMODE_SWCTRL,
 817                 },
 818         },
 819         .dev_attr       = &am33xx_mmc2_dev_attr,
 820 };
 821
 822 /*
 823  * 'rtc' class
 824  * rtc subsystem
 825  */
 826 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 827         .rev_offs       = 0x0074,
 828         .sysc_offs      = 0x0078,
 829         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 830         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 831                           SIDLE_SMART | SIDLE_SMART_WKUP),
 832         .sysc_fields    = &omap_hwmod_sysc_type3,
 833 };
 834
 835 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 836         .name           = "rtc",
 837         .sysc           = &am33xx_rtc_sysc,
 838         .unlock         = &omap_hwmod_rtc_unlock,
 839         .lock           = &omap_hwmod_rtc_lock,
 840 };
 841
 842 struct omap_hwmod am33xx_rtc_hwmod = {
 843         .name           = "rtc",
 844         .class          = &am33xx_rtc_hwmod_class,
 845         .clkdm_name     = "l4_rtc_clkdm",
 846         .main_clk       = "clk_32768_ck",
 847         .prcm           = {
 848                 .omap4  = {
 849                         .modulemode     = MODULEMODE_SWCTRL,
 850                 },
 851         },
 852 };
 853
 854 /* 'spi' class */
 855 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 856         .rev_offs       = 0x0000,
 857         .sysc_offs      = 0x0110,
 858         .syss_offs      = 0x0114,
 859         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 860                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 861                           SYSS_HAS_RESET_STATUS),
 862         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 863         .sysc_fields    = &omap_hwmod_sysc_type1,
 864 };
 865
 866 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 867         .name           = "mcspi",
 868         .sysc           = &am33xx_mcspi_sysc,
 869         .rev            = OMAP4_MCSPI_REV,
 870 };
 871
 872 /* spi0 */
 873 struct omap2_mcspi_dev_attr mcspi_attrib = {
 874         .num_chipselect = 2,
 875 };
 876 struct omap_hwmod am33xx_spi0_hwmod = {
 877         .name           = "spi0",
 878         .class          = &am33xx_spi_hwmod_class,
 879         .clkdm_name     = "l4ls_clkdm",
 880         .main_clk       = "dpll_per_m2_div4_ck",
 881         .prcm           = {
 882                 .omap4  = {
 883                         .modulemode     = MODULEMODE_SWCTRL,
 884                 },
 885         },
 886         .dev_attr       = &mcspi_attrib,
 887 };
 888
 889 /* spi1 */
 890 struct omap_hwmod am33xx_spi1_hwmod = {
 891         .name           = "spi1",
 892         .class          = &am33xx_spi_hwmod_class,
 893         .clkdm_name     = "l4ls_clkdm",
 894         .main_clk       = "dpll_per_m2_div4_ck",
 895         .prcm           = {
 896                 .omap4  = {
 897                         .modulemode     = MODULEMODE_SWCTRL,
 898                 },
 899         },
 900         .dev_attr       = &mcspi_attrib,
 901 };
 902
 903 /*
 904  * 'spinlock' class
 905  * spinlock provides hardware assistance for synchronizing the
 906  * processes running on multiple processors
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .syss_offs      = 0x0014,
 913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 914                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 915                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 916         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 917         .sysc_fields    = &omap_hwmod_sysc_type1,
 918 };
 919
 920 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 921         .name           = "spinlock",
 922         .sysc           = &am33xx_spinlock_sysc,
 923 };
 924
 925 struct omap_hwmod am33xx_spinlock_hwmod = {
 926         .name           = "spinlock",
 927         .class          = &am33xx_spinlock_hwmod_class,
 928         .clkdm_name     = "l4ls_clkdm",
 929         .main_clk       = "l4ls_gclk",
 930         .prcm           = {
 931                 .omap4  = {
 932                         .modulemode     = MODULEMODE_SWCTRL,
 933                 },
 934         },
 935 };
 936
 937 /* 'timer 2-7' class */
 938 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 939         .rev_offs       = 0x0000,
 940         .sysc_offs      = 0x0010,
 941         .syss_offs      = 0x0014,
 942         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 944                           SIDLE_SMART_WKUP),
 945         .sysc_fields    = &omap_hwmod_sysc_type2,
 946 };
 947
 948 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 949         .name           = "timer",
 950         .sysc           = &am33xx_timer_sysc,
 951 };
 952
 953 /* timer1 1ms */
 954 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 955         .rev_offs       = 0x0000,
 956         .sysc_offs      = 0x0010,
 957         .syss_offs      = 0x0014,
 958         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 959                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 960                         SYSS_HAS_RESET_STATUS),
 961         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 962         .sysc_fields    = &omap_hwmod_sysc_type1,
 963 };
 964
 965 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 966         .name           = "timer",
 967         .sysc           = &am33xx_timer1ms_sysc,
 968 };
 969
 970 struct omap_hwmod am33xx_timer1_hwmod = {
 971         .name           = "timer1",
 972         .class          = &am33xx_timer1ms_hwmod_class,
 973         .clkdm_name     = "l4_wkup_clkdm",
 974         .main_clk       = "timer1_fck",
 975         .prcm           = {
 976                 .omap4  = {
 977                         .modulemode     = MODULEMODE_SWCTRL,
 978                 },
 979         },
 980 };
 981
 982 struct omap_hwmod am33xx_timer2_hwmod = {
 983         .name           = "timer2",
 984         .class          = &am33xx_timer_hwmod_class,
 985         .clkdm_name     = "l4ls_clkdm",
 986         .main_clk       = "timer2_fck",
 987         .prcm           = {
 988                 .omap4  = {
 989                         .modulemode     = MODULEMODE_SWCTRL,
 990                 },
 991         },
 992 };
 993
 994 struct omap_hwmod am33xx_timer3_hwmod = {
 995         .name           = "timer3",
 996         .class          = &am33xx_timer_hwmod_class,
 997         .clkdm_name     = "l4ls_clkdm",
 998         .main_clk       = "timer3_fck",
 999         .prcm           = {
1000                 .omap4  = {
1001                         .modulemode     = MODULEMODE_SWCTRL,
1002                 },
1003         },
1004 };
1005
1006 struct omap_hwmod am33xx_timer4_hwmod = {
1007         .name           = "timer4",
1008         .class          = &am33xx_timer_hwmod_class,
1009         .clkdm_name     = "l4ls_clkdm",
1010         .main_clk       = "timer4_fck",
1011         .prcm           = {
1012                 .omap4  = {
1013                         .modulemode     = MODULEMODE_SWCTRL,
1014                 },
1015         },
1016 };
1017
1018 struct omap_hwmod am33xx_timer5_hwmod = {
1019         .name           = "timer5",
1020         .class          = &am33xx_timer_hwmod_class,
1021         .clkdm_name     = "l4ls_clkdm",
1022         .main_clk       = "timer5_fck",
1023         .prcm           = {
1024                 .omap4  = {
1025                         .modulemode     = MODULEMODE_SWCTRL,
1026                 },
1027         },
1028 };
1029
1030 struct omap_hwmod am33xx_timer6_hwmod = {
1031         .name           = "timer6",
1032         .class          = &am33xx_timer_hwmod_class,
1033         .clkdm_name     = "l4ls_clkdm",
1034         .main_clk       = "timer6_fck",
1035         .prcm           = {
1036                 .omap4  = {
1037                         .modulemode     = MODULEMODE_SWCTRL,
1038                 },
1039         },
1040 };
1041
1042 struct omap_hwmod am33xx_timer7_hwmod = {
1043         .name           = "timer7",
1044         .class          = &am33xx_timer_hwmod_class,
1045         .clkdm_name     = "l4ls_clkdm",
1046         .main_clk       = "timer7_fck",
1047         .prcm           = {
1048                 .omap4  = {
1049                         .modulemode     = MODULEMODE_SWCTRL,
1050                 },
1051         },
1052 };
1053
1054 /* tpcc */
1055 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1056         .name           = "tpcc",
1057 };
1058
1059 struct omap_hwmod am33xx_tpcc_hwmod = {
1060         .name           = "tpcc",
1061         .class          = &am33xx_tpcc_hwmod_class,
1062         .clkdm_name     = "l3_clkdm",
1063         .main_clk       = "l3_gclk",
1064         .prcm           = {
1065                 .omap4  = {
1066                         .modulemode     = MODULEMODE_SWCTRL,
1067                 },
1068         },
1069 };
1070
1071 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1072         .rev_offs       = 0x0,
1073         .sysc_offs      = 0x10,
1074         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1075                           SYSC_HAS_MIDLEMODE),
1076         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1077         .sysc_fields    = &omap_hwmod_sysc_type2,
1078 };
1079
1080 /* 'tptc' class */
1081 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1082         .name           = "tptc",
1083         .sysc           = &am33xx_tptc_sysc,
1084 };
1085
1086 /* tptc0 */
1087 struct omap_hwmod am33xx_tptc0_hwmod = {
1088         .name           = "tptc0",
1089         .class          = &am33xx_tptc_hwmod_class,
1090         .clkdm_name     = "l3_clkdm",
1091         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1092         .main_clk       = "l3_gclk",
1093         .prcm           = {
1094                 .omap4  = {
1095                         .modulemode     = MODULEMODE_SWCTRL,
1096                 },
1097         },
1098 };
1099
1100 /* tptc1 */
1101 struct omap_hwmod am33xx_tptc1_hwmod = {
1102         .name           = "tptc1",
1103         .class          = &am33xx_tptc_hwmod_class,
1104         .clkdm_name     = "l3_clkdm",
1105         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1106         .main_clk       = "l3_gclk",
1107         .prcm           = {
1108                 .omap4  = {
1109                         .modulemode     = MODULEMODE_SWCTRL,
1110                 },
1111         },
1112 };
1113
1114 /* tptc2 */
1115 struct omap_hwmod am33xx_tptc2_hwmod = {
1116         .name           = "tptc2",
1117         .class          = &am33xx_tptc_hwmod_class,
1118         .clkdm_name     = "l3_clkdm",
1119         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1120         .main_clk       = "l3_gclk",
1121         .prcm           = {
1122                 .omap4  = {
1123                         .modulemode     = MODULEMODE_SWCTRL,
1124                 },
1125         },
1126 };
1127
1128 /* 'uart' class */
1129 static struct omap_hwmod_class_sysconfig uart_sysc = {
1130         .rev_offs       = 0x50,
1131         .sysc_offs      = 0x54,
1132         .syss_offs      = 0x58,
1133         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1134                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1135         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1136                           SIDLE_SMART_WKUP),
1137         .sysc_fields    = &omap_hwmod_sysc_type1,
1138 };
1139
1140 static struct omap_hwmod_class uart_class = {
1141         .name           = "uart",
1142         .sysc           = &uart_sysc,
1143 };
1144
1145 struct omap_hwmod am33xx_uart1_hwmod = {
1146         .name           = "uart1",
1147         .class          = &uart_class,
1148         .clkdm_name     = "l4_wkup_clkdm",
1149         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1150         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1151         .prcm           = {
1152                 .omap4  = {
1153                         .modulemode     = MODULEMODE_SWCTRL,
1154                 },
1155         },
1156 };
1157
1158 struct omap_hwmod am33xx_uart2_hwmod = {
1159         .name           = "uart2",
1160         .class          = &uart_class,
1161         .clkdm_name     = "l4ls_clkdm",
1162         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1163         .main_clk       = "dpll_per_m2_div4_ck",
1164         .prcm           = {
1165                 .omap4  = {
1166                         .modulemode     = MODULEMODE_SWCTRL,
1167                 },
1168         },
1169 };
1170
1171 /* uart3 */
1172 struct omap_hwmod am33xx_uart3_hwmod = {
1173         .name           = "uart3",
1174         .class          = &uart_class,
1175         .clkdm_name     = "l4ls_clkdm",
1176         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1177         .main_clk       = "dpll_per_m2_div4_ck",
1178         .prcm           = {
1179                 .omap4  = {
1180                         .modulemode     = MODULEMODE_SWCTRL,
1181                 },
1182         },
1183 };
1184
1185 struct omap_hwmod am33xx_uart4_hwmod = {
1186         .name           = "uart4",
1187         .class          = &uart_class,
1188         .clkdm_name     = "l4ls_clkdm",
1189         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1190         .main_clk       = "dpll_per_m2_div4_ck",
1191         .prcm           = {
1192                 .omap4  = {
1193                         .modulemode     = MODULEMODE_SWCTRL,
1194                 },
1195         },
1196 };
1197
1198 struct omap_hwmod am33xx_uart5_hwmod = {
1199         .name           = "uart5",
1200         .class          = &uart_class,
1201         .clkdm_name     = "l4ls_clkdm",
1202         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1203         .main_clk       = "dpll_per_m2_div4_ck",
1204         .prcm           = {
1205                 .omap4  = {
1206                         .modulemode     = MODULEMODE_SWCTRL,
1207                 },
1208         },
1209 };
1210
1211 struct omap_hwmod am33xx_uart6_hwmod = {
1212         .name           = "uart6",
1213         .class          = &uart_class,
1214         .clkdm_name     = "l4ls_clkdm",
1215         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1216         .main_clk       = "dpll_per_m2_div4_ck",
1217         .prcm           = {
1218                 .omap4  = {
1219                         .modulemode     = MODULEMODE_SWCTRL,
1220                 },
1221         },
1222 };
1223
1224 /* 'wd_timer' class */
1225 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1226         .rev_offs       = 0x0,
1227         .sysc_offs      = 0x10,
1228         .syss_offs      = 0x14,
1229         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1230                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1231         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1232                         SIDLE_SMART_WKUP),
1233         .sysc_fields    = &omap_hwmod_sysc_type1,
1234 };
1235
1236 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1237         .name           = "wd_timer",
1238         .sysc           = &wdt_sysc,
1239         .pre_shutdown   = &omap2_wd_timer_disable,
1240 };
1241
1242 /*
1243  * XXX: device.c file uses hardcoded name for watchdog timer
1244  * driver "wd_timer2, so we are also using same name as of now...
1245  */
1246 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1247         .name           = "wd_timer2",
1248         .class          = &am33xx_wd_timer_hwmod_class,
1249         .clkdm_name     = "l4_wkup_clkdm",
1250         .flags          = HWMOD_SWSUP_SIDLE,
1251         .main_clk       = "wdt1_fck",
1252         .prcm           = {
1253                 .omap4  = {
1254                         .modulemode     = MODULEMODE_SWCTRL,
1255                 },
1256         },
1257 };
1258
1259 static void omap_hwmod_am33xx_clkctrl(void)
1260 {
1261         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1262         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1263         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1264         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1265         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1266         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1267         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1268         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1269         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1270         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1271         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1272         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1273         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1274         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1275         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1276         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1277         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1278         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1279         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1280         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1281         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1282         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1283         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1284         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1285         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1286         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1287         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1288         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1289         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1290         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1291         CLKCTRL(am33xx_smartreflex0_hwmod,
1292                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1293         CLKCTRL(am33xx_smartreflex1_hwmod,
1294                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1295         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1296         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1297         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1298         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1299         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1300         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1301         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1302         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1303         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1304         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1305         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1306         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1307         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1308         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1309         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1310         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1311         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1312         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1313         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1314         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1315         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1316         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1317         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1318 }
1319
1320 static void omap_hwmod_am33xx_rst(void)
1321 {
1322         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1323         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1324         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1325 }
1326
1327 void omap_hwmod_am33xx_reg(void)
1328 {
1329         omap_hwmod_am33xx_clkctrl();
1330         omap_hwmod_am33xx_rst();
1331 }
1332
1333 static void omap_hwmod_am43xx_clkctrl(void)
1334 {
1335         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1336         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1337         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1338         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1339         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1340         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1341         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1342         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1343         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1360         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_smartreflex0_hwmod,
1366                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_smartreflex1_hwmod,
1368                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1373         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1375         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1385         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1386         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1387         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1388         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1389         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1390         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1391 }
1392
1393 static void omap_hwmod_am43xx_rst(void)
1394 {
1395         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1396         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1397         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1398         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1399 }
1400
1401 void omap_hwmod_am43xx_reg(void)
1402 {
1403         omap_hwmod_am43xx_clkctrl();
1404         omap_hwmod_am43xx_rst();
1405 }