arch/arm/mach-sa1100/generic.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/generic.c
   3  *
   4  * Author: Nicolas Pitre
   5  *
   6  * Code common to all SA11x0 machines.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/gpio.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/pm.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/ioport.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/reboot.h>
  23 #include <linux/irqchip/irq-sa11x0.h>
  24
  25 #include <video/sa1100fb.h>
  26
  27 #include <soc/sa1100/pwer.h>
  28
  29 #include <asm/div64.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/flash.h>
  32 #include <asm/irq.h>
  33 #include <asm/system_misc.h>
  34
  35 #include <mach/hardware.h>
  36 #include <mach/irqs.h>
  37 #include <mach/reset.h>
  38
  39 #include "generic.h"
  40 #include <clocksource/pxa.h>
  41
  42 unsigned int reset_status;
  43 EXPORT_SYMBOL(reset_status);
  44
  45 #define NR_FREQS        16
  46
  47 /*
  48  * This table is setup for a 3.6864MHz Crystal.
  49  */
  50 struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
  51         { .frequency = 59000,   /*  59.0 MHz */},
  52         { .frequency = 73700,   /*  73.7 MHz */},
  53         { .frequency = 88500,   /*  88.5 MHz */},
  54         { .frequency = 103200,  /* 103.2 MHz */},
  55         { .frequency = 118000,  /* 118.0 MHz */},
  56         { .frequency = 132700,  /* 132.7 MHz */},
  57         { .frequency = 147500,  /* 147.5 MHz */},
  58         { .frequency = 162200,  /* 162.2 MHz */},
  59         { .frequency = 176900,  /* 176.9 MHz */},
  60         { .frequency = 191700,  /* 191.7 MHz */},
  61         { .frequency = 206400,  /* 206.4 MHz */},
  62         { .frequency = 221200,  /* 221.2 MHz */},
  63         { .frequency = 235900,  /* 235.9 MHz */},
  64         { .frequency = 250700,  /* 250.7 MHz */},
  65         { .frequency = 265400,  /* 265.4 MHz */},
  66         { .frequency = 280200,  /* 280.2 MHz */},
  67         { .frequency = CPUFREQ_TABLE_END, },
  68 };
  69
  70 unsigned int sa11x0_getspeed(unsigned int cpu)
  71 {
  72         if (cpu)
  73                 return 0;
  74         return sa11x0_freq_table[PPCR & 0xf].frequency;
  75 }
  76
  77 /*
  78  * Default power-off for SA1100
  79  */
  80 static void sa1100_power_off(void)
  81 {
  82         mdelay(100);
  83         local_irq_disable();
  84         /* disable internal oscillator, float CS lines */
  85         PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
  86         /* enable wake-up on GPIO0 (Assabet...) */
  87         PWER = GFER = GRER = 1;
  88         /*
  89          * set scratchpad to zero, just in case it is used as a
  90          * restart address by the bootloader.
  91          */
  92         PSPR = 0;
  93         /* enter sleep mode */
  94         PMCR = PMCR_SF;
  95 }
  96
  97 void sa11x0_restart(enum reboot_mode mode, const char *cmd)
  98 {
  99         clear_reset_status(RESET_STATUS_ALL);
 100
 101         if (mode == REBOOT_SOFT) {
 102                 /* Jump into ROM at address 0 */
 103                 soft_restart(0);
 104         } else {
 105                 /* Use on-chip reset capability */
 106                 RSRR = RSRR_SWR;
 107         }
 108 }
 109
 110 static void sa11x0_register_device(struct platform_device *dev, void *data)
 111 {
 112         int err;
 113         dev->dev.platform_data = data;
 114         err = platform_device_register(dev);
 115         if (err)
 116                 printk(KERN_ERR "Unable to register device %s: %d\n",
 117                         dev->name, err);
 118 }
 119
 120
 121 static struct resource sa11x0udc_resources[] = {
 122         [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
 123         [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
 124 };
 125
 126 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
 127
 128 static struct platform_device sa11x0udc_device = {
 129         .name           = "sa11x0-udc",
 130         .id             = -1,
 131         .dev            = {
 132                 .dma_mask = &sa11x0udc_dma_mask,
 133                 .coherent_dma_mask = 0xffffffff,
 134         },
 135         .num_resources  = ARRAY_SIZE(sa11x0udc_resources),
 136         .resource       = sa11x0udc_resources,
 137 };
 138
 139 static struct resource sa11x0uart1_resources[] = {
 140         [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
 141         [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
 142 };
 143
 144 static struct platform_device sa11x0uart1_device = {
 145         .name           = "sa11x0-uart",
 146         .id             = 1,
 147         .num_resources  = ARRAY_SIZE(sa11x0uart1_resources),
 148         .resource       = sa11x0uart1_resources,
 149 };
 150
 151 static struct resource sa11x0uart3_resources[] = {
 152         [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
 153         [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
 154 };
 155
 156 static struct platform_device sa11x0uart3_device = {
 157         .name           = "sa11x0-uart",
 158         .id             = 3,
 159         .num_resources  = ARRAY_SIZE(sa11x0uart3_resources),
 160         .resource       = sa11x0uart3_resources,
 161 };
 162
 163 static struct resource sa11x0mcp_resources[] = {
 164         [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
 165         [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
 166         [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
 167 };
 168
 169 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
 170
 171 static struct platform_device sa11x0mcp_device = {
 172         .name           = "sa11x0-mcp",
 173         .id             = -1,
 174         .dev = {
 175                 .dma_mask = &sa11x0mcp_dma_mask,
 176                 .coherent_dma_mask = 0xffffffff,
 177         },
 178         .num_resources  = ARRAY_SIZE(sa11x0mcp_resources),
 179         .resource       = sa11x0mcp_resources,
 180 };
 181
 182 void __init sa11x0_ppc_configure_mcp(void)
 183 {
 184         /* Setup the PPC unit for the MCP */
 185         PPDR &= ~PPC_RXD4;
 186         PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
 187         PSDR |= PPC_RXD4;
 188         PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
 189         PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
 190 }
 191
 192 void sa11x0_register_mcp(struct mcp_plat_data *data)
 193 {
 194         sa11x0_register_device(&sa11x0mcp_device, data);
 195 }
 196
 197 static struct resource sa11x0ssp_resources[] = {
 198         [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
 199         [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
 200 };
 201
 202 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
 203
 204 static struct platform_device sa11x0ssp_device = {
 205         .name           = "sa11x0-ssp",
 206         .id             = -1,
 207         .dev = {
 208                 .dma_mask = &sa11x0ssp_dma_mask,
 209                 .coherent_dma_mask = 0xffffffff,
 210         },
 211         .num_resources  = ARRAY_SIZE(sa11x0ssp_resources),
 212         .resource       = sa11x0ssp_resources,
 213 };
 214
 215 static struct resource sa11x0fb_resources[] = {
 216         [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
 217         [1] = DEFINE_RES_IRQ(IRQ_LCD),
 218 };
 219
 220 static struct platform_device sa11x0fb_device = {
 221         .name           = "sa11x0-fb",
 222         .id             = -1,
 223         .dev = {
 224                 .coherent_dma_mask = 0xffffffff,
 225         },
 226         .num_resources  = ARRAY_SIZE(sa11x0fb_resources),
 227         .resource       = sa11x0fb_resources,
 228 };
 229
 230 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
 231 {
 232         sa11x0_register_device(&sa11x0fb_device, inf);
 233 }
 234
 235 static struct platform_device sa11x0pcmcia_device = {
 236         .name           = "sa11x0-pcmcia",
 237         .id             = -1,
 238 };
 239
 240 static struct platform_device sa11x0mtd_device = {
 241         .name           = "sa1100-mtd",
 242         .id             = -1,
 243 };
 244
 245 void sa11x0_register_mtd(struct flash_platform_data *flash,
 246                          struct resource *res, int nr)
 247 {
 248         flash->name = "sa1100";
 249         sa11x0mtd_device.resource = res;
 250         sa11x0mtd_device.num_resources = nr;
 251         sa11x0_register_device(&sa11x0mtd_device, flash);
 252 }
 253
 254 static struct resource sa11x0ir_resources[] = {
 255         DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
 256         DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
 257         DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
 258         DEFINE_RES_IRQ(IRQ_Ser2ICP),
 259 };
 260
 261 static struct platform_device sa11x0ir_device = {
 262         .name           = "sa11x0-ir",
 263         .id             = -1,
 264         .num_resources  = ARRAY_SIZE(sa11x0ir_resources),
 265         .resource       = sa11x0ir_resources,
 266 };
 267
 268 void sa11x0_register_irda(struct irda_platform_data *irda)
 269 {
 270         sa11x0_register_device(&sa11x0ir_device, irda);
 271 }
 272
 273 static struct resource sa1100_rtc_resources[] = {
 274         DEFINE_RES_MEM(0x90010000, 0x40),
 275         DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
 276         DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
 277 };
 278
 279 static struct platform_device sa11x0rtc_device = {
 280         .name           = "sa1100-rtc",
 281         .id             = -1,
 282         .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
 283         .resource       = sa1100_rtc_resources,
 284 };
 285
 286 static struct resource sa11x0dma_resources[] = {
 287         DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
 288         DEFINE_RES_IRQ(IRQ_DMA0),
 289         DEFINE_RES_IRQ(IRQ_DMA1),
 290         DEFINE_RES_IRQ(IRQ_DMA2),
 291         DEFINE_RES_IRQ(IRQ_DMA3),
 292         DEFINE_RES_IRQ(IRQ_DMA4),
 293         DEFINE_RES_IRQ(IRQ_DMA5),
 294 };
 295
 296 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
 297
 298 static struct platform_device sa11x0dma_device = {
 299         .name           = "sa11x0-dma",
 300         .id             = -1,
 301         .dev = {
 302                 .dma_mask = &sa11x0dma_dma_mask,
 303                 .coherent_dma_mask = 0xffffffff,
 304         },
 305         .num_resources  = ARRAY_SIZE(sa11x0dma_resources),
 306         .resource       = sa11x0dma_resources,
 307 };
 308
 309 static struct platform_device *sa11x0_devices[] __initdata = {
 310         &sa11x0udc_device,
 311         &sa11x0uart1_device,
 312         &sa11x0uart3_device,
 313         &sa11x0ssp_device,
 314         &sa11x0pcmcia_device,
 315         &sa11x0rtc_device,
 316         &sa11x0dma_device,
 317 };
 318
 319 static int __init sa1100_init(void)
 320 {
 321         pm_power_off = sa1100_power_off;
 322         return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
 323 }
 324
 325 arch_initcall(sa1100_init);
 326
 327 void __init sa11x0_init_late(void)
 328 {
 329         sa11x0_pm_init();
 330 }
 331
 332 /*
 333  * Common I/O mapping:
 334  *
 335  * Typically, static virtual address mappings are as follow:
 336  *
 337  * 0xf0000000-0xf3ffffff:       miscellaneous stuff (CPLDs, etc.)
 338  * 0xf4000000-0xf4ffffff:       SA-1111
 339  * 0xf5000000-0xf5ffffff:       reserved (used by cache flushing area)
 340  * 0xf6000000-0xfffeffff:       reserved (internal SA1100 IO defined above)
 341  * 0xffff0000-0xffff0fff:       SA1100 exception vectors
 342  * 0xffff2000-0xffff2fff:       Minicache copy_user_page area
 343  *
 344  * Below 0xe8000000 is reserved for vm allocation.
 345  *
 346  * The machine specific code must provide the extra mapping beside the
 347  * default mapping provided here.
 348  */
 349
 350 static struct map_desc standard_io_desc[] __initdata = {
 351         {       /* PCM */
 352                 .virtual        =  0xf8000000,
 353                 .pfn            = __phys_to_pfn(0x80000000),
 354                 .length         = 0x00100000,
 355                 .type           = MT_DEVICE
 356         }, {    /* SCM */
 357                 .virtual        =  0xfa000000,
 358                 .pfn            = __phys_to_pfn(0x90000000),
 359                 .length         = 0x00100000,
 360                 .type           = MT_DEVICE
 361         }, {    /* MER */
 362                 .virtual        =  0xfc000000,
 363                 .pfn            = __phys_to_pfn(0xa0000000),
 364                 .length         = 0x00100000,
 365                 .type           = MT_DEVICE
 366         }, {    /* LCD + DMA */
 367                 .virtual        =  0xfe000000,
 368                 .pfn            = __phys_to_pfn(0xb0000000),
 369                 .length         = 0x00200000,
 370                 .type           = MT_DEVICE
 371         },
 372 };
 373
 374 void __init sa1100_map_io(void)
 375 {
 376         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
 377 }
 378
 379 void __init sa1100_timer_init(void)
 380 {
 381         pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
 382 }
 383
 384 static struct resource irq_resource =
 385         DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 386
 387 void __init sa1100_init_irq(void)
 388 {
 389         request_resource(&iomem_resource, &irq_resource);
 390
 391         sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
 392
 393         sa1100_init_gpio();
 394         sa11xx_clk_init();
 395 }
 396
 397 /*
 398  * Disable the memory bus request/grant signals on the SA1110 to
 399  * ensure that we don't receive spurious memory requests.  We set
 400  * the MBGNT signal false to ensure the SA1111 doesn't own the
 401  * SDRAM bus.
 402  */
 403 void sa1110_mb_disable(void)
 404 {
 405         unsigned long flags;
 406
 407         local_irq_save(flags);
 408
 409         PGSR &= ~GPIO_MBGNT;
 410         GPCR = GPIO_MBGNT;
 411         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 412
 413         GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
 414
 415         local_irq_restore(flags);
 416 }
 417
 418 /*
 419  * If the system is going to use the SA-1111 DMA engines, set up
 420  * the memory bus request/grant pins.
 421  */
 422 void sa1110_mb_enable(void)
 423 {
 424         unsigned long flags;
 425
 426         local_irq_save(flags);
 427
 428         PGSR &= ~GPIO_MBGNT;
 429         GPCR = GPIO_MBGNT;
 430         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 431
 432         GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
 433         TUCR |= TUCR_MR;
 434
 435         local_irq_restore(flags);
 436 }
 437
 438 int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
 439 {
 440         if (on)
 441                 PWER |= BIT(gpio);
 442         else
 443                 PWER &= ~BIT(gpio);
 444
 445         return 0;
 446 }
 447
 448 int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
 449 {
 450         if (BIT(irq) != IC_RTCAlrm)
 451                 return -EINVAL;
 452
 453         if (on)
 454                 PWER |= PWER_RTC;
 455         else
 456                 PWER &= ~PWER_RTC;
 457
 458         return 0;
 459 }