arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/delay.h>
  24 #include <linux/input.h>
  25 #include <linux/io.h>
  26 #include <linux/serial_sci.h>
  27 #include <linux/sh_dma.h>
  28 #include <linux/sh_timer.h>
  29 #include <linux/platform_data/sh_ipmmu.h>
  30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  31
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/time.h>
  36
  37 #include "common.h"
  38 #include "dma-register.h"
  39 #include "intc.h"
  40 #include "irqs.h"
  41 #include "sh73a0.h"
  42
  43 static struct map_desc sh73a0_io_desc[] __initdata = {
  44         /* create a 1:1 entity map for 0xe6xxxxxx
  45          * used by CPGA, INTC and PFC.
  46          */
  47         {
  48                 .virtual        = 0xe6000000,
  49                 .pfn            = __phys_to_pfn(0xe6000000),
  50                 .length         = 256 << 20,
  51                 .type           = MT_DEVICE_NONSHARED
  52         },
  53 };
  54
  55 void __init sh73a0_map_io(void)
  56 {
  57         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  58 }
  59
  60 /* PFC */
  61 static struct resource pfc_resources[] __initdata = {
  62         DEFINE_RES_MEM(0xe6050000, 0x8000),
  63         DEFINE_RES_MEM(0xe605801c, 0x000c),
  64 };
  65
  66 void __init sh73a0_pinmux_init(void)
  67 {
  68         platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
  69                                         ARRAY_SIZE(pfc_resources));
  70 }
  71
  72 /* SCIF */
  73 #define SH73A0_SCIF(scif_type, index, baseaddr, irq)            \
  74 static struct plat_sci_port scif##index##_platform_data = {     \
  75         .type           = scif_type,                            \
  76         .flags          = UPF_BOOT_AUTOCONF,                    \
  77         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  78 };                                                              \
  79                                                                 \
  80 static struct resource scif##index##_resources[] = {            \
  81         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  82         DEFINE_RES_IRQ(irq),                                    \
  83 };                                                              \
  84                                                                 \
  85 static struct platform_device scif##index##_device = {          \
  86         .name           = "sh-sci",                             \
  87         .id             = index,                                \
  88         .resource       = scif##index##_resources,              \
  89         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
  90         .dev            = {                                     \
  91                 .platform_data  = &scif##index##_platform_data, \
  92         },                                                      \
  93 }
  94
  95 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
  96 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
  97 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
  98 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
  99 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
 100 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
 101 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
 102 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
 103 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
 104
 105 static struct sh_timer_config cmt1_platform_data = {
 106         .channels_mask = 0x3f,
 107 };
 108
 109 static struct resource cmt1_resources[] = {
 110         DEFINE_RES_MEM(0xe6138000, 0x200),
 111         DEFINE_RES_IRQ(gic_spi(65)),
 112 };
 113
 114 static struct platform_device cmt1_device = {
 115         .name           = "sh-cmt-48",
 116         .id             = 1,
 117         .dev = {
 118                 .platform_data  = &cmt1_platform_data,
 119         },
 120         .resource       = cmt1_resources,
 121         .num_resources  = ARRAY_SIZE(cmt1_resources),
 122 };
 123
 124 /* TMU */
 125 static struct sh_timer_config tmu0_platform_data = {
 126         .channels_mask = 7,
 127 };
 128
 129 static struct resource tmu0_resources[] = {
 130         DEFINE_RES_MEM(0xfff60000, 0x2c),
 131         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 132         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 133         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 134 };
 135
 136 static struct platform_device tmu0_device = {
 137         .name           = "sh-tmu",
 138         .id             = 0,
 139         .dev = {
 140                 .platform_data  = &tmu0_platform_data,
 141         },
 142         .resource       = tmu0_resources,
 143         .num_resources  = ARRAY_SIZE(tmu0_resources),
 144 };
 145
 146 static struct resource i2c0_resources[] = {
 147         [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
 148         [1] = {
 149                 .start  = gic_spi(167),
 150                 .end    = gic_spi(170),
 151                 .flags  = IORESOURCE_IRQ,
 152         },
 153 };
 154
 155 static struct resource i2c1_resources[] = {
 156         [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
 157         [1] = {
 158                 .start  = gic_spi(51),
 159                 .end    = gic_spi(54),
 160                 .flags  = IORESOURCE_IRQ,
 161         },
 162 };
 163
 164 static struct resource i2c2_resources[] = {
 165         [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
 166         [1] = {
 167                 .start  = gic_spi(171),
 168                 .end    = gic_spi(174),
 169                 .flags  = IORESOURCE_IRQ,
 170         },
 171 };
 172
 173 static struct resource i2c3_resources[] = {
 174         [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
 175         [1] = {
 176                 .start  = gic_spi(183),
 177                 .end    = gic_spi(186),
 178                 .flags  = IORESOURCE_IRQ,
 179         },
 180 };
 181
 182 static struct resource i2c4_resources[] = {
 183         [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
 184         [1] = {
 185                 .start  = gic_spi(187),
 186                 .end    = gic_spi(190),
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189 };
 190
 191 static struct platform_device i2c0_device = {
 192         .name           = "i2c-sh_mobile",
 193         .id             = 0,
 194         .resource       = i2c0_resources,
 195         .num_resources  = ARRAY_SIZE(i2c0_resources),
 196 };
 197
 198 static struct platform_device i2c1_device = {
 199         .name           = "i2c-sh_mobile",
 200         .id             = 1,
 201         .resource       = i2c1_resources,
 202         .num_resources  = ARRAY_SIZE(i2c1_resources),
 203 };
 204
 205 static struct platform_device i2c2_device = {
 206         .name           = "i2c-sh_mobile",
 207         .id             = 2,
 208         .resource       = i2c2_resources,
 209         .num_resources  = ARRAY_SIZE(i2c2_resources),
 210 };
 211
 212 static struct platform_device i2c3_device = {
 213         .name           = "i2c-sh_mobile",
 214         .id             = 3,
 215         .resource       = i2c3_resources,
 216         .num_resources  = ARRAY_SIZE(i2c3_resources),
 217 };
 218
 219 static struct platform_device i2c4_device = {
 220         .name           = "i2c-sh_mobile",
 221         .id             = 4,
 222         .resource       = i2c4_resources,
 223         .num_resources  = ARRAY_SIZE(i2c4_resources),
 224 };
 225
 226 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 227         {
 228                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 229                 .addr           = 0xe6c40020,
 230                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 231                 .mid_rid        = 0x21,
 232         }, {
 233                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 234                 .addr           = 0xe6c40024,
 235                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 236                 .mid_rid        = 0x22,
 237         }, {
 238                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 239                 .addr           = 0xe6c50020,
 240                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 241                 .mid_rid        = 0x25,
 242         }, {
 243                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 244                 .addr           = 0xe6c50024,
 245                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 246                 .mid_rid        = 0x26,
 247         }, {
 248                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 249                 .addr           = 0xe6c60020,
 250                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 251                 .mid_rid        = 0x29,
 252         }, {
 253                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 254                 .addr           = 0xe6c60024,
 255                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 256                 .mid_rid        = 0x2a,
 257         }, {
 258                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 259                 .addr           = 0xe6c70020,
 260                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 261                 .mid_rid        = 0x2d,
 262         }, {
 263                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 264                 .addr           = 0xe6c70024,
 265                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 266                 .mid_rid        = 0x2e,
 267         }, {
 268                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 269                 .addr           = 0xe6c80020,
 270                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 271                 .mid_rid        = 0x39,
 272         }, {
 273                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 274                 .addr           = 0xe6c80024,
 275                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 276                 .mid_rid        = 0x3a,
 277         }, {
 278                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 279                 .addr           = 0xe6cb0020,
 280                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 281                 .mid_rid        = 0x35,
 282         }, {
 283                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 284                 .addr           = 0xe6cb0024,
 285                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 286                 .mid_rid        = 0x36,
 287         }, {
 288                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 289                 .addr           = 0xe6cc0020,
 290                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 291                 .mid_rid        = 0x1d,
 292         }, {
 293                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 294                 .addr           = 0xe6cc0024,
 295                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 296                 .mid_rid        = 0x1e,
 297         }, {
 298                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 299                 .addr           = 0xe6cd0020,
 300                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 301                 .mid_rid        = 0x19,
 302         }, {
 303                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 304                 .addr           = 0xe6cd0024,
 305                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 306                 .mid_rid        = 0x1a,
 307         }, {
 308                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 309                 .addr           = 0xe6c30040,
 310                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 311                 .mid_rid        = 0x3d,
 312         }, {
 313                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 314                 .addr           = 0xe6c30060,
 315                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 316                 .mid_rid        = 0x3e,
 317         }, {
 318                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 319                 .addr           = 0xee100030,
 320                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 321                 .mid_rid        = 0xc1,
 322         }, {
 323                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 324                 .addr           = 0xee100030,
 325                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 326                 .mid_rid        = 0xc2,
 327         }, {
 328                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 329                 .addr           = 0xee120030,
 330                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 331                 .mid_rid        = 0xc9,
 332         }, {
 333                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 334                 .addr           = 0xee120030,
 335                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 336                 .mid_rid        = 0xca,
 337         }, {
 338                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 339                 .addr           = 0xee140030,
 340                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 341                 .mid_rid        = 0xcd,
 342         }, {
 343                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 344                 .addr           = 0xee140030,
 345                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 346                 .mid_rid        = 0xce,
 347         }, {
 348                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 349                 .addr           = 0xe6bd0034,
 350                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 351                 .mid_rid        = 0xd1,
 352         }, {
 353                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 354                 .addr           = 0xe6bd0034,
 355                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 356                 .mid_rid        = 0xd2,
 357         },
 358 };
 359
 360 #define DMAE_CHANNEL(_offset)                                   \
 361         {                                                       \
 362                 .offset         = _offset - 0x20,               \
 363                 .dmars          = _offset - 0x20 + 0x40,        \
 364         }
 365
 366 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 367         DMAE_CHANNEL(0x8000),
 368         DMAE_CHANNEL(0x8080),
 369         DMAE_CHANNEL(0x8100),
 370         DMAE_CHANNEL(0x8180),
 371         DMAE_CHANNEL(0x8200),
 372         DMAE_CHANNEL(0x8280),
 373         DMAE_CHANNEL(0x8300),
 374         DMAE_CHANNEL(0x8380),
 375         DMAE_CHANNEL(0x8400),
 376         DMAE_CHANNEL(0x8480),
 377         DMAE_CHANNEL(0x8500),
 378         DMAE_CHANNEL(0x8580),
 379         DMAE_CHANNEL(0x8600),
 380         DMAE_CHANNEL(0x8680),
 381         DMAE_CHANNEL(0x8700),
 382         DMAE_CHANNEL(0x8780),
 383         DMAE_CHANNEL(0x8800),
 384         DMAE_CHANNEL(0x8880),
 385         DMAE_CHANNEL(0x8900),
 386         DMAE_CHANNEL(0x8980),
 387 };
 388
 389 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 390         .slave          = sh73a0_dmae_slaves,
 391         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 392         .channel        = sh73a0_dmae_channels,
 393         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 394         .ts_low_shift   = TS_LOW_SHIFT,
 395         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 396         .ts_high_shift  = TS_HI_SHIFT,
 397         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 398         .ts_shift       = dma_ts_shift,
 399         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 400         .dmaor_init     = DMAOR_DME,
 401 };
 402
 403 static struct resource sh73a0_dmae_resources[] = {
 404         DEFINE_RES_MEM(0xfe000020, 0x89e0),
 405         {
 406                 .name   = "error_irq",
 407                 .start  = gic_spi(129),
 408                 .end    = gic_spi(129),
 409                 .flags  = IORESOURCE_IRQ,
 410         },
 411         {
 412                 /* IRQ for channels 0-19 */
 413                 .start  = gic_spi(109),
 414                 .end    = gic_spi(128),
 415                 .flags  = IORESOURCE_IRQ,
 416         },
 417 };
 418
 419 static struct platform_device dma0_device = {
 420         .name           = "sh-dma-engine",
 421         .id             = 0,
 422         .resource       = sh73a0_dmae_resources,
 423         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 424         .dev            = {
 425                 .platform_data  = &sh73a0_dmae_platform_data,
 426         },
 427 };
 428
 429 /* MPDMAC */
 430 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 431         {
 432                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 433                 .addr           = 0xec230020,
 434                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 435                 .mid_rid        = 0xd6, /* CHECK ME */
 436         }, {
 437                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 438                 .addr           = 0xec230024,
 439                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 440                 .mid_rid        = 0xd5, /* CHECK ME */
 441         }, {
 442                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 443                 .addr           = 0xec230060,
 444                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 445                 .mid_rid        = 0xda, /* CHECK ME */
 446         }, {
 447                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 448                 .addr           = 0xec230064,
 449                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 450                 .mid_rid        = 0xd9, /* CHECK ME */
 451         }, {
 452                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 453                 .addr           = 0xec240020,
 454                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 455                 .mid_rid        = 0x8e, /* CHECK ME */
 456         }, {
 457                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 458                 .addr           = 0xec240024,
 459                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 460                 .mid_rid        = 0x8d, /* CHECK ME */
 461         }, {
 462                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 463                 .addr           =  0xec240060,
 464                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 465                 .mid_rid        = 0x9a, /* CHECK ME */
 466         },
 467 };
 468
 469 #define MPDMA_CHANNEL(a, b, c)                  \
 470 {                                               \
 471         .offset         = a,                    \
 472         .dmars          = b,                    \
 473         .dmars_bit      = c,                    \
 474         .chclr_offset   = (0x220 - 0x20) + a    \
 475 }
 476
 477 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 478         MPDMA_CHANNEL(0x00, 0, 0),
 479         MPDMA_CHANNEL(0x10, 0, 8),
 480         MPDMA_CHANNEL(0x20, 4, 0),
 481         MPDMA_CHANNEL(0x30, 4, 8),
 482         MPDMA_CHANNEL(0x50, 8, 0),
 483         MPDMA_CHANNEL(0x70, 8, 8),
 484 };
 485
 486 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 487         .slave          = sh73a0_mpdma_slaves,
 488         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 489         .channel        = sh73a0_mpdma_channels,
 490         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 491         .ts_low_shift   = TS_LOW_SHIFT,
 492         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 493         .ts_high_shift  = TS_HI_SHIFT,
 494         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 495         .ts_shift       = dma_ts_shift,
 496         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 497         .dmaor_init     = DMAOR_DME,
 498         .chclr_present  = 1,
 499 };
 500
 501 /* Resource order important! */
 502 static struct resource sh73a0_mpdma_resources[] = {
 503         /* Channel registers and DMAOR */
 504         DEFINE_RES_MEM(0xec618020, 0x270),
 505         /* DMARSx */
 506         DEFINE_RES_MEM(0xec619000, 0xc),
 507         {
 508                 .name   = "error_irq",
 509                 .start  = gic_spi(181),
 510                 .end    = gic_spi(181),
 511                 .flags  = IORESOURCE_IRQ,
 512         },
 513         {
 514                 /* IRQ for channels 0-5 */
 515                 .start  = gic_spi(175),
 516                 .end    = gic_spi(180),
 517                 .flags  = IORESOURCE_IRQ,
 518         },
 519 };
 520
 521 static struct platform_device mpdma0_device = {
 522         .name           = "sh-dma-engine",
 523         .id             = 1,
 524         .resource       = sh73a0_mpdma_resources,
 525         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 526         .dev            = {
 527                 .platform_data  = &sh73a0_mpdma_platform_data,
 528         },
 529 };
 530
 531 static struct resource pmu_resources[] = {
 532         [0] = {
 533                 .start  = gic_spi(55),
 534                 .end    = gic_spi(55),
 535                 .flags  = IORESOURCE_IRQ,
 536         },
 537         [1] = {
 538                 .start  = gic_spi(56),
 539                 .end    = gic_spi(56),
 540                 .flags  = IORESOURCE_IRQ,
 541         },
 542 };
 543
 544 static struct platform_device pmu_device = {
 545         .name           = "arm-pmu",
 546         .id             = -1,
 547         .num_resources  = ARRAY_SIZE(pmu_resources),
 548         .resource       = pmu_resources,
 549 };
 550
 551 /* an IPMMU module for ICB */
 552 static struct resource ipmmu_resources[] = {
 553         DEFINE_RES_MEM(0xfe951000, 0x100),
 554 };
 555
 556 static const char * const ipmmu_dev_names[] = {
 557         "sh_mobile_lcdc_fb.0",
 558 };
 559
 560 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 561         .dev_names = ipmmu_dev_names,
 562         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 563 };
 564
 565 static struct platform_device ipmmu_device = {
 566         .name           = "ipmmu",
 567         .id             = -1,
 568         .dev = {
 569                 .platform_data = &ipmmu_platform_data,
 570         },
 571         .resource       = ipmmu_resources,
 572         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 573 };
 574
 575 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
 576         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
 577 };
 578
 579 static struct resource irqpin0_resources[] = {
 580         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
 581         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
 582         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
 583         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
 584         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
 585         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
 586         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
 587         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
 588         DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
 589         DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
 590         DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
 591         DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
 592         DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
 593 };
 594
 595 static struct platform_device irqpin0_device = {
 596         .name           = "renesas_intc_irqpin",
 597         .id             = 0,
 598         .resource       = irqpin0_resources,
 599         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 600         .dev            = {
 601                 .platform_data  = &irqpin0_platform_data,
 602         },
 603 };
 604
 605 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 606         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 607         .control_parent = true, /* Disable spurious IRQ10 */
 608 };
 609
 610 static struct resource irqpin1_resources[] = {
 611         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 612         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 613         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 614         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 615         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 616         DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
 617         DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
 618         DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
 619         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
 620         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
 621         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
 622         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
 623         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
 624 };
 625
 626 static struct platform_device irqpin1_device = {
 627         .name           = "renesas_intc_irqpin",
 628         .id             = 1,
 629         .resource       = irqpin1_resources,
 630         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 631         .dev            = {
 632                 .platform_data  = &irqpin1_platform_data,
 633         },
 634 };
 635
 636 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 637         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 638 };
 639
 640 static struct resource irqpin2_resources[] = {
 641         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 642         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
 643         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
 644         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
 645         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
 646         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
 647         DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
 648         DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
 649         DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
 650         DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
 651         DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
 652         DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
 653         DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
 654 };
 655
 656 static struct platform_device irqpin2_device = {
 657         .name           = "renesas_intc_irqpin",
 658         .id             = 2,
 659         .resource       = irqpin2_resources,
 660         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 661         .dev            = {
 662                 .platform_data  = &irqpin2_platform_data,
 663         },
 664 };
 665
 666 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 667         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 668 };
 669
 670 static struct resource irqpin3_resources[] = {
 671         DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
 672         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 673         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 674         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 675         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 676         DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
 677         DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
 678         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
 679         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
 680         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
 681         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
 682         DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
 683         DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
 684 };
 685
 686 static struct platform_device irqpin3_device = {
 687         .name           = "renesas_intc_irqpin",
 688         .id             = 3,
 689         .resource       = irqpin3_resources,
 690         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 691         .dev            = {
 692                 .platform_data  = &irqpin3_platform_data,
 693         },
 694 };
 695
 696 static struct platform_device *sh73a0_early_devices[] __initdata = {
 697         &scif0_device,
 698         &scif1_device,
 699         &scif2_device,
 700         &scif3_device,
 701         &scif4_device,
 702         &scif5_device,
 703         &scif6_device,
 704         &scif7_device,
 705         &scif8_device,
 706         &tmu0_device,
 707         &ipmmu_device,
 708         &cmt1_device,
 709 };
 710
 711 static struct platform_device *sh73a0_late_devices[] __initdata = {
 712         &i2c0_device,
 713         &i2c1_device,
 714         &i2c2_device,
 715         &i2c3_device,
 716         &i2c4_device,
 717         &dma0_device,
 718         &mpdma0_device,
 719         &pmu_device,
 720         &irqpin0_device,
 721         &irqpin1_device,
 722         &irqpin2_device,
 723         &irqpin3_device,
 724 };
 725
 726 #define SRCR2          IOMEM(0xe61580b0)
 727
 728 void __init sh73a0_add_standard_devices(void)
 729 {
 730         /* Clear software reset bit on SY-DMAC module */
 731         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 732
 733         platform_add_devices(sh73a0_early_devices,
 734                             ARRAY_SIZE(sh73a0_early_devices));
 735         platform_add_devices(sh73a0_late_devices,
 736                             ARRAY_SIZE(sh73a0_late_devices));
 737 }
 738
 739 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 740 void __init __weak sh73a0_register_twd(void) { }
 741
 742 void __init sh73a0_earlytimer_init(void)
 743 {
 744         shmobile_init_delay();
 745         sh73a0_clock_init();
 746         shmobile_earlytimer_init();
 747         sh73a0_register_twd();
 748 }
 749
 750 void __init sh73a0_add_early_devices(void)
 751 {
 752         early_platform_add_devices(sh73a0_early_devices,
 753                                    ARRAY_SIZE(sh73a0_early_devices));
 754
 755         /* setup early console here as well */
 756         shmobile_setup_console();
 757 }
 758
 759 #ifdef CONFIG_USE_OF
 760
 761 void __init sh73a0_add_standard_devices_dt(void)
 762 {
 763         /* clocks are setup late during boot in the case of DT */
 764         sh73a0_clock_init();
 765
 766         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 767 }
 768
 769 static const char *sh73a0_boards_compat_dt[] __initdata = {
 770         "renesas,sh73a0",
 771         NULL,
 772 };
 773
 774 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 775         .smp            = smp_ops(sh73a0_smp_ops),
 776         .map_io         = sh73a0_map_io,
 777         .init_early     = shmobile_init_delay,
 778         .init_machine   = sh73a0_add_standard_devices_dt,
 779         .init_late      = shmobile_init_late,
 780         .dt_compat      = sh73a0_boards_compat_dt,
 781 MACHINE_END
 782 #endif /* CONFIG_USE_OF */