arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/delay.h>
  24 #include <linux/input.h>
  25 #include <linux/i2c/i2c-sh_mobile.h>
  26 #include <linux/io.h>
  27 #include <linux/serial_sci.h>
  28 #include <linux/sh_dma.h>
  29 #include <linux/sh_timer.h>
  30 #include <linux/platform_data/sh_ipmmu.h>
  31 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  32
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/time.h>
  37
  38 #include "common.h"
  39 #include "dma-register.h"
  40 #include "intc.h"
  41 #include "irqs.h"
  42 #include "sh73a0.h"
  43
  44 static struct map_desc sh73a0_io_desc[] __initdata = {
  45         /* create a 1:1 identity mapping for 0xe6xxxxxx
  46          * used by CPGA, INTC and PFC.
  47          */
  48         {
  49                 .virtual        = 0xe6000000,
  50                 .pfn            = __phys_to_pfn(0xe6000000),
  51                 .length         = 256 << 20,
  52                 .type           = MT_DEVICE_NONSHARED
  53         },
  54 };
  55
  56 void __init sh73a0_map_io(void)
  57 {
  58         debug_ll_io_init();
  59         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  60 }
  61
  62 /* PFC */
  63 static struct resource pfc_resources[] __initdata = {
  64         DEFINE_RES_MEM(0xe6050000, 0x8000),
  65         DEFINE_RES_MEM(0xe605801c, 0x000c),
  66 };
  67
  68 void __init sh73a0_pinmux_init(void)
  69 {
  70         platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
  71                                         ARRAY_SIZE(pfc_resources));
  72 }
  73
  74 /* SCIF */
  75 #define SH73A0_SCIF(scif_type, index, baseaddr, irq)            \
  76 static struct plat_sci_port scif##index##_platform_data = {     \
  77         .type           = scif_type,                            \
  78         .flags          = UPF_BOOT_AUTOCONF,                    \
  79         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  80 };                                                              \
  81                                                                 \
  82 static struct resource scif##index##_resources[] = {            \
  83         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  84         DEFINE_RES_IRQ(irq),                                    \
  85 };                                                              \
  86                                                                 \
  87 static struct platform_device scif##index##_device = {          \
  88         .name           = "sh-sci",                             \
  89         .id             = index,                                \
  90         .resource       = scif##index##_resources,              \
  91         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
  92         .dev            = {                                     \
  93                 .platform_data  = &scif##index##_platform_data, \
  94         },                                                      \
  95 }
  96
  97 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
  98 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
  99 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
 100 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
 101 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
 102 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
 103 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
 104 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
 105 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
 106
 107 static struct sh_timer_config cmt1_platform_data = {
 108         .channels_mask = 0x3f,
 109 };
 110
 111 static struct resource cmt1_resources[] = {
 112         DEFINE_RES_MEM(0xe6138000, 0x200),
 113         DEFINE_RES_IRQ(gic_spi(65)),
 114 };
 115
 116 static struct platform_device cmt1_device = {
 117         .name           = "sh-cmt-48",
 118         .id             = 1,
 119         .dev = {
 120                 .platform_data  = &cmt1_platform_data,
 121         },
 122         .resource       = cmt1_resources,
 123         .num_resources  = ARRAY_SIZE(cmt1_resources),
 124 };
 125
 126 /* TMU */
 127 static struct sh_timer_config tmu0_platform_data = {
 128         .channels_mask = 7,
 129 };
 130
 131 static struct resource tmu0_resources[] = {
 132         DEFINE_RES_MEM(0xfff60000, 0x2c),
 133         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 134         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 135         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 136 };
 137
 138 static struct platform_device tmu0_device = {
 139         .name           = "sh-tmu",
 140         .id             = 0,
 141         .dev = {
 142                 .platform_data  = &tmu0_platform_data,
 143         },
 144         .resource       = tmu0_resources,
 145         .num_resources  = ARRAY_SIZE(tmu0_resources),
 146 };
 147
 148 static struct resource i2c0_resources[] = {
 149         [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
 150         [1] = {
 151                 .start  = gic_spi(167),
 152                 .end    = gic_spi(170),
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct resource i2c1_resources[] = {
 158         [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
 159         [1] = {
 160                 .start  = gic_spi(51),
 161                 .end    = gic_spi(54),
 162                 .flags  = IORESOURCE_IRQ,
 163         },
 164 };
 165
 166 static struct resource i2c2_resources[] = {
 167         [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
 168         [1] = {
 169                 .start  = gic_spi(171),
 170                 .end    = gic_spi(174),
 171                 .flags  = IORESOURCE_IRQ,
 172         },
 173 };
 174
 175 static struct resource i2c3_resources[] = {
 176         [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
 177         [1] = {
 178                 .start  = gic_spi(183),
 179                 .end    = gic_spi(186),
 180                 .flags  = IORESOURCE_IRQ,
 181         },
 182 };
 183
 184 static struct resource i2c4_resources[] = {
 185         [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
 186         [1] = {
 187                 .start  = gic_spi(187),
 188                 .end    = gic_spi(190),
 189                 .flags  = IORESOURCE_IRQ,
 190         },
 191 };
 192
 193 static struct i2c_sh_mobile_platform_data i2c_platform_data = {
 194         .clks_per_count = 2,
 195 };
 196
 197 static struct platform_device i2c0_device = {
 198         .name           = "i2c-sh_mobile",
 199         .id             = 0,
 200         .resource       = i2c0_resources,
 201         .num_resources  = ARRAY_SIZE(i2c0_resources),
 202         .dev            = {
 203                 .platform_data  = &i2c_platform_data,
 204         },
 205 };
 206
 207 static struct platform_device i2c1_device = {
 208         .name           = "i2c-sh_mobile",
 209         .id             = 1,
 210         .resource       = i2c1_resources,
 211         .num_resources  = ARRAY_SIZE(i2c1_resources),
 212         .dev            = {
 213                 .platform_data  = &i2c_platform_data,
 214         },
 215 };
 216
 217 static struct platform_device i2c2_device = {
 218         .name           = "i2c-sh_mobile",
 219         .id             = 2,
 220         .resource       = i2c2_resources,
 221         .num_resources  = ARRAY_SIZE(i2c2_resources),
 222         .dev            = {
 223                 .platform_data  = &i2c_platform_data,
 224         },
 225 };
 226
 227 static struct platform_device i2c3_device = {
 228         .name           = "i2c-sh_mobile",
 229         .id             = 3,
 230         .resource       = i2c3_resources,
 231         .num_resources  = ARRAY_SIZE(i2c3_resources),
 232         .dev            = {
 233                 .platform_data  = &i2c_platform_data,
 234         },
 235 };
 236
 237 static struct platform_device i2c4_device = {
 238         .name           = "i2c-sh_mobile",
 239         .id             = 4,
 240         .resource       = i2c4_resources,
 241         .num_resources  = ARRAY_SIZE(i2c4_resources),
 242         .dev            = {
 243                 .platform_data  = &i2c_platform_data,
 244         },
 245 };
 246
 247 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 248         {
 249                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 250                 .addr           = 0xe6c40020,
 251                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 252                 .mid_rid        = 0x21,
 253         }, {
 254                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 255                 .addr           = 0xe6c40024,
 256                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 257                 .mid_rid        = 0x22,
 258         }, {
 259                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 260                 .addr           = 0xe6c50020,
 261                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 262                 .mid_rid        = 0x25,
 263         }, {
 264                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 265                 .addr           = 0xe6c50024,
 266                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 267                 .mid_rid        = 0x26,
 268         }, {
 269                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 270                 .addr           = 0xe6c60020,
 271                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 272                 .mid_rid        = 0x29,
 273         }, {
 274                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 275                 .addr           = 0xe6c60024,
 276                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 277                 .mid_rid        = 0x2a,
 278         }, {
 279                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 280                 .addr           = 0xe6c70020,
 281                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 282                 .mid_rid        = 0x2d,
 283         }, {
 284                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 285                 .addr           = 0xe6c70024,
 286                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 287                 .mid_rid        = 0x2e,
 288         }, {
 289                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 290                 .addr           = 0xe6c80020,
 291                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 292                 .mid_rid        = 0x39,
 293         }, {
 294                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 295                 .addr           = 0xe6c80024,
 296                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 297                 .mid_rid        = 0x3a,
 298         }, {
 299                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 300                 .addr           = 0xe6cb0020,
 301                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 302                 .mid_rid        = 0x35,
 303         }, {
 304                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 305                 .addr           = 0xe6cb0024,
 306                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 307                 .mid_rid        = 0x36,
 308         }, {
 309                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 310                 .addr           = 0xe6cc0020,
 311                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 312                 .mid_rid        = 0x1d,
 313         }, {
 314                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 315                 .addr           = 0xe6cc0024,
 316                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 317                 .mid_rid        = 0x1e,
 318         }, {
 319                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 320                 .addr           = 0xe6cd0020,
 321                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 322                 .mid_rid        = 0x19,
 323         }, {
 324                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 325                 .addr           = 0xe6cd0024,
 326                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 327                 .mid_rid        = 0x1a,
 328         }, {
 329                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 330                 .addr           = 0xe6c30040,
 331                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 332                 .mid_rid        = 0x3d,
 333         }, {
 334                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 335                 .addr           = 0xe6c30060,
 336                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 337                 .mid_rid        = 0x3e,
 338         }, {
 339                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 340                 .addr           = 0xee100030,
 341                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 342                 .mid_rid        = 0xc1,
 343         }, {
 344                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 345                 .addr           = 0xee100030,
 346                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 347                 .mid_rid        = 0xc2,
 348         }, {
 349                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 350                 .addr           = 0xee120030,
 351                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 352                 .mid_rid        = 0xc9,
 353         }, {
 354                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 355                 .addr           = 0xee120030,
 356                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 357                 .mid_rid        = 0xca,
 358         }, {
 359                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 360                 .addr           = 0xee140030,
 361                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 362                 .mid_rid        = 0xcd,
 363         }, {
 364                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 365                 .addr           = 0xee140030,
 366                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 367                 .mid_rid        = 0xce,
 368         }, {
 369                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 370                 .addr           = 0xe6bd0034,
 371                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 372                 .mid_rid        = 0xd1,
 373         }, {
 374                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 375                 .addr           = 0xe6bd0034,
 376                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 377                 .mid_rid        = 0xd2,
 378         },
 379 };
 380
 381 #define DMAE_CHANNEL(_offset)                                   \
 382         {                                                       \
 383                 .offset         = _offset - 0x20,               \
 384                 .dmars          = _offset - 0x20 + 0x40,        \
 385         }
 386
 387 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 388         DMAE_CHANNEL(0x8000),
 389         DMAE_CHANNEL(0x8080),
 390         DMAE_CHANNEL(0x8100),
 391         DMAE_CHANNEL(0x8180),
 392         DMAE_CHANNEL(0x8200),
 393         DMAE_CHANNEL(0x8280),
 394         DMAE_CHANNEL(0x8300),
 395         DMAE_CHANNEL(0x8380),
 396         DMAE_CHANNEL(0x8400),
 397         DMAE_CHANNEL(0x8480),
 398         DMAE_CHANNEL(0x8500),
 399         DMAE_CHANNEL(0x8580),
 400         DMAE_CHANNEL(0x8600),
 401         DMAE_CHANNEL(0x8680),
 402         DMAE_CHANNEL(0x8700),
 403         DMAE_CHANNEL(0x8780),
 404         DMAE_CHANNEL(0x8800),
 405         DMAE_CHANNEL(0x8880),
 406         DMAE_CHANNEL(0x8900),
 407         DMAE_CHANNEL(0x8980),
 408 };
 409
 410 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 411         .slave          = sh73a0_dmae_slaves,
 412         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 413         .channel        = sh73a0_dmae_channels,
 414         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 415         .ts_low_shift   = TS_LOW_SHIFT,
 416         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 417         .ts_high_shift  = TS_HI_SHIFT,
 418         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 419         .ts_shift       = dma_ts_shift,
 420         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 421         .dmaor_init     = DMAOR_DME,
 422 };
 423
 424 static struct resource sh73a0_dmae_resources[] = {
 425         DEFINE_RES_MEM(0xfe000020, 0x89e0),
 426         {
 427                 .name   = "error_irq",
 428                 .start  = gic_spi(129),
 429                 .end    = gic_spi(129),
 430                 .flags  = IORESOURCE_IRQ,
 431         },
 432         {
 433                 /* IRQ for channels 0-19 */
 434                 .start  = gic_spi(109),
 435                 .end    = gic_spi(128),
 436                 .flags  = IORESOURCE_IRQ,
 437         },
 438 };
 439
 440 static struct platform_device dma0_device = {
 441         .name           = "sh-dma-engine",
 442         .id             = 0,
 443         .resource       = sh73a0_dmae_resources,
 444         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 445         .dev            = {
 446                 .platform_data  = &sh73a0_dmae_platform_data,
 447         },
 448 };
 449
 450 /* MPDMAC */
 451 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 452         {
 453                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 454                 .addr           = 0xec230020,
 455                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 456                 .mid_rid        = 0xd6, /* CHECK ME */
 457         }, {
 458                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 459                 .addr           = 0xec230024,
 460                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 461                 .mid_rid        = 0xd5, /* CHECK ME */
 462         }, {
 463                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 464                 .addr           = 0xec230060,
 465                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 466                 .mid_rid        = 0xda, /* CHECK ME */
 467         }, {
 468                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 469                 .addr           = 0xec230064,
 470                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 471                 .mid_rid        = 0xd9, /* CHECK ME */
 472         }, {
 473                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 474                 .addr           = 0xec240020,
 475                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 476                 .mid_rid        = 0x8e, /* CHECK ME */
 477         }, {
 478                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 479                 .addr           = 0xec240024,
 480                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 481                 .mid_rid        = 0x8d, /* CHECK ME */
 482         }, {
 483                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 484                 .addr           =  0xec240060,
 485                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 486                 .mid_rid        = 0x9a, /* CHECK ME */
 487         },
 488 };
 489
 490 #define MPDMA_CHANNEL(a, b, c)                  \
 491 {                                               \
 492         .offset         = a,                    \
 493         .dmars          = b,                    \
 494         .dmars_bit      = c,                    \
 495         .chclr_offset   = (0x220 - 0x20) + a    \
 496 }
 497
 498 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 499         MPDMA_CHANNEL(0x00, 0, 0),
 500         MPDMA_CHANNEL(0x10, 0, 8),
 501         MPDMA_CHANNEL(0x20, 4, 0),
 502         MPDMA_CHANNEL(0x30, 4, 8),
 503         MPDMA_CHANNEL(0x50, 8, 0),
 504         MPDMA_CHANNEL(0x70, 8, 8),
 505 };
 506
 507 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 508         .slave          = sh73a0_mpdma_slaves,
 509         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 510         .channel        = sh73a0_mpdma_channels,
 511         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 512         .ts_low_shift   = TS_LOW_SHIFT,
 513         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 514         .ts_high_shift  = TS_HI_SHIFT,
 515         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 516         .ts_shift       = dma_ts_shift,
 517         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 518         .dmaor_init     = DMAOR_DME,
 519         .chclr_present  = 1,
 520 };
 521
 522 /* Resource order important! */
 523 static struct resource sh73a0_mpdma_resources[] = {
 524         /* Channel registers and DMAOR */
 525         DEFINE_RES_MEM(0xec618020, 0x270),
 526         /* DMARSx */
 527         DEFINE_RES_MEM(0xec619000, 0xc),
 528         {
 529                 .name   = "error_irq",
 530                 .start  = gic_spi(181),
 531                 .end    = gic_spi(181),
 532                 .flags  = IORESOURCE_IRQ,
 533         },
 534         {
 535                 /* IRQ for channels 0-5 */
 536                 .start  = gic_spi(175),
 537                 .end    = gic_spi(180),
 538                 .flags  = IORESOURCE_IRQ,
 539         },
 540 };
 541
 542 static struct platform_device mpdma0_device = {
 543         .name           = "sh-dma-engine",
 544         .id             = 1,
 545         .resource       = sh73a0_mpdma_resources,
 546         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 547         .dev            = {
 548                 .platform_data  = &sh73a0_mpdma_platform_data,
 549         },
 550 };
 551
 552 static struct resource pmu_resources[] = {
 553         [0] = {
 554                 .start  = gic_spi(55),
 555                 .end    = gic_spi(55),
 556                 .flags  = IORESOURCE_IRQ,
 557         },
 558         [1] = {
 559                 .start  = gic_spi(56),
 560                 .end    = gic_spi(56),
 561                 .flags  = IORESOURCE_IRQ,
 562         },
 563 };
 564
 565 static struct platform_device pmu_device = {
 566         .name           = "arm-pmu",
 567         .id             = -1,
 568         .num_resources  = ARRAY_SIZE(pmu_resources),
 569         .resource       = pmu_resources,
 570 };
 571
 572 /* an IPMMU module for ICB */
 573 static struct resource ipmmu_resources[] = {
 574         DEFINE_RES_MEM(0xfe951000, 0x100),
 575 };
 576
 577 static const char * const ipmmu_dev_names[] = {
 578         "sh_mobile_lcdc_fb.0",
 579 };
 580
 581 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 582         .dev_names = ipmmu_dev_names,
 583         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 584 };
 585
 586 static struct platform_device ipmmu_device = {
 587         .name           = "ipmmu",
 588         .id             = -1,
 589         .dev = {
 590                 .platform_data = &ipmmu_platform_data,
 591         },
 592         .resource       = ipmmu_resources,
 593         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 594 };
 595
 596 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
 597         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
 598         .control_parent = true,
 599 };
 600
 601 static struct resource irqpin0_resources[] = {
 602         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
 603         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
 604         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
 605         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
 606         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
 607         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
 608         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
 609         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
 610         DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
 611         DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
 612         DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
 613         DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
 614         DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
 615 };
 616
 617 static struct platform_device irqpin0_device = {
 618         .name           = "renesas_intc_irqpin",
 619         .id             = 0,
 620         .resource       = irqpin0_resources,
 621         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 622         .dev            = {
 623                 .platform_data  = &irqpin0_platform_data,
 624         },
 625 };
 626
 627 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 628         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 629         .control_parent = true, /* Disable spurious IRQ10 */
 630 };
 631
 632 static struct resource irqpin1_resources[] = {
 633         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 634         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 635         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 636         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 637         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 638         DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
 639         DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
 640         DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
 641         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
 642         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
 643         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
 644         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
 645         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
 646 };
 647
 648 static struct platform_device irqpin1_device = {
 649         .name           = "renesas_intc_irqpin",
 650         .id             = 1,
 651         .resource       = irqpin1_resources,
 652         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 653         .dev            = {
 654                 .platform_data  = &irqpin1_platform_data,
 655         },
 656 };
 657
 658 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 659         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 660         .control_parent = true,
 661 };
 662
 663 static struct resource irqpin2_resources[] = {
 664         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 665         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
 666         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
 667         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
 668         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
 669         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
 670         DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
 671         DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
 672         DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
 673         DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
 674         DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
 675         DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
 676         DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
 677 };
 678
 679 static struct platform_device irqpin2_device = {
 680         .name           = "renesas_intc_irqpin",
 681         .id             = 2,
 682         .resource       = irqpin2_resources,
 683         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 684         .dev            = {
 685                 .platform_data  = &irqpin2_platform_data,
 686         },
 687 };
 688
 689 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 690         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 691         .control_parent = true,
 692 };
 693
 694 static struct resource irqpin3_resources[] = {
 695         DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
 696         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 697         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 698         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 699         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 700         DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
 701         DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
 702         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
 703         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
 704         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
 705         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
 706         DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
 707         DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
 708 };
 709
 710 static struct platform_device irqpin3_device = {
 711         .name           = "renesas_intc_irqpin",
 712         .id             = 3,
 713         .resource       = irqpin3_resources,
 714         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 715         .dev            = {
 716                 .platform_data  = &irqpin3_platform_data,
 717         },
 718 };
 719
 720 static struct platform_device *sh73a0_early_devices[] __initdata = {
 721         &scif0_device,
 722         &scif1_device,
 723         &scif2_device,
 724         &scif3_device,
 725         &scif4_device,
 726         &scif5_device,
 727         &scif6_device,
 728         &scif7_device,
 729         &scif8_device,
 730         &tmu0_device,
 731         &ipmmu_device,
 732         &cmt1_device,
 733 };
 734
 735 static struct platform_device *sh73a0_late_devices[] __initdata = {
 736         &i2c0_device,
 737         &i2c1_device,
 738         &i2c2_device,
 739         &i2c3_device,
 740         &i2c4_device,
 741         &dma0_device,
 742         &mpdma0_device,
 743         &pmu_device,
 744         &irqpin0_device,
 745         &irqpin1_device,
 746         &irqpin2_device,
 747         &irqpin3_device,
 748 };
 749
 750 #define SRCR2          IOMEM(0xe61580b0)
 751
 752 void __init sh73a0_add_standard_devices(void)
 753 {
 754         /* Clear software reset bit on SY-DMAC module */
 755         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 756
 757         platform_add_devices(sh73a0_early_devices,
 758                             ARRAY_SIZE(sh73a0_early_devices));
 759         platform_add_devices(sh73a0_late_devices,
 760                             ARRAY_SIZE(sh73a0_late_devices));
 761 }
 762
 763 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 764 void __init __weak sh73a0_register_twd(void) { }
 765
 766 void __init sh73a0_earlytimer_init(void)
 767 {
 768         shmobile_init_delay();
 769         sh73a0_clock_init();
 770         shmobile_earlytimer_init();
 771         sh73a0_register_twd();
 772 }
 773
 774 void __init sh73a0_add_early_devices(void)
 775 {
 776         early_platform_add_devices(sh73a0_early_devices,
 777                                    ARRAY_SIZE(sh73a0_early_devices));
 778
 779         /* setup early console here as well */
 780         shmobile_setup_console();
 781 }
 782
 783 #ifdef CONFIG_USE_OF
 784
 785 void __init sh73a0_add_standard_devices_dt(void)
 786 {
 787         /* clocks are setup late during boot in the case of DT */
 788         sh73a0_clock_init();
 789
 790         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 791 }
 792
 793 #define RESCNT2 IOMEM(0xe6188020)
 794 static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
 795 {
 796         /* Do soft power on reset */
 797         writel((1 << 31), RESCNT2);
 798 }
 799
 800 static const char *sh73a0_boards_compat_dt[] __initdata = {
 801         "renesas,sh73a0",
 802         NULL,
 803 };
 804
 805 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 806         .smp            = smp_ops(sh73a0_smp_ops),
 807         .map_io         = sh73a0_map_io,
 808         .init_early     = shmobile_init_delay,
 809         .init_machine   = sh73a0_add_standard_devices_dt,
 810         .init_late      = shmobile_init_late,
 811         .restart        = sh73a0_restart,
 812         .dt_compat      = sh73a0_boards_compat_dt,
 813 MACHINE_END
 814 #endif /* CONFIG_USE_OF */