arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 /*
   2  * dts file for Hisilicon Hi6220 SoC
   3  *
   4  * Copyright (C) 2015, Hisilicon Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/reset/hisi,hi6220-resets.h>
   9 #include <dt-bindings/clock/hi6220-clock.h>
  10 #include <dt-bindings/pinctrl/hisi.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "hisilicon,hi6220";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         psci {
  20                 compatible = "arm,psci-0.2";
  21                 method = "smc";
  22         };
  23
  24         cpus {
  25                 #address-cells = <2>;
  26                 #size-cells = <0>;
  27
  28                 cpu-map {
  29                         cluster0 {
  30                                 core0 {
  31                                         cpu = <&cpu0>;
  32                                 };
  33                                 core1 {
  34                                         cpu = <&cpu1>;
  35                                 };
  36                                 core2 {
  37                                         cpu = <&cpu2>;
  38                                 };
  39                                 core3 {
  40                                         cpu = <&cpu3>;
  41                                 };
  42                         };
  43                         cluster1 {
  44                                 core0 {
  45                                         cpu = <&cpu4>;
  46                                 };
  47                                 core1 {
  48                                         cpu = <&cpu5>;
  49                                 };
  50                                 core2 {
  51                                         cpu = <&cpu6>;
  52                                 };
  53                                 core3 {
  54                                         cpu = <&cpu7>;
  55                                 };
  56                         };
  57                 };
  58
  59                 idle-states {
  60                         entry-method = "psci";
  61
  62                         CPU_SLEEP: cpu-sleep {
  63                                 compatible = "arm,idle-state";
  64                                 local-timer-stop;
  65                                 arm,psci-suspend-param = <0x0010000>;
  66                                 entry-latency-us = <700>;
  67                                 exit-latency-us = <250>;
  68                                 min-residency-us = <1000>;
  69                         };
  70
  71                         CLUSTER_SLEEP: cluster-sleep {
  72                                 compatible = "arm,idle-state";
  73                                 local-timer-stop;
  74                                 arm,psci-suspend-param = <0x1010000>;
  75                                 entry-latency-us = <1000>;
  76                                 exit-latency-us = <700>;
  77                                 min-residency-us = <2700>;
  78                                 wakeup-latency-us = <1500>;
  79                         };
  80                 };
  81
  82                 cpu0: cpu@0 {
  83                         compatible = "arm,cortex-a53", "arm,armv8";
  84                         device_type = "cpu";
  85                         reg = <0x0 0x0>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&CLUSTER0_L2>;
  88                         clocks = <&stub_clock 0>;
  89                         operating-points-v2 = <&cpu_opp_table>;
  90                         cooling-min-level = <4>;
  91                         cooling-max-level = <0>;
  92                         #cooling-cells = <2>; /* min followed by max */
  93                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  94                         dynamic-power-coefficient = <311>;
  95                 };
  96
  97                 cpu1: cpu@1 {
  98                         compatible = "arm,cortex-a53", "arm,armv8";
  99                         device_type = "cpu";
 100                         reg = <0x0 0x1>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&CLUSTER0_L2>;
 103                         operating-points-v2 = <&cpu_opp_table>;
 104                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 105                 };
 106
 107                 cpu2: cpu@2 {
 108                         compatible = "arm,cortex-a53", "arm,armv8";
 109                         device_type = "cpu";
 110                         reg = <0x0 0x2>;
 111                         enable-method = "psci";
 112                         next-level-cache = <&CLUSTER0_L2>;
 113                         operating-points-v2 = <&cpu_opp_table>;
 114                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 115                 };
 116
 117                 cpu3: cpu@3 {
 118                         compatible = "arm,cortex-a53", "arm,armv8";
 119                         device_type = "cpu";
 120                         reg = <0x0 0x3>;
 121                         enable-method = "psci";
 122                         next-level-cache = <&CLUSTER0_L2>;
 123                         operating-points-v2 = <&cpu_opp_table>;
 124                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 125                 };
 126
 127                 cpu4: cpu@100 {
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         device_type = "cpu";
 130                         reg = <0x0 0x100>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&CLUSTER1_L2>;
 133                         operating-points-v2 = <&cpu_opp_table>;
 134                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 135                 };
 136
 137                 cpu5: cpu@101 {
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         device_type = "cpu";
 140                         reg = <0x0 0x101>;
 141                         enable-method = "psci";
 142                         next-level-cache = <&CLUSTER1_L2>;
 143                         operating-points-v2 = <&cpu_opp_table>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu6: cpu@102 {
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         device_type = "cpu";
 150                         reg = <0x0 0x102>;
 151                         enable-method = "psci";
 152                         next-level-cache = <&CLUSTER1_L2>;
 153                         operating-points-v2 = <&cpu_opp_table>;
 154                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 155                 };
 156
 157                 cpu7: cpu@103 {
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         device_type = "cpu";
 160                         reg = <0x0 0x103>;
 161                         enable-method = "psci";
 162                         next-level-cache = <&CLUSTER1_L2>;
 163                         operating-points-v2 = <&cpu_opp_table>;
 164                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 165                 };
 166
 167                 CLUSTER0_L2: l2-cache0 {
 168                         compatible = "cache";
 169                 };
 170
 171                 CLUSTER1_L2: l2-cache1 {
 172                         compatible = "cache";
 173                 };
 174         };
 175
 176         cpu_opp_table: cpu_opp_table {
 177                 compatible = "operating-points-v2";
 178                 opp-shared;
 179
 180                 opp00 {
 181                         opp-hz = /bits/ 64 <208000000>;
 182                         opp-microvolt = <1040000>;
 183                         clock-latency-ns = <500000>;
 184                 };
 185                 opp01 {
 186                         opp-hz = /bits/ 64 <432000000>;
 187                         opp-microvolt = <1040000>;
 188                         clock-latency-ns = <500000>;
 189                 };
 190                 opp02 {
 191                         opp-hz = /bits/ 64 <729000000>;
 192                         opp-microvolt = <1090000>;
 193                         clock-latency-ns = <500000>;
 194                 };
 195                 opp03 {
 196                         opp-hz = /bits/ 64 <960000000>;
 197                         opp-microvolt = <1180000>;
 198                         clock-latency-ns = <500000>;
 199                 };
 200                 opp04 {
 201                         opp-hz = /bits/ 64 <1200000000>;
 202                         opp-microvolt = <1330000>;
 203                         clock-latency-ns = <500000>;
 204                 };
 205         };
 206
 207         gic: interrupt-controller@f6801000 {
 208                 compatible = "arm,gic-400";
 209                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 210                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 211                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 212                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 213                 #address-cells = <0>;
 214                 #interrupt-cells = <3>;
 215                 interrupt-controller;
 216                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 217         };
 218
 219         timer {
 220                 compatible = "arm,armv8-timer";
 221                 interrupt-parent = <&gic>;
 222                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 223                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 224                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 225                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 226         };
 227
 228         soc {
 229                 compatible = "simple-bus";
 230                 #address-cells = <2>;
 231                 #size-cells = <2>;
 232                 ranges;
 233
 234                 sram: sram@fff80000 {
 235                         compatible = "hisilicon,hi6220-sramctrl", "syscon";
 236                         reg = <0x0 0xfff80000 0x0 0x12000>;
 237                 };
 238
 239                 ao_ctrl: ao_ctrl@f7800000 {
 240                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 241                         reg = <0x0 0xf7800000 0x0 0x2000>;
 242                         #clock-cells = <1>;
 243                 };
 244
 245                 sys_ctrl: sys_ctrl@f7030000 {
 246                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 247                         reg = <0x0 0xf7030000 0x0 0x2000>;
 248                         #clock-cells = <1>;
 249                         #reset-cells = <1>;
 250                 };
 251
 252                 media_ctrl: media_ctrl@f4410000 {
 253                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 254                         reg = <0x0 0xf4410000 0x0 0x1000>;
 255                         #clock-cells = <1>;
 256                         #reset-cells = <1>;
 257                 };
 258
 259                 pm_ctrl: pm_ctrl@f7032000 {
 260                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 261                         reg = <0x0 0xf7032000 0x0 0x1000>;
 262                         #clock-cells = <1>;
 263                 };
 264
 265                 medianoc_ade: medianoc_ade@f4520000 {
 266                         compatible = "syscon";
 267                         reg = <0x0 0xf4520000 0x0 0x4000>;
 268                 };
 269
 270                 stub_clock: stub_clock {
 271                         compatible = "hisilicon,hi6220-stub-clk";
 272                         hisilicon,hi6220-clk-sram = <&sram>;
 273                         #clock-cells = <1>;
 274                         mbox-names = "mbox-tx";
 275                         mboxes = <&mailbox 1 0 11>;
 276                 };
 277
 278                 uart0: uart@f8015000 {  /* console */
 279                         compatible = "arm,pl011", "arm,primecell";
 280                         reg = <0x0 0xf8015000 0x0 0x1000>;
 281                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 282                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 283                                  <&ao_ctrl HI6220_UART0_PCLK>;
 284                         clock-names = "uartclk", "apb_pclk";
 285                 };
 286
 287                 uart1: uart@f7111000 {
 288                         compatible = "arm,pl011", "arm,primecell";
 289                         reg = <0x0 0xf7111000 0x0 0x1000>;
 290                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 292                                  <&sys_ctrl HI6220_UART1_PCLK>;
 293                         clock-names = "uartclk", "apb_pclk";
 294                         pinctrl-names = "default";
 295                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
 296                         status = "disabled";
 297                 };
 298
 299                 uart2: uart@f7112000 {
 300                         compatible = "arm,pl011", "arm,primecell";
 301                         reg = <0x0 0xf7112000 0x0 0x1000>;
 302                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 304                                  <&sys_ctrl HI6220_UART2_PCLK>;
 305                         clock-names = "uartclk", "apb_pclk";
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 308                         status = "disabled";
 309                 };
 310
 311                 uart3: uart@f7113000 {
 312                         compatible = "arm,pl011", "arm,primecell";
 313                         reg = <0x0 0xf7113000 0x0 0x1000>;
 314                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 315                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 316                                  <&sys_ctrl HI6220_UART3_PCLK>;
 317                         clock-names = "uartclk", "apb_pclk";
 318                         pinctrl-names = "default";
 319                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 320                         status = "disabled";
 321                 };
 322
 323                 uart4: uart@f7114000 {
 324                         compatible = "arm,pl011", "arm,primecell";
 325                         reg = <0x0 0xf7114000 0x0 0x1000>;
 326                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 328                                  <&sys_ctrl HI6220_UART4_PCLK>;
 329                         clock-names = "uartclk", "apb_pclk";
 330                         pinctrl-names = "default";
 331                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 332                         status = "disabled";
 333                 };
 334
 335                 dual_timer0: timer@f8008000 {
 336                         compatible = "arm,sp804", "arm,primecell";
 337                         reg = <0x0 0xf8008000 0x0 0x1000>;
 338                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 339                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
 341                                  <&ao_ctrl HI6220_TIMER0_PCLK>,
 342                                  <&ao_ctrl HI6220_TIMER0_PCLK>;
 343                         clock-names = "timer1", "timer2", "apb_pclk";
 344                 };
 345
 346                 rtc0: rtc@f8003000 {
 347                         compatible = "arm,pl031", "arm,primecell";
 348                         reg = <0x0 0xf8003000 0x0 0x1000>;
 349                         interrupts = <0 12 4>;
 350                         clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
 351                         clock-names = "apb_pclk";
 352                 };
 353
 354                 rtc1: rtc@f8004000 {
 355                         compatible = "arm,pl031", "arm,primecell";
 356                         reg = <0x0 0xf8004000 0x0 0x1000>;
 357                         interrupts = <0 8 4>;
 358                         clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
 359                         clock-names = "apb_pclk";
 360                 };
 361
 362                 pmx0: pinmux@f7010000 {
 363                         compatible = "pinctrl-single";
 364                         reg = <0x0 0xf7010000  0x0 0x27c>;
 365                         #address-cells = <1>;
 366                         #size-cells = <1>;
 367                         #gpio-range-cells = <3>;
 368                         pinctrl-single,register-width = <32>;
 369                         pinctrl-single,function-mask = <7>;
 370                         pinctrl-single,gpio-range = <
 371                                 &range  80  8 MUX_M0 /* gpio  3: [0..7] */
 372                                 &range  88  8 MUX_M0 /* gpio  4: [0..7] */
 373                                 &range  96  8 MUX_M0 /* gpio  5: [0..7] */
 374                                 &range 104  8 MUX_M0 /* gpio  6: [0..7] */
 375                                 &range 112  8 MUX_M0 /* gpio  7: [0..7] */
 376                                 &range 120  2 MUX_M0 /* gpio  8: [0..1] */
 377                                 &range   2  6 MUX_M1 /* gpio  8: [2..7] */
 378                                 &range   8  8 MUX_M1 /* gpio  9: [0..7] */
 379                                 &range   0  1 MUX_M1 /* gpio 10: [0]    */
 380                                 &range  16  7 MUX_M1 /* gpio 10: [1..7] */
 381                                 &range  23  3 MUX_M1 /* gpio 11: [0..2] */
 382                                 &range  28  5 MUX_M1 /* gpio 11: [3..7] */
 383                                 &range  33  3 MUX_M1 /* gpio 12: [0..2] */
 384                                 &range  43  5 MUX_M1 /* gpio 12: [3..7] */
 385                                 &range  48  8 MUX_M1 /* gpio 13: [0..7] */
 386                                 &range  56  8 MUX_M1 /* gpio 14: [0..7] */
 387                                 &range  74  6 MUX_M1 /* gpio 15: [0..5] */
 388                                 &range 122  1 MUX_M1 /* gpio 15: [6]    */
 389                                 &range 126  1 MUX_M1 /* gpio 15: [7]    */
 390                                 &range 127  8 MUX_M1 /* gpio 16: [0..7] */
 391                                 &range 135  8 MUX_M1 /* gpio 17: [0..7] */
 392                                 &range 143  8 MUX_M1 /* gpio 18: [0..7] */
 393                                 &range 151  8 MUX_M1 /* gpio 19: [0..7] */
 394                         >;
 395                         range: gpio-range {
 396                                 #pinctrl-single,gpio-range-cells = <3>;
 397                         };
 398                 };
 399
 400                 pmx1: pinmux@f7010800 {
 401                         compatible = "pinconf-single";
 402                         reg = <0x0 0xf7010800 0x0 0x28c>;
 403                         #address-cells = <1>;
 404                         #size-cells = <1>;
 405                         pinctrl-single,register-width = <32>;
 406                 };
 407
 408                 pmx2: pinmux@f8001800 {
 409                         compatible = "pinconf-single";
 410                         reg = <0x0 0xf8001800 0x0 0x78>;
 411                         #address-cells = <1>;
 412                         #size-cells = <1>;
 413                         pinctrl-single,register-width = <32>;
 414                 };
 415
 416                 gpio0: gpio@f8011000 {
 417                         compatible = "arm,pl061", "arm,primecell";
 418                         reg = <0x0 0xf8011000 0x0 0x1000>;
 419                         interrupts = <0 52 0x4>;
 420                         gpio-controller;
 421                         #gpio-cells = <2>;
 422                         interrupt-controller;
 423                         #interrupt-cells = <2>;
 424                         clocks = <&ao_ctrl 2>;
 425                         clock-names = "apb_pclk";
 426                 };
 427
 428                 gpio1: gpio@f8012000 {
 429                         compatible = "arm,pl061", "arm,primecell";
 430                         reg = <0x0 0xf8012000 0x0 0x1000>;
 431                         interrupts = <0 53 0x4>;
 432                         gpio-controller;
 433                         #gpio-cells = <2>;
 434                         interrupt-controller;
 435                         #interrupt-cells = <2>;
 436                         clocks = <&ao_ctrl 2>;
 437                         clock-names = "apb_pclk";
 438                 };
 439
 440                 gpio2: gpio@f8013000 {
 441                         compatible = "arm,pl061", "arm,primecell";
 442                         reg = <0x0 0xf8013000 0x0 0x1000>;
 443                         interrupts = <0 54 0x4>;
 444                         gpio-controller;
 445                         #gpio-cells = <2>;
 446                         interrupt-controller;
 447                         #interrupt-cells = <2>;
 448                         clocks = <&ao_ctrl 2>;
 449                         clock-names = "apb_pclk";
 450                 };
 451
 452                 gpio3: gpio@f8014000 {
 453                         compatible = "arm,pl061", "arm,primecell";
 454                         reg = <0x0 0xf8014000 0x0 0x1000>;
 455                         interrupts = <0 55 0x4>;
 456                         gpio-controller;
 457                         #gpio-cells = <2>;
 458                         gpio-ranges = <&pmx0 0 80 8>;
 459                         interrupt-controller;
 460                         #interrupt-cells = <2>;
 461                         clocks = <&ao_ctrl 2>;
 462                         clock-names = "apb_pclk";
 463                 };
 464
 465                 gpio4: gpio@f7020000 {
 466                         compatible = "arm,pl061", "arm,primecell";
 467                         reg = <0x0 0xf7020000 0x0 0x1000>;
 468                         interrupts = <0 56 0x4>;
 469                         gpio-controller;
 470                         #gpio-cells = <2>;
 471                         gpio-ranges = <&pmx0 0 88 8>;
 472                         interrupt-controller;
 473                         #interrupt-cells = <2>;
 474                         clocks = <&ao_ctrl 2>;
 475                         clock-names = "apb_pclk";
 476                 };
 477
 478                 gpio5: gpio@f7021000 {
 479                         compatible = "arm,pl061", "arm,primecell";
 480                         reg = <0x0 0xf7021000 0x0 0x1000>;
 481                         interrupts = <0 57 0x4>;
 482                         gpio-controller;
 483                         #gpio-cells = <2>;
 484                         gpio-ranges = <&pmx0 0 96 8>;
 485                         interrupt-controller;
 486                         #interrupt-cells = <2>;
 487                         clocks = <&ao_ctrl 2>;
 488                         clock-names = "apb_pclk";
 489                 };
 490
 491                 gpio6: gpio@f7022000 {
 492                         compatible = "arm,pl061", "arm,primecell";
 493                         reg = <0x0 0xf7022000 0x0 0x1000>;
 494                         interrupts = <0 58 0x4>;
 495                         gpio-controller;
 496                         #gpio-cells = <2>;
 497                         gpio-ranges = <&pmx0 0 104 8>;
 498                         interrupt-controller;
 499                         #interrupt-cells = <2>;
 500                         clocks = <&ao_ctrl 2>;
 501                         clock-names = "apb_pclk";
 502                 };
 503
 504                 gpio7: gpio@f7023000 {
 505                         compatible = "arm,pl061", "arm,primecell";
 506                         reg = <0x0 0xf7023000 0x0 0x1000>;
 507                         interrupts = <0 59 0x4>;
 508                         gpio-controller;
 509                         #gpio-cells = <2>;
 510                         gpio-ranges = <&pmx0 0 112 8>;
 511                         interrupt-controller;
 512                         #interrupt-cells = <2>;
 513                         clocks = <&ao_ctrl 2>;
 514                         clock-names = "apb_pclk";
 515                 };
 516
 517                 gpio8: gpio@f7024000 {
 518                         compatible = "arm,pl061", "arm,primecell";
 519                         reg = <0x0 0xf7024000 0x0 0x1000>;
 520                         interrupts = <0 60 0x4>;
 521                         gpio-controller;
 522                         #gpio-cells = <2>;
 523                         gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
 524                         interrupt-controller;
 525                         #interrupt-cells = <2>;
 526                         clocks = <&ao_ctrl 2>;
 527                         clock-names = "apb_pclk";
 528                 };
 529
 530                 gpio9: gpio@f7025000 {
 531                         compatible = "arm,pl061", "arm,primecell";
 532                         reg = <0x0 0xf7025000 0x0 0x1000>;
 533                         interrupts = <0 61 0x4>;
 534                         gpio-controller;
 535                         #gpio-cells = <2>;
 536                         gpio-ranges = <&pmx0 0 8 8>;
 537                         interrupt-controller;
 538                         #interrupt-cells = <2>;
 539                         clocks = <&ao_ctrl 2>;
 540                         clock-names = "apb_pclk";
 541                 };
 542
 543                 gpio10: gpio@f7026000 {
 544                         compatible = "arm,pl061", "arm,primecell";
 545                         reg = <0x0 0xf7026000 0x0 0x1000>;
 546                         interrupts = <0 62 0x4>;
 547                         gpio-controller;
 548                         #gpio-cells = <2>;
 549                         gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
 550                         interrupt-controller;
 551                         #interrupt-cells = <2>;
 552                         clocks = <&ao_ctrl 2>;
 553                         clock-names = "apb_pclk";
 554                 };
 555
 556                 gpio11: gpio@f7027000 {
 557                         compatible = "arm,pl061", "arm,primecell";
 558                         reg = <0x0 0xf7027000 0x0 0x1000>;
 559                         interrupts = <0 63 0x4>;
 560                         gpio-controller;
 561                         #gpio-cells = <2>;
 562                         gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
 563                         interrupt-controller;
 564                         #interrupt-cells = <2>;
 565                         clocks = <&ao_ctrl 2>;
 566                         clock-names = "apb_pclk";
 567                 };
 568
 569                 gpio12: gpio@f7028000 {
 570                         compatible = "arm,pl061", "arm,primecell";
 571                         reg = <0x0 0xf7028000 0x0 0x1000>;
 572                         interrupts = <0 64 0x4>;
 573                         gpio-controller;
 574                         #gpio-cells = <2>;
 575                         gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
 576                         interrupt-controller;
 577                         #interrupt-cells = <2>;
 578                         clocks = <&ao_ctrl 2>;
 579                         clock-names = "apb_pclk";
 580                 };
 581
 582                 gpio13: gpio@f7029000 {
 583                         compatible = "arm,pl061", "arm,primecell";
 584                         reg = <0x0 0xf7029000 0x0 0x1000>;
 585                         interrupts = <0 65 0x4>;
 586                         gpio-controller;
 587                         #gpio-cells = <2>;
 588                         gpio-ranges = <&pmx0 0 48 8>;
 589                         interrupt-controller;
 590                         #interrupt-cells = <2>;
 591                         clocks = <&ao_ctrl 2>;
 592                         clock-names = "apb_pclk";
 593                 };
 594
 595                 gpio14: gpio@f702a000 {
 596                         compatible = "arm,pl061", "arm,primecell";
 597                         reg = <0x0 0xf702a000 0x0 0x1000>;
 598                         interrupts = <0 66 0x4>;
 599                         gpio-controller;
 600                         #gpio-cells = <2>;
 601                         gpio-ranges = <&pmx0 0 56 8>;
 602                         interrupt-controller;
 603                         #interrupt-cells = <2>;
 604                         clocks = <&ao_ctrl 2>;
 605                         clock-names = "apb_pclk";
 606                 };
 607
 608                 gpio15: gpio@f702b000 {
 609                         compatible = "arm,pl061", "arm,primecell";
 610                         reg = <0x0 0xf702b000 0x0 0x1000>;
 611                         interrupts = <0 67 0x4>;
 612                         gpio-controller;
 613                         #gpio-cells = <2>;
 614                         gpio-ranges = <
 615                                 &pmx0 0 74 6
 616                                 &pmx0 6 122 1
 617                                 &pmx0 7 126 1
 618                         >;
 619                         interrupt-controller;
 620                         #interrupt-cells = <2>;
 621                         clocks = <&ao_ctrl 2>;
 622                         clock-names = "apb_pclk";
 623                 };
 624
 625                 gpio16: gpio@f702c000 {
 626                         compatible = "arm,pl061", "arm,primecell";
 627                         reg = <0x0 0xf702c000 0x0 0x1000>;
 628                         interrupts = <0 68 0x4>;
 629                         gpio-controller;
 630                         #gpio-cells = <2>;
 631                         gpio-ranges = <&pmx0 0 127 8>;
 632                         interrupt-controller;
 633                         #interrupt-cells = <2>;
 634                         clocks = <&ao_ctrl 2>;
 635                         clock-names = "apb_pclk";
 636                 };
 637
 638                 gpio17: gpio@f702d000 {
 639                         compatible = "arm,pl061", "arm,primecell";
 640                         reg = <0x0 0xf702d000 0x0 0x1000>;
 641                         interrupts = <0 69 0x4>;
 642                         gpio-controller;
 643                         #gpio-cells = <2>;
 644                         gpio-ranges = <&pmx0 0 135 8>;
 645                         interrupt-controller;
 646                         #interrupt-cells = <2>;
 647                         clocks = <&ao_ctrl 2>;
 648                         clock-names = "apb_pclk";
 649                 };
 650
 651                 gpio18: gpio@f702e000 {
 652                         compatible = "arm,pl061", "arm,primecell";
 653                         reg = <0x0 0xf702e000 0x0 0x1000>;
 654                         interrupts = <0 70 0x4>;
 655                         gpio-controller;
 656                         #gpio-cells = <2>;
 657                         gpio-ranges = <&pmx0 0 143 8>;
 658                         interrupt-controller;
 659                         #interrupt-cells = <2>;
 660                         clocks = <&ao_ctrl 2>;
 661                         clock-names = "apb_pclk";
 662                 };
 663
 664                 gpio19: gpio@f702f000 {
 665                         compatible = "arm,pl061", "arm,primecell";
 666                         reg = <0x0 0xf702f000 0x0 0x1000>;
 667                         interrupts = <0 71 0x4>;
 668                         gpio-controller;
 669                         #gpio-cells = <2>;
 670                         gpio-ranges = <&pmx0 0 151 8>;
 671                         interrupt-controller;
 672                         #interrupt-cells = <2>;
 673                         clocks = <&ao_ctrl 2>;
 674                         clock-names = "apb_pclk";
 675                 };
 676
 677                 spi0: spi@f7106000 {
 678                         compatible = "arm,pl022", "arm,primecell";
 679                         reg = <0x0 0xf7106000 0x0 0x1000>;
 680                         interrupts = <0 50 4>;
 681                         bus-id = <0>;
 682                         enable-dma = <0>;
 683                         clocks = <&sys_ctrl HI6220_SPI_CLK>;
 684                         clock-names = "apb_pclk";
 685                         pinctrl-names = "default";
 686                         pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 687                         num-cs = <1>;
 688                         cs-gpios = <&gpio6 2 0>;
 689                         status = "disabled";
 690                 };
 691
 692                 i2c0: i2c@f7100000 {
 693                         compatible = "snps,designware-i2c";
 694                         reg = <0x0 0xf7100000 0x0 0x1000>;
 695                         interrupts = <0 44 4>;
 696                         clocks = <&sys_ctrl HI6220_I2C0_CLK>;
 697                         i2c-sda-hold-time-ns = <300>;
 698                         pinctrl-names = "default";
 699                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 700                         status = "disabled";
 701                 };
 702
 703                 i2c1: i2c@f7101000 {
 704                         compatible = "snps,designware-i2c";
 705                         reg = <0x0 0xf7101000 0x0 0x1000>;
 706                         clocks = <&sys_ctrl HI6220_I2C1_CLK>;
 707                         interrupts = <0 45 4>;
 708                         i2c-sda-hold-time-ns = <300>;
 709                         pinctrl-names = "default";
 710                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 711                         status = "disabled";
 712                 };
 713
 714                 i2c2: i2c@f7102000 {
 715                         compatible = "snps,designware-i2c";
 716                         reg = <0x0 0xf7102000 0x0 0x1000>;
 717                         clocks = <&sys_ctrl HI6220_I2C2_CLK>;
 718                         interrupts = <0 46 4>;
 719                         i2c-sda-hold-time-ns = <300>;
 720                         pinctrl-names = "default";
 721                         pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
 722                         status = "disabled";
 723                 };
 724
 725                 fixed_5v_hub: regulator@0 {
 726                         compatible = "regulator-fixed";
 727                         regulator-name = "fixed_5v_hub";
 728                         regulator-min-microvolt = <5000000>;
 729                         regulator-max-microvolt = <5000000>;
 730                         regulator-boot-on;
 731                         gpio = <&gpio0 7 0>;
 732                         regulator-always-on;
 733                 };
 734
 735                 usb_phy: usbphy {
 736                         compatible = "hisilicon,hi6220-usb-phy";
 737                         #phy-cells = <0>;
 738                         phy-supply = <&fixed_5v_hub>;
 739                         hisilicon,peripheral-syscon = <&sys_ctrl>;
 740                 };
 741
 742                 usb: usb@f72c0000 {
 743                         compatible = "hisilicon,hi6220-usb";
 744                         reg = <0x0 0xf72c0000 0x0 0x40000>;
 745                         phys = <&usb_phy>;
 746                         phy-names = "usb2-phy";
 747                         clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
 748                         clock-names = "otg";
 749                         dr_mode = "otg";
 750                         g-use-dma;
 751                         g-rx-fifo-size = <512>;
 752                         g-np-tx-fifo-size = <128>;
 753                         g-tx-fifo-size = <128 128 128 128 128 128>;
 754                         interrupts = <0 77 0x4>;
 755                 };
 756
 757                 mailbox: mailbox@f7510000 {
 758                         compatible = "hisilicon,hi6220-mbox";
 759                         reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
 760                               <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
 761                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 762                         #mbox-cells = <3>;
 763                 };
 764
 765                 dwmmc_0: dwmmc0@f723d000 {
 766                         compatible = "hisilicon,hi6220-dw-mshc";
 767                         num-slots = <0x1>;
 768                         cap-mmc-highspeed;
 769                         non-removable;
 770                         reg = <0x0 0xf723d000 0x0 0x1000>;
 771                         interrupts = <0x0 0x48 0x4>;
 772                         clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 773                         clock-names = "ciu", "biu";
 774                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
 775                         bus-width = <0x8>;
 776                         vmmc-supply = <&ldo19>;
 777                         pinctrl-names = "default";
 778                         pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
 779                                      &emmc_cfg_func &emmc_rst_cfg_func>;
 780                 };
 781
 782                 dwmmc_1: dwmmc1@f723e000 {
 783                         compatible = "hisilicon,hi6220-dw-mshc";
 784                         num-slots = <0x1>;
 785                         card-detect-delay = <200>;
 786                         hisilicon,peripheral-syscon = <&ao_ctrl>;
 787                         cap-sd-highspeed;
 788                         sd-uhs-sdr12;
 789                         sd-uhs-sdr25;
 790                         sd-uhs-sdr50;
 791                         reg = <0x0 0xf723e000 0x0 0x1000>;
 792                         interrupts = <0x0 0x49 0x4>;
 793                         #address-cells = <0x1>;
 794                         #size-cells = <0x0>;
 795                         clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 796                         clock-names = "ciu", "biu";
 797                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
 798                         vqmmc-supply = <&ldo7>;
 799                         vmmc-supply = <&ldo10>;
 800                         bus-width = <0x4>;
 801                         disable-wp;
 802                         cd-gpios = <&gpio1 0 1>;
 803                         pinctrl-names = "default", "idle";
 804                         pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
 805                         pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
 806                 };
 807
 808                 dwmmc_2: dwmmc2@f723f000 {
 809                         compatible = "hisilicon,hi6220-dw-mshc";
 810                         num-slots = <0x1>;
 811                         reg = <0x0 0xf723f000 0x0 0x1000>;
 812                         interrupts = <0x0 0x4a 0x4>;
 813                         clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 814                         clock-names = "ciu", "biu";
 815                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
 816                         bus-width = <0x4>;
 817                         broken-cd;
 818                         pinctrl-names = "default", "idle";
 819                         pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
 820                         pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
 821                 };
 822
 823                 tsensor: tsensor@0,f7030700 {
 824                         compatible = "hisilicon,tsensor";
 825                         reg = <0x0 0xf7030700 0x0 0x1000>;
 826                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 827                         clocks = <&sys_ctrl 22>;
 828                         clock-names = "thermal_clk";
 829                         #thermal-sensor-cells = <1>;
 830                 };
 831
 832                 thermal-zones {
 833
 834                         cls0: cls0 {
 835                                 polling-delay = <1000>;
 836                                 polling-delay-passive = <100>;
 837                                 sustainable-power = <3326>;
 838
 839                                 /* sensor ID */
 840                                 thermal-sensors = <&tsensor 2>;
 841
 842                                 trips {
 843                                         threshold: trip-point@0 {
 844                                                 temperature = <65000>;
 845                                                 hysteresis = <0>;
 846                                                 type = "passive";
 847                                         };
 848
 849                                         target: trip-point@1 {
 850                                                 temperature = <75000>;
 851                                                 hysteresis = <0>;
 852                                                 type = "passive";
 853                                         };
 854                                 };
 855
 856                                 cooling-maps {
 857                                         map0 {
 858                                                 trip = <&target>;
 859                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 860                                         };
 861                                 };
 862                         };
 863                 };
 864
 865                 ade: ade@f4100000 {
 866                         compatible = "hisilicon,hi6220-ade";
 867                         reg = <0x0 0xf4100000 0x0 0x7800>;
 868                         reg-names = "ade_base";
 869                         hisilicon,noc-syscon = <&medianoc_ade>;
 870                         resets = <&media_ctrl MEDIA_ADE>;
 871                         interrupts = <0 115 4>; /* ldi interrupt */
 872
 873                         clocks = <&media_ctrl HI6220_ADE_CORE>,
 874                                  <&media_ctrl HI6220_CODEC_JPEG>,
 875                                  <&media_ctrl HI6220_ADE_PIX_SRC>;
 876                         /*clock name*/
 877                         clock-names  = "clk_ade_core",
 878                                        "clk_codec_jpeg",
 879                                        "clk_ade_pix";
 880
 881                         assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
 882                                 <&media_ctrl HI6220_CODEC_JPEG>;
 883                         assigned-clock-rates = <360000000>, <288000000>;
 884                         dma-coherent;
 885                         status = "disabled";
 886
 887                         port {
 888                                 ade_out: endpoint {
 889                                         remote-endpoint = <&dsi_in>;
 890                                 };
 891                         };
 892                 };
 893
 894                 dsi: dsi@f4107800 {
 895                         compatible = "hisilicon,hi6220-dsi";
 896                         reg = <0x0 0xf4107800 0x0 0x100>;
 897                         clocks = <&media_ctrl  HI6220_DSI_PCLK>;
 898                         clock-names = "pclk";
 899                         status = "disabled";
 900
 901                         ports {
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904
 905                                 /* 0 for input port */
 906                                 port@0 {
 907                                         reg = <0>;
 908                                         dsi_in: endpoint {
 909                                                 remote-endpoint = <&ade_out>;
 910                                         };
 911                                 };
 912                         };
 913                 };
 914         };
 915 };