arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <asm/irq_regs.h>
  23 #include <asm/perf_event.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/virt.h>
  26
  27 #include <linux/acpi.h>
  28 #include <linux/of.h>
  29 #include <linux/perf/arm_pmu.h>
  30 #include <linux/platform_device.h>
  31
  32 /*
  33  * ARMv8 PMUv3 Performance Events handling code.
  34  * Common event types.
  35  */
  36
  37 /* Required events. */
  38 #define ARMV8_PMUV3_PERFCTR_SW_INCR                             0x00
  39 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL                    0x03
  40 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE                           0x04
  41 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED                         0x10
  42 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES                          0x11
  43 #define ARMV8_PMUV3_PERFCTR_BR_PRED                             0x12
  44
  45 /* At least one of the following is required. */
  46 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED                        0x08
  47 #define ARMV8_PMUV3_PERFCTR_INST_SPEC                           0x1B
  48
  49 /* Common architectural events. */
  50 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED                          0x06
  51 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED                          0x07
  52 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x09
  53 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN                          0x0A
  54 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED                   0x0B
  55 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED                    0x0C
  56 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED                    0x0D
  57 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED                   0x0E
  58 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED              0x0F
  59 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED                  0x1C
  60 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x1E
  61 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x21
  62
  63 /* Common microarchitectural events. */
  64 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL                    0x01
  65 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL                      0x02
  66 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL                      0x05
  67 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x13
  68 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE                           0x14
  69 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB                        0x15
  70 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE                           0x16
  71 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL                    0x17
  72 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB                        0x18
  73 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x19
  74 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR                        0x1A
  75 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x1D
  76 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x1F
  77 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x20
  78 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x22
  79 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x23
  80 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x24
  81 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x25
  82 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x26
  83 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x27
  84 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x28
  85 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x29
  86 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x2A
  87 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x2B
  88 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x2C
  89 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x2D
  90 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL                      0x2E
  91 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x2F
  92 #define ARMV8_PMUV3_PERFCTR_L2I_TLB                             0x30
  93
  94 /* ARMv8 recommended implementation defined event types */
  95 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD                       0x40
  96 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                       0x41
  97 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD                0x42
  98 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR                0x43
  99 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER             0x44
 100 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER             0x45
 101 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM                0x46
 102 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                 0x47
 103 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                    0x48
 104
 105 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                  0x4C
 106 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                  0x4D
 107 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                         0x4E
 108 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                         0x4F
 109 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                       0x50
 110 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                       0x51
 111 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD                0x52
 112 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR                0x53
 113
 114 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM                0x56
 115 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                 0x57
 116 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                    0x58
 117
 118 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                  0x5C
 119 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                  0x5D
 120 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                         0x5E
 121 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                         0x5F
 122
 123 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                      0x60
 124 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                      0x61
 125 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                  0x62
 126 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED              0x63
 127 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                  0x64
 128 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                  0x65
 129
 130 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                      0x66
 131 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                      0x67
 132 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                  0x68
 133 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                  0x69
 134 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC                0x6A
 135
 136 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                         0x6C
 137 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                    0x6D
 138 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                    0x6E
 139 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                         0x6F
 140 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC                            0x70
 141 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC                            0x71
 142 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                          0x72
 143 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC                            0x73
 144 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                           0x74
 145 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                           0x75
 146 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                      0x76
 147 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                        0x77
 148 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                      0x78
 149 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                     0x79
 150 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                   0x7A
 151
 152 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                           0x7C
 153 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                           0x7D
 154 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                           0x7E
 155
 156 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                          0x81
 157 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC                            0x82
 158 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                         0x83
 159 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                         0x84
 160
 161 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                            0x86
 162 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                            0x87
 163 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC                            0x88
 164
 165 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC                            0x8A
 166 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                    0x8B
 167 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                    0x8C
 168 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                     0x8D
 169 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                       0x8E
 170 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                       0x8F
 171 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                         0x90
 172 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                         0x91
 173
 174 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                       0xA0
 175 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                       0xA1
 176 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD                0xA2
 177 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR                0xA3
 178
 179 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM                0xA6
 180 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                 0xA7
 181 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                    0xA8
 182
 183 /* ARMv8 Cortex-A53 specific event types. */
 184 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
 185
 186 /* ARMv8 Cavium ThunderX specific event types. */
 187 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
 188 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
 189 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
 190 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
 191 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
 192
 193 /* PMUv3 HW events mapping. */
 194
 195 /*
 196  * ARMv8 Architectural defined events, not all of these may
 197  * be supported on any given implementation. Undefined events will
 198  * be disabled at run-time.
 199  */
 200 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 201         PERF_MAP_ALL_UNSUPPORTED,
 202         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 203         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 204         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 205         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 206         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 207         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 208         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 209         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 210         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 211 };
 212
 213 /* ARM Cortex-A53 HW events mapping. */
 214 static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
 215         PERF_MAP_ALL_UNSUPPORTED,
 216         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 217         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 218         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 219         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 220         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 221         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 222         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 223 };
 224
 225 /* ARM Cortex-A57 and Cortex-A72 events mapping. */
 226 static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
 227         PERF_MAP_ALL_UNSUPPORTED,
 228         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 229         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 230         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 231         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 232         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 233         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 234 };
 235
 236 static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
 237         PERF_MAP_ALL_UNSUPPORTED,
 238         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 239         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 240         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 241         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 242         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 243         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 244         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 245         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 246 };
 247
 248 /* Broadcom Vulcan events mapping */
 249 static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {
 250         PERF_MAP_ALL_UNSUPPORTED,
 251         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 252         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 253         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 254         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 255         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_BR_RETIRED,
 256         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 257         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 258         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 259         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 260 };
 261
 262 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 263                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 264                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 265         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 266
 267         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 268         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 269         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 270         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 271
 272         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 273         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 274
 275         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
 276         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
 277
 278         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 279         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
 280
 281         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 282         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 283         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 284         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 285 };
 286
 287 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 288                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 289                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 290         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 291
 292         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 293         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 294         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 295         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 296         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
 297
 298         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 299         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 300
 301         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 302
 303         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 304         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 305         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 306         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 307 };
 308
 309 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 310                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 311                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 312         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 313
 314         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 315         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 316         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 317         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 318
 319         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 320         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 321
 322         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 323         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 324
 325         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 326
 327         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 328         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 329         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 330         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 331 };
 332
 333 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 334                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 335                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 336         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 337
 338         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 339         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 340         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 341         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 342         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 343         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 344
 345         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 346         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 347         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 348         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 349
 350         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 351         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 352         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 353         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 354
 355         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 356
 357         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 358         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 359         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 360         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 361 };
 362
 363 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 364                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 365                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 366         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 367
 368         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 369         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 370         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 371         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 372
 373         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 374         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 375
 376         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 377         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
 378
 379         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 380         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 381         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 382         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 383
 384         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 385         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 386         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 387         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 388
 389         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 390         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 391 };
 392
 393 static ssize_t
 394 armv8pmu_events_sysfs_show(struct device *dev,
 395                            struct device_attribute *attr, char *page)
 396 {
 397         struct perf_pmu_events_attr *pmu_attr;
 398
 399         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 400
 401         return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
 402 }
 403
 404 #define ARMV8_EVENT_ATTR_RESOLVE(m) #m
 405 #define ARMV8_EVENT_ATTR(name, config) \
 406         PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
 407                        config, armv8pmu_events_sysfs_show)
 408
 409 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
 410 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
 411 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
 412 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
 413 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
 414 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
 415 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
 416 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
 417 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
 418 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
 419 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
 420 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
 421 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
 422 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
 423 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
 424 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
 425 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
 426 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
 427 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
 428 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
 429 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
 430 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
 431 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
 432 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
 433 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
 434 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
 435 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
 436 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
 437 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
 438 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
 439 /* Don't expose the chain event in /sys, since it's useless in isolation */
 440 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
 441 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
 442 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
 443 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
 444 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
 445 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
 446 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
 447 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
 448 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
 449 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
 450 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
 451 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
 452 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
 453 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
 454 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
 455 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
 456 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
 457 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
 458
 459 static struct attribute *armv8_pmuv3_event_attrs[] = {
 460         &armv8_event_attr_sw_incr.attr.attr,
 461         &armv8_event_attr_l1i_cache_refill.attr.attr,
 462         &armv8_event_attr_l1i_tlb_refill.attr.attr,
 463         &armv8_event_attr_l1d_cache_refill.attr.attr,
 464         &armv8_event_attr_l1d_cache.attr.attr,
 465         &armv8_event_attr_l1d_tlb_refill.attr.attr,
 466         &armv8_event_attr_ld_retired.attr.attr,
 467         &armv8_event_attr_st_retired.attr.attr,
 468         &armv8_event_attr_inst_retired.attr.attr,
 469         &armv8_event_attr_exc_taken.attr.attr,
 470         &armv8_event_attr_exc_return.attr.attr,
 471         &armv8_event_attr_cid_write_retired.attr.attr,
 472         &armv8_event_attr_pc_write_retired.attr.attr,
 473         &armv8_event_attr_br_immed_retired.attr.attr,
 474         &armv8_event_attr_br_return_retired.attr.attr,
 475         &armv8_event_attr_unaligned_ldst_retired.attr.attr,
 476         &armv8_event_attr_br_mis_pred.attr.attr,
 477         &armv8_event_attr_cpu_cycles.attr.attr,
 478         &armv8_event_attr_br_pred.attr.attr,
 479         &armv8_event_attr_mem_access.attr.attr,
 480         &armv8_event_attr_l1i_cache.attr.attr,
 481         &armv8_event_attr_l1d_cache_wb.attr.attr,
 482         &armv8_event_attr_l2d_cache.attr.attr,
 483         &armv8_event_attr_l2d_cache_refill.attr.attr,
 484         &armv8_event_attr_l2d_cache_wb.attr.attr,
 485         &armv8_event_attr_bus_access.attr.attr,
 486         &armv8_event_attr_memory_error.attr.attr,
 487         &armv8_event_attr_inst_spec.attr.attr,
 488         &armv8_event_attr_ttbr_write_retired.attr.attr,
 489         &armv8_event_attr_bus_cycles.attr.attr,
 490         &armv8_event_attr_l1d_cache_allocate.attr.attr,
 491         &armv8_event_attr_l2d_cache_allocate.attr.attr,
 492         &armv8_event_attr_br_retired.attr.attr,
 493         &armv8_event_attr_br_mis_pred_retired.attr.attr,
 494         &armv8_event_attr_stall_frontend.attr.attr,
 495         &armv8_event_attr_stall_backend.attr.attr,
 496         &armv8_event_attr_l1d_tlb.attr.attr,
 497         &armv8_event_attr_l1i_tlb.attr.attr,
 498         &armv8_event_attr_l2i_cache.attr.attr,
 499         &armv8_event_attr_l2i_cache_refill.attr.attr,
 500         &armv8_event_attr_l3d_cache_allocate.attr.attr,
 501         &armv8_event_attr_l3d_cache_refill.attr.attr,
 502         &armv8_event_attr_l3d_cache.attr.attr,
 503         &armv8_event_attr_l3d_cache_wb.attr.attr,
 504         &armv8_event_attr_l2d_tlb_refill.attr.attr,
 505         &armv8_event_attr_l2i_tlb_refill.attr.attr,
 506         &armv8_event_attr_l2d_tlb.attr.attr,
 507         &armv8_event_attr_l2i_tlb.attr.attr,
 508         NULL,
 509 };
 510
 511 static umode_t
 512 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 513                                struct attribute *attr, int unused)
 514 {
 515         struct device *dev = kobj_to_dev(kobj);
 516         struct pmu *pmu = dev_get_drvdata(dev);
 517         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 518         struct perf_pmu_events_attr *pmu_attr;
 519
 520         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 521
 522         if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 523                 return attr->mode;
 524
 525         return 0;
 526 }
 527
 528 static struct attribute_group armv8_pmuv3_events_attr_group = {
 529         .name = "events",
 530         .attrs = armv8_pmuv3_event_attrs,
 531         .is_visible = armv8pmu_event_attr_is_visible,
 532 };
 533
 534 PMU_FORMAT_ATTR(event, "config:0-9");
 535
 536 static struct attribute *armv8_pmuv3_format_attrs[] = {
 537         &format_attr_event.attr,
 538         NULL,
 539 };
 540
 541 static struct attribute_group armv8_pmuv3_format_attr_group = {
 542         .name = "format",
 543         .attrs = armv8_pmuv3_format_attrs,
 544 };
 545
 546 /*
 547  * Perf Events' indices
 548  */
 549 #define ARMV8_IDX_CYCLE_COUNTER 0
 550 #define ARMV8_IDX_COUNTER0      1
 551 #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
 552         (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 553
 554 /*
 555  * ARMv8 low level PMU access
 556  */
 557
 558 /*
 559  * Perf Event to low level counters mapping
 560  */
 561 #define ARMV8_IDX_TO_COUNTER(x) \
 562         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 563
 564 static inline u32 armv8pmu_pmcr_read(void)
 565 {
 566         return read_sysreg(pmcr_el0);
 567 }
 568
 569 static inline void armv8pmu_pmcr_write(u32 val)
 570 {
 571         val &= ARMV8_PMU_PMCR_MASK;
 572         isb();
 573         write_sysreg(val, pmcr_el0);
 574 }
 575
 576 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 577 {
 578         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 579 }
 580
 581 static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
 582 {
 583         return idx >= ARMV8_IDX_CYCLE_COUNTER &&
 584                 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
 585 }
 586
 587 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 588 {
 589         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 590 }
 591
 592 static inline int armv8pmu_select_counter(int idx)
 593 {
 594         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 595         write_sysreg(counter, pmselr_el0);
 596         isb();
 597
 598         return idx;
 599 }
 600
 601 static inline u32 armv8pmu_read_counter(struct perf_event *event)
 602 {
 603         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 604         struct hw_perf_event *hwc = &event->hw;
 605         int idx = hwc->idx;
 606         u32 value = 0;
 607
 608         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 609                 pr_err("CPU%u reading wrong counter %d\n",
 610                         smp_processor_id(), idx);
 611         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 612                 value = read_sysreg(pmccntr_el0);
 613         else if (armv8pmu_select_counter(idx) == idx)
 614                 value = read_sysreg(pmxevcntr_el0);
 615
 616         return value;
 617 }
 618
 619 static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
 620 {
 621         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 622         struct hw_perf_event *hwc = &event->hw;
 623         int idx = hwc->idx;
 624
 625         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 626                 pr_err("CPU%u writing wrong counter %d\n",
 627                         smp_processor_id(), idx);
 628         else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
 629                 /*
 630                  * Set the upper 32bits as this is a 64bit counter but we only
 631                  * count using the lower 32bits and we want an interrupt when
 632                  * it overflows.
 633                  */
 634                 u64 value64 = 0xffffffff00000000ULL | value;
 635
 636                 write_sysreg(value64, pmccntr_el0);
 637         } else if (armv8pmu_select_counter(idx) == idx)
 638                 write_sysreg(value, pmxevcntr_el0);
 639 }
 640
 641 static inline void armv8pmu_write_evtype(int idx, u32 val)
 642 {
 643         if (armv8pmu_select_counter(idx) == idx) {
 644                 val &= ARMV8_PMU_EVTYPE_MASK;
 645                 write_sysreg(val, pmxevtyper_el0);
 646         }
 647 }
 648
 649 static inline int armv8pmu_enable_counter(int idx)
 650 {
 651         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 652         write_sysreg(BIT(counter), pmcntenset_el0);
 653         return idx;
 654 }
 655
 656 static inline int armv8pmu_disable_counter(int idx)
 657 {
 658         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 659         write_sysreg(BIT(counter), pmcntenclr_el0);
 660         return idx;
 661 }
 662
 663 static inline int armv8pmu_enable_intens(int idx)
 664 {
 665         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 666         write_sysreg(BIT(counter), pmintenset_el1);
 667         return idx;
 668 }
 669
 670 static inline int armv8pmu_disable_intens(int idx)
 671 {
 672         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 673         write_sysreg(BIT(counter), pmintenclr_el1);
 674         isb();
 675         /* Clear the overflow flag in case an interrupt is pending. */
 676         write_sysreg(BIT(counter), pmovsclr_el0);
 677         isb();
 678
 679         return idx;
 680 }
 681
 682 static inline u32 armv8pmu_getreset_flags(void)
 683 {
 684         u32 value;
 685
 686         /* Read */
 687         value = read_sysreg(pmovsclr_el0);
 688
 689         /* Write to clear flags */
 690         value &= ARMV8_PMU_OVSR_MASK;
 691         write_sysreg(value, pmovsclr_el0);
 692
 693         return value;
 694 }
 695
 696 static void armv8pmu_enable_event(struct perf_event *event)
 697 {
 698         unsigned long flags;
 699         struct hw_perf_event *hwc = &event->hw;
 700         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 701         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 702         int idx = hwc->idx;
 703
 704         /*
 705          * Enable counter and interrupt, and set the counter to count
 706          * the event that we're interested in.
 707          */
 708         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 709
 710         /*
 711          * Disable counter
 712          */
 713         armv8pmu_disable_counter(idx);
 714
 715         /*
 716          * Set event (if destined for PMNx counters).
 717          */
 718         armv8pmu_write_evtype(idx, hwc->config_base);
 719
 720         /*
 721          * Enable interrupt for this counter
 722          */
 723         armv8pmu_enable_intens(idx);
 724
 725         /*
 726          * Enable counter
 727          */
 728         armv8pmu_enable_counter(idx);
 729
 730         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 731 }
 732
 733 static void armv8pmu_disable_event(struct perf_event *event)
 734 {
 735         unsigned long flags;
 736         struct hw_perf_event *hwc = &event->hw;
 737         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 738         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 739         int idx = hwc->idx;
 740
 741         /*
 742          * Disable counter and interrupt
 743          */
 744         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 745
 746         /*
 747          * Disable counter
 748          */
 749         armv8pmu_disable_counter(idx);
 750
 751         /*
 752          * Disable interrupt for this counter
 753          */
 754         armv8pmu_disable_intens(idx);
 755
 756         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 757 }
 758
 759 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
 760 {
 761         u32 pmovsr;
 762         struct perf_sample_data data;
 763         struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
 764         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 765         struct pt_regs *regs;
 766         int idx;
 767
 768         /*
 769          * Get and reset the IRQ flags
 770          */
 771         pmovsr = armv8pmu_getreset_flags();
 772
 773         /*
 774          * Did an overflow occur?
 775          */
 776         if (!armv8pmu_has_overflowed(pmovsr))
 777                 return IRQ_NONE;
 778
 779         /*
 780          * Handle the counter(s) overflow(s)
 781          */
 782         regs = get_irq_regs();
 783
 784         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 785                 struct perf_event *event = cpuc->events[idx];
 786                 struct hw_perf_event *hwc;
 787
 788                 /* Ignore if we don't have an event. */
 789                 if (!event)
 790                         continue;
 791
 792                 /*
 793                  * We have a single interrupt for all counters. Check that
 794                  * each counter has overflowed before we process it.
 795                  */
 796                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 797                         continue;
 798
 799                 hwc = &event->hw;
 800                 armpmu_event_update(event);
 801                 perf_sample_data_init(&data, 0, hwc->last_period);
 802                 if (!armpmu_event_set_period(event))
 803                         continue;
 804
 805                 if (perf_event_overflow(event, &data, regs))
 806                         cpu_pmu->disable(event);
 807         }
 808
 809         /*
 810          * Handle the pending perf events.
 811          *
 812          * Note: this call *must* be run with interrupts disabled. For
 813          * platforms that can have the PMU interrupts raised as an NMI, this
 814          * will not work.
 815          */
 816         irq_work_run();
 817
 818         return IRQ_HANDLED;
 819 }
 820
 821 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 822 {
 823         unsigned long flags;
 824         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 825
 826         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 827         /* Enable all counters */
 828         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 829         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 830 }
 831
 832 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 833 {
 834         unsigned long flags;
 835         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 836
 837         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 838         /* Disable all counters */
 839         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 840         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 841 }
 842
 843 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 844                                   struct perf_event *event)
 845 {
 846         int idx;
 847         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 848         struct hw_perf_event *hwc = &event->hw;
 849         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 850
 851         /* Always place a cycle counter into the cycle counter. */
 852         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 853                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 854                         return -EAGAIN;
 855
 856                 return ARMV8_IDX_CYCLE_COUNTER;
 857         }
 858
 859         /*
 860          * For anything other than a cycle counter, try and use
 861          * the events counters
 862          */
 863         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
 864                 if (!test_and_set_bit(idx, cpuc->used_mask))
 865                         return idx;
 866         }
 867
 868         /* The counters are all in use. */
 869         return -EAGAIN;
 870 }
 871
 872 /*
 873  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
 874  */
 875 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 876                                      struct perf_event_attr *attr)
 877 {
 878         unsigned long config_base = 0;
 879
 880         if (attr->exclude_idle)
 881                 return -EPERM;
 882         if (is_kernel_in_hyp_mode() &&
 883             attr->exclude_kernel != attr->exclude_hv)
 884                 return -EINVAL;
 885         if (attr->exclude_user)
 886                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 887         if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
 888                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 889         if (!attr->exclude_hv)
 890                 config_base |= ARMV8_PMU_INCLUDE_EL2;
 891
 892         /*
 893          * Install the filter into config_base as this is used to
 894          * construct the event type.
 895          */
 896         event->config_base = config_base;
 897
 898         return 0;
 899 }
 900
 901 static void armv8pmu_reset(void *info)
 902 {
 903         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 904         u32 idx, nb_cnt = cpu_pmu->num_events;
 905
 906         /* The counter and interrupt enable registers are unknown at reset. */
 907         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
 908                 armv8pmu_disable_counter(idx);
 909                 armv8pmu_disable_intens(idx);
 910         }
 911
 912         /*
 913          * Initialize & Reset PMNC. Request overflow interrupt for
 914          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 915          */
 916         armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
 917                             ARMV8_PMU_PMCR_LC);
 918 }
 919
 920 static int armv8_pmuv3_map_event(struct perf_event *event)
 921 {
 922         int hw_event_id;
 923         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 924
 925         hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
 926                                        &armv8_pmuv3_perf_cache_map,
 927                                        ARMV8_PMU_EVTYPE_EVENT);
 928         if (hw_event_id < 0)
 929                 return hw_event_id;
 930
 931         /* disable micro/arch events not supported by this PMU */
 932         if ((hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) &&
 933                 !test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
 934                         return -EOPNOTSUPP;
 935         }
 936
 937         return hw_event_id;
 938 }
 939
 940 static int armv8_a53_map_event(struct perf_event *event)
 941 {
 942         return armpmu_map_event(event, &armv8_a53_perf_map,
 943                                 &armv8_a53_perf_cache_map,
 944                                 ARMV8_PMU_EVTYPE_EVENT);
 945 }
 946
 947 static int armv8_a57_map_event(struct perf_event *event)
 948 {
 949         return armpmu_map_event(event, &armv8_a57_perf_map,
 950                                 &armv8_a57_perf_cache_map,
 951                                 ARMV8_PMU_EVTYPE_EVENT);
 952 }
 953
 954 static int armv8_thunder_map_event(struct perf_event *event)
 955 {
 956         return armpmu_map_event(event, &armv8_thunder_perf_map,
 957                                 &armv8_thunder_perf_cache_map,
 958                                 ARMV8_PMU_EVTYPE_EVENT);
 959 }
 960
 961 static int armv8_vulcan_map_event(struct perf_event *event)
 962 {
 963         return armpmu_map_event(event, &armv8_vulcan_perf_map,
 964                                 &armv8_vulcan_perf_cache_map,
 965                                 ARMV8_PMU_EVTYPE_EVENT);
 966 }
 967
 968 static void __armv8pmu_probe_pmu(void *info)
 969 {
 970         struct arm_pmu *cpu_pmu = info;
 971         u32 pmceid[2];
 972
 973         /* Read the nb of CNTx counters supported from PMNC */
 974         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
 975                 & ARMV8_PMU_PMCR_N_MASK;
 976
 977         /* Add the CPU cycles counter */
 978         cpu_pmu->num_events += 1;
 979
 980         pmceid[0] = read_sysreg(pmceid0_el0);
 981         pmceid[1] = read_sysreg(pmceid1_el0);
 982
 983         bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
 984                              ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
 985                              ARRAY_SIZE(pmceid));
 986 }
 987
 988 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
 989 {
 990         return smp_call_function_any(&cpu_pmu->supported_cpus,
 991                                     __armv8pmu_probe_pmu,
 992                                     cpu_pmu, 1);
 993 }
 994
 995 static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
 996 {
 997         cpu_pmu->handle_irq             = armv8pmu_handle_irq,
 998         cpu_pmu->enable                 = armv8pmu_enable_event,
 999         cpu_pmu->disable                = armv8pmu_disable_event,
1000         cpu_pmu->read_counter           = armv8pmu_read_counter,
1001         cpu_pmu->write_counter          = armv8pmu_write_counter,
1002         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx,
1003         cpu_pmu->start                  = armv8pmu_start,
1004         cpu_pmu->stop                   = armv8pmu_stop,
1005         cpu_pmu->reset                  = armv8pmu_reset,
1006         cpu_pmu->max_period             = (1LLU << 32) - 1,
1007         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1008 }
1009
1010 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1011 {
1012         armv8_pmu_init(cpu_pmu);
1013         cpu_pmu->name                   = "armv8_pmuv3";
1014         cpu_pmu->map_event              = armv8_pmuv3_map_event;
1015         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1016                 &armv8_pmuv3_events_attr_group;
1017         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1018                 &armv8_pmuv3_format_attr_group;
1019         return armv8pmu_probe_pmu(cpu_pmu);
1020 }
1021
1022 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1023 {
1024         armv8_pmu_init(cpu_pmu);
1025         cpu_pmu->name                   = "armv8_cortex_a53";
1026         cpu_pmu->map_event              = armv8_a53_map_event;
1027         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1028                 &armv8_pmuv3_events_attr_group;
1029         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1030                 &armv8_pmuv3_format_attr_group;
1031         return armv8pmu_probe_pmu(cpu_pmu);
1032 }
1033
1034 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1035 {
1036         armv8_pmu_init(cpu_pmu);
1037         cpu_pmu->name                   = "armv8_cortex_a57";
1038         cpu_pmu->map_event              = armv8_a57_map_event;
1039         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1040                 &armv8_pmuv3_events_attr_group;
1041         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1042                 &armv8_pmuv3_format_attr_group;
1043         return armv8pmu_probe_pmu(cpu_pmu);
1044 }
1045
1046 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1047 {
1048         armv8_pmu_init(cpu_pmu);
1049         cpu_pmu->name                   = "armv8_cortex_a72";
1050         cpu_pmu->map_event              = armv8_a57_map_event;
1051         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1052                 &armv8_pmuv3_events_attr_group;
1053         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1054                 &armv8_pmuv3_format_attr_group;
1055         return armv8pmu_probe_pmu(cpu_pmu);
1056 }
1057
1058 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1059 {
1060         armv8_pmu_init(cpu_pmu);
1061         cpu_pmu->name                   = "armv8_cavium_thunder";
1062         cpu_pmu->map_event              = armv8_thunder_map_event;
1063         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1064                 &armv8_pmuv3_events_attr_group;
1065         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1066                 &armv8_pmuv3_format_attr_group;
1067         return armv8pmu_probe_pmu(cpu_pmu);
1068 }
1069
1070 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1071 {
1072         armv8_pmu_init(cpu_pmu);
1073         cpu_pmu->name                   = "armv8_brcm_vulcan";
1074         cpu_pmu->map_event              = armv8_vulcan_map_event;
1075         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1076                 &armv8_pmuv3_events_attr_group;
1077         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1078                 &armv8_pmuv3_format_attr_group;
1079         return armv8pmu_probe_pmu(cpu_pmu);
1080 }
1081
1082 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1083         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
1084         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1085         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1086         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1087         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1088         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1089         {},
1090 };
1091
1092 /*
1093  * Non DT systems have their micro/arch events probed at run-time.
1094  * A fairly complete list of generic events are provided and ones that
1095  * aren't supported by the current PMU are disabled.
1096  */
1097 static const struct pmu_probe_info armv8_pmu_probe_table[] = {
1098         PMU_PROBE(0, 0, armv8_pmuv3_init), /* enable all defined counters */
1099         { /* sentinel value */ }
1100 };
1101
1102 static int armv8_pmu_device_probe(struct platform_device *pdev)
1103 {
1104         if (acpi_disabled)
1105                 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids,
1106                                             NULL);
1107
1108         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids,
1109                                     armv8_pmu_probe_table);
1110 }
1111
1112 static struct platform_driver armv8_pmu_driver = {
1113         .driver         = {
1114                 .name   = ARMV8_PMU_PDEV_NAME,
1115                 .of_match_table = armv8_pmu_of_device_ids,
1116         },
1117         .probe          = armv8_pmu_device_probe,
1118 };
1119
1120 builtin_platform_driver(armv8_pmu_driver);