3 #include <linux/interrupt.h>
4 #include <linux/module.h>
6 #include <asm/irq_cpu.h>
8 #include <asm/mipsregs.h>
12 unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
14 static void ht_irqdispatch(void)
18 irq = LOONGSON_HT1_INT_VECTOR(0);
19 LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
21 for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
22 if (irq & (0x1 << ht_irq[i]))
27 void mach_irq_dispatch(unsigned int pending)
29 if (pending & CAUSEF_IP7)
30 do_IRQ(LOONGSON_TIMER_IRQ);
31 #if defined(CONFIG_SMP)
32 else if (pending & CAUSEF_IP6)
33 loongson3_ipi_interrupt(NULL);
35 else if (pending & CAUSEF_IP3)
37 else if (pending & CAUSEF_IP2)
38 do_IRQ(LOONGSON_UART_IRQ);
40 pr_err("%s : spurious interrupt\n", __func__);
45 static struct irqaction cascade_irqaction = {
50 static inline void mask_loongson_irq(struct irq_data *d)
52 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
55 /* Workaround: UART IRQ may deliver to any core */
56 if (d->irq == LOONGSON_UART_IRQ) {
57 int cpu = smp_processor_id();
58 int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
59 int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
60 u64 intenclr_addr = smp_group[node_id] |
61 (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
62 u64 introuter_lpc_addr = smp_group[node_id] |
63 (u64)(&LOONGSON_INT_ROUTER_LPC);
65 *(volatile u32 *)intenclr_addr = 1 << 10;
66 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
70 static inline void unmask_loongson_irq(struct irq_data *d)
72 /* Workaround: UART IRQ may deliver to any core */
73 if (d->irq == LOONGSON_UART_IRQ) {
74 int cpu = smp_processor_id();
75 int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
76 int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
77 u64 intenset_addr = smp_group[node_id] |
78 (u64)(&LOONGSON_INT_ROUTER_INTENSET);
79 u64 introuter_lpc_addr = smp_group[node_id] |
80 (u64)(&LOONGSON_INT_ROUTER_LPC);
82 *(volatile u32 *)intenset_addr = 1 << 10;
83 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
86 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
90 /* For MIPS IRQs which shared by all cores */
91 static struct irq_chip loongson_irq_chip = {
93 .irq_ack = mask_loongson_irq,
94 .irq_mask = mask_loongson_irq,
95 .irq_mask_ack = mask_loongson_irq,
96 .irq_unmask = unmask_loongson_irq,
97 .irq_eoi = unmask_loongson_irq,
100 void irq_router_init(void)
104 /* route LPC int to cpu core0 int 0 */
105 LOONGSON_INT_ROUTER_LPC =
106 LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
107 /* route HT1 int0 ~ int7 to cpu core0 INT1*/
108 for (i = 0; i < 8; i++)
109 LOONGSON_INT_ROUTER_HT1(i) =
110 LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
111 /* enable HT1 interrupt */
112 LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
113 /* enable router interrupt intenset */
114 LOONGSON_INT_ROUTER_INTENSET =
115 LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
118 void __init mach_init_irq(void)
120 clear_c0_status(ST0_IM | ST0_BEV);
125 irq_set_chip_and_handler(LOONGSON_UART_IRQ,
126 &loongson_irq_chip, handle_level_irq);
129 setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
131 set_c0_status(STATUSF_IP2 | STATUSF_IP6);
134 #ifdef CONFIG_HOTPLUG_CPU
136 void fixup_irqs(void)
139 clear_c0_status(ST0_IM);