arch/mips/math-emu/ieee754sp.c

   1 /* IEEE754 floating point arithmetic
   2  * single precision
   3  */
   4 /*
   5  * MIPS floating point support
   6  * Copyright (C) 1994-2000 Algorithmics Ltd.
   7  *
   8  *  This program is free software; you can distribute it and/or modify it
   9  *  under the terms of the GNU General Public License (Version 2) as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, write to the Free Software Foundation, Inc.,
  19  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  20  */
  21
  22 #include <linux/compiler.h>
  23
  24 #include "ieee754sp.h"
  25
  26 int ieee754sp_class(union ieee754sp x)
  27 {
  28         COMPXSP;
  29         EXPLODEXSP;
  30         return xc;
  31 }
  32
  33 int ieee754sp_isnan(union ieee754sp x)
  34 {
  35         return ieee754sp_class(x) >= IEEE754_CLASS_SNAN;
  36 }
  37
  38 static inline int ieee754sp_issnan(union ieee754sp x)
  39 {
  40         assert(ieee754sp_isnan(x));
  41         return SPMANT(x) & SP_MBIT(SP_FBITS - 1);
  42 }
  43
  44
  45 union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
  46 {
  47         assert(ieee754sp_isnan(r));
  48
  49         if (!ieee754sp_issnan(r))       /* QNAN does not cause invalid op !! */
  50                 return r;
  51
  52         if (!ieee754_setandtestcx(IEEE754_INVALID_OPERATION)) {
  53                 /* not enabled convert to a quiet NaN */
  54                 SPMANT(r) &= (~SP_MBIT(SP_FBITS-1));
  55                 if (ieee754sp_isnan(r))
  56                         return r;
  57                 else
  58                         return ieee754sp_indef();
  59         }
  60
  61         return r;
  62 }
  63
  64 static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
  65 {
  66         /* inexact must round of 3 bits
  67          */
  68         if (xm & (SP_MBIT(3) - 1)) {
  69                 switch (ieee754_csr.rm) {
  70                 case FPU_CSR_RZ:
  71                         break;
  72                 case FPU_CSR_RN:
  73                         xm += 0x3 + ((xm >> 3) & 1);
  74                         /* xm += (xm&0x8)?0x4:0x3 */
  75                         break;
  76                 case FPU_CSR_RU:        /* toward +Infinity */
  77                         if (!sn)        /* ?? */
  78                                 xm += 0x8;
  79                         break;
  80                 case FPU_CSR_RD:        /* toward -Infinity */
  81                         if (sn) /* ?? */
  82                                 xm += 0x8;
  83                         break;
  84                 }
  85         }
  86         return xm;
  87 }
  88
  89
  90 /* generate a normal/denormal number with over,under handling
  91  * sn is sign
  92  * xe is an unbiased exponent
  93  * xm is 3bit extended precision value.
  94  */
  95 union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
  96 {
  97         assert(xm);             /* we don't gen exact zeros (probably should) */
  98
  99         assert((xm >> (SP_FBITS + 1 + 3)) == 0);        /* no execess */
 100         assert(xm & (SP_HIDDEN_BIT << 3));
 101
 102         if (xe < SP_EMIN) {
 103                 /* strip lower bits */
 104                 int es = SP_EMIN - xe;
 105
 106                 if (ieee754_csr.nod) {
 107                         ieee754_setcx(IEEE754_UNDERFLOW);
 108                         ieee754_setcx(IEEE754_INEXACT);
 109
 110                         switch(ieee754_csr.rm) {
 111                         case FPU_CSR_RN:
 112                         case FPU_CSR_RZ:
 113                                 return ieee754sp_zero(sn);
 114                         case FPU_CSR_RU:      /* toward +Infinity */
 115                                 if (sn == 0)
 116                                         return ieee754sp_min(0);
 117                                 else
 118                                         return ieee754sp_zero(1);
 119                         case FPU_CSR_RD:      /* toward -Infinity */
 120                                 if (sn == 0)
 121                                         return ieee754sp_zero(0);
 122                                 else
 123                                         return ieee754sp_min(1);
 124                         }
 125                 }
 126
 127                 if (xe == SP_EMIN - 1 &&
 128                     ieee754sp_get_rounding(sn, xm) >> (SP_FBITS + 1 + 3))
 129                 {
 130                         /* Not tiny after rounding */
 131                         ieee754_setcx(IEEE754_INEXACT);
 132                         xm = ieee754sp_get_rounding(sn, xm);
 133                         xm >>= 1;
 134                         /* Clear grs bits */
 135                         xm &= ~(SP_MBIT(3) - 1);
 136                         xe++;
 137                 } else {
 138                         /* sticky right shift es bits
 139                          */
 140                         SPXSRSXn(es);
 141                         assert((xm & (SP_HIDDEN_BIT << 3)) == 0);
 142                         assert(xe == SP_EMIN);
 143                 }
 144         }
 145         if (xm & (SP_MBIT(3) - 1)) {
 146                 ieee754_setcx(IEEE754_INEXACT);
 147                 if ((xm & (SP_HIDDEN_BIT << 3)) == 0) {
 148                         ieee754_setcx(IEEE754_UNDERFLOW);
 149                 }
 150
 151                 /* inexact must round of 3 bits
 152                  */
 153                 xm = ieee754sp_get_rounding(sn, xm);
 154                 /* adjust exponent for rounding add overflowing
 155                  */
 156                 if (xm >> (SP_FBITS + 1 + 3)) {
 157                         /* add causes mantissa overflow */
 158                         xm >>= 1;
 159                         xe++;
 160                 }
 161         }
 162         /* strip grs bits */
 163         xm >>= 3;
 164
 165         assert((xm >> (SP_FBITS + 1)) == 0);    /* no execess */
 166         assert(xe >= SP_EMIN);
 167
 168         if (xe > SP_EMAX) {
 169                 ieee754_setcx(IEEE754_OVERFLOW);
 170                 ieee754_setcx(IEEE754_INEXACT);
 171                 /* -O can be table indexed by (rm,sn) */
 172                 switch (ieee754_csr.rm) {
 173                 case FPU_CSR_RN:
 174                         return ieee754sp_inf(sn);
 175                 case FPU_CSR_RZ:
 176                         return ieee754sp_max(sn);
 177                 case FPU_CSR_RU:        /* toward +Infinity */
 178                         if (sn == 0)
 179                                 return ieee754sp_inf(0);
 180                         else
 181                                 return ieee754sp_max(1);
 182                 case FPU_CSR_RD:        /* toward -Infinity */
 183                         if (sn == 0)
 184                                 return ieee754sp_max(0);
 185                         else
 186                                 return ieee754sp_inf(1);
 187                 }
 188         }
 189         /* gen norm/denorm/zero */
 190
 191         if ((xm & SP_HIDDEN_BIT) == 0) {
 192                 /* we underflow (tiny/zero) */
 193                 assert(xe == SP_EMIN);
 194                 if (ieee754_csr.mx & IEEE754_UNDERFLOW)
 195                         ieee754_setcx(IEEE754_UNDERFLOW);
 196                 return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
 197         } else {
 198                 assert((xm >> (SP_FBITS + 1)) == 0);    /* no execess */
 199                 assert(xm & SP_HIDDEN_BIT);
 200
 201                 return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);
 202         }
 203 }