arch/powerpc/boot/dts/fsl/p4080si-post.dtsi

   1 /*
   2  * P4080/P4040 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &lbc {
  36         compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
  37         interrupts = <25 2 0 0>;
  38         #address-cells = <2>;
  39         #size-cells = <1>;
  40 };
  41
  42 /* controller at 0x200000 */
  43 &pci0 {
  44         compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0x0 0xff>;
  49         clock-frequency = <33333333>;
  50         interrupts = <16 2 1 15>;
  51         fsl,iommu-parent = <&pamu0>;
  52         fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  53         pcie@0 {
  54                 reg = <0 0 0 0 0>;
  55                 #interrupt-cells = <1>;
  56                 #size-cells = <2>;
  57                 #address-cells = <3>;
  58                 device_type = "pci";
  59                 interrupts = <16 2 1 15>;
  60                 interrupt-map-mask = <0xf800 0 0 7>;
  61                 interrupt-map = <
  62                         /* IDSEL 0x0 */
  63                         0000 0 0 1 &mpic 40 1 0 0
  64                         0000 0 0 2 &mpic 1 1 0 0
  65                         0000 0 0 3 &mpic 2 1 0 0
  66                         0000 0 0 4 &mpic 3 1 0 0
  67                         >;
  68         };
  69 };
  70
  71 /* controller at 0x201000 */
  72 &pci1 {
  73         compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  74         device_type = "pci";
  75         #size-cells = <2>;
  76         #address-cells = <3>;
  77         bus-range = <0 0xff>;
  78         clock-frequency = <33333333>;
  79         interrupts = <16 2 1 14>;
  80         fsl,iommu-parent = <&pamu0>;
  81         fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  82         pcie@0 {
  83                 reg = <0 0 0 0 0>;
  84                 #interrupt-cells = <1>;
  85                 #size-cells = <2>;
  86                 #address-cells = <3>;
  87                 device_type = "pci";
  88                 interrupts = <16 2 1 14>;
  89                 interrupt-map-mask = <0xf800 0 0 7>;
  90                 interrupt-map = <
  91                         /* IDSEL 0x0 */
  92                         0000 0 0 1 &mpic 41 1 0 0
  93                         0000 0 0 2 &mpic 5 1 0 0
  94                         0000 0 0 3 &mpic 6 1 0 0
  95                         0000 0 0 4 &mpic 7 1 0 0
  96                         >;
  97         };
  98 };
  99
 100 /* controller at 0x202000 */
 101 &pci2 {
 102         compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
 103         device_type = "pci";
 104         #size-cells = <2>;
 105         #address-cells = <3>;
 106         bus-range = <0x0 0xff>;
 107         clock-frequency = <33333333>;
 108         interrupts = <16 2 1 13>;
 109         fsl,iommu-parent = <&pamu0>;
 110         fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
 111         pcie@0 {
 112                 reg = <0 0 0 0 0>;
 113                 #interrupt-cells = <1>;
 114                 #size-cells = <2>;
 115                 #address-cells = <3>;
 116                 device_type = "pci";
 117                 interrupts = <16 2 1 13>;
 118                 interrupt-map-mask = <0xf800 0 0 7>;
 119                 interrupt-map = <
 120                         /* IDSEL 0x0 */
 121                         0000 0 0 1 &mpic 42 1 0 0
 122                         0000 0 0 2 &mpic 9 1 0 0
 123                         0000 0 0 3 &mpic 10 1 0 0
 124                         0000 0 0 4 &mpic 11 1 0 0
 125                         >;
 126         };
 127 };
 128
 129 &rio {
 130         compatible = "fsl,srio";
 131         interrupts = <16 2 1 11>;
 132         #address-cells = <2>;
 133         #size-cells = <2>;
 134         fsl,srio-rmu-handle = <&rmu>;
 135         fsl,iommu-parent = <&pamu0>;
 136         ranges;
 137
 138         port1 {
 139                 #address-cells = <2>;
 140                 #size-cells = <2>;
 141                 cell-index = <1>;
 142                 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
 143         };
 144
 145         port2 {
 146                 #address-cells = <2>;
 147                 #size-cells = <2>;
 148                 cell-index = <2>;
 149                 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
 150         };
 151 };
 152
 153 &dcsr {
 154         #address-cells = <1>;
 155         #size-cells = <1>;
 156         compatible = "fsl,dcsr", "simple-bus";
 157
 158         dcsr-epu@0 {
 159                 compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
 160                 interrupts = <52 2 0 0
 161                               84 2 0 0
 162                               85 2 0 0>;
 163                 reg = <0x0 0x1000>;
 164         };
 165         dcsr-npc {
 166                 compatible = "fsl,dcsr-npc";
 167                 reg = <0x1000 0x1000 0x1000000 0x8000>;
 168         };
 169         dcsr-nxc@2000 {
 170                 compatible = "fsl,dcsr-nxc";
 171                 reg = <0x2000 0x1000>;
 172         };
 173         dcsr-corenet {
 174                 compatible = "fsl,dcsr-corenet";
 175                 reg = <0x8000 0x1000 0xB0000 0x1000>;
 176         };
 177         dcsr-dpaa@9000 {
 178                 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
 179                 reg = <0x9000 0x1000>;
 180         };
 181         dcsr-ocn@11000 {
 182                 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
 183                 reg = <0x11000 0x1000>;
 184         };
 185         dcsr-ddr@12000 {
 186                 compatible = "fsl,dcsr-ddr";
 187                 dev-handle = <&ddr1>;
 188                 reg = <0x12000 0x1000>;
 189         };
 190         dcsr-ddr@13000 {
 191                 compatible = "fsl,dcsr-ddr";
 192                 dev-handle = <&ddr2>;
 193                 reg = <0x13000 0x1000>;
 194         };
 195         dcsr-nal@18000 {
 196                 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
 197                 reg = <0x18000 0x1000>;
 198         };
 199         dcsr-rcpm@22000 {
 200                 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
 201                 reg = <0x22000 0x1000>;
 202         };
 203         dcsr-cpu-sb-proxy@40000 {
 204                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 205                 cpu-handle = <&cpu0>;
 206                 reg = <0x40000 0x1000>;
 207         };
 208         dcsr-cpu-sb-proxy@41000 {
 209                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 210                 cpu-handle = <&cpu1>;
 211                 reg = <0x41000 0x1000>;
 212         };
 213         dcsr-cpu-sb-proxy@42000 {
 214                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 215                 cpu-handle = <&cpu2>;
 216                 reg = <0x42000 0x1000>;
 217         };
 218         dcsr-cpu-sb-proxy@43000 {
 219                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 220                 cpu-handle = <&cpu3>;
 221                 reg = <0x43000 0x1000>;
 222         };
 223         dcsr-cpu-sb-proxy@44000 {
 224                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 225                 cpu-handle = <&cpu4>;
 226                 reg = <0x44000 0x1000>;
 227         };
 228         dcsr-cpu-sb-proxy@45000 {
 229                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 230                 cpu-handle = <&cpu5>;
 231                 reg = <0x45000 0x1000>;
 232         };
 233         dcsr-cpu-sb-proxy@46000 {
 234                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 235                 cpu-handle = <&cpu6>;
 236                 reg = <0x46000 0x1000>;
 237         };
 238         dcsr-cpu-sb-proxy@47000 {
 239                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 240                 cpu-handle = <&cpu7>;
 241                 reg = <0x47000 0x1000>;
 242         };
 243
 244 };
 245
 246 &soc {
 247         #address-cells = <1>;
 248         #size-cells = <1>;
 249         device_type = "soc";
 250         compatible = "simple-bus";
 251
 252         soc-sram-error {
 253                 compatible = "fsl,soc-sram-error";
 254                 interrupts = <16 2 1 29>;
 255         };
 256
 257         corenet-law@0 {
 258                 compatible = "fsl,corenet-law";
 259                 reg = <0x0 0x1000>;
 260                 fsl,num-laws = <32>;
 261         };
 262
 263         ddr1: memory-controller@8000 {
 264                 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
 265                 reg = <0x8000 0x1000>;
 266                 interrupts = <16 2 1 23>;
 267         };
 268
 269         ddr2: memory-controller@9000 {
 270                 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
 271                 reg = <0x9000 0x1000>;
 272                 interrupts = <16 2 1 22>;
 273         };
 274
 275         cpc: l3-cache-controller@10000 {
 276                 compatible = "fsl,p4080-l3-cache-controller", "cache";
 277                 reg = <0x10000 0x1000
 278                        0x11000 0x1000>;
 279                 interrupts = <16 2 1 27
 280                               16 2 1 26>;
 281         };
 282
 283         corenet-cf@18000 {
 284                 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
 285                 reg = <0x18000 0x1000>;
 286                 interrupts = <16 2 1 31>;
 287                 fsl,ccf-num-csdids = <32>;
 288                 fsl,ccf-num-snoopids = <32>;
 289         };
 290
 291         iommu@20000 {
 292                 compatible = "fsl,pamu-v1.0", "fsl,pamu";
 293                 reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
 294                 ranges = <0 0x20000 0x5000>;
 295                 #address-cells = <1>;
 296                 #size-cells = <1>;
 297                 interrupts = <
 298                         24 2 0 0
 299                         16 2 1 30>;
 300                 fsl,portid-mapping = <0x00f80000>;
 301
 302                 pamu0: pamu@0 {
 303                         reg = <0 0x1000>;
 304                         fsl,primary-cache-geometry = <32 1>;
 305                         fsl,secondary-cache-geometry = <128 2>;
 306                 };
 307
 308                 pamu1: pamu@1000 {
 309                         reg = <0x1000 0x1000>;
 310                         fsl,primary-cache-geometry = <32 1>;
 311                         fsl,secondary-cache-geometry = <128 2>;
 312                 };
 313
 314                 pamu2: pamu@2000 {
 315                         reg = <0x2000 0x1000>;
 316                         fsl,primary-cache-geometry = <32 1>;
 317                         fsl,secondary-cache-geometry = <128 2>;
 318                 };
 319
 320                 pamu3: pamu@3000 {
 321                         reg = <0x3000 0x1000>;
 322                         fsl,primary-cache-geometry = <32 1>;
 323                         fsl,secondary-cache-geometry = <128 2>;
 324                 };
 325
 326                 pamu4: pamu@4000 {
 327                         reg = <0x4000 0x1000>;
 328                         fsl,primary-cache-geometry = <32 1>;
 329                         fsl,secondary-cache-geometry = <128 2>;
 330                 };
 331         };
 332
 333 /include/ "qoriq-rmu-0.dtsi"
 334         rmu@d3000 {
 335                 fsl,iommu-parent = <&pamu0>;
 336                 fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */
 337         };
 338
 339 /include/ "qoriq-mpic.dtsi"
 340
 341         guts: global-utilities@e0000 {
 342                 compatible = "fsl,qoriq-device-config-1.0";
 343                 reg = <0xe0000 0xe00>;
 344                 fsl,has-rstcr;
 345                 #sleep-cells = <1>;
 346                 fsl,liodn-bits = <12>;
 347         };
 348
 349         pins: global-utilities@e0e00 {
 350                 compatible = "fsl,qoriq-pin-control-1.0";
 351                 reg = <0xe0e00 0x200>;
 352                 #sleep-cells = <2>;
 353         };
 354
 355 /include/ "qoriq-clockgen1.dtsi"
 356         global-utilities@e1000 {
 357                 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
 358
 359                 pll2: pll2@840 {
 360                         #clock-cells = <1>;
 361                         reg = <0x840 0x4>;
 362                         compatible = "fsl,qoriq-core-pll-1.0";
 363                         clocks = <&sysclk>;
 364                         clock-output-names = "pll2", "pll2-div2";
 365                 };
 366
 367                 pll3: pll3@860 {
 368                         #clock-cells = <1>;
 369                         reg = <0x860 0x4>;
 370                         compatible = "fsl,qoriq-core-pll-1.0";
 371                         clocks = <&sysclk>;
 372                         clock-output-names = "pll3", "pll3-div2";
 373                 };
 374
 375                 mux2: mux2@40 {
 376                         #clock-cells = <0>;
 377                         reg = <0x40 0x4>;
 378                         compatible = "fsl,qoriq-core-mux-1.0";
 379                         clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 380                         clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 381                         clock-output-names = "cmux2";
 382                 };
 383
 384                 mux3: mux3@60 {
 385                         #clock-cells = <0>;
 386                         reg = <0x60 0x4>;
 387                         compatible = "fsl,qoriq-core-mux-1.0";
 388                         clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 389                         clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 390                         clock-output-names = "cmux3";
 391                 };
 392
 393                 mux4: mux4@80 {
 394                         #clock-cells = <0>;
 395                         reg = <0x80 0x4>;
 396                         compatible = "fsl,qoriq-core-mux-1.0";
 397                         clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
 398                         clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 399                         clock-output-names = "cmux4";
 400                 };
 401
 402                 mux5: mux5@a0 {
 403                         #clock-cells = <0>;
 404                         reg = <0xa0 0x4>;
 405                         compatible = "fsl,qoriq-core-mux-1.0";
 406                         clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
 407                         clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 408                         clock-output-names = "cmux5";
 409                 };
 410
 411                 mux6: mux6@c0 {
 412                         #clock-cells = <0>;
 413                         reg = <0xc0 0x4>;
 414                         compatible = "fsl,qoriq-core-mux-1.0";
 415                         clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
 416                         clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 417                         clock-output-names = "cmux6";
 418                 };
 419
 420                 mux7: mux7@e0 {
 421                         #clock-cells = <0>;
 422                         reg = <0xe0 0x4>;
 423                         compatible = "fsl,qoriq-core-mux-1.0";
 424                         clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
 425                         clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 426                         clock-output-names = "cmux7";
 427                 };
 428         };
 429
 430         rcpm: global-utilities@e2000 {
 431                 compatible = "fsl,qoriq-rcpm-1.0";
 432                 reg = <0xe2000 0x1000>;
 433                 #sleep-cells = <1>;
 434         };
 435
 436         sfp: sfp@e8000 {
 437                 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
 438                 reg        = <0xe8000 0x1000>;
 439         };
 440
 441         serdes: serdes@ea000 {
 442                 compatible = "fsl,p4080-serdes";
 443                 reg        = <0xea000 0x1000>;
 444         };
 445
 446 /include/ "qoriq-dma-0.dtsi"
 447         dma@100300 {
 448                 fsl,iommu-parent = <&pamu0>;
 449                 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 450         };
 451
 452 /include/ "qoriq-dma-1.dtsi"
 453         dma@101300 {
 454                 fsl,iommu-parent = <&pamu0>;
 455                 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 456         };
 457
 458 /include/ "qoriq-espi-0.dtsi"
 459         spi@110000 {
 460                 fsl,espi-num-chipselects = <4>;
 461         };
 462
 463 /include/ "qoriq-esdhc-0.dtsi"
 464         sdhc@114000 {
 465                 fsl,iommu-parent = <&pamu1>;
 466                 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
 467                 voltage-ranges = <3300 3300>;
 468                 sdhci,auto-cmd12;
 469         };
 470
 471 /include/ "qoriq-i2c-0.dtsi"
 472 /include/ "qoriq-i2c-1.dtsi"
 473 /include/ "qoriq-duart-0.dtsi"
 474 /include/ "qoriq-duart-1.dtsi"
 475 /include/ "qoriq-gpio-0.dtsi"
 476 /include/ "qoriq-usb2-mph-0.dtsi"
 477         usb@210000 {
 478                 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 479                 fsl,iommu-parent = <&pamu1>;
 480                 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 481                 port0;
 482         };
 483 /include/ "qoriq-usb2-dr-0.dtsi"
 484         usb@211000 {
 485                 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 486                 fsl,iommu-parent = <&pamu1>;
 487                 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
 488         };
 489 /include/ "qoriq-sec4.0-0.dtsi"
 490 crypto: crypto@300000 {
 491                 fsl,iommu-parent = <&pamu1>;
 492         };
 493 };