arch/powerpc/boot/dts/t208xqds.dtsi

   1 /*
   2  * T2080/T2081 QDS Device Tree Source
   3  *
   4  * Copyright 2013 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 / {
  36         model = "fsl,T2080QDS";
  37         compatible = "fsl,T2080QDS";
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40         interrupt-parent = <&mpic>;
  41
  42         ifc: localbus@ffe124000 {
  43                 reg = <0xf 0xfe124000 0 0x2000>;
  44                 ranges = <0 0 0xf 0xe8000000 0x08000000
  45                           2 0 0xf 0xff800000 0x00010000
  46                           3 0 0xf 0xffdf0000 0x00008000>;
  47
  48                 nor@0,0 {
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         compatible = "cfi-flash";
  52                         reg = <0x0 0x0 0x8000000>;
  53                         bank-width = <2>;
  54                         device-width = <1>;
  55                 };
  56
  57                 nand@2,0 {
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         compatible = "fsl,ifc-nand";
  61                         reg = <0x2 0x0 0x10000>;
  62                 };
  63
  64                 boardctrl: board-control@3,0 {
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         compatible = "fsl,fpga-qixis";
  68                         reg = <3 0 0x300>;
  69                         ranges = <0 3 0 0x300>;
  70                 };
  71         };
  72
  73         memory {
  74                 device_type = "memory";
  75         };
  76
  77         dcsr: dcsr@f00000000 {
  78                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
  79         };
  80
  81         soc: soc@ffe000000 {
  82                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  83                 reg = <0xf 0xfe000000 0 0x00001000>;
  84                 spi@110000 {
  85                         flash@0 {
  86                                 #address-cells = <1>;
  87                                 #size-cells = <1>;
  88                                 compatible = "micron,n25q128a11"; /* 16MB */
  89                                 reg = <0>;
  90                                 spi-max-frequency = <40000000>; /* input clock */
  91                         };
  92
  93                         flash@1 {
  94                                 #address-cells = <1>;
  95                                 #size-cells = <1>;
  96                                 compatible = "sst,sst25wf040";
  97                                 reg = <1>;
  98                                 spi-max-frequency = <35000000>;
  99                         };
 100
 101                         flash@2 {
 102                                 #address-cells = <1>;
 103                                 #size-cells = <1>;
 104                                 compatible = "eon,en25s64";
 105                                 reg = <2>;
 106                                 spi-max-frequency = <35000000>;
 107                         };
 108                 };
 109
 110                 i2c@118000 {
 111                         pca9547@77 {
 112                                 compatible = "nxp,pca9547";
 113                                 reg = <0x77>;
 114                                 #address-cells = <1>;
 115                                 #size-cells = <0>;
 116
 117                                 i2c@0 {
 118                                         #address-cells = <1>;
 119                                         #size-cells = <0>;
 120                                         reg = <0x0>;
 121
 122                                         eeprom@50 {
 123                                                 compatible = "at24,24c512";
 124                                                 reg = <0x50>;
 125                                         };
 126
 127                                         eeprom@51 {
 128                                                 compatible = "at24,24c02";
 129                                                 reg = <0x51>;
 130                                         };
 131
 132                                         eeprom@57 {
 133                                                 compatible = "at24,24c02";
 134                                                 reg = <0x57>;
 135                                         };
 136
 137                                         rtc@68 {
 138                                                 compatible = "dallas,ds3232";
 139                                                 reg = <0x68>;
 140                                                 interrupts = <0x1 0x1 0 0>;
 141                                         };
 142                                 };
 143
 144                                 i2c@1 {
 145                                         #address-cells = <1>;
 146                                         #size-cells = <0>;
 147                                         reg = <0x1>;
 148
 149                                         eeprom@55 {
 150                                                 compatible = "at24,24c02";
 151                                                 reg = <0x55>;
 152                                         };
 153                                 };
 154
 155                                 i2c@2 {
 156                                         #address-cells = <1>;
 157                                         #size-cells = <0>;
 158                                         reg = <0x2>;
 159
 160                                         ina220@40 {
 161                                                 compatible = "ti,ina220";
 162                                                 reg = <0x40>;
 163                                                 shunt-resistor = <1000>;
 164                                         };
 165
 166                                         ina220@41 {
 167                                                 compatible = "ti,ina220";
 168                                                 reg = <0x41>;
 169                                                 shunt-resistor = <1000>;
 170                                         };
 171                                 };
 172
 173                                 i2c@3 {
 174                                         #address-cells = <1>;
 175                                         #size-cells = <0>;
 176                                         reg = <0x3>;
 177
 178                                         adt7461@4c {
 179                                                 compatible = "adi,adt7461";
 180                                                 reg = <0x4c>;
 181                                         };
 182                                 };
 183                         };
 184                 };
 185
 186                 sdhc@114000 {
 187                         voltage-ranges = <1800 1800 3300 3300>;
 188                 };
 189         };
 190
 191         pci0: pcie@ffe240000 {
 192                 reg = <0xf 0xfe240000 0 0x10000>;
 193                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 194                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 195                 pcie@0 {
 196                         ranges = <0x02000000 0 0xe0000000
 197                                   0x02000000 0 0xe0000000
 198                                   0 0x20000000
 199
 200                                   0x01000000 0 0x00000000
 201                                   0x01000000 0 0x00000000
 202                                   0 0x00010000>;
 203                 };
 204         };
 205
 206         pci1: pcie@ffe250000 {
 207                 reg = <0xf 0xfe250000 0 0x10000>;
 208                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
 209                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 210                 pcie@0 {
 211                         ranges = <0x02000000 0 0xe0000000
 212                                   0x02000000 0 0xe0000000
 213                                   0 0x20000000
 214
 215                                   0x01000000 0 0x00000000
 216                                   0x01000000 0 0x00000000
 217                                   0 0x00010000>;
 218                 };
 219         };
 220
 221         pci2: pcie@ffe260000 {
 222                 reg = <0xf 0xfe260000 0 0x1000>;
 223                 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
 224                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 225                 pcie@0 {
 226                         ranges = <0x02000000 0 0xe0000000
 227                                   0x02000000 0 0xe0000000
 228                                   0 0x20000000
 229
 230                                   0x01000000 0 0x00000000
 231                                   0x01000000 0 0x00000000
 232                                   0 0x00010000>;
 233                 };
 234         };
 235
 236         pci3: pcie@ffe270000 {
 237                 reg = <0xf 0xfe270000 0 0x10000>;
 238                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
 239                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 240                 pcie@0 {
 241                         ranges = <0x02000000 0 0xe0000000
 242                                   0x02000000 0 0xe0000000
 243                                   0 0x20000000
 244
 245                                   0x01000000 0 0x00000000
 246                                   0x01000000 0 0x00000000
 247                                   0 0x00010000>;
 248                 };
 249         };
 250 };