2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
9 #ifndef _ASM_POWERPC_REG_H
10 #define _ASM_POWERPC_REG_H
13 #include <linux/stringify.h>
14 #include <asm/cputable.h>
16 /* Pickup Book E specific registers. */
17 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18 #include <asm/reg_booke.h>
19 #endif /* CONFIG_BOOKE || CONFIG_40x */
21 #ifdef CONFIG_FSL_EMB_PERFMON
22 #include <asm/reg_fsl_emb.h>
26 #include <asm/reg_8xx.h>
27 #endif /* CONFIG_8xx */
29 #define MSR_SF_LG 63 /* Enable 64 bit mode */
30 #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
31 #define MSR_HV_LG 60 /* Hypervisor state */
32 #define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */
33 #define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
34 #define MSR_TS_LG 33 /* Trans Mem state (2 bits) */
35 #define MSR_TM_LG 32 /* Trans Mem Available */
36 #define MSR_VEC_LG 25 /* Enable AltiVec */
37 #define MSR_VSX_LG 23 /* Enable VSX */
38 #define MSR_POW_LG 18 /* Enable Power Management */
39 #define MSR_WE_LG 18 /* Wait State Enable */
40 #define MSR_TGPR_LG 17 /* TLB Update registers in use */
41 #define MSR_CE_LG 17 /* Critical Interrupt Enable */
42 #define MSR_ILE_LG 16 /* Interrupt Little Endian */
43 #define MSR_EE_LG 15 /* External Interrupt Enable */
44 #define MSR_PR_LG 14 /* Problem State / Privilege Level */
45 #define MSR_FP_LG 13 /* Floating Point enable */
46 #define MSR_ME_LG 12 /* Machine Check Enable */
47 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
48 #define MSR_SE_LG 10 /* Single Step */
49 #define MSR_BE_LG 9 /* Branch Trace */
50 #define MSR_DE_LG 9 /* Debug Exception Enable */
51 #define MSR_FE1_LG 8 /* Floating Exception mode 1 */
52 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
53 #define MSR_IR_LG 5 /* Instruction Relocate */
54 #define MSR_DR_LG 4 /* Data Relocate */
55 #define MSR_PE_LG 3 /* Protection Enable */
56 #define MSR_PX_LG 2 /* Protection Exclusive Mode */
57 #define MSR_PMM_LG 2 /* Performance monitor */
58 #define MSR_RI_LG 1 /* Recoverable Exception */
59 #define MSR_LE_LG 0 /* Little Endian */
62 #define __MASK(X) (1<<(X))
64 #define __MASK(X) (1UL<<(X))
68 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
69 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
70 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
72 /* so tests for these bits fail on 32-bit */
79 * To be used in shared book E/book S, this avoids needing to worry about
80 * book S/book E in shared code
86 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
87 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
88 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
89 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
90 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
91 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
92 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
93 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
94 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
95 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
96 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
97 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
98 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
99 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
100 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
101 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
102 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
103 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
104 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
105 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
106 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
108 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
110 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
111 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
113 #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
114 #define MSR_TS_N 0 /* Non-transactional */
115 #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
116 #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
117 #define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */
118 #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
119 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
120 #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
121 #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
123 #if defined(CONFIG_PPC_BOOK3S_64)
124 #define MSR_64BIT MSR_SF
127 #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
128 #ifdef __BIG_ENDIAN__
130 #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
132 #define MSR_ (__MSR | MSR_LE)
133 #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
135 #define MSR_KERNEL (MSR_ | MSR_64BIT)
136 #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
137 #define MSR_USER64 (MSR_USER32 | MSR_64BIT)
138 #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
139 /* Default MSR for kernel mode. */
140 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
141 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
148 /* Power Management - Processor Stop Status and Control Register Fields */
149 #define PSSCR_RL_MASK 0x0000000F /* Requested Level */
150 #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
151 #define PSSCR_TR_MASK 0x00000300 /* Transition State */
152 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
153 #define PSSCR_EC 0x00100000 /* Exit Criterion */
154 #define PSSCR_ESL 0x00200000 /* Enable State Loss */
155 #define PSSCR_SD 0x00400000 /* Status Disable */
157 /* Floating Point Status and Control Register (FPSCR) Fields */
158 #define FPSCR_FX 0x80000000 /* FPU exception summary */
159 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
160 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
161 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
162 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
163 #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
164 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
165 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
166 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
167 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
168 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
169 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
170 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
171 #define FPSCR_FR 0x00040000 /* Fraction rounded */
172 #define FPSCR_FI 0x00020000 /* Fraction inexact */
173 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
174 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
175 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
176 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
177 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
178 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
179 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
180 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
181 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
182 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
183 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
184 #define FPSCR_RN 0x00000003 /* FPU rounding control */
186 /* Bit definitions for SPEFSCR. */
187 #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
188 #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
189 #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
190 #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
191 #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
192 #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
193 #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
194 #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
195 #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
196 #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
197 #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
198 #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
199 #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
200 #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
201 #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
202 #define SPEFSCR_OV 0x00004000 /* Integer overflow */
203 #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
204 #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
205 #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
206 #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
207 #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
208 #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
209 #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
210 #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
211 #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
212 #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
213 #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
214 #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
216 /* Special Purpose Registers (SPRNs)*/
219 #define SPRN_PID 0x3B1 /* Process ID */
221 #define SPRN_PID 0x030 /* Process ID */
223 #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
227 #define SPRN_CTR 0x009 /* Count Register */
228 #define SPRN_DSCR 0x11
229 #define SPRN_CFAR 0x1c /* Come From Address Register */
230 #define SPRN_AMR 0x1d /* Authority Mask Register */
231 #define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
232 #define SPRN_AMOR 0x15d /* Authority Mask Override Register */
233 #define SPRN_ACOP 0x1F /* Available Coprocessor Register */
234 #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
235 #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
236 #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
237 #define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */
238 #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
239 #define SPRN_CTRLF 0x088
240 #define SPRN_CTRLT 0x098
241 #define CTRL_CT 0xc0000000 /* current thread */
242 #define CTRL_CT0 0x80000000 /* thread 0 */
243 #define CTRL_CT1 0x40000000 /* thread 1 */
244 #define CTRL_TE 0x00c00000 /* thread enable */
245 #define CTRL_RUNLATCH 0x1
246 #define SPRN_DAWR 0xB4
247 #define SPRN_RPR 0xBA /* Relative Priority Register */
248 #define SPRN_CIABR 0xBB
249 #define CIABR_PRIV 0x3
250 #define CIABR_PRIV_USER 1
251 #define CIABR_PRIV_SUPER 2
252 #define CIABR_PRIV_HYPER 3
253 #define SPRN_DAWRX 0xBC
254 #define DAWRX_USER __MASK(0)
255 #define DAWRX_KERNEL __MASK(1)
256 #define DAWRX_HYP __MASK(2)
257 #define DAWRX_WTI __MASK(3)
258 #define DAWRX_WT __MASK(4)
259 #define DAWRX_DR __MASK(5)
260 #define DAWRX_DW __MASK(6)
261 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
262 #define SPRN_DABR2 0x13D /* e300 */
263 #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
264 #define DABRX_USER __MASK(0)
265 #define DABRX_KERNEL __MASK(1)
266 #define DABRX_HYP __MASK(2)
267 #define DABRX_BTI __MASK(3)
268 #define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
269 #define SPRN_DAR 0x013 /* Data Address Register */
270 #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
271 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
272 #define DSISR_NOHPTE 0x40000000 /* no translation found */
273 #define DSISR_PROTFAULT 0x08000000 /* protection fault */
274 #define DSISR_ISSTORE 0x02000000 /* access was a store */
275 #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
276 #define DSISR_NOSEGMENT 0x00200000 /* SLB miss */
277 #define DSISR_KEYFAULT 0x00200000 /* Key fault */
278 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
279 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
280 #define SPRN_CIR 0x11B /* Chip Information Register (hyper, R/0) */
281 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
282 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
283 #define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */
284 #define SPRN_SPURR 0x134 /* Scaled PURR */
285 #define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
286 #define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
287 #define SPRN_HDSISR 0x132
288 #define SPRN_HDAR 0x133
289 #define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
290 #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
291 #define SPRN_RMOR 0x138 /* Real mode offset register */
292 #define SPRN_HRMOR 0x139 /* Real mode offset register */
293 #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
294 #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
295 #define SPRN_LMRR 0x32D /* Load Monitor Region Register */
296 #define SPRN_LMSER 0x32E /* Load Monitor Section Enable Register */
297 #define SPRN_IC 0x350 /* Virtual Instruction Count */
298 #define SPRN_VTB 0x351 /* Virtual Time Base */
299 #define SPRN_LDBAR 0x352 /* LD Base Address Register */
300 #define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */
301 #define SPRN_PMSR 0x355 /* Power Management Status Reg */
302 #define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */
303 #define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
304 #define SPRN_PMCR 0x374 /* Power Management Control Register */
306 /* HFSCR and FSCR bit numbers are the same */
307 #define FSCR_LM_LG 11 /* Enable Load Monitor Registers */
308 #define FSCR_TAR_LG 8 /* Enable Target Address Register */
309 #define FSCR_EBB_LG 7 /* Enable Event Based Branching */
310 #define FSCR_TM_LG 5 /* Enable Transactional Memory */
311 #define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/
312 #define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */
313 #define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
314 #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
315 #define FSCR_FP_LG 0 /* Enable Floating Point */
316 #define SPRN_FSCR 0x099 /* Facility Status & Control Register */
317 #define FSCR_LM __MASK(FSCR_LM_LG)
318 #define FSCR_TAR __MASK(FSCR_TAR_LG)
319 #define FSCR_EBB __MASK(FSCR_EBB_LG)
320 #define FSCR_DSCR __MASK(FSCR_DSCR_LG)
321 #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
322 #define HFSCR_LM __MASK(FSCR_LM_LG)
323 #define HFSCR_TAR __MASK(FSCR_TAR_LG)
324 #define HFSCR_EBB __MASK(FSCR_EBB_LG)
325 #define HFSCR_TM __MASK(FSCR_TM_LG)
326 #define HFSCR_PM __MASK(FSCR_PM_LG)
327 #define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
328 #define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
329 #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
330 #define HFSCR_FP __MASK(FSCR_FP_LG)
331 #define SPRN_TAR 0x32f /* Target Address Register */
332 #define SPRN_LPCR 0x13E /* LPAR Control Register */
333 #define LPCR_VPM0 ASM_CONST(0x8000000000000000)
334 #define LPCR_VPM1 ASM_CONST(0x4000000000000000)
335 #define LPCR_ISL ASM_CONST(0x2000000000000000)
336 #define LPCR_VC_SH 61
337 #define LPCR_DPFD_SH 52
338 #define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
339 #define LPCR_VRMASD_SH 47
340 #define LPCR_VRMASD (ASM_CONST(1) << LPCR_VRMASD_SH)
341 #define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
342 #define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
343 #define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
344 #define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */
345 #define LPCR_RMLS_SH 26
346 #define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
347 #define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
348 #define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
349 #define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
350 #define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
351 #define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
352 #define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
353 #define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
354 #define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
355 #define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
356 #define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
357 #define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
358 #define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
359 #define LPCR_MER_SH 11
360 #define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
361 #define LPCR_LPES 0x0000000c
362 #define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
363 #define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
364 #define LPCR_LPES_SH 2
365 #define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
366 #define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
367 #define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
368 #define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
369 #define LPCR_HR ASM_CONST(0x0000000000100000)
371 #define SPRN_LPID 0x13F /* Logical Partition Identifier */
373 #define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */
374 #define SPRN_HMER 0x150 /* Hardware m? error recovery */
375 #define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
376 #define SPRN_PCR 0x152 /* Processor compatibility register */
377 #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
378 #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
379 #define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */
380 #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
381 #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
382 #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
383 #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
384 #define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
385 #define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
386 #define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
387 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
388 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
389 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
390 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
391 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
392 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
393 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
394 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
395 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
396 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
397 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
398 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
399 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
400 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
401 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
402 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
403 #define SPRN_PPR 0x380 /* SMT Thread status Register */
404 #define SPRN_TSCR 0x399 /* Thread Switch Control Register */
406 #define SPRN_DEC 0x016 /* Decrement Register */
407 #define SPRN_DER 0x095 /* Debug Enable Register */
408 #define DER_RSTE 0x40000000 /* Reset Interrupt */
409 #define DER_CHSTPE 0x20000000 /* Check Stop */
410 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */
411 #define DER_EXTIE 0x02000000 /* External Interrupt */
412 #define DER_ALIE 0x01000000 /* Alignment Interrupt */
413 #define DER_PRIE 0x00800000 /* Program Interrupt */
414 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
415 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */
416 #define DER_SYSIE 0x00040000 /* System Call Interrupt */
417 #define DER_TRE 0x00020000 /* Trace Interrupt */
418 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
419 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
420 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
421 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
422 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
423 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
424 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
425 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
426 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
427 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
428 #define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */
429 #define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */
430 #define SPRN_EAR 0x11A /* External Address Register */
431 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
432 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Register */
433 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
434 #define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */
435 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
436 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
437 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
438 #define HID0_SBCLK (1<<27)
439 #define HID0_EICE (1<<26)
440 #define HID0_TBEN (1<<26) /* Timebase enable - 745x */
441 #define HID0_ECLK (1<<25)
442 #define HID0_PAR (1<<24)
443 #define HID0_STEN (1<<24) /* Software table search enable - 745x */
444 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
445 #define HID0_DOZE (1<<23)
446 #define HID0_NAP (1<<22)
447 #define HID0_SLEEP (1<<21)
448 #define HID0_DPM (1<<20)
449 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
450 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
451 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
452 #define HID0_ICE (1<<15) /* Instruction Cache Enable */
453 #define HID0_DCE (1<<14) /* Data Cache Enable */
454 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
455 #define HID0_DLOCK (1<<12) /* Data Cache Lock */
456 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
457 #define HID0_DCI (1<<10) /* Data Cache Invalidate */
458 #define HID0_SPD (1<<9) /* Speculative disable */
459 #define HID0_DAPUEN (1<<8) /* Debug APU enable */
460 #define HID0_SGE (1<<7) /* Store Gathering Enable */
461 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
462 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
463 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */
464 #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
465 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
466 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
467 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
468 #define HID0_BTCD (1<<1) /* Branch target cache disable */
469 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
470 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
471 /* POWER8 HID0 bits */
472 #define HID0_POWER8_4LPARMODE __MASK(61)
473 #define HID0_POWER8_2LPARMODE __MASK(57)
474 #define HID0_POWER8_1TO2LPAR __MASK(52)
475 #define HID0_POWER8_1TO4LPAR __MASK(51)
476 #define HID0_POWER8_DYNLPARDIS __MASK(48)
478 /* POWER9 HID0 bits */
479 #define HID0_POWER9_RADIX __MASK(63 - 8)
481 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
483 #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
484 #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
485 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
486 #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
487 #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
488 #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
489 #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
490 #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
491 #define HID1_PS (1<<16) /* 750FX PLL selection */
493 #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
494 #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */
495 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
496 #define SPRN_IABR2 0x3FA /* 83xx */
497 #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
498 #define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */
499 #define SPRN_HID4 0x3F4 /* 970 HID4 */
500 #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
501 #define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */
502 #define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */
503 #define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */
504 #define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
505 #define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */
506 #define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */
507 #define HID4_LPID1_SH 0 /* partition ID top 2 bits */
508 #define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */
509 #define SPRN_HID5 0x3F6 /* 970 HID5 */
510 #define SPRN_HID6 0x3F9 /* BE HID 6 */
511 #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
512 #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
513 #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
514 #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
515 #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
516 #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
517 #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
518 #define SPRN_TSC 0x3FD /* Thread switch control on others */
519 #define SPRN_TST 0x3FC /* Thread switch timeout on others */
520 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
521 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
522 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
524 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
525 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
526 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
527 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
528 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
529 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
530 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
531 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
532 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
533 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
534 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
535 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
536 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
537 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
538 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
539 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
540 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
541 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
542 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
543 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */
544 #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
545 #define ICTRL_EICP 0x00000100 /* enable icache par. check */
546 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
547 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
548 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */
549 #define SPRN_L2CR2 0x3f8
550 #define L2CR_L2E 0x80000000 /* L2 enable */
551 #define L2CR_L2PE 0x40000000 /* L2 parity enable */
552 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
553 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
554 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
555 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
556 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
557 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
558 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
559 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
560 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
561 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
562 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
563 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
564 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
565 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
566 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
567 #define L2CR_L2DO 0x00400000 /* L2 data only */
568 #define L2CR_L2I 0x00200000 /* L2 global invalidate */
569 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
570 #define L2CR_L2WT 0x00080000 /* L2 write-through */
571 #define L2CR_L2TS 0x00040000 /* L2 test support */
572 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
573 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
574 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
575 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
576 #define L2CR_L2DF 0x00004000 /* L2 differential clock */
577 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
578 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
579 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
580 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
581 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
582 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
583 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Register */
584 #define L3CR_L3E 0x80000000 /* L3 enable */
585 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
586 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
587 #define L3CR_L3SIZ 0x10000000 /* L3 size */
588 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
589 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
590 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
591 #define L3CR_L3IO 0x00400000 /* L3 instruction only */
592 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
593 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
594 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
595 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
596 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
597 #define L3CR_L3I 0x00000400 /* L3 global invalidate */
598 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
599 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
600 #define L3CR_L3DO 0x00000040 /* L3 data only mode */
601 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
602 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
604 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
605 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
606 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
607 #define SPRN_LDSTDB 0x3f4 /* */
608 #define SPRN_LR 0x008 /* Link Register */
610 #define SPRN_PIR 0x3FF /* Processor Identification Register */
612 #define SPRN_TIR 0x1BE /* Thread Identification Register */
613 #define SPRN_PTCR 0x1D0 /* Partition table control Register */
614 #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
615 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
616 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
617 #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
618 #define SPRN_PVR 0x11F /* Processor Version Register */
619 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
620 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
621 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
622 #define SPRN_ASR 0x118 /* Address Space Register */
623 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
624 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
625 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
626 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
627 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
628 #define SPRN_USPRG3 0x103 /* SPRG3 userspace read */
629 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
630 #define SPRN_USPRG4 0x104 /* SPRG4 userspace read */
631 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
632 #define SPRN_USPRG5 0x105 /* SPRG5 userspace read */
633 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
634 #define SPRN_USPRG6 0x106 /* SPRG6 userspace read */
635 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
636 #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */
637 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
638 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
639 #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
640 #define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */
641 #define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */
642 #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
643 #define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 */
644 #define SRR1_WAKESYSERR 0x00300000 /* System error */
645 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
646 #define SRR1_WAKEMT 0x00280000 /* mtctrl */
647 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
648 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
649 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell on P8 */
650 #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
651 #define SRR1_WAKERESET 0x00100000 /* System reset */
652 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell on P8 */
653 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
654 #define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained,
655 * may not be recoverable */
656 #define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */
657 #define SRR1_WS_DEEP 0x00010000 /* All resources maintained */
658 #define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
659 #define SRR1_PROGILL 0x00080000 /* Illegal instruction */
660 #define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
661 #define SRR1_PROGTRAP 0x00020000 /* Trap */
662 #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
664 #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
665 #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
666 #define HSRR1_DENORM 0x00100000 /* Denorm exception */
668 #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
669 #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
670 #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
671 #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
672 #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
675 #define SPRN_SVR 0x11E /* System Version Register */
677 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
678 /* these bits were defined in inverted endian sense originally, ugh, confusing */
679 #define THRM1_TIN (1 << 31)
680 #define THRM1_TIV (1 << 30)
681 #define THRM1_THRES(x) ((x&0x7f)<<23)
682 #define THRM3_SITV(x) ((x&0x3fff)<<1)
683 #define THRM1_TID (1<<2)
684 #define THRM1_TIE (1<<1)
685 #define THRM1_V (1<<0)
686 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
687 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
688 #define THRM3_E (1<<0)
689 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
690 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
691 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
692 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
693 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
694 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
695 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
696 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
697 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
698 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
700 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
701 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
702 #define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */
703 #define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */
704 #define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */
705 #define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */
706 #define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */
708 #define SPRN_SCOMC 0x114 /* SCOM Access Control */
709 #define SPRN_SCOMD 0x115 /* SCOM Access DATA */
711 /* Performance monitor SPRs */
713 #define SPRN_MMCR0 795
714 #define MMCR0_FC 0x80000000UL /* freeze counters */
715 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
716 #define MMCR0_KERNEL_DISABLE MMCR0_FCS
717 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
718 #define MMCR0_PROBLEM_DISABLE MMCR0_FCP
719 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
720 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
721 #define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */
722 #define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
723 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
724 #define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
725 #define MMCR0_EBE 0x00100000UL /* Event based branch enable */
726 #define MMCR0_PMCC 0x000c0000UL /* PMC control */
727 #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
728 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
729 #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
730 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
731 #define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
732 #define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
733 /* performance monitor alert has occurred, set to 0 after handling exception */
734 #define MMCR0_PMAO ASM_CONST(0x00000080)
735 #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
736 #define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
737 #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
738 #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
739 #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
740 #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
741 #define SPRN_MMCR1 798
742 #define SPRN_MMCR2 785
743 #define SPRN_UMMCR2 769
744 #define SPRN_MMCRA 0x312
745 #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
746 #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
747 #define MMCRA_SDAR_ERAT_MISS 0x20000000UL
748 #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
749 #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
750 #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
751 #define MMCRA_SLOT_SHIFT 24
752 #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
753 #define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
754 #define POWER6_MMCRA_SIHV 0x0000040000000000ULL
755 #define POWER6_MMCRA_SIPR 0x0000020000000000ULL
756 #define POWER6_MMCRA_THRM 0x00000020UL
757 #define POWER6_MMCRA_OTHER 0x0000000EUL
759 #define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */
760 #define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */
762 #define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */
763 #define SPRN_MMCRS 894 /* Supervisor monitor mode control register */
764 #define SPRN_MMCRC 851 /* Core monitor mode control register */
765 #define SPRN_EBBHR 804 /* Event based branch handler register */
766 #define SPRN_EBBRR 805 /* Event based branch return register */
767 #define SPRN_BESCR 806 /* Branch event status and control register */
768 #define BESCR_GE 0x8000000000000000ULL /* Global Enable */
769 #define SPRN_WORT 895 /* Workload optimization register - thread */
770 #define SPRN_WORC 863 /* Workload optimization register - core */
772 #define SPRN_PMC1 787
773 #define SPRN_PMC2 788
774 #define SPRN_PMC3 789
775 #define SPRN_PMC4 790
776 #define SPRN_PMC5 791
777 #define SPRN_PMC6 792
778 #define SPRN_PMC7 793
779 #define SPRN_PMC8 794
780 #define SPRN_SIER 784
781 #define SIER_SIPR 0x2000000 /* Sampled MSR_PR */
782 #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */
783 #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
784 #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
785 #define SPRN_SIAR 796
786 #define SPRN_SDAR 797
787 #define SPRN_TACR 888
788 #define SPRN_TCSCR 889
789 #define SPRN_CSIGR 890
790 #define SPRN_SPMC1 892
791 #define SPRN_SPMC2 893
793 /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
794 #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
795 #define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
796 #define SIER_USER_MASK 0x7fffffUL
798 #define SPRN_PA6T_MMCR0 795
799 #define PA6T_MMCR0_EN0 0x0000000000000001UL
800 #define PA6T_MMCR0_EN1 0x0000000000000002UL
801 #define PA6T_MMCR0_EN2 0x0000000000000004UL
802 #define PA6T_MMCR0_EN3 0x0000000000000008UL
803 #define PA6T_MMCR0_EN4 0x0000000000000010UL
804 #define PA6T_MMCR0_EN5 0x0000000000000020UL
805 #define PA6T_MMCR0_SUPEN 0x0000000000000040UL
806 #define PA6T_MMCR0_PREN 0x0000000000000080UL
807 #define PA6T_MMCR0_HYPEN 0x0000000000000100UL
808 #define PA6T_MMCR0_FCM0 0x0000000000000200UL
809 #define PA6T_MMCR0_FCM1 0x0000000000000400UL
810 #define PA6T_MMCR0_INTGEN 0x0000000000000800UL
811 #define PA6T_MMCR0_INTEN0 0x0000000000001000UL
812 #define PA6T_MMCR0_INTEN1 0x0000000000002000UL
813 #define PA6T_MMCR0_INTEN2 0x0000000000004000UL
814 #define PA6T_MMCR0_INTEN3 0x0000000000008000UL
815 #define PA6T_MMCR0_INTEN4 0x0000000000010000UL
816 #define PA6T_MMCR0_INTEN5 0x0000000000020000UL
817 #define PA6T_MMCR0_DISCNT 0x0000000000040000UL
818 #define PA6T_MMCR0_UOP 0x0000000000080000UL
819 #define PA6T_MMCR0_TRG 0x0000000000100000UL
820 #define PA6T_MMCR0_TRGEN 0x0000000000200000UL
821 #define PA6T_MMCR0_TRGREG 0x0000000001600000UL
822 #define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
823 #define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
824 #define PA6T_MMCR0_PROEN 0x0000000008000000UL
825 #define PA6T_MMCR0_PROLOG 0x0000000010000000UL
826 #define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
827 #define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
828 #define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
829 #define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
830 #define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
831 #define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
832 #define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
833 #define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
834 #define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
835 #define PA6T_MMCR0_PCTEN 0x0000004000000000UL
836 #define PA6T_MMCR0_SOCEN 0x0000008000000000UL
837 #define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
839 #define SPRN_PA6T_MMCR1 798
840 #define PA6T_MMCR1_ES2 0x00000000000000ffUL
841 #define PA6T_MMCR1_ES3 0x000000000000ff00UL
842 #define PA6T_MMCR1_ES4 0x0000000000ff0000UL
843 #define PA6T_MMCR1_ES5 0x00000000ff000000UL
845 #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
846 #define SPRN_PA6T_UPMC1 772 /* ... */
847 #define SPRN_PA6T_UPMC2 773
848 #define SPRN_PA6T_UPMC3 774
849 #define SPRN_PA6T_UPMC4 775
850 #define SPRN_PA6T_UPMC5 776
851 #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
852 #define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */
853 #define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */
854 #define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */
855 #define SPRN_PA6T_PMC0 787
856 #define SPRN_PA6T_PMC1 788
857 #define SPRN_PA6T_PMC2 789
858 #define SPRN_PA6T_PMC3 790
859 #define SPRN_PA6T_PMC4 791
860 #define SPRN_PA6T_PMC5 792
861 #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
862 #define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */
863 #define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */
864 #define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */
866 #define SPRN_PA6T_IER 981 /* Icache Error Register */
867 #define SPRN_PA6T_DER 982 /* Dcache Error Register */
868 #define SPRN_PA6T_BER 862 /* BIU Error Address Register */
869 #define SPRN_PA6T_MER 849 /* MMU Error Register */
871 #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
872 #define SPRN_PA6T_IMA1 881 /* ... */
873 #define SPRN_PA6T_IMA2 882
874 #define SPRN_PA6T_IMA3 883
875 #define SPRN_PA6T_IMA4 884
876 #define SPRN_PA6T_IMA5 885
877 #define SPRN_PA6T_IMA6 886
878 #define SPRN_PA6T_IMA7 887
879 #define SPRN_PA6T_IMA8 888
880 #define SPRN_PA6T_IMA9 889
881 #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
882 #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
883 #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
884 #define SPRN_BKMK 1020 /* Cell Bookmark Register */
885 #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
889 #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
890 #define MMCR0_FC 0x80000000UL /* freeze counters */
891 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
892 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
893 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
894 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
895 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
896 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
897 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
898 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
899 #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
900 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
901 #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
902 #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
904 #define SPRN_MMCR1 956
905 #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
906 #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
907 #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
908 #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
909 #define SPRN_MMCR2 944
910 #define SPRN_PMC1 953 /* Performance Counter Register 1 */
911 #define SPRN_PMC2 954 /* Performance Counter Register 2 */
912 #define SPRN_PMC3 957 /* Performance Counter Register 3 */
913 #define SPRN_PMC4 958 /* Performance Counter Register 4 */
914 #define SPRN_PMC5 945 /* Performance Counter Register 5 */
915 #define SPRN_PMC6 946 /* Performance Counter Register 6 */
917 #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
919 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
920 #define MMCR0_PMC1_CYCLES (1 << 7)
921 #define MMCR0_PMC1_ICACHEMISS (5 << 7)
922 #define MMCR0_PMC1_DTLB (6 << 7)
923 #define MMCR0_PMC2_DCACHEMISS 0x6
924 #define MMCR0_PMC2_CYCLES 0x1
925 #define MMCR0_PMC2_ITLB 0x7
926 #define MMCR0_PMC2_LOADMISSTIME 0x5
933 * - SPRG1 stores PACA pointer except 64-bit server in
934 * HV mode in which case it is HSPRG0
937 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
938 * - SPRG2 scratch for exception vectors
939 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
940 * - HSPRG0 stores PACA in HV mode
941 * - HSPRG1 scratch for "HV" exceptions
944 * - SPRG0 generic exception scratch
945 * - SPRG2 TLB exception stack
946 * - SPRG3 critical exception scratch (user visible, sorry!)
947 * - SPRG4 unused (user visible)
948 * - SPRG6 TLB miss scratch (user visible, sorry !)
949 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
950 * - SPRG8 machine check exception scratch
951 * - SPRG9 debug exception scratch
954 * - SPRG3 current thread_info pointer
955 * (virtual on BookE, physical on others)
958 * - SPRG0 scratch for exception vectors
959 * - SPRG1 scratch for exception vectors
960 * - SPRG2 indicator that we are in RTAS
961 * - SPRG4 (603 only) pseudo TLB LRU data
964 * - SPRG0 scratch for exception vectors
965 * - SPRG1 scratch for exception vectors
966 * - SPRG2 scratch for exception vectors
967 * - SPRG4 scratch for exception vectors (not 403)
968 * - SPRG5 scratch for exception vectors (not 403)
969 * - SPRG6 scratch for exception vectors (not 403)
970 * - SPRG7 scratch for exception vectors (not 403)
972 * 32-bit 440 and FSL BookE:
973 * - SPRG0 scratch for exception vectors
974 * - SPRG1 scratch for exception vectors (*)
975 * - SPRG2 scratch for crit interrupts handler
976 * - SPRG4 scratch for exception vectors
977 * - SPRG5 scratch for exception vectors
978 * - SPRG6 scratch for machine check handler
979 * - SPRG7 scratch for exception vectors
980 * - SPRG9 scratch for debug vectors (e500 only)
982 * Additionally, BookE separates "read" and "write"
983 * of those registers. That allows to use the userspace
984 * readable variant for reads, which can avoid a fault
985 * with KVM type virtualization.
988 * - SPRG0 scratch for exception vectors
989 * - SPRG1 scratch for exception vectors
990 * - SPRG2 scratch for exception vectors
994 #define SPRN_SPRG_PACA SPRN_SPRG1
996 #define SPRN_SPRG_THREAD SPRN_SPRG3
999 #ifdef CONFIG_PPC_BOOK3S_64
1000 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1001 #define SPRN_SPRG_HPACA SPRN_HSPRG0
1002 #define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1003 #define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1004 #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1006 #define GET_PACA(rX) \
1007 BEGIN_FTR_SECTION_NESTED(66); \
1008 mfspr rX,SPRN_SPRG_PACA; \
1009 FTR_SECTION_ELSE_NESTED(66); \
1010 mfspr rX,SPRN_SPRG_HPACA; \
1011 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1013 #define SET_PACA(rX) \
1014 BEGIN_FTR_SECTION_NESTED(66); \
1015 mtspr SPRN_SPRG_PACA,rX; \
1016 FTR_SECTION_ELSE_NESTED(66); \
1017 mtspr SPRN_SPRG_HPACA,rX; \
1018 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1020 #define GET_SCRATCH0(rX) \
1021 BEGIN_FTR_SECTION_NESTED(66); \
1022 mfspr rX,SPRN_SPRG_SCRATCH0; \
1023 FTR_SECTION_ELSE_NESTED(66); \
1024 mfspr rX,SPRN_SPRG_HSCRATCH0; \
1025 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1027 #define SET_SCRATCH0(rX) \
1028 BEGIN_FTR_SECTION_NESTED(66); \
1029 mtspr SPRN_SPRG_SCRATCH0,rX; \
1030 FTR_SECTION_ELSE_NESTED(66); \
1031 mtspr SPRN_SPRG_HSCRATCH0,rX; \
1032 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1034 #else /* CONFIG_PPC_BOOK3S_64 */
1035 #define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
1036 #define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
1040 #ifdef CONFIG_PPC_BOOK3E_64
1041 #define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1042 #define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1043 #define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1044 #define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1045 #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1046 #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1047 #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1048 #define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1049 #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1051 #define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
1052 #define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
1056 #ifdef CONFIG_PPC_BOOK3S_32
1057 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1058 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1059 #define SPRN_SPRG_RTAS SPRN_SPRG2
1060 #define SPRN_SPRG_603_LRU SPRN_SPRG4
1064 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1065 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1066 #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1067 #define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1068 #define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1069 #define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1070 #define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
1074 #define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1075 #define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1076 #define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1077 #define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1078 #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1079 #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1080 #define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1081 #define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1082 #define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1083 #define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1084 #define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1085 #define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1086 #define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1087 #define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1089 #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
1090 #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
1092 #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1093 #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1098 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1099 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1100 #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1106 * An mtfsf instruction with the L bit set. On CPUs that support this a
1107 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
1109 * Until binutils gets the new form of mtfsf, hardwire the instruction.
1112 #define MTFSF_L(REG) \
1113 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1115 #define MTFSF_L(REG) mtfsf 0xff, (REG)
1118 /* Processor Version Register (PVR) field extraction */
1120 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
1121 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
1123 #define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1126 * IBM has further subdivided the standard PowerPC 16-bit version and
1127 * revision subfields of the PVR for the PowerPC 403s into the following:
1130 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
1131 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
1132 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
1133 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
1134 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
1135 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
1137 /* Processor Version Numbers */
1139 #define PVR_403GA 0x00200000
1140 #define PVR_403GB 0x00200100
1141 #define PVR_403GC 0x00200200
1142 #define PVR_403GCX 0x00201400
1143 #define PVR_405GP 0x40110000
1144 #define PVR_476 0x11a52000
1145 #define PVR_476FPE 0x7ff50000
1146 #define PVR_STB03XXX 0x40310000
1147 #define PVR_NP405H 0x41410000
1148 #define PVR_NP405L 0x41610000
1149 #define PVR_601 0x00010000
1150 #define PVR_602 0x00050000
1151 #define PVR_603 0x00030000
1152 #define PVR_603e 0x00060000
1153 #define PVR_603ev 0x00070000
1154 #define PVR_603r 0x00071000
1155 #define PVR_604 0x00040000
1156 #define PVR_604e 0x00090000
1157 #define PVR_604r 0x000A0000
1158 #define PVR_620 0x00140000
1159 #define PVR_740 0x00080000
1160 #define PVR_750 PVR_740
1161 #define PVR_740P 0x10080000
1162 #define PVR_750P PVR_740P
1163 #define PVR_7400 0x000C0000
1164 #define PVR_7410 0x800C0000
1165 #define PVR_7450 0x80000000
1166 #define PVR_8540 0x80200000
1167 #define PVR_8560 0x80200000
1168 #define PVR_VER_E500V1 0x8020
1169 #define PVR_VER_E500V2 0x8021
1170 #define PVR_VER_E500MC 0x8023
1171 #define PVR_VER_E5500 0x8024
1172 #define PVR_VER_E6500 0x8040
1175 * For the 8xx processors, all of them report the same PVR family for
1176 * the PowerPC core. The various versions of these processors must be
1177 * differentiated by the version number in the Communication Processor
1180 #define PVR_821 0x00500000
1181 #define PVR_823 PVR_821
1182 #define PVR_850 PVR_821
1183 #define PVR_860 PVR_821
1184 #define PVR_8240 0x00810100
1185 #define PVR_8245 0x80811014
1186 #define PVR_8260 PVR_8240
1188 /* 476 Simulator seems to currently have the PVR of the 602... */
1189 #define PVR_476_ISS 0x00052000
1191 /* 64-bit processors */
1192 #define PVR_NORTHSTAR 0x0033
1193 #define PVR_PULSAR 0x0034
1194 #define PVR_POWER4 0x0035
1195 #define PVR_ICESTAR 0x0036
1196 #define PVR_SSTAR 0x0037
1197 #define PVR_POWER4p 0x0038
1198 #define PVR_970 0x0039
1199 #define PVR_POWER5 0x003A
1200 #define PVR_POWER5p 0x003B
1201 #define PVR_970FX 0x003C
1202 #define PVR_POWER6 0x003E
1203 #define PVR_POWER7 0x003F
1204 #define PVR_630 0x0040
1205 #define PVR_630p 0x0041
1206 #define PVR_970MP 0x0044
1207 #define PVR_970GX 0x0045
1208 #define PVR_POWER7p 0x004A
1209 #define PVR_POWER8E 0x004B
1210 #define PVR_POWER8NVL 0x004C
1211 #define PVR_POWER8 0x004D
1212 #define PVR_BE 0x0070
1213 #define PVR_PA6T 0x0090
1215 /* "Logical" PVR values defined in PAPR, representing architecture levels */
1216 #define PVR_ARCH_204 0x0f000001
1217 #define PVR_ARCH_205 0x0f000002
1218 #define PVR_ARCH_206 0x0f000003
1219 #define PVR_ARCH_206p 0x0f100003
1220 #define PVR_ARCH_207 0x0f000004
1222 /* Macros for setting and retrieving special purpose registers */
1223 #ifndef __ASSEMBLY__
1224 #define mfmsr() ({unsigned long rval; \
1225 asm volatile("mfmsr %0" : "=r" (rval) : \
1226 : "memory"); rval;})
1227 #ifdef CONFIG_PPC_BOOK3S_64
1228 #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1229 : : "r" (v) : "memory")
1230 #define mtmsr(v) __mtmsrd((v), 0)
1231 #define __MTMSR "mtmsrd"
1233 #define mtmsr(v) asm volatile("mtmsr %0" : \
1234 : "r" ((unsigned long)(v)) \
1236 #define __MTMSR "mtmsr"
1239 static inline void mtmsr_isync(unsigned long val)
1241 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1242 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1245 #define mfspr(rn) ({unsigned long rval; \
1246 asm volatile("mfspr %0," __stringify(rn) \
1247 : "=r" (rval)); rval;})
1249 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1250 : "r" ((unsigned long)(v)) \
1254 extern unsigned long msr_check_and_set(unsigned long bits);
1255 extern bool strict_msr_control;
1256 extern void __msr_check_and_clear(unsigned long bits);
1257 static inline void msr_check_and_clear(unsigned long bits)
1259 if (strict_msr_control)
1260 __msr_check_and_clear(bits);
1263 #ifdef __powerpc64__
1264 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1265 #define mftb() ({unsigned long rval; \
1267 "90: mfspr %0, %2;\n" \
1268 "97: cmpwi %0,0;\n" \
1271 ".section __ftr_fixup,\"a\"\n" \
1276 " .llong 97b-98b\n" \
1277 " .llong 99b-98b\n" \
1282 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \
1285 #define mftb() ({unsigned long rval; \
1286 asm volatile("mfspr %0, %1" : \
1287 "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1288 #endif /* !CONFIG_PPC_CELL */
1290 #else /* __powerpc64__ */
1292 #if defined(CONFIG_8xx)
1293 #define mftbl() ({unsigned long rval; \
1294 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1295 #define mftbu() ({unsigned long rval; \
1296 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1298 #define mftbl() ({unsigned long rval; \
1299 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1300 "i" (SPRN_TBRL)); rval;})
1301 #define mftbu() ({unsigned long rval; \
1302 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1303 "i" (SPRN_TBRU)); rval;})
1305 #define mftb() mftbl()
1306 #endif /* !__powerpc64__ */
1308 #define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1309 #define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1312 #define mfsrin(v) ({unsigned int rval; \
1313 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1317 #define proc_trap() asm volatile("trap")
1319 extern unsigned long current_stack_pointer(void);
1321 extern unsigned long scom970_read(unsigned int address);
1322 extern void scom970_write(unsigned int address, unsigned long value);
1326 extern void ppc_save_regs(struct pt_regs *regs);
1328 static inline void update_power8_hid0(unsigned long hid0)
1331 * The HID0 update on Power8 should at the very least be
1332 * preceded by a a SYNC instruction followed by an ISYNC
1335 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1337 #endif /* __ASSEMBLY__ */
1338 #endif /* __KERNEL__ */
1339 #endif /* _ASM_POWERPC_REG_H */
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