arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/io.h>
  44 #include <asm/processor.h>
  45 #include <asm/mmu.h>
  46 #include <asm/prom.h>
  47 #include <asm/machdep.h>
  48 #include <asm/time.h>
  49 #include <asm/runlatch.h>
  50 #include <asm/syscalls.h>
  51 #include <asm/switch_to.h>
  52 #include <asm/tm.h>
  53 #include <asm/debug.h>
  54 #ifdef CONFIG_PPC64
  55 #include <asm/firmware.h>
  56 #endif
  57 #include <asm/code-patching.h>
  58 #include <linux/kprobes.h>
  59 #include <linux/kdebug.h>
  60
  61 /* Transactional Memory debug */
  62 #ifdef TM_DEBUG_SW
  63 #define TM_DEBUG(x...) printk(KERN_INFO x)
  64 #else
  65 #define TM_DEBUG(x...) do { } while(0)
  66 #endif
  67
  68 extern unsigned long _get_SP(void);
  69
  70 #ifndef CONFIG_SMP
  71 struct task_struct *last_task_used_math = NULL;
  72 struct task_struct *last_task_used_altivec = NULL;
  73 struct task_struct *last_task_used_vsx = NULL;
  74 struct task_struct *last_task_used_spe = NULL;
  75 #endif
  76
  77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  78 void giveup_fpu_maybe_transactional(struct task_struct *tsk)
  79 {
  80         /*
  81          * If we are saving the current thread's registers, and the
  82          * thread is in a transactional state, set the TIF_RESTORE_TM
  83          * bit so that we know to restore the registers before
  84          * returning to userspace.
  85          */
  86         if (tsk == current && tsk->thread.regs &&
  87             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  88             !test_thread_flag(TIF_RESTORE_TM)) {
  89                 tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
  90                 set_thread_flag(TIF_RESTORE_TM);
  91         }
  92
  93         giveup_fpu(tsk);
  94 }
  95
  96 void giveup_altivec_maybe_transactional(struct task_struct *tsk)
  97 {
  98         /*
  99          * If we are saving the current thread's registers, and the
 100          * thread is in a transactional state, set the TIF_RESTORE_TM
 101          * bit so that we know to restore the registers before
 102          * returning to userspace.
 103          */
 104         if (tsk == current && tsk->thread.regs &&
 105             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 106             !test_thread_flag(TIF_RESTORE_TM)) {
 107                 tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
 108                 set_thread_flag(TIF_RESTORE_TM);
 109         }
 110
 111         giveup_altivec(tsk);
 112 }
 113
 114 #else
 115 #define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
 116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
 117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 118
 119 #ifdef CONFIG_PPC_FPU
 120 /*
 121  * Make sure the floating-point register state in the
 122  * the thread_struct is up to date for task tsk.
 123  */
 124 void flush_fp_to_thread(struct task_struct *tsk)
 125 {
 126         if (tsk->thread.regs) {
 127                 /*
 128                  * We need to disable preemption here because if we didn't,
 129                  * another process could get scheduled after the regs->msr
 130                  * test but before we have finished saving the FP registers
 131                  * to the thread_struct.  That process could take over the
 132                  * FPU, and then when we get scheduled again we would store
 133                  * bogus values for the remaining FP registers.
 134                  */
 135                 preempt_disable();
 136                 if (tsk->thread.regs->msr & MSR_FP) {
 137 #ifdef CONFIG_SMP
 138                         /*
 139                          * This should only ever be called for current or
 140                          * for a stopped child process.  Since we save away
 141                          * the FP register state on context switch on SMP,
 142                          * there is something wrong if a stopped child appears
 143                          * to still have its FP state in the CPU registers.
 144                          */
 145                         BUG_ON(tsk != current);
 146 #endif
 147                         giveup_fpu_maybe_transactional(tsk);
 148                 }
 149                 preempt_enable();
 150         }
 151 }
 152 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 153 #endif /* CONFIG_PPC_FPU */
 154
 155 void enable_kernel_fp(void)
 156 {
 157         WARN_ON(preemptible());
 158
 159 #ifdef CONFIG_SMP
 160         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
 161                 giveup_fpu_maybe_transactional(current);
 162         else
 163                 giveup_fpu(NULL);       /* just enables FP for kernel */
 164 #else
 165         giveup_fpu_maybe_transactional(last_task_used_math);
 166 #endif /* CONFIG_SMP */
 167 }
 168 EXPORT_SYMBOL(enable_kernel_fp);
 169
 170 #ifdef CONFIG_ALTIVEC
 171 void enable_kernel_altivec(void)
 172 {
 173         WARN_ON(preemptible());
 174
 175 #ifdef CONFIG_SMP
 176         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
 177                 giveup_altivec_maybe_transactional(current);
 178         else
 179                 giveup_altivec_notask();
 180 #else
 181         giveup_altivec_maybe_transactional(last_task_used_altivec);
 182 #endif /* CONFIG_SMP */
 183 }
 184 EXPORT_SYMBOL(enable_kernel_altivec);
 185
 186 /*
 187  * Make sure the VMX/Altivec register state in the
 188  * the thread_struct is up to date for task tsk.
 189  */
 190 void flush_altivec_to_thread(struct task_struct *tsk)
 191 {
 192         if (tsk->thread.regs) {
 193                 preempt_disable();
 194                 if (tsk->thread.regs->msr & MSR_VEC) {
 195 #ifdef CONFIG_SMP
 196                         BUG_ON(tsk != current);
 197 #endif
 198                         giveup_altivec_maybe_transactional(tsk);
 199                 }
 200                 preempt_enable();
 201         }
 202 }
 203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 204 #endif /* CONFIG_ALTIVEC */
 205
 206 #ifdef CONFIG_VSX
 207 #if 0
 208 /* not currently used, but some crazy RAID module might want to later */
 209 void enable_kernel_vsx(void)
 210 {
 211         WARN_ON(preemptible());
 212
 213 #ifdef CONFIG_SMP
 214         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
 215                 giveup_vsx(current);
 216         else
 217                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
 218 #else
 219         giveup_vsx(last_task_used_vsx);
 220 #endif /* CONFIG_SMP */
 221 }
 222 EXPORT_SYMBOL(enable_kernel_vsx);
 223 #endif
 224
 225 void giveup_vsx(struct task_struct *tsk)
 226 {
 227         giveup_fpu_maybe_transactional(tsk);
 228         giveup_altivec_maybe_transactional(tsk);
 229         __giveup_vsx(tsk);
 230 }
 231 EXPORT_SYMBOL(giveup_vsx);
 232
 233 void flush_vsx_to_thread(struct task_struct *tsk)
 234 {
 235         if (tsk->thread.regs) {
 236                 preempt_disable();
 237                 if (tsk->thread.regs->msr & MSR_VSX) {
 238 #ifdef CONFIG_SMP
 239                         BUG_ON(tsk != current);
 240 #endif
 241                         giveup_vsx(tsk);
 242                 }
 243                 preempt_enable();
 244         }
 245 }
 246 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 247 #endif /* CONFIG_VSX */
 248
 249 #ifdef CONFIG_SPE
 250
 251 void enable_kernel_spe(void)
 252 {
 253         WARN_ON(preemptible());
 254
 255 #ifdef CONFIG_SMP
 256         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
 257                 giveup_spe(current);
 258         else
 259                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
 260 #else
 261         giveup_spe(last_task_used_spe);
 262 #endif /* __SMP __ */
 263 }
 264 EXPORT_SYMBOL(enable_kernel_spe);
 265
 266 void flush_spe_to_thread(struct task_struct *tsk)
 267 {
 268         if (tsk->thread.regs) {
 269                 preempt_disable();
 270                 if (tsk->thread.regs->msr & MSR_SPE) {
 271 #ifdef CONFIG_SMP
 272                         BUG_ON(tsk != current);
 273 #endif
 274                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 275                         giveup_spe(tsk);
 276                 }
 277                 preempt_enable();
 278         }
 279 }
 280 #endif /* CONFIG_SPE */
 281
 282 #ifndef CONFIG_SMP
 283 /*
 284  * If we are doing lazy switching of CPU state (FP, altivec or SPE),
 285  * and the current task has some state, discard it.
 286  */
 287 void discard_lazy_cpu_state(void)
 288 {
 289         preempt_disable();
 290         if (last_task_used_math == current)
 291                 last_task_used_math = NULL;
 292 #ifdef CONFIG_ALTIVEC
 293         if (last_task_used_altivec == current)
 294                 last_task_used_altivec = NULL;
 295 #endif /* CONFIG_ALTIVEC */
 296 #ifdef CONFIG_VSX
 297         if (last_task_used_vsx == current)
 298                 last_task_used_vsx = NULL;
 299 #endif /* CONFIG_VSX */
 300 #ifdef CONFIG_SPE
 301         if (last_task_used_spe == current)
 302                 last_task_used_spe = NULL;
 303 #endif
 304         preempt_enable();
 305 }
 306 #endif /* CONFIG_SMP */
 307
 308 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 309 void do_send_trap(struct pt_regs *regs, unsigned long address,
 310                   unsigned long error_code, int signal_code, int breakpt)
 311 {
 312         siginfo_t info;
 313
 314         current->thread.trap_nr = signal_code;
 315         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 316                         11, SIGSEGV) == NOTIFY_STOP)
 317                 return;
 318
 319         /* Deliver the signal to userspace */
 320         info.si_signo = SIGTRAP;
 321         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 322         info.si_code = signal_code;
 323         info.si_addr = (void __user *)address;
 324         force_sig_info(SIGTRAP, &info, current);
 325 }
 326 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 327 void do_break (struct pt_regs *regs, unsigned long address,
 328                     unsigned long error_code)
 329 {
 330         siginfo_t info;
 331
 332         current->thread.trap_nr = TRAP_HWBKPT;
 333         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 334                         11, SIGSEGV) == NOTIFY_STOP)
 335                 return;
 336
 337         if (debugger_break_match(regs))
 338                 return;
 339
 340         /* Clear the breakpoint */
 341         hw_breakpoint_disable();
 342
 343         /* Deliver the signal to userspace */
 344         info.si_signo = SIGTRAP;
 345         info.si_errno = 0;
 346         info.si_code = TRAP_HWBKPT;
 347         info.si_addr = (void __user *)address;
 348         force_sig_info(SIGTRAP, &info, current);
 349 }
 350 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 351
 352 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 353
 354 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 355 /*
 356  * Set the debug registers back to their default "safe" values.
 357  */
 358 static void set_debug_reg_defaults(struct thread_struct *thread)
 359 {
 360         thread->debug.iac1 = thread->debug.iac2 = 0;
 361 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 362         thread->debug.iac3 = thread->debug.iac4 = 0;
 363 #endif
 364         thread->debug.dac1 = thread->debug.dac2 = 0;
 365 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 366         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 367 #endif
 368         thread->debug.dbcr0 = 0;
 369 #ifdef CONFIG_BOOKE
 370         /*
 371          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 372          */
 373         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 374                         DBCR1_IAC3US | DBCR1_IAC4US;
 375         /*
 376          * Force Data Address Compare User/Supervisor bits to be User-only
 377          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 378          */
 379         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 380 #else
 381         thread->debug.dbcr1 = 0;
 382 #endif
 383 }
 384
 385 static void prime_debug_regs(struct debug_reg *debug)
 386 {
 387         /*
 388          * We could have inherited MSR_DE from userspace, since
 389          * it doesn't get cleared on exception entry.  Make sure
 390          * MSR_DE is clear before we enable any debug events.
 391          */
 392         mtmsr(mfmsr() & ~MSR_DE);
 393
 394         mtspr(SPRN_IAC1, debug->iac1);
 395         mtspr(SPRN_IAC2, debug->iac2);
 396 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 397         mtspr(SPRN_IAC3, debug->iac3);
 398         mtspr(SPRN_IAC4, debug->iac4);
 399 #endif
 400         mtspr(SPRN_DAC1, debug->dac1);
 401         mtspr(SPRN_DAC2, debug->dac2);
 402 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 403         mtspr(SPRN_DVC1, debug->dvc1);
 404         mtspr(SPRN_DVC2, debug->dvc2);
 405 #endif
 406         mtspr(SPRN_DBCR0, debug->dbcr0);
 407         mtspr(SPRN_DBCR1, debug->dbcr1);
 408 #ifdef CONFIG_BOOKE
 409         mtspr(SPRN_DBCR2, debug->dbcr2);
 410 #endif
 411 }
 412 /*
 413  * Unless neither the old or new thread are making use of the
 414  * debug registers, set the debug registers from the values
 415  * stored in the new thread.
 416  */
 417 void switch_booke_debug_regs(struct debug_reg *new_debug)
 418 {
 419         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 420                 || (new_debug->dbcr0 & DBCR0_IDM))
 421                         prime_debug_regs(new_debug);
 422 }
 423 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 424 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 425 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 426 static void set_debug_reg_defaults(struct thread_struct *thread)
 427 {
 428         thread->hw_brk.address = 0;
 429         thread->hw_brk.type = 0;
 430         set_breakpoint(&thread->hw_brk);
 431 }
 432 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 433 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 434
 435 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 436 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 437 {
 438         mtspr(SPRN_DAC1, dabr);
 439 #ifdef CONFIG_PPC_47x
 440         isync();
 441 #endif
 442         return 0;
 443 }
 444 #elif defined(CONFIG_PPC_BOOK3S)
 445 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 446 {
 447         mtspr(SPRN_DABR, dabr);
 448         if (cpu_has_feature(CPU_FTR_DABRX))
 449                 mtspr(SPRN_DABRX, dabrx);
 450         return 0;
 451 }
 452 #else
 453 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 454 {
 455         return -EINVAL;
 456 }
 457 #endif
 458
 459 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 460 {
 461         unsigned long dabr, dabrx;
 462
 463         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 464         dabrx = ((brk->type >> 3) & 0x7);
 465
 466         if (ppc_md.set_dabr)
 467                 return ppc_md.set_dabr(dabr, dabrx);
 468
 469         return __set_dabr(dabr, dabrx);
 470 }
 471
 472 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 473 {
 474         unsigned long dawr, dawrx, mrd;
 475
 476         dawr = brk->address;
 477
 478         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 479                                    << (63 - 58); //* read/write bits */
 480         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 481                                    << (63 - 59); //* translate */
 482         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 483                                    >> 3; //* PRIM bits */
 484         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 485            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 486            0b111111=64DW.
 487            brk->len is in bytes.
 488            This aligns up to double word size, shifts and does the bias.
 489         */
 490         mrd = ((brk->len + 7) >> 3) - 1;
 491         dawrx |= (mrd & 0x3f) << (63 - 53);
 492
 493         if (ppc_md.set_dawr)
 494                 return ppc_md.set_dawr(dawr, dawrx);
 495         mtspr(SPRN_DAWR, dawr);
 496         mtspr(SPRN_DAWRX, dawrx);
 497         return 0;
 498 }
 499
 500 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 501 {
 502         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 503
 504         if (cpu_has_feature(CPU_FTR_DAWR))
 505                 set_dawr(brk);
 506         else
 507                 set_dabr(brk);
 508 }
 509
 510 void set_breakpoint(struct arch_hw_breakpoint *brk)
 511 {
 512         preempt_disable();
 513         __set_breakpoint(brk);
 514         preempt_enable();
 515 }
 516
 517 #ifdef CONFIG_PPC64
 518 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 519 #endif
 520
 521 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 522                               struct arch_hw_breakpoint *b)
 523 {
 524         if (a->address != b->address)
 525                 return false;
 526         if (a->type != b->type)
 527                 return false;
 528         if (a->len != b->len)
 529                 return false;
 530         return true;
 531 }
 532
 533 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 534 static void tm_reclaim_thread(struct thread_struct *thr,
 535                               struct thread_info *ti, uint8_t cause)
 536 {
 537         unsigned long msr_diff = 0;
 538
 539         /*
 540          * If FP/VSX registers have been already saved to the
 541          * thread_struct, move them to the transact_fp array.
 542          * We clear the TIF_RESTORE_TM bit since after the reclaim
 543          * the thread will no longer be transactional.
 544          */
 545         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 546                 msr_diff = thr->tm_orig_msr & ~thr->regs->msr;
 547                 if (msr_diff & MSR_FP)
 548                         memcpy(&thr->transact_fp, &thr->fp_state,
 549                                sizeof(struct thread_fp_state));
 550                 if (msr_diff & MSR_VEC)
 551                         memcpy(&thr->transact_vr, &thr->vr_state,
 552                                sizeof(struct thread_vr_state));
 553                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 554                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 555         }
 556
 557         tm_reclaim(thr, thr->regs->msr, cause);
 558
 559         /* Having done the reclaim, we now have the checkpointed
 560          * FP/VSX values in the registers.  These might be valid
 561          * even if we have previously called enable_kernel_fp() or
 562          * flush_fp_to_thread(), so update thr->regs->msr to
 563          * indicate their current validity.
 564          */
 565         thr->regs->msr |= msr_diff;
 566 }
 567
 568 void tm_reclaim_current(uint8_t cause)
 569 {
 570         tm_enable();
 571         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 572 }
 573
 574 static inline void tm_reclaim_task(struct task_struct *tsk)
 575 {
 576         /* We have to work out if we're switching from/to a task that's in the
 577          * middle of a transaction.
 578          *
 579          * In switching we need to maintain a 2nd register state as
 580          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 581          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 582          * (current) FPRs into oldtask->thread.transact_fpr[].
 583          *
 584          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 585          */
 586         struct thread_struct *thr = &tsk->thread;
 587
 588         if (!thr->regs)
 589                 return;
 590
 591         if (!MSR_TM_ACTIVE(thr->regs->msr))
 592                 goto out_and_saveregs;
 593
 594         /* Stash the original thread MSR, as giveup_fpu et al will
 595          * modify it.  We hold onto it to see whether the task used
 596          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 597          * tm_orig_msr is already set.
 598          */
 599         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 600                 thr->tm_orig_msr = thr->regs->msr;
 601
 602         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 603                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 604                  tsk->pid, thr->regs->nip,
 605                  thr->regs->ccr, thr->regs->msr,
 606                  thr->regs->trap);
 607
 608         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 609
 610         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 611                  tsk->pid);
 612
 613 out_and_saveregs:
 614         /* Always save the regs here, even if a transaction's not active.
 615          * This context-switches a thread's TM info SPRs.  We do it here to
 616          * be consistent with the restore path (in recheckpoint) which
 617          * cannot happen later in _switch().
 618          */
 619         tm_save_sprs(thr);
 620 }
 621
 622 extern void __tm_recheckpoint(struct thread_struct *thread,
 623                               unsigned long orig_msr);
 624
 625 void tm_recheckpoint(struct thread_struct *thread,
 626                      unsigned long orig_msr)
 627 {
 628         unsigned long flags;
 629
 630         /* We really can't be interrupted here as the TEXASR registers can't
 631          * change and later in the trecheckpoint code, we have a userspace R1.
 632          * So let's hard disable over this region.
 633          */
 634         local_irq_save(flags);
 635         hard_irq_disable();
 636
 637         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 638          * before the trecheckpoint and no explosion occurs.
 639          */
 640         tm_restore_sprs(thread);
 641
 642         __tm_recheckpoint(thread, orig_msr);
 643
 644         local_irq_restore(flags);
 645 }
 646
 647 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 648 {
 649         unsigned long msr;
 650
 651         if (!cpu_has_feature(CPU_FTR_TM))
 652                 return;
 653
 654         /* Recheckpoint the registers of the thread we're about to switch to.
 655          *
 656          * If the task was using FP, we non-lazily reload both the original and
 657          * the speculative FP register states.  This is because the kernel
 658          * doesn't see if/when a TM rollback occurs, so if we take an FP
 659          * unavoidable later, we are unable to determine which set of FP regs
 660          * need to be restored.
 661          */
 662         if (!new->thread.regs)
 663                 return;
 664
 665         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 666                 tm_restore_sprs(&new->thread);
 667                 return;
 668         }
 669         msr = new->thread.tm_orig_msr;
 670         /* Recheckpoint to restore original checkpointed register state. */
 671         TM_DEBUG("*** tm_recheckpoint of pid %d "
 672                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 673                  new->pid, new->thread.regs->msr, msr);
 674
 675         /* This loads the checkpointed FP/VEC state, if used */
 676         tm_recheckpoint(&new->thread, msr);
 677
 678         /* This loads the speculative FP/VEC state, if used */
 679         if (msr & MSR_FP) {
 680                 do_load_up_transact_fpu(&new->thread);
 681                 new->thread.regs->msr |=
 682                         (MSR_FP | new->thread.fpexc_mode);
 683         }
 684 #ifdef CONFIG_ALTIVEC
 685         if (msr & MSR_VEC) {
 686                 do_load_up_transact_altivec(&new->thread);
 687                 new->thread.regs->msr |= MSR_VEC;
 688         }
 689 #endif
 690         /* We may as well turn on VSX too since all the state is restored now */
 691         if (msr & MSR_VSX)
 692                 new->thread.regs->msr |= MSR_VSX;
 693
 694         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 695                  "(kernel msr 0x%lx)\n",
 696                  new->pid, mfmsr());
 697 }
 698
 699 static inline void __switch_to_tm(struct task_struct *prev)
 700 {
 701         if (cpu_has_feature(CPU_FTR_TM)) {
 702                 tm_enable();
 703                 tm_reclaim_task(prev);
 704         }
 705 }
 706
 707 /*
 708  * This is called if we are on the way out to userspace and the
 709  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 710  * FP and/or vector state and does so if necessary.
 711  * If userspace is inside a transaction (whether active or
 712  * suspended) and FP/VMX/VSX instructions have ever been enabled
 713  * inside that transaction, then we have to keep them enabled
 714  * and keep the FP/VMX/VSX state loaded while ever the transaction
 715  * continues.  The reason is that if we didn't, and subsequently
 716  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 717  * we don't know whether it's the same transaction, and thus we
 718  * don't know which of the checkpointed state and the transactional
 719  * state to use.
 720  */
 721 void restore_tm_state(struct pt_regs *regs)
 722 {
 723         unsigned long msr_diff;
 724
 725         clear_thread_flag(TIF_RESTORE_TM);
 726         if (!MSR_TM_ACTIVE(regs->msr))
 727                 return;
 728
 729         msr_diff = current->thread.tm_orig_msr & ~regs->msr;
 730         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 731         if (msr_diff & MSR_FP) {
 732                 fp_enable();
 733                 load_fp_state(&current->thread.fp_state);
 734                 regs->msr |= current->thread.fpexc_mode;
 735         }
 736         if (msr_diff & MSR_VEC) {
 737                 vec_enable();
 738                 load_vr_state(&current->thread.vr_state);
 739         }
 740         regs->msr |= msr_diff;
 741 }
 742
 743 #else
 744 #define tm_recheckpoint_new_task(new)
 745 #define __switch_to_tm(prev)
 746 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 747
 748 struct task_struct *__switch_to(struct task_struct *prev,
 749         struct task_struct *new)
 750 {
 751         struct thread_struct *new_thread, *old_thread;
 752         struct task_struct *last;
 753 #ifdef CONFIG_PPC_BOOK3S_64
 754         struct ppc64_tlb_batch *batch;
 755 #endif
 756
 757         WARN_ON(!irqs_disabled());
 758
 759         /* Back up the TAR and DSCR across context switches.
 760          * Note that the TAR is not available for use in the kernel.  (To
 761          * provide this, the TAR should be backed up/restored on exception
 762          * entry/exit instead, and be in pt_regs.  FIXME, this should be in
 763          * pt_regs anyway (for debug).)
 764          * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
 765          * these will change them.
 766          */
 767         save_early_sprs(&prev->thread);
 768
 769         __switch_to_tm(prev);
 770
 771 #ifdef CONFIG_SMP
 772         /* avoid complexity of lazy save/restore of fpu
 773          * by just saving it every time we switch out if
 774          * this task used the fpu during the last quantum.
 775          *
 776          * If it tries to use the fpu again, it'll trap and
 777          * reload its fp regs.  So we don't have to do a restore
 778          * every switch, just a save.
 779          *  -- Cort
 780          */
 781         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
 782                 giveup_fpu(prev);
 783 #ifdef CONFIG_ALTIVEC
 784         /*
 785          * If the previous thread used altivec in the last quantum
 786          * (thus changing altivec regs) then save them.
 787          * We used to check the VRSAVE register but not all apps
 788          * set it, so we don't rely on it now (and in fact we need
 789          * to save & restore VSCR even if VRSAVE == 0).  -- paulus
 790          *
 791          * On SMP we always save/restore altivec regs just to avoid the
 792          * complexity of changing processors.
 793          *  -- Cort
 794          */
 795         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
 796                 giveup_altivec(prev);
 797 #endif /* CONFIG_ALTIVEC */
 798 #ifdef CONFIG_VSX
 799         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
 800                 /* VMX and FPU registers are already save here */
 801                 __giveup_vsx(prev);
 802 #endif /* CONFIG_VSX */
 803 #ifdef CONFIG_SPE
 804         /*
 805          * If the previous thread used spe in the last quantum
 806          * (thus changing spe regs) then save them.
 807          *
 808          * On SMP we always save/restore spe regs just to avoid the
 809          * complexity of changing processors.
 810          */
 811         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
 812                 giveup_spe(prev);
 813 #endif /* CONFIG_SPE */
 814
 815 #else  /* CONFIG_SMP */
 816 #ifdef CONFIG_ALTIVEC
 817         /* Avoid the trap.  On smp this this never happens since
 818          * we don't set last_task_used_altivec -- Cort
 819          */
 820         if (new->thread.regs && last_task_used_altivec == new)
 821                 new->thread.regs->msr |= MSR_VEC;
 822 #endif /* CONFIG_ALTIVEC */
 823 #ifdef CONFIG_VSX
 824         if (new->thread.regs && last_task_used_vsx == new)
 825                 new->thread.regs->msr |= MSR_VSX;
 826 #endif /* CONFIG_VSX */
 827 #ifdef CONFIG_SPE
 828         /* Avoid the trap.  On smp this this never happens since
 829          * we don't set last_task_used_spe
 830          */
 831         if (new->thread.regs && last_task_used_spe == new)
 832                 new->thread.regs->msr |= MSR_SPE;
 833 #endif /* CONFIG_SPE */
 834
 835 #endif /* CONFIG_SMP */
 836
 837 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 838         switch_booke_debug_regs(&new->thread.debug);
 839 #else
 840 /*
 841  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
 842  * schedule DABR
 843  */
 844 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 845         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
 846                 __set_breakpoint(&new->thread.hw_brk);
 847 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 848 #endif
 849
 850
 851         new_thread = &new->thread;
 852         old_thread = &current->thread;
 853
 854 #ifdef CONFIG_PPC64
 855         /*
 856          * Collect processor utilization data per process
 857          */
 858         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
 859                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
 860                 long unsigned start_tb, current_tb;
 861                 start_tb = old_thread->start_tb;
 862                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
 863                 old_thread->accum_tb += (current_tb - start_tb);
 864                 new_thread->start_tb = current_tb;
 865         }
 866 #endif /* CONFIG_PPC64 */
 867
 868 #ifdef CONFIG_PPC_BOOK3S_64
 869         batch = this_cpu_ptr(&ppc64_tlb_batch);
 870         if (batch->active) {
 871                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
 872                 if (batch->index)
 873                         __flush_tlb_pending(batch);
 874                 batch->active = 0;
 875         }
 876 #endif /* CONFIG_PPC_BOOK3S_64 */
 877
 878         /*
 879          * We can't take a PMU exception inside _switch() since there is a
 880          * window where the kernel stack SLB and the kernel stack are out
 881          * of sync. Hard disable here.
 882          */
 883         hard_irq_disable();
 884
 885         tm_recheckpoint_new_task(new);
 886
 887         last = _switch(old_thread, new_thread);
 888
 889 #ifdef CONFIG_PPC_BOOK3S_64
 890         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
 891                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
 892                 batch = this_cpu_ptr(&ppc64_tlb_batch);
 893                 batch->active = 1;
 894         }
 895 #endif /* CONFIG_PPC_BOOK3S_64 */
 896
 897         return last;
 898 }
 899
 900 static int instructions_to_print = 16;
 901
 902 static void show_instructions(struct pt_regs *regs)
 903 {
 904         int i;
 905         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
 906                         sizeof(int));
 907
 908         printk("Instruction dump:");
 909
 910         for (i = 0; i < instructions_to_print; i++) {
 911                 int instr;
 912
 913                 if (!(i % 8))
 914                         printk("\n");
 915
 916 #if !defined(CONFIG_BOOKE)
 917                 /* If executing with the IMMU off, adjust pc rather
 918                  * than print XXXXXXXX.
 919                  */
 920                 if (!(regs->msr & MSR_IR))
 921                         pc = (unsigned long)phys_to_virt(pc);
 922 #endif
 923
 924                 if (!__kernel_text_address(pc) ||
 925                      probe_kernel_address((unsigned int __user *)pc, instr)) {
 926                         printk(KERN_CONT "XXXXXXXX ");
 927                 } else {
 928                         if (regs->nip == pc)
 929                                 printk(KERN_CONT "<%08x> ", instr);
 930                         else
 931                                 printk(KERN_CONT "%08x ", instr);
 932                 }
 933
 934                 pc += sizeof(int);
 935         }
 936
 937         printk("\n");
 938 }
 939
 940 static struct regbit {
 941         unsigned long bit;
 942         const char *name;
 943 } msr_bits[] = {
 944 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
 945         {MSR_SF,        "SF"},
 946         {MSR_HV,        "HV"},
 947 #endif
 948         {MSR_VEC,       "VEC"},
 949         {MSR_VSX,       "VSX"},
 950 #ifdef CONFIG_BOOKE
 951         {MSR_CE,        "CE"},
 952 #endif
 953         {MSR_EE,        "EE"},
 954         {MSR_PR,        "PR"},
 955         {MSR_FP,        "FP"},
 956         {MSR_ME,        "ME"},
 957 #ifdef CONFIG_BOOKE
 958         {MSR_DE,        "DE"},
 959 #else
 960         {MSR_SE,        "SE"},
 961         {MSR_BE,        "BE"},
 962 #endif
 963         {MSR_IR,        "IR"},
 964         {MSR_DR,        "DR"},
 965         {MSR_PMM,       "PMM"},
 966 #ifndef CONFIG_BOOKE
 967         {MSR_RI,        "RI"},
 968         {MSR_LE,        "LE"},
 969 #endif
 970         {0,             NULL}
 971 };
 972
 973 static void printbits(unsigned long val, struct regbit *bits)
 974 {
 975         const char *sep = "";
 976
 977         printk("<");
 978         for (; bits->bit; ++bits)
 979                 if (val & bits->bit) {
 980                         printk("%s%s", sep, bits->name);
 981                         sep = ",";
 982                 }
 983         printk(">");
 984 }
 985
 986 #ifdef CONFIG_PPC64
 987 #define REG             "%016lx"
 988 #define REGS_PER_LINE   4
 989 #define LAST_VOLATILE   13
 990 #else
 991 #define REG             "%08lx"
 992 #define REGS_PER_LINE   8
 993 #define LAST_VOLATILE   12
 994 #endif
 995
 996 void show_regs(struct pt_regs * regs)
 997 {
 998         int i, trap;
 999
1000         show_regs_print_info(KERN_DEFAULT);
1001
1002         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1003                regs->nip, regs->link, regs->ctr);
1004         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1005                regs, regs->trap, print_tainted(), init_utsname()->release);
1006         printk("MSR: "REG" ", regs->msr);
1007         printbits(regs->msr, msr_bits);
1008         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1009         trap = TRAP(regs);
1010         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1011                 printk("CFAR: "REG" ", regs->orig_gpr3);
1012         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1013 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1014                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1015 #else
1016                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1017 #endif
1018 #ifdef CONFIG_PPC64
1019         printk("SOFTE: %ld ", regs->softe);
1020 #endif
1021 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1022         if (MSR_TM_ACTIVE(regs->msr))
1023                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1024 #endif
1025
1026         for (i = 0;  i < 32;  i++) {
1027                 if ((i % REGS_PER_LINE) == 0)
1028                         printk("\nGPR%02d: ", i);
1029                 printk(REG " ", regs->gpr[i]);
1030                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1031                         break;
1032         }
1033         printk("\n");
1034 #ifdef CONFIG_KALLSYMS
1035         /*
1036          * Lookup NIP late so we have the best change of getting the
1037          * above info out without failing
1038          */
1039         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1040         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1041 #endif
1042         show_stack(current, (unsigned long *) regs->gpr[1]);
1043         if (!user_mode(regs))
1044                 show_instructions(regs);
1045 }
1046
1047 void exit_thread(void)
1048 {
1049         discard_lazy_cpu_state();
1050 }
1051
1052 void flush_thread(void)
1053 {
1054         discard_lazy_cpu_state();
1055
1056 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1057         flush_ptrace_hw_breakpoint(current);
1058 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1059         set_debug_reg_defaults(&current->thread);
1060 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1061 }
1062
1063 void
1064 release_thread(struct task_struct *t)
1065 {
1066 }
1067
1068 /*
1069  * this gets called so that we can store coprocessor state into memory and
1070  * copy the current task into the new thread.
1071  */
1072 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1073 {
1074         flush_fp_to_thread(src);
1075         flush_altivec_to_thread(src);
1076         flush_vsx_to_thread(src);
1077         flush_spe_to_thread(src);
1078         /*
1079          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1080          * flush but it removes the checkpointed state from the current CPU and
1081          * transitions the CPU out of TM mode.  Hence we need to call
1082          * tm_recheckpoint_new_task() (on the same task) to restore the
1083          * checkpointed state back and the TM mode.
1084          */
1085         __switch_to_tm(src);
1086         tm_recheckpoint_new_task(src);
1087
1088         *dst = *src;
1089
1090         clear_task_ebb(dst);
1091
1092         return 0;
1093 }
1094
1095 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1096 {
1097 #ifdef CONFIG_PPC_STD_MMU_64
1098         unsigned long sp_vsid;
1099         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1100
1101         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1102                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1103                         << SLB_VSID_SHIFT_1T;
1104         else
1105                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1106                         << SLB_VSID_SHIFT;
1107         sp_vsid |= SLB_VSID_KERNEL | llp;
1108         p->thread.ksp_vsid = sp_vsid;
1109 #endif
1110 }
1111
1112 /*
1113  * Copy a thread..
1114  */
1115 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
1116
1117 int copy_thread(unsigned long clone_flags, unsigned long usp,
1118                 unsigned long arg, struct task_struct *p)
1119 {
1120         struct pt_regs *childregs, *kregs;
1121         extern void ret_from_fork(void);
1122         extern void ret_from_kernel_thread(void);
1123         void (*f)(void);
1124         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1125
1126         /* Copy registers */
1127         sp -= sizeof(struct pt_regs);
1128         childregs = (struct pt_regs *) sp;
1129         if (unlikely(p->flags & PF_KTHREAD)) {
1130                 struct thread_info *ti = (void *)task_stack_page(p);
1131                 memset(childregs, 0, sizeof(struct pt_regs));
1132                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1133                 /* function */
1134                 if (usp)
1135                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1136 #ifdef CONFIG_PPC64
1137                 clear_tsk_thread_flag(p, TIF_32BIT);
1138                 childregs->softe = 1;
1139 #endif
1140                 childregs->gpr[15] = arg;
1141                 p->thread.regs = NULL;  /* no user register state */
1142                 ti->flags |= _TIF_RESTOREALL;
1143                 f = ret_from_kernel_thread;
1144         } else {
1145                 struct pt_regs *regs = current_pt_regs();
1146                 CHECK_FULL_REGS(regs);
1147                 *childregs = *regs;
1148                 if (usp)
1149                         childregs->gpr[1] = usp;
1150                 p->thread.regs = childregs;
1151                 childregs->gpr[3] = 0;  /* Result from fork() */
1152                 if (clone_flags & CLONE_SETTLS) {
1153 #ifdef CONFIG_PPC64
1154                         if (!is_32bit_task())
1155                                 childregs->gpr[13] = childregs->gpr[6];
1156                         else
1157 #endif
1158                                 childregs->gpr[2] = childregs->gpr[6];
1159                 }
1160
1161                 f = ret_from_fork;
1162         }
1163         sp -= STACK_FRAME_OVERHEAD;
1164
1165         /*
1166          * The way this works is that at some point in the future
1167          * some task will call _switch to switch to the new task.
1168          * That will pop off the stack frame created below and start
1169          * the new task running at ret_from_fork.  The new task will
1170          * do some house keeping and then return from the fork or clone
1171          * system call, using the stack frame created above.
1172          */
1173         ((unsigned long *)sp)[0] = 0;
1174         sp -= sizeof(struct pt_regs);
1175         kregs = (struct pt_regs *) sp;
1176         sp -= STACK_FRAME_OVERHEAD;
1177         p->thread.ksp = sp;
1178 #ifdef CONFIG_PPC32
1179         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1180                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1181 #endif
1182 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1183         p->thread.ptrace_bps[0] = NULL;
1184 #endif
1185
1186         p->thread.fp_save_area = NULL;
1187 #ifdef CONFIG_ALTIVEC
1188         p->thread.vr_save_area = NULL;
1189 #endif
1190
1191         setup_ksp_vsid(p, sp);
1192
1193 #ifdef CONFIG_PPC64
1194         if (cpu_has_feature(CPU_FTR_DSCR)) {
1195                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1196                 p->thread.dscr = current->thread.dscr;
1197         }
1198         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1199                 p->thread.ppr = INIT_PPR;
1200 #endif
1201         kregs->nip = ppc_function_entry(f);
1202         return 0;
1203 }
1204
1205 /*
1206  * Set up a thread for executing a new program
1207  */
1208 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1209 {
1210 #ifdef CONFIG_PPC64
1211         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1212 #endif
1213
1214         /*
1215          * If we exec out of a kernel thread then thread.regs will not be
1216          * set.  Do it now.
1217          */
1218         if (!current->thread.regs) {
1219                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1220                 current->thread.regs = regs - 1;
1221         }
1222
1223         memset(regs->gpr, 0, sizeof(regs->gpr));
1224         regs->ctr = 0;
1225         regs->link = 0;
1226         regs->xer = 0;
1227         regs->ccr = 0;
1228         regs->gpr[1] = sp;
1229
1230         /*
1231          * We have just cleared all the nonvolatile GPRs, so make
1232          * FULL_REGS(regs) return true.  This is necessary to allow
1233          * ptrace to examine the thread immediately after exec.
1234          */
1235         regs->trap &= ~1UL;
1236
1237 #ifdef CONFIG_PPC32
1238         regs->mq = 0;
1239         regs->nip = start;
1240         regs->msr = MSR_USER;
1241 #else
1242         if (!is_32bit_task()) {
1243                 unsigned long entry;
1244
1245                 if (is_elf2_task()) {
1246                         /* Look ma, no function descriptors! */
1247                         entry = start;
1248
1249                         /*
1250                          * Ulrich says:
1251                          *   The latest iteration of the ABI requires that when
1252                          *   calling a function (at its global entry point),
1253                          *   the caller must ensure r12 holds the entry point
1254                          *   address (so that the function can quickly
1255                          *   establish addressability).
1256                          */
1257                         regs->gpr[12] = start;
1258                         /* Make sure that's restored on entry to userspace. */
1259                         set_thread_flag(TIF_RESTOREALL);
1260                 } else {
1261                         unsigned long toc;
1262
1263                         /* start is a relocated pointer to the function
1264                          * descriptor for the elf _start routine.  The first
1265                          * entry in the function descriptor is the entry
1266                          * address of _start and the second entry is the TOC
1267                          * value we need to use.
1268                          */
1269                         __get_user(entry, (unsigned long __user *)start);
1270                         __get_user(toc, (unsigned long __user *)start+1);
1271
1272                         /* Check whether the e_entry function descriptor entries
1273                          * need to be relocated before we can use them.
1274                          */
1275                         if (load_addr != 0) {
1276                                 entry += load_addr;
1277                                 toc   += load_addr;
1278                         }
1279                         regs->gpr[2] = toc;
1280                 }
1281                 regs->nip = entry;
1282                 regs->msr = MSR_USER64;
1283         } else {
1284                 regs->nip = start;
1285                 regs->gpr[2] = 0;
1286                 regs->msr = MSR_USER32;
1287         }
1288 #endif
1289         discard_lazy_cpu_state();
1290 #ifdef CONFIG_VSX
1291         current->thread.used_vsr = 0;
1292 #endif
1293         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1294         current->thread.fp_save_area = NULL;
1295 #ifdef CONFIG_ALTIVEC
1296         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1297         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1298         current->thread.vr_save_area = NULL;
1299         current->thread.vrsave = 0;
1300         current->thread.used_vr = 0;
1301 #endif /* CONFIG_ALTIVEC */
1302 #ifdef CONFIG_SPE
1303         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1304         current->thread.acc = 0;
1305         current->thread.spefscr = 0;
1306         current->thread.used_spe = 0;
1307 #endif /* CONFIG_SPE */
1308 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1309         if (cpu_has_feature(CPU_FTR_TM))
1310                 regs->msr |= MSR_TM;
1311         current->thread.tm_tfhar = 0;
1312         current->thread.tm_texasr = 0;
1313         current->thread.tm_tfiar = 0;
1314 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1315 }
1316 EXPORT_SYMBOL(start_thread);
1317
1318 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1319                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1320
1321 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1322 {
1323         struct pt_regs *regs = tsk->thread.regs;
1324
1325         /* This is a bit hairy.  If we are an SPE enabled  processor
1326          * (have embedded fp) we store the IEEE exception enable flags in
1327          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1328          * mode (asyn, precise, disabled) for 'Classic' FP. */
1329         if (val & PR_FP_EXC_SW_ENABLE) {
1330 #ifdef CONFIG_SPE
1331                 if (cpu_has_feature(CPU_FTR_SPE)) {
1332                         /*
1333                          * When the sticky exception bits are set
1334                          * directly by userspace, it must call prctl
1335                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1336                          * in the existing prctl settings) or
1337                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1338                          * the bits being set).  <fenv.h> functions
1339                          * saving and restoring the whole
1340                          * floating-point environment need to do so
1341                          * anyway to restore the prctl settings from
1342                          * the saved environment.
1343                          */
1344                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1345                         tsk->thread.fpexc_mode = val &
1346                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1347                         return 0;
1348                 } else {
1349                         return -EINVAL;
1350                 }
1351 #else
1352                 return -EINVAL;
1353 #endif
1354         }
1355
1356         /* on a CONFIG_SPE this does not hurt us.  The bits that
1357          * __pack_fe01 use do not overlap with bits used for
1358          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1359          * on CONFIG_SPE implementations are reserved so writing to
1360          * them does not change anything */
1361         if (val > PR_FP_EXC_PRECISE)
1362                 return -EINVAL;
1363         tsk->thread.fpexc_mode = __pack_fe01(val);
1364         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1365                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1366                         | tsk->thread.fpexc_mode;
1367         return 0;
1368 }
1369
1370 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1371 {
1372         unsigned int val;
1373
1374         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1375 #ifdef CONFIG_SPE
1376                 if (cpu_has_feature(CPU_FTR_SPE)) {
1377                         /*
1378                          * When the sticky exception bits are set
1379                          * directly by userspace, it must call prctl
1380                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1381                          * in the existing prctl settings) or
1382                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1383                          * the bits being set).  <fenv.h> functions
1384                          * saving and restoring the whole
1385                          * floating-point environment need to do so
1386                          * anyway to restore the prctl settings from
1387                          * the saved environment.
1388                          */
1389                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1390                         val = tsk->thread.fpexc_mode;
1391                 } else
1392                         return -EINVAL;
1393 #else
1394                 return -EINVAL;
1395 #endif
1396         else
1397                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1398         return put_user(val, (unsigned int __user *) adr);
1399 }
1400
1401 int set_endian(struct task_struct *tsk, unsigned int val)
1402 {
1403         struct pt_regs *regs = tsk->thread.regs;
1404
1405         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1406             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1407                 return -EINVAL;
1408
1409         if (regs == NULL)
1410                 return -EINVAL;
1411
1412         if (val == PR_ENDIAN_BIG)
1413                 regs->msr &= ~MSR_LE;
1414         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1415                 regs->msr |= MSR_LE;
1416         else
1417                 return -EINVAL;
1418
1419         return 0;
1420 }
1421
1422 int get_endian(struct task_struct *tsk, unsigned long adr)
1423 {
1424         struct pt_regs *regs = tsk->thread.regs;
1425         unsigned int val;
1426
1427         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1428             !cpu_has_feature(CPU_FTR_REAL_LE))
1429                 return -EINVAL;
1430
1431         if (regs == NULL)
1432                 return -EINVAL;
1433
1434         if (regs->msr & MSR_LE) {
1435                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1436                         val = PR_ENDIAN_LITTLE;
1437                 else
1438                         val = PR_ENDIAN_PPC_LITTLE;
1439         } else
1440                 val = PR_ENDIAN_BIG;
1441
1442         return put_user(val, (unsigned int __user *)adr);
1443 }
1444
1445 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1446 {
1447         tsk->thread.align_ctl = val;
1448         return 0;
1449 }
1450
1451 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1452 {
1453         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1454 }
1455
1456 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1457                                   unsigned long nbytes)
1458 {
1459         unsigned long stack_page;
1460         unsigned long cpu = task_cpu(p);
1461
1462         /*
1463          * Avoid crashing if the stack has overflowed and corrupted
1464          * task_cpu(p), which is in the thread_info struct.
1465          */
1466         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1467                 stack_page = (unsigned long) hardirq_ctx[cpu];
1468                 if (sp >= stack_page + sizeof(struct thread_struct)
1469                     && sp <= stack_page + THREAD_SIZE - nbytes)
1470                         return 1;
1471
1472                 stack_page = (unsigned long) softirq_ctx[cpu];
1473                 if (sp >= stack_page + sizeof(struct thread_struct)
1474                     && sp <= stack_page + THREAD_SIZE - nbytes)
1475                         return 1;
1476         }
1477         return 0;
1478 }
1479
1480 int validate_sp(unsigned long sp, struct task_struct *p,
1481                        unsigned long nbytes)
1482 {
1483         unsigned long stack_page = (unsigned long)task_stack_page(p);
1484
1485         if (sp >= stack_page + sizeof(struct thread_struct)
1486             && sp <= stack_page + THREAD_SIZE - nbytes)
1487                 return 1;
1488
1489         return valid_irq_stack(sp, p, nbytes);
1490 }
1491
1492 EXPORT_SYMBOL(validate_sp);
1493
1494 unsigned long get_wchan(struct task_struct *p)
1495 {
1496         unsigned long ip, sp;
1497         int count = 0;
1498
1499         if (!p || p == current || p->state == TASK_RUNNING)
1500                 return 0;
1501
1502         sp = p->thread.ksp;
1503         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1504                 return 0;
1505
1506         do {
1507                 sp = *(unsigned long *)sp;
1508                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1509                         return 0;
1510                 if (count > 0) {
1511                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1512                         if (!in_sched_functions(ip))
1513                                 return ip;
1514                 }
1515         } while (count++ < 16);
1516         return 0;
1517 }
1518
1519 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1520
1521 void show_stack(struct task_struct *tsk, unsigned long *stack)
1522 {
1523         unsigned long sp, ip, lr, newsp;
1524         int count = 0;
1525         int firstframe = 1;
1526 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1527         int curr_frame = current->curr_ret_stack;
1528         extern void return_to_handler(void);
1529         unsigned long rth = (unsigned long)return_to_handler;
1530 #endif
1531
1532         sp = (unsigned long) stack;
1533         if (tsk == NULL)
1534                 tsk = current;
1535         if (sp == 0) {
1536                 if (tsk == current)
1537                         sp = current_stack_pointer();
1538                 else
1539                         sp = tsk->thread.ksp;
1540         }
1541
1542         lr = 0;
1543         printk("Call Trace:\n");
1544         do {
1545                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1546                         return;
1547
1548                 stack = (unsigned long *) sp;
1549                 newsp = stack[0];
1550                 ip = stack[STACK_FRAME_LR_SAVE];
1551                 if (!firstframe || ip != lr) {
1552                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1553 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1554                         if ((ip == rth) && curr_frame >= 0) {
1555                                 printk(" (%pS)",
1556                                        (void *)current->ret_stack[curr_frame].ret);
1557                                 curr_frame--;
1558                         }
1559 #endif
1560                         if (firstframe)
1561                                 printk(" (unreliable)");
1562                         printk("\n");
1563                 }
1564                 firstframe = 0;
1565
1566                 /*
1567                  * See if this is an exception frame.
1568                  * We look for the "regshere" marker in the current frame.
1569                  */
1570                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1571                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1572                         struct pt_regs *regs = (struct pt_regs *)
1573                                 (sp + STACK_FRAME_OVERHEAD);
1574                         lr = regs->link;
1575                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1576                                regs->trap, (void *)regs->nip, (void *)lr);
1577                         firstframe = 1;
1578                 }
1579
1580                 sp = newsp;
1581         } while (count++ < kstack_depth_to_print);
1582 }
1583
1584 #ifdef CONFIG_PPC64
1585 /* Called with hard IRQs off */
1586 void notrace __ppc64_runlatch_on(void)
1587 {
1588         struct thread_info *ti = current_thread_info();
1589         unsigned long ctrl;
1590
1591         ctrl = mfspr(SPRN_CTRLF);
1592         ctrl |= CTRL_RUNLATCH;
1593         mtspr(SPRN_CTRLT, ctrl);
1594
1595         ti->local_flags |= _TLF_RUNLATCH;
1596 }
1597
1598 /* Called with hard IRQs off */
1599 void notrace __ppc64_runlatch_off(void)
1600 {
1601         struct thread_info *ti = current_thread_info();
1602         unsigned long ctrl;
1603
1604         ti->local_flags &= ~_TLF_RUNLATCH;
1605
1606         ctrl = mfspr(SPRN_CTRLF);
1607         ctrl &= ~CTRL_RUNLATCH;
1608         mtspr(SPRN_CTRLT, ctrl);
1609 }
1610 #endif /* CONFIG_PPC64 */
1611
1612 unsigned long arch_align_stack(unsigned long sp)
1613 {
1614         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1615                 sp -= get_random_int() & ~PAGE_MASK;
1616         return sp & ~0xf;
1617 }
1618
1619 static inline unsigned long brk_rnd(void)
1620 {
1621         unsigned long rnd = 0;
1622
1623         /* 8MB for 32bit, 1GB for 64bit */
1624         if (is_32bit_task())
1625                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1626         else
1627                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1628
1629         return rnd << PAGE_SHIFT;
1630 }
1631
1632 unsigned long arch_randomize_brk(struct mm_struct *mm)
1633 {
1634         unsigned long base = mm->brk;
1635         unsigned long ret;
1636
1637 #ifdef CONFIG_PPC_STD_MMU_64
1638         /*
1639          * If we are using 1TB segments and we are allowed to randomise
1640          * the heap, we can put it above 1TB so it is backed by a 1TB
1641          * segment. Otherwise the heap will be in the bottom 1TB
1642          * which always uses 256MB segments and this may result in a
1643          * performance penalty.
1644          */
1645         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1646                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1647 #endif
1648
1649         ret = PAGE_ALIGN(base + brk_rnd());
1650
1651         if (ret < mm->brk)
1652                 return mm->brk;
1653
1654         return ret;
1655 }
1656