arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define APIC_BROADCAST                  0xFF
  72 #define X2APIC_BROADCAST                0xFFFFFFFFul
  73
  74 #define VEC_POS(v) ((v) & (32 - 1))
  75 #define REG_POS(v) (((v) >> 5) << 4)
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_vector(int vec, void *bitmap)
  83 {
  84         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  88 {
  89         struct kvm_lapic *apic = vcpu->arch.apic;
  90
  91         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  92                 apic_test_vector(vector, apic->regs + APIC_IRR);
  93 }
  94
  95 static inline void apic_set_vector(int vec, void *bitmap)
  96 {
  97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_clear_vector(int vec, void *bitmap)
 101 {
 102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 106 {
 107         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 struct static_key_deferred apic_hw_disabled __read_mostly;
 116 struct static_key_deferred apic_sw_disabled __read_mostly;
 117
 118 static inline int apic_enabled(struct kvm_lapic *apic)
 119 {
 120         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 121 }
 122
 123 #define LVT_MASK        \
 124         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 125
 126 #define LINT_MASK       \
 127         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 128          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 129
 130 static inline int kvm_apic_id(struct kvm_lapic *apic)
 131 {
 132         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 133 }
 134
 135 static void recalculate_apic_map(struct kvm *kvm)
 136 {
 137         struct kvm_apic_map *new, *old = NULL;
 138         struct kvm_vcpu *vcpu;
 139         int i;
 140
 141         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 142
 143         mutex_lock(&kvm->arch.apic_map_lock);
 144
 145         if (!new)
 146                 goto out;
 147
 148         new->ldr_bits = 8;
 149         /* flat mode is default */
 150         new->cid_shift = 8;
 151         new->cid_mask = 0;
 152         new->lid_mask = 0xff;
 153         new->broadcast = APIC_BROADCAST;
 154
 155         kvm_for_each_vcpu(i, vcpu, kvm) {
 156                 struct kvm_lapic *apic = vcpu->arch.apic;
 157
 158                 if (!kvm_apic_present(vcpu))
 159                         continue;
 160
 161                 if (apic_x2apic_mode(apic)) {
 162                         new->ldr_bits = 32;
 163                         new->cid_shift = 16;
 164                         new->cid_mask = new->lid_mask = 0xffff;
 165                         new->broadcast = X2APIC_BROADCAST;
 166                 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
 167                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 168                                                         APIC_DFR_CLUSTER) {
 169                                 new->cid_shift = 4;
 170                                 new->cid_mask = 0xf;
 171                                 new->lid_mask = 0xf;
 172                         } else {
 173                                 new->cid_shift = 8;
 174                                 new->cid_mask = 0;
 175                                 new->lid_mask = 0xff;
 176                         }
 177                 }
 178
 179                 /*
 180                  * All APICs have to be configured in the same mode by an OS.
 181                  * We take advatage of this while building logical id loockup
 182                  * table. After reset APICs are in software disabled mode, so if
 183                  * we find apic with different setting we assume this is the mode
 184                  * OS wants all apics to be in; build lookup table accordingly.
 185                  */
 186                 if (kvm_apic_sw_enabled(apic))
 187                         break;
 188         }
 189
 190         kvm_for_each_vcpu(i, vcpu, kvm) {
 191                 struct kvm_lapic *apic = vcpu->arch.apic;
 192                 u16 cid, lid;
 193                 u32 ldr, aid;
 194
 195                 aid = kvm_apic_id(apic);
 196                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 197                 cid = apic_cluster_id(new, ldr);
 198                 lid = apic_logical_id(new, ldr);
 199
 200                 if (aid < ARRAY_SIZE(new->phys_map))
 201                         new->phys_map[aid] = apic;
 202                 if (lid && cid < ARRAY_SIZE(new->logical_map))
 203                         new->logical_map[cid][ffs(lid) - 1] = apic;
 204         }
 205 out:
 206         old = rcu_dereference_protected(kvm->arch.apic_map,
 207                         lockdep_is_held(&kvm->arch.apic_map_lock));
 208         rcu_assign_pointer(kvm->arch.apic_map, new);
 209         mutex_unlock(&kvm->arch.apic_map_lock);
 210
 211         if (old)
 212                 kfree_rcu(old, rcu);
 213
 214         kvm_vcpu_request_scan_ioapic(kvm);
 215 }
 216
 217 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 218 {
 219         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 220
 221         apic_set_reg(apic, APIC_SPIV, val);
 222
 223         if (enabled != apic->sw_enabled) {
 224                 apic->sw_enabled = enabled;
 225                 if (enabled) {
 226                         static_key_slow_dec_deferred(&apic_sw_disabled);
 227                         recalculate_apic_map(apic->vcpu->kvm);
 228                 } else
 229                         static_key_slow_inc(&apic_sw_disabled.key);
 230         }
 231 }
 232
 233 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 234 {
 235         apic_set_reg(apic, APIC_ID, id << 24);
 236         recalculate_apic_map(apic->vcpu->kvm);
 237 }
 238
 239 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 240 {
 241         apic_set_reg(apic, APIC_LDR, id);
 242         recalculate_apic_map(apic->vcpu->kvm);
 243 }
 244
 245 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 246 {
 247         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 248 }
 249
 250 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 251 {
 252         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 253 }
 254
 255 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 256 {
 257         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 258 }
 259
 260 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 261 {
 262         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 263 }
 264
 265 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 266 {
 267         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 268 }
 269
 270 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 271 {
 272         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 273 }
 274
 275 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 276 {
 277         struct kvm_lapic *apic = vcpu->arch.apic;
 278         struct kvm_cpuid_entry2 *feat;
 279         u32 v = APIC_VERSION;
 280
 281         if (!kvm_vcpu_has_lapic(vcpu))
 282                 return;
 283
 284         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 285         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 286                 v |= APIC_LVR_DIRECTED_EOI;
 287         apic_set_reg(apic, APIC_LVR, v);
 288 }
 289
 290 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 291         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 292         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 293         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 294         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 295         LVT_MASK                /* LVTERR */
 296 };
 297
 298 static int find_highest_vector(void *bitmap)
 299 {
 300         int vec;
 301         u32 *reg;
 302
 303         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 304              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 305                 reg = bitmap + REG_POS(vec);
 306                 if (*reg)
 307                         return fls(*reg) - 1 + vec;
 308         }
 309
 310         return -1;
 311 }
 312
 313 static u8 count_vectors(void *bitmap)
 314 {
 315         int vec;
 316         u32 *reg;
 317         u8 count = 0;
 318
 319         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 320                 reg = bitmap + REG_POS(vec);
 321                 count += hweight32(*reg);
 322         }
 323
 324         return count;
 325 }
 326
 327 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 328 {
 329         u32 i, pir_val;
 330         struct kvm_lapic *apic = vcpu->arch.apic;
 331
 332         for (i = 0; i <= 7; i++) {
 333                 pir_val = xchg(&pir[i], 0);
 334                 if (pir_val)
 335                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 336         }
 337 }
 338 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 339
 340 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 341 {
 342         apic_set_vector(vec, apic->regs + APIC_IRR);
 343         /*
 344          * irr_pending must be true if any interrupt is pending; set it after
 345          * APIC_IRR to avoid race with apic_clear_irr
 346          */
 347         apic->irr_pending = true;
 348 }
 349
 350 static inline int apic_search_irr(struct kvm_lapic *apic)
 351 {
 352         return find_highest_vector(apic->regs + APIC_IRR);
 353 }
 354
 355 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 356 {
 357         int result;
 358
 359         /*
 360          * Note that irr_pending is just a hint. It will be always
 361          * true with virtual interrupt delivery enabled.
 362          */
 363         if (!apic->irr_pending)
 364                 return -1;
 365
 366         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 367         result = apic_search_irr(apic);
 368         ASSERT(result == -1 || result >= 16);
 369
 370         return result;
 371 }
 372
 373 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 374 {
 375         struct kvm_vcpu *vcpu;
 376
 377         vcpu = apic->vcpu;
 378
 379         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
 380                 /* try to update RVI */
 381                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 382                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 383         } else {
 384                 apic->irr_pending = false;
 385                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 386                 if (apic_search_irr(apic) != -1)
 387                         apic->irr_pending = true;
 388         }
 389 }
 390
 391 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 392 {
 393         struct kvm_vcpu *vcpu;
 394
 395         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 396                 return;
 397
 398         vcpu = apic->vcpu;
 399
 400         /*
 401          * With APIC virtualization enabled, all caching is disabled
 402          * because the processor can modify ISR under the hood.  Instead
 403          * just set SVI.
 404          */
 405         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 406                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 407         else {
 408                 ++apic->isr_count;
 409                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 410                 /*
 411                  * ISR (in service register) bit is set when injecting an interrupt.
 412                  * The highest vector is injected. Thus the latest bit set matches
 413                  * the highest bit in ISR.
 414                  */
 415                 apic->highest_isr_cache = vec;
 416         }
 417 }
 418
 419 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 420 {
 421         int result;
 422
 423         /*
 424          * Note that isr_count is always 1, and highest_isr_cache
 425          * is always -1, with APIC virtualization enabled.
 426          */
 427         if (!apic->isr_count)
 428                 return -1;
 429         if (likely(apic->highest_isr_cache != -1))
 430                 return apic->highest_isr_cache;
 431
 432         result = find_highest_vector(apic->regs + APIC_ISR);
 433         ASSERT(result == -1 || result >= 16);
 434
 435         return result;
 436 }
 437
 438 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 439 {
 440         struct kvm_vcpu *vcpu;
 441         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 442                 return;
 443
 444         vcpu = apic->vcpu;
 445
 446         /*
 447          * We do get here for APIC virtualization enabled if the guest
 448          * uses the Hyper-V APIC enlightenment.  In this case we may need
 449          * to trigger a new interrupt delivery by writing the SVI field;
 450          * on the other hand isr_count and highest_isr_cache are unused
 451          * and must be left alone.
 452          */
 453         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 454                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 455                                                apic_find_highest_isr(apic));
 456         else {
 457                 --apic->isr_count;
 458                 BUG_ON(apic->isr_count < 0);
 459                 apic->highest_isr_cache = -1;
 460         }
 461 }
 462
 463 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 464 {
 465         int highest_irr;
 466
 467         /* This may race with setting of irr in __apic_accept_irq() and
 468          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 469          * will cause vmexit immediately and the value will be recalculated
 470          * on the next vmentry.
 471          */
 472         if (!kvm_vcpu_has_lapic(vcpu))
 473                 return 0;
 474         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 475
 476         return highest_irr;
 477 }
 478
 479 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 480                              int vector, int level, int trig_mode,
 481                              unsigned long *dest_map);
 482
 483 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 484                 unsigned long *dest_map)
 485 {
 486         struct kvm_lapic *apic = vcpu->arch.apic;
 487
 488         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 489                         irq->level, irq->trig_mode, dest_map);
 490 }
 491
 492 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 493 {
 494
 495         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 496                                       sizeof(val));
 497 }
 498
 499 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 500 {
 501
 502         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 503                                       sizeof(*val));
 504 }
 505
 506 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 507 {
 508         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 509 }
 510
 511 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 512 {
 513         u8 val;
 514         if (pv_eoi_get_user(vcpu, &val) < 0)
 515                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 516                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 517         return val & 0x1;
 518 }
 519
 520 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 521 {
 522         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 523                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 524                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 525                 return;
 526         }
 527         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 528 }
 529
 530 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 531 {
 532         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 533                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 534                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 535                 return;
 536         }
 537         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 538 }
 539
 540 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 541 {
 542         struct kvm_lapic *apic = vcpu->arch.apic;
 543         int i;
 544
 545         for (i = 0; i < 8; i++)
 546                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 547 }
 548
 549 static void apic_update_ppr(struct kvm_lapic *apic)
 550 {
 551         u32 tpr, isrv, ppr, old_ppr;
 552         int isr;
 553
 554         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 555         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 556         isr = apic_find_highest_isr(apic);
 557         isrv = (isr != -1) ? isr : 0;
 558
 559         if ((tpr & 0xf0) >= (isrv & 0xf0))
 560                 ppr = tpr & 0xff;
 561         else
 562                 ppr = isrv & 0xf0;
 563
 564         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 565                    apic, ppr, isr, isrv);
 566
 567         if (old_ppr != ppr) {
 568                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 569                 if (ppr < old_ppr)
 570                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 571         }
 572 }
 573
 574 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 575 {
 576         apic_set_reg(apic, APIC_TASKPRI, tpr);
 577         apic_update_ppr(apic);
 578 }
 579
 580 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 581 {
 582         return dest == (apic_x2apic_mode(apic) ?
 583                         X2APIC_BROADCAST : APIC_BROADCAST);
 584 }
 585
 586 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 587 {
 588         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 589 }
 590
 591 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 592 {
 593         int result = 0;
 594         u32 logical_id;
 595
 596         if (kvm_apic_broadcast(apic, mda))
 597                 return 1;
 598
 599         if (apic_x2apic_mode(apic)) {
 600                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 601                 return logical_id & mda;
 602         }
 603
 604         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 605
 606         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 607         case APIC_DFR_FLAT:
 608                 if (logical_id & mda)
 609                         result = 1;
 610                 break;
 611         case APIC_DFR_CLUSTER:
 612                 if (((logical_id >> 4) == (mda >> 0x4))
 613                     && (logical_id & mda & 0xf))
 614                         result = 1;
 615                 break;
 616         default:
 617                 apic_debug("Bad DFR vcpu %d: %08x\n",
 618                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 619                 break;
 620         }
 621
 622         return result;
 623 }
 624
 625 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 626                            int short_hand, unsigned int dest, int dest_mode)
 627 {
 628         int result = 0;
 629         struct kvm_lapic *target = vcpu->arch.apic;
 630
 631         apic_debug("target %p, source %p, dest 0x%x, "
 632                    "dest_mode 0x%x, short_hand 0x%x\n",
 633                    target, source, dest, dest_mode, short_hand);
 634
 635         ASSERT(target);
 636         switch (short_hand) {
 637         case APIC_DEST_NOSHORT:
 638                 if (dest_mode == 0)
 639                         /* Physical mode. */
 640                         result = kvm_apic_match_physical_addr(target, dest);
 641                 else
 642                         /* Logical mode. */
 643                         result = kvm_apic_match_logical_addr(target, dest);
 644                 break;
 645         case APIC_DEST_SELF:
 646                 result = (target == source);
 647                 break;
 648         case APIC_DEST_ALLINC:
 649                 result = 1;
 650                 break;
 651         case APIC_DEST_ALLBUT:
 652                 result = (target != source);
 653                 break;
 654         default:
 655                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 656                            short_hand);
 657                 break;
 658         }
 659
 660         return result;
 661 }
 662
 663 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 664                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 665 {
 666         struct kvm_apic_map *map;
 667         unsigned long bitmap = 1;
 668         struct kvm_lapic **dst;
 669         int i;
 670         bool ret = false;
 671
 672         *r = -1;
 673
 674         if (irq->shorthand == APIC_DEST_SELF) {
 675                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 676                 return true;
 677         }
 678
 679         if (irq->shorthand)
 680                 return false;
 681
 682         rcu_read_lock();
 683         map = rcu_dereference(kvm->arch.apic_map);
 684
 685         if (!map)
 686                 goto out;
 687
 688         if (irq->dest_id == map->broadcast)
 689                 goto out;
 690
 691         ret = true;
 692
 693         if (irq->dest_mode == 0) { /* physical mode */
 694                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 695                         goto out;
 696
 697                 dst = &map->phys_map[irq->dest_id];
 698         } else {
 699                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 700                 u16 cid = apic_cluster_id(map, mda);
 701
 702                 if (cid >= ARRAY_SIZE(map->logical_map))
 703                         goto out;
 704
 705                 dst = map->logical_map[cid];
 706
 707                 bitmap = apic_logical_id(map, mda);
 708
 709                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 710                         int l = -1;
 711                         for_each_set_bit(i, &bitmap, 16) {
 712                                 if (!dst[i])
 713                                         continue;
 714                                 if (l < 0)
 715                                         l = i;
 716                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 717                                         l = i;
 718                         }
 719
 720                         bitmap = (l >= 0) ? 1 << l : 0;
 721                 }
 722         }
 723
 724         for_each_set_bit(i, &bitmap, 16) {
 725                 if (!dst[i])
 726                         continue;
 727                 if (*r < 0)
 728                         *r = 0;
 729                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 730         }
 731 out:
 732         rcu_read_unlock();
 733         return ret;
 734 }
 735
 736 /*
 737  * Add a pending IRQ into lapic.
 738  * Return 1 if successfully added and 0 if discarded.
 739  */
 740 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 741                              int vector, int level, int trig_mode,
 742                              unsigned long *dest_map)
 743 {
 744         int result = 0;
 745         struct kvm_vcpu *vcpu = apic->vcpu;
 746
 747         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 748                                   trig_mode, vector);
 749         switch (delivery_mode) {
 750         case APIC_DM_LOWEST:
 751                 vcpu->arch.apic_arb_prio++;
 752         case APIC_DM_FIXED:
 753                 /* FIXME add logic for vcpu on reset */
 754                 if (unlikely(!apic_enabled(apic)))
 755                         break;
 756
 757                 result = 1;
 758
 759                 if (dest_map)
 760                         __set_bit(vcpu->vcpu_id, dest_map);
 761
 762                 if (kvm_x86_ops->deliver_posted_interrupt)
 763                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 764                 else {
 765                         apic_set_irr(vector, apic);
 766
 767                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 768                         kvm_vcpu_kick(vcpu);
 769                 }
 770                 break;
 771
 772         case APIC_DM_REMRD:
 773                 result = 1;
 774                 vcpu->arch.pv.pv_unhalted = 1;
 775                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 776                 kvm_vcpu_kick(vcpu);
 777                 break;
 778
 779         case APIC_DM_SMI:
 780                 apic_debug("Ignoring guest SMI\n");
 781                 break;
 782
 783         case APIC_DM_NMI:
 784                 result = 1;
 785                 kvm_inject_nmi(vcpu);
 786                 kvm_vcpu_kick(vcpu);
 787                 break;
 788
 789         case APIC_DM_INIT:
 790                 if (!trig_mode || level) {
 791                         result = 1;
 792                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 793                         apic->pending_events = (1UL << KVM_APIC_INIT);
 794                         /* make sure pending_events is visible before sending
 795                          * the request */
 796                         smp_wmb();
 797                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 798                         kvm_vcpu_kick(vcpu);
 799                 } else {
 800                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 801                                    vcpu->vcpu_id);
 802                 }
 803                 break;
 804
 805         case APIC_DM_STARTUP:
 806                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 807                            vcpu->vcpu_id, vector);
 808                 result = 1;
 809                 apic->sipi_vector = vector;
 810                 /* make sure sipi_vector is visible for the receiver */
 811                 smp_wmb();
 812                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 813                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 814                 kvm_vcpu_kick(vcpu);
 815                 break;
 816
 817         case APIC_DM_EXTINT:
 818                 /*
 819                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 820                  * before NMI watchdog was enabled. Already handled by
 821                  * kvm_apic_accept_pic_intr().
 822                  */
 823                 break;
 824
 825         default:
 826                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 827                        delivery_mode);
 828                 break;
 829         }
 830         return result;
 831 }
 832
 833 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 834 {
 835         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 836 }
 837
 838 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 839 {
 840         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 841             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 842                 int trigger_mode;
 843                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 844                         trigger_mode = IOAPIC_LEVEL_TRIG;
 845                 else
 846                         trigger_mode = IOAPIC_EDGE_TRIG;
 847                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 848         }
 849 }
 850
 851 static int apic_set_eoi(struct kvm_lapic *apic)
 852 {
 853         int vector = apic_find_highest_isr(apic);
 854
 855         trace_kvm_eoi(apic, vector);
 856
 857         /*
 858          * Not every write EOI will has corresponding ISR,
 859          * one example is when Kernel check timer on setup_IO_APIC
 860          */
 861         if (vector == -1)
 862                 return vector;
 863
 864         apic_clear_isr(vector, apic);
 865         apic_update_ppr(apic);
 866
 867         kvm_ioapic_send_eoi(apic, vector);
 868         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 869         return vector;
 870 }
 871
 872 /*
 873  * this interface assumes a trap-like exit, which has already finished
 874  * desired side effect including vISR and vPPR update.
 875  */
 876 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 877 {
 878         struct kvm_lapic *apic = vcpu->arch.apic;
 879
 880         trace_kvm_eoi(apic, vector);
 881
 882         kvm_ioapic_send_eoi(apic, vector);
 883         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 884 }
 885 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 886
 887 static void apic_send_ipi(struct kvm_lapic *apic)
 888 {
 889         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 890         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 891         struct kvm_lapic_irq irq;
 892
 893         irq.vector = icr_low & APIC_VECTOR_MASK;
 894         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 895         irq.dest_mode = icr_low & APIC_DEST_MASK;
 896         irq.level = icr_low & APIC_INT_ASSERT;
 897         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 898         irq.shorthand = icr_low & APIC_SHORT_MASK;
 899         if (apic_x2apic_mode(apic))
 900                 irq.dest_id = icr_high;
 901         else
 902                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 903
 904         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 905
 906         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 907                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 908                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 909                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 910                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 911                    irq.vector);
 912
 913         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 914 }
 915
 916 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 917 {
 918         ktime_t remaining;
 919         s64 ns;
 920         u32 tmcct;
 921
 922         ASSERT(apic != NULL);
 923
 924         /* if initial count is 0, current count should also be 0 */
 925         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 926                 apic->lapic_timer.period == 0)
 927                 return 0;
 928
 929         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 930         if (ktime_to_ns(remaining) < 0)
 931                 remaining = ktime_set(0, 0);
 932
 933         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 934         tmcct = div64_u64(ns,
 935                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 936
 937         return tmcct;
 938 }
 939
 940 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 941 {
 942         struct kvm_vcpu *vcpu = apic->vcpu;
 943         struct kvm_run *run = vcpu->run;
 944
 945         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 946         run->tpr_access.rip = kvm_rip_read(vcpu);
 947         run->tpr_access.is_write = write;
 948 }
 949
 950 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 951 {
 952         if (apic->vcpu->arch.tpr_access_reporting)
 953                 __report_tpr_access(apic, write);
 954 }
 955
 956 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 957 {
 958         u32 val = 0;
 959
 960         if (offset >= LAPIC_MMIO_LENGTH)
 961                 return 0;
 962
 963         switch (offset) {
 964         case APIC_ID:
 965                 if (apic_x2apic_mode(apic))
 966                         val = kvm_apic_id(apic);
 967                 else
 968                         val = kvm_apic_id(apic) << 24;
 969                 break;
 970         case APIC_ARBPRI:
 971                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 972                 break;
 973
 974         case APIC_TMCCT:        /* Timer CCR */
 975                 if (apic_lvtt_tscdeadline(apic))
 976                         return 0;
 977
 978                 val = apic_get_tmcct(apic);
 979                 break;
 980         case APIC_PROCPRI:
 981                 apic_update_ppr(apic);
 982                 val = kvm_apic_get_reg(apic, offset);
 983                 break;
 984         case APIC_TASKPRI:
 985                 report_tpr_access(apic, false);
 986                 /* fall thru */
 987         default:
 988                 val = kvm_apic_get_reg(apic, offset);
 989                 break;
 990         }
 991
 992         return val;
 993 }
 994
 995 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 996 {
 997         return container_of(dev, struct kvm_lapic, dev);
 998 }
 999
1000 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1001                 void *data)
1002 {
1003         unsigned char alignment = offset & 0xf;
1004         u32 result;
1005         /* this bitmask has a bit cleared for each reserved register */
1006         static const u64 rmask = 0x43ff01ffffffe70cULL;
1007
1008         if ((alignment + len) > 4) {
1009                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1010                            offset, len);
1011                 return 1;
1012         }
1013
1014         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1015                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1016                            offset);
1017                 return 1;
1018         }
1019
1020         result = __apic_read(apic, offset & ~0xf);
1021
1022         trace_kvm_apic_read(offset, result);
1023
1024         switch (len) {
1025         case 1:
1026         case 2:
1027         case 4:
1028                 memcpy(data, (char *)&result + alignment, len);
1029                 break;
1030         default:
1031                 printk(KERN_ERR "Local APIC read with len = %x, "
1032                        "should be 1,2, or 4 instead\n", len);
1033                 break;
1034         }
1035         return 0;
1036 }
1037
1038 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1039 {
1040         return kvm_apic_hw_enabled(apic) &&
1041             addr >= apic->base_address &&
1042             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1043 }
1044
1045 static int apic_mmio_read(struct kvm_io_device *this,
1046                            gpa_t address, int len, void *data)
1047 {
1048         struct kvm_lapic *apic = to_lapic(this);
1049         u32 offset = address - apic->base_address;
1050
1051         if (!apic_mmio_in_range(apic, address))
1052                 return -EOPNOTSUPP;
1053
1054         apic_reg_read(apic, offset, len, data);
1055
1056         return 0;
1057 }
1058
1059 static void update_divide_count(struct kvm_lapic *apic)
1060 {
1061         u32 tmp1, tmp2, tdcr;
1062
1063         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1064         tmp1 = tdcr & 0xf;
1065         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1066         apic->divide_count = 0x1 << (tmp2 & 0x7);
1067
1068         apic_debug("timer divide count is 0x%x\n",
1069                                    apic->divide_count);
1070 }
1071
1072 static void apic_timer_expired(struct kvm_lapic *apic)
1073 {
1074         struct kvm_vcpu *vcpu = apic->vcpu;
1075         wait_queue_head_t *q = &vcpu->wq;
1076
1077         /*
1078          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1079          * vcpu_enter_guest.
1080          */
1081         if (atomic_read(&apic->lapic_timer.pending))
1082                 return;
1083
1084         atomic_inc(&apic->lapic_timer.pending);
1085         /* FIXME: this code should not know anything about vcpus */
1086         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1087
1088         if (waitqueue_active(q))
1089                 wake_up_interruptible(q);
1090 }
1091
1092 static void start_apic_timer(struct kvm_lapic *apic)
1093 {
1094         ktime_t now;
1095         atomic_set(&apic->lapic_timer.pending, 0);
1096
1097         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1098                 /* lapic timer in oneshot or periodic mode */
1099                 now = apic->lapic_timer.timer.base->get_time();
1100                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1101                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1102
1103                 if (!apic->lapic_timer.period)
1104                         return;
1105                 /*
1106                  * Do not allow the guest to program periodic timers with small
1107                  * interval, since the hrtimers are not throttled by the host
1108                  * scheduler.
1109                  */
1110                 if (apic_lvtt_period(apic)) {
1111                         s64 min_period = min_timer_period_us * 1000LL;
1112
1113                         if (apic->lapic_timer.period < min_period) {
1114                                 pr_info_ratelimited(
1115                                     "kvm: vcpu %i: requested %lld ns "
1116                                     "lapic timer period limited to %lld ns\n",
1117                                     apic->vcpu->vcpu_id,
1118                                     apic->lapic_timer.period, min_period);
1119                                 apic->lapic_timer.period = min_period;
1120                         }
1121                 }
1122
1123                 hrtimer_start(&apic->lapic_timer.timer,
1124                               ktime_add_ns(now, apic->lapic_timer.period),
1125                               HRTIMER_MODE_ABS);
1126
1127                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1128                            PRIx64 ", "
1129                            "timer initial count 0x%x, period %lldns, "
1130                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1131                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1132                            kvm_apic_get_reg(apic, APIC_TMICT),
1133                            apic->lapic_timer.period,
1134                            ktime_to_ns(ktime_add_ns(now,
1135                                         apic->lapic_timer.period)));
1136         } else if (apic_lvtt_tscdeadline(apic)) {
1137                 /* lapic timer in tsc deadline mode */
1138                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1139                 u64 ns = 0;
1140                 struct kvm_vcpu *vcpu = apic->vcpu;
1141                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1142                 unsigned long flags;
1143
1144                 if (unlikely(!tscdeadline || !this_tsc_khz))
1145                         return;
1146
1147                 local_irq_save(flags);
1148
1149                 now = apic->lapic_timer.timer.base->get_time();
1150                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1151                 if (likely(tscdeadline > guest_tsc)) {
1152                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1153                         do_div(ns, this_tsc_khz);
1154                         hrtimer_start(&apic->lapic_timer.timer,
1155                                 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1156                 } else
1157                         apic_timer_expired(apic);
1158
1159                 local_irq_restore(flags);
1160         }
1161 }
1162
1163 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1164 {
1165         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1166
1167         if (apic_lvt_nmi_mode(lvt0_val)) {
1168                 if (!nmi_wd_enabled) {
1169                         apic_debug("Receive NMI setting on APIC_LVT0 "
1170                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1171                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1172                 }
1173         } else if (nmi_wd_enabled)
1174                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1175 }
1176
1177 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1178 {
1179         int ret = 0;
1180
1181         trace_kvm_apic_write(reg, val);
1182
1183         switch (reg) {
1184         case APIC_ID:           /* Local APIC ID */
1185                 if (!apic_x2apic_mode(apic))
1186                         kvm_apic_set_id(apic, val >> 24);
1187                 else
1188                         ret = 1;
1189                 break;
1190
1191         case APIC_TASKPRI:
1192                 report_tpr_access(apic, true);
1193                 apic_set_tpr(apic, val & 0xff);
1194                 break;
1195
1196         case APIC_EOI:
1197                 apic_set_eoi(apic);
1198                 break;
1199
1200         case APIC_LDR:
1201                 if (!apic_x2apic_mode(apic))
1202                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1203                 else
1204                         ret = 1;
1205                 break;
1206
1207         case APIC_DFR:
1208                 if (!apic_x2apic_mode(apic)) {
1209                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1210                         recalculate_apic_map(apic->vcpu->kvm);
1211                 } else
1212                         ret = 1;
1213                 break;
1214
1215         case APIC_SPIV: {
1216                 u32 mask = 0x3ff;
1217                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1218                         mask |= APIC_SPIV_DIRECTED_EOI;
1219                 apic_set_spiv(apic, val & mask);
1220                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1221                         int i;
1222                         u32 lvt_val;
1223
1224                         for (i = 0; i < APIC_LVT_NUM; i++) {
1225                                 lvt_val = kvm_apic_get_reg(apic,
1226                                                        APIC_LVTT + 0x10 * i);
1227                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1228                                              lvt_val | APIC_LVT_MASKED);
1229                         }
1230                         atomic_set(&apic->lapic_timer.pending, 0);
1231
1232                 }
1233                 break;
1234         }
1235         case APIC_ICR:
1236                 /* No delay here, so we always clear the pending bit */
1237                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1238                 apic_send_ipi(apic);
1239                 break;
1240
1241         case APIC_ICR2:
1242                 if (!apic_x2apic_mode(apic))
1243                         val &= 0xff000000;
1244                 apic_set_reg(apic, APIC_ICR2, val);
1245                 break;
1246
1247         case APIC_LVT0:
1248                 apic_manage_nmi_watchdog(apic, val);
1249         case APIC_LVTTHMR:
1250         case APIC_LVTPC:
1251         case APIC_LVT1:
1252         case APIC_LVTERR:
1253                 /* TODO: Check vector */
1254                 if (!kvm_apic_sw_enabled(apic))
1255                         val |= APIC_LVT_MASKED;
1256
1257                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1258                 apic_set_reg(apic, reg, val);
1259
1260                 break;
1261
1262         case APIC_LVTT: {
1263                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1264
1265                 if (apic->lapic_timer.timer_mode != timer_mode) {
1266                         apic->lapic_timer.timer_mode = timer_mode;
1267                         hrtimer_cancel(&apic->lapic_timer.timer);
1268                 }
1269
1270                 if (!kvm_apic_sw_enabled(apic))
1271                         val |= APIC_LVT_MASKED;
1272                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1273                 apic_set_reg(apic, APIC_LVTT, val);
1274                 break;
1275         }
1276
1277         case APIC_TMICT:
1278                 if (apic_lvtt_tscdeadline(apic))
1279                         break;
1280
1281                 hrtimer_cancel(&apic->lapic_timer.timer);
1282                 apic_set_reg(apic, APIC_TMICT, val);
1283                 start_apic_timer(apic);
1284                 break;
1285
1286         case APIC_TDCR:
1287                 if (val & 4)
1288                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1289                 apic_set_reg(apic, APIC_TDCR, val);
1290                 update_divide_count(apic);
1291                 break;
1292
1293         case APIC_ESR:
1294                 if (apic_x2apic_mode(apic) && val != 0) {
1295                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1296                         ret = 1;
1297                 }
1298                 break;
1299
1300         case APIC_SELF_IPI:
1301                 if (apic_x2apic_mode(apic)) {
1302                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1303                 } else
1304                         ret = 1;
1305                 break;
1306         default:
1307                 ret = 1;
1308                 break;
1309         }
1310         if (ret)
1311                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1312         return ret;
1313 }
1314
1315 static int apic_mmio_write(struct kvm_io_device *this,
1316                             gpa_t address, int len, const void *data)
1317 {
1318         struct kvm_lapic *apic = to_lapic(this);
1319         unsigned int offset = address - apic->base_address;
1320         u32 val;
1321
1322         if (!apic_mmio_in_range(apic, address))
1323                 return -EOPNOTSUPP;
1324
1325         /*
1326          * APIC register must be aligned on 128-bits boundary.
1327          * 32/64/128 bits registers must be accessed thru 32 bits.
1328          * Refer SDM 8.4.1
1329          */
1330         if (len != 4 || (offset & 0xf)) {
1331                 /* Don't shout loud, $infamous_os would cause only noise. */
1332                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1333                 return 0;
1334         }
1335
1336         val = *(u32*)data;
1337
1338         /* too common printing */
1339         if (offset != APIC_EOI)
1340                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1341                            "0x%x\n", __func__, offset, len, val);
1342
1343         apic_reg_write(apic, offset & 0xff0, val);
1344
1345         return 0;
1346 }
1347
1348 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1349 {
1350         if (kvm_vcpu_has_lapic(vcpu))
1351                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1352 }
1353 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1354
1355 /* emulate APIC access in a trap manner */
1356 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1357 {
1358         u32 val = 0;
1359
1360         /* hw has done the conditional check and inst decode */
1361         offset &= 0xff0;
1362
1363         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1364
1365         /* TODO: optimize to just emulate side effect w/o one more write */
1366         apic_reg_write(vcpu->arch.apic, offset, val);
1367 }
1368 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1369
1370 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1371 {
1372         struct kvm_lapic *apic = vcpu->arch.apic;
1373
1374         if (!vcpu->arch.apic)
1375                 return;
1376
1377         hrtimer_cancel(&apic->lapic_timer.timer);
1378
1379         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1380                 static_key_slow_dec_deferred(&apic_hw_disabled);
1381
1382         if (!apic->sw_enabled)
1383                 static_key_slow_dec_deferred(&apic_sw_disabled);
1384
1385         if (apic->regs)
1386                 free_page((unsigned long)apic->regs);
1387
1388         kfree(apic);
1389 }
1390
1391 /*
1392  *----------------------------------------------------------------------
1393  * LAPIC interface
1394  *----------------------------------------------------------------------
1395  */
1396
1397 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1398 {
1399         struct kvm_lapic *apic = vcpu->arch.apic;
1400
1401         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1402                         apic_lvtt_period(apic))
1403                 return 0;
1404
1405         return apic->lapic_timer.tscdeadline;
1406 }
1407
1408 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1409 {
1410         struct kvm_lapic *apic = vcpu->arch.apic;
1411
1412         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1413                         apic_lvtt_period(apic))
1414                 return;
1415
1416         hrtimer_cancel(&apic->lapic_timer.timer);
1417         apic->lapic_timer.tscdeadline = data;
1418         start_apic_timer(apic);
1419 }
1420
1421 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1422 {
1423         struct kvm_lapic *apic = vcpu->arch.apic;
1424
1425         if (!kvm_vcpu_has_lapic(vcpu))
1426                 return;
1427
1428         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1429                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1430 }
1431
1432 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1433 {
1434         u64 tpr;
1435
1436         if (!kvm_vcpu_has_lapic(vcpu))
1437                 return 0;
1438
1439         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1440
1441         return (tpr & 0xf0) >> 4;
1442 }
1443
1444 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1445 {
1446         u64 old_value = vcpu->arch.apic_base;
1447         struct kvm_lapic *apic = vcpu->arch.apic;
1448
1449         if (!apic) {
1450                 value |= MSR_IA32_APICBASE_BSP;
1451                 vcpu->arch.apic_base = value;
1452                 return;
1453         }
1454
1455         if (!kvm_vcpu_is_bsp(apic->vcpu))
1456                 value &= ~MSR_IA32_APICBASE_BSP;
1457         vcpu->arch.apic_base = value;
1458
1459         /* update jump label if enable bit changes */
1460         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1461                 if (value & MSR_IA32_APICBASE_ENABLE)
1462                         static_key_slow_dec_deferred(&apic_hw_disabled);
1463                 else
1464                         static_key_slow_inc(&apic_hw_disabled.key);
1465                 recalculate_apic_map(vcpu->kvm);
1466         }
1467
1468         if ((old_value ^ value) & X2APIC_ENABLE) {
1469                 if (value & X2APIC_ENABLE) {
1470                         u32 id = kvm_apic_id(apic);
1471                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1472                         kvm_apic_set_ldr(apic, ldr);
1473                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1474                 } else
1475                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1476         }
1477
1478         apic->base_address = apic->vcpu->arch.apic_base &
1479                              MSR_IA32_APICBASE_BASE;
1480
1481         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1482              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1483                 pr_warn_once("APIC base relocation is unsupported by KVM");
1484
1485         /* with FSB delivery interrupt, we can restart APIC functionality */
1486         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1487                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1488
1489 }
1490
1491 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1492 {
1493         struct kvm_lapic *apic;
1494         int i;
1495
1496         apic_debug("%s\n", __func__);
1497
1498         ASSERT(vcpu);
1499         apic = vcpu->arch.apic;
1500         ASSERT(apic != NULL);
1501
1502         /* Stop the timer in case it's a reset to an active apic */
1503         hrtimer_cancel(&apic->lapic_timer.timer);
1504
1505         kvm_apic_set_id(apic, vcpu->vcpu_id);
1506         kvm_apic_set_version(apic->vcpu);
1507
1508         for (i = 0; i < APIC_LVT_NUM; i++)
1509                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1510         apic->lapic_timer.timer_mode = 0;
1511         apic_set_reg(apic, APIC_LVT0,
1512                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1513
1514         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1515         apic_set_spiv(apic, 0xff);
1516         apic_set_reg(apic, APIC_TASKPRI, 0);
1517         kvm_apic_set_ldr(apic, 0);
1518         apic_set_reg(apic, APIC_ESR, 0);
1519         apic_set_reg(apic, APIC_ICR, 0);
1520         apic_set_reg(apic, APIC_ICR2, 0);
1521         apic_set_reg(apic, APIC_TDCR, 0);
1522         apic_set_reg(apic, APIC_TMICT, 0);
1523         for (i = 0; i < 8; i++) {
1524                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1525                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1526                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1527         }
1528         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1529         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1530         apic->highest_isr_cache = -1;
1531         update_divide_count(apic);
1532         atomic_set(&apic->lapic_timer.pending, 0);
1533         if (kvm_vcpu_is_bsp(vcpu))
1534                 kvm_lapic_set_base(vcpu,
1535                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1536         vcpu->arch.pv_eoi.msr_val = 0;
1537         apic_update_ppr(apic);
1538
1539         vcpu->arch.apic_arb_prio = 0;
1540         vcpu->arch.apic_attention = 0;
1541
1542         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1543                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1544                    vcpu, kvm_apic_id(apic),
1545                    vcpu->arch.apic_base, apic->base_address);
1546 }
1547
1548 /*
1549  *----------------------------------------------------------------------
1550  * timer interface
1551  *----------------------------------------------------------------------
1552  */
1553
1554 static bool lapic_is_periodic(struct kvm_lapic *apic)
1555 {
1556         return apic_lvtt_period(apic);
1557 }
1558
1559 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1560 {
1561         struct kvm_lapic *apic = vcpu->arch.apic;
1562
1563         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1564                         apic_lvt_enabled(apic, APIC_LVTT))
1565                 return atomic_read(&apic->lapic_timer.pending);
1566
1567         return 0;
1568 }
1569
1570 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1571 {
1572         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1573         int vector, mode, trig_mode;
1574
1575         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1576                 vector = reg & APIC_VECTOR_MASK;
1577                 mode = reg & APIC_MODE_MASK;
1578                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1579                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1580                                         NULL);
1581         }
1582         return 0;
1583 }
1584
1585 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1586 {
1587         struct kvm_lapic *apic = vcpu->arch.apic;
1588
1589         if (apic)
1590                 kvm_apic_local_deliver(apic, APIC_LVT0);
1591 }
1592
1593 static const struct kvm_io_device_ops apic_mmio_ops = {
1594         .read     = apic_mmio_read,
1595         .write    = apic_mmio_write,
1596 };
1597
1598 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1599 {
1600         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1601         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1602
1603         apic_timer_expired(apic);
1604
1605         if (lapic_is_periodic(apic)) {
1606                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1607                 return HRTIMER_RESTART;
1608         } else
1609                 return HRTIMER_NORESTART;
1610 }
1611
1612 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1613 {
1614         struct kvm_lapic *apic;
1615
1616         ASSERT(vcpu != NULL);
1617         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1618
1619         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1620         if (!apic)
1621                 goto nomem;
1622
1623         vcpu->arch.apic = apic;
1624
1625         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1626         if (!apic->regs) {
1627                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1628                        vcpu->vcpu_id);
1629                 goto nomem_free_apic;
1630         }
1631         apic->vcpu = vcpu;
1632
1633         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1634                      HRTIMER_MODE_ABS);
1635         apic->lapic_timer.timer.function = apic_timer_fn;
1636
1637         /*
1638          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1639          * thinking that APIC satet has changed.
1640          */
1641         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1642         kvm_lapic_set_base(vcpu,
1643                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1644
1645         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1646         kvm_lapic_reset(vcpu);
1647         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1648
1649         return 0;
1650 nomem_free_apic:
1651         kfree(apic);
1652 nomem:
1653         return -ENOMEM;
1654 }
1655
1656 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1657 {
1658         struct kvm_lapic *apic = vcpu->arch.apic;
1659         int highest_irr;
1660
1661         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1662                 return -1;
1663
1664         apic_update_ppr(apic);
1665         highest_irr = apic_find_highest_irr(apic);
1666         if ((highest_irr == -1) ||
1667             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1668                 return -1;
1669         return highest_irr;
1670 }
1671
1672 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1673 {
1674         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1675         int r = 0;
1676
1677         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1678                 r = 1;
1679         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1680             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1681                 r = 1;
1682         return r;
1683 }
1684
1685 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1686 {
1687         struct kvm_lapic *apic = vcpu->arch.apic;
1688
1689         if (!kvm_vcpu_has_lapic(vcpu))
1690                 return;
1691
1692         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1693                 kvm_apic_local_deliver(apic, APIC_LVTT);
1694                 if (apic_lvtt_tscdeadline(apic))
1695                         apic->lapic_timer.tscdeadline = 0;
1696                 atomic_set(&apic->lapic_timer.pending, 0);
1697         }
1698 }
1699
1700 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1701 {
1702         int vector = kvm_apic_has_interrupt(vcpu);
1703         struct kvm_lapic *apic = vcpu->arch.apic;
1704
1705         if (vector == -1)
1706                 return -1;
1707
1708         /*
1709          * We get here even with APIC virtualization enabled, if doing
1710          * nested virtualization and L1 runs with the "acknowledge interrupt
1711          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1712          * because the process would deliver it through the IDT.
1713          */
1714
1715         apic_set_isr(vector, apic);
1716         apic_update_ppr(apic);
1717         apic_clear_irr(vector, apic);
1718         return vector;
1719 }
1720
1721 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1722                 struct kvm_lapic_state *s)
1723 {
1724         struct kvm_lapic *apic = vcpu->arch.apic;
1725
1726         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1727         /* set SPIV separately to get count of SW disabled APICs right */
1728         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1729         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1730         /* call kvm_apic_set_id() to put apic into apic_map */
1731         kvm_apic_set_id(apic, kvm_apic_id(apic));
1732         kvm_apic_set_version(vcpu);
1733
1734         apic_update_ppr(apic);
1735         hrtimer_cancel(&apic->lapic_timer.timer);
1736         update_divide_count(apic);
1737         start_apic_timer(apic);
1738         apic->irr_pending = true;
1739         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1740                                 1 : count_vectors(apic->regs + APIC_ISR);
1741         apic->highest_isr_cache = -1;
1742         if (kvm_x86_ops->hwapic_irr_update)
1743                 kvm_x86_ops->hwapic_irr_update(vcpu,
1744                                 apic_find_highest_irr(apic));
1745         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1746         kvm_make_request(KVM_REQ_EVENT, vcpu);
1747         kvm_rtc_eoi_tracking_restore_one(vcpu);
1748 }
1749
1750 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1751 {
1752         struct hrtimer *timer;
1753
1754         if (!kvm_vcpu_has_lapic(vcpu))
1755                 return;
1756
1757         timer = &vcpu->arch.apic->lapic_timer.timer;
1758         if (hrtimer_cancel(timer))
1759                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1760 }
1761
1762 /*
1763  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1764  *
1765  * Detect whether guest triggered PV EOI since the
1766  * last entry. If yes, set EOI on guests's behalf.
1767  * Clear PV EOI in guest memory in any case.
1768  */
1769 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1770                                         struct kvm_lapic *apic)
1771 {
1772         bool pending;
1773         int vector;
1774         /*
1775          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1776          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1777          *
1778          * KVM_APIC_PV_EOI_PENDING is unset:
1779          *      -> host disabled PV EOI.
1780          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1781          *      -> host enabled PV EOI, guest did not execute EOI yet.
1782          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1783          *      -> host enabled PV EOI, guest executed EOI.
1784          */
1785         BUG_ON(!pv_eoi_enabled(vcpu));
1786         pending = pv_eoi_get_pending(vcpu);
1787         /*
1788          * Clear pending bit in any case: it will be set again on vmentry.
1789          * While this might not be ideal from performance point of view,
1790          * this makes sure pv eoi is only enabled when we know it's safe.
1791          */
1792         pv_eoi_clr_pending(vcpu);
1793         if (pending)
1794                 return;
1795         vector = apic_set_eoi(apic);
1796         trace_kvm_pv_eoi(apic, vector);
1797 }
1798
1799 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1800 {
1801         u32 data;
1802
1803         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1804                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1805
1806         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1807                 return;
1808
1809         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1810                                 sizeof(u32));
1811
1812         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1813 }
1814
1815 /*
1816  * apic_sync_pv_eoi_to_guest - called before vmentry
1817  *
1818  * Detect whether it's safe to enable PV EOI and
1819  * if yes do so.
1820  */
1821 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1822                                         struct kvm_lapic *apic)
1823 {
1824         if (!pv_eoi_enabled(vcpu) ||
1825             /* IRR set or many bits in ISR: could be nested. */
1826             apic->irr_pending ||
1827             /* Cache not set: could be safe but we don't bother. */
1828             apic->highest_isr_cache == -1 ||
1829             /* Need EOI to update ioapic. */
1830             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1831                 /*
1832                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1833                  * so we need not do anything here.
1834                  */
1835                 return;
1836         }
1837
1838         pv_eoi_set_pending(apic->vcpu);
1839 }
1840
1841 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1842 {
1843         u32 data, tpr;
1844         int max_irr, max_isr;
1845         struct kvm_lapic *apic = vcpu->arch.apic;
1846
1847         apic_sync_pv_eoi_to_guest(vcpu, apic);
1848
1849         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1850                 return;
1851
1852         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1853         max_irr = apic_find_highest_irr(apic);
1854         if (max_irr < 0)
1855                 max_irr = 0;
1856         max_isr = apic_find_highest_isr(apic);
1857         if (max_isr < 0)
1858                 max_isr = 0;
1859         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1860
1861         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1862                                 sizeof(u32));
1863 }
1864
1865 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1866 {
1867         if (vapic_addr) {
1868                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1869                                         &vcpu->arch.apic->vapic_cache,
1870                                         vapic_addr, sizeof(u32)))
1871                         return -EINVAL;
1872                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1873         } else {
1874                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1875         }
1876
1877         vcpu->arch.apic->vapic_addr = vapic_addr;
1878         return 0;
1879 }
1880
1881 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1882 {
1883         struct kvm_lapic *apic = vcpu->arch.apic;
1884         u32 reg = (msr - APIC_BASE_MSR) << 4;
1885
1886         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1887                 return 1;
1888
1889         if (reg == APIC_ICR2)
1890                 return 1;
1891
1892         /* if this is ICR write vector before command */
1893         if (reg == APIC_ICR)
1894                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1895         return apic_reg_write(apic, reg, (u32)data);
1896 }
1897
1898 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1899 {
1900         struct kvm_lapic *apic = vcpu->arch.apic;
1901         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1902
1903         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1904                 return 1;
1905
1906         if (reg == APIC_DFR || reg == APIC_ICR2) {
1907                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1908                            reg);
1909                 return 1;
1910         }
1911
1912         if (apic_reg_read(apic, reg, 4, &low))
1913                 return 1;
1914         if (reg == APIC_ICR)
1915                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1916
1917         *data = (((u64)high) << 32) | low;
1918
1919         return 0;
1920 }
1921
1922 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1923 {
1924         struct kvm_lapic *apic = vcpu->arch.apic;
1925
1926         if (!kvm_vcpu_has_lapic(vcpu))
1927                 return 1;
1928
1929         /* if this is ICR write vector before command */
1930         if (reg == APIC_ICR)
1931                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1932         return apic_reg_write(apic, reg, (u32)data);
1933 }
1934
1935 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1936 {
1937         struct kvm_lapic *apic = vcpu->arch.apic;
1938         u32 low, high = 0;
1939
1940         if (!kvm_vcpu_has_lapic(vcpu))
1941                 return 1;
1942
1943         if (apic_reg_read(apic, reg, 4, &low))
1944                 return 1;
1945         if (reg == APIC_ICR)
1946                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1947
1948         *data = (((u64)high) << 32) | low;
1949
1950         return 0;
1951 }
1952
1953 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1954 {
1955         u64 addr = data & ~KVM_MSR_ENABLED;
1956         if (!IS_ALIGNED(addr, 4))
1957                 return 1;
1958
1959         vcpu->arch.pv_eoi.msr_val = data;
1960         if (!pv_eoi_enabled(vcpu))
1961                 return 0;
1962         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1963                                          addr, sizeof(u8));
1964 }
1965
1966 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1967 {
1968         struct kvm_lapic *apic = vcpu->arch.apic;
1969         u8 sipi_vector;
1970         unsigned long pe;
1971
1972         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1973                 return;
1974
1975         pe = xchg(&apic->pending_events, 0);
1976
1977         if (test_bit(KVM_APIC_INIT, &pe)) {
1978                 kvm_lapic_reset(vcpu);
1979                 kvm_vcpu_reset(vcpu);
1980                 if (kvm_vcpu_is_bsp(apic->vcpu))
1981                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1982                 else
1983                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1984         }
1985         if (test_bit(KVM_APIC_SIPI, &pe) &&
1986             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1987                 /* evaluate pending_events before reading the vector */
1988                 smp_rmb();
1989                 sipi_vector = apic->sipi_vector;
1990                 apic_debug("vcpu %d received sipi with vector # %x\n",
1991                          vcpu->vcpu_id, sipi_vector);
1992                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1993                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1994         }
1995 }
1996
1997 void kvm_lapic_init(void)
1998 {
1999         /* do not patch jump label more than once per second */
2000         jump_label_rate_limit(&apic_hw_disabled, HZ);
2001         jump_label_rate_limit(&apic_sw_disabled, HZ);
2002 }