drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  64
  65 static bool cpu_cache_is_coherent(struct drm_device *dev,
  66                                   enum i915_cache_level level)
  67 {
  68         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  69 }
  70
  71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  72 {
  73         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  74                 return true;
  75
  76         return obj->pin_display;
  77 }
  78
  79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  80 {
  81         if (obj->tiling_mode)
  82                 i915_gem_release_mmap(obj);
  83
  84         /* As we do not have an associated fence register, we will force
  85          * a tiling change if we ever need to acquire one.
  86          */
  87         obj->fence_dirty = false;
  88         obj->fence_reg = I915_FENCE_REG_NONE;
  89 }
  90
  91 /* some bookkeeping */
  92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  93                                   size_t size)
  94 {
  95         spin_lock(&dev_priv->mm.object_stat_lock);
  96         dev_priv->mm.object_count++;
  97         dev_priv->mm.object_memory += size;
  98         spin_unlock(&dev_priv->mm.object_stat_lock);
  99 }
 100
 101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 102                                      size_t size)
 103 {
 104         spin_lock(&dev_priv->mm.object_stat_lock);
 105         dev_priv->mm.object_count--;
 106         dev_priv->mm.object_memory -= size;
 107         spin_unlock(&dev_priv->mm.object_stat_lock);
 108 }
 109
 110 static int
 111 i915_gem_wait_for_error(struct i915_gpu_error *error)
 112 {
 113         int ret;
 114
 115 #define EXIT_COND (!i915_reset_in_progress(error) || \
 116                    i915_terminally_wedged(error))
 117         if (EXIT_COND)
 118                 return 0;
 119
 120         /*
 121          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 122          * userspace. If it takes that long something really bad is going on and
 123          * we should simply try to bail out and fail as gracefully as possible.
 124          */
 125         ret = wait_event_interruptible_timeout(error->reset_queue,
 126                                                EXIT_COND,
 127                                                10*HZ);
 128         if (ret == 0) {
 129                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 130                 return -EIO;
 131         } else if (ret < 0) {
 132                 return ret;
 133         }
 134 #undef EXIT_COND
 135
 136         return 0;
 137 }
 138
 139 int i915_mutex_lock_interruptible(struct drm_device *dev)
 140 {
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         int ret;
 143
 144         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 145         if (ret)
 146                 return ret;
 147
 148         ret = mutex_lock_interruptible(&dev->struct_mutex);
 149         if (ret)
 150                 return ret;
 151
 152         WARN_ON(i915_verify_lists(dev));
 153         return 0;
 154 }
 155
 156 static inline bool
 157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 158 {
 159         return i915_gem_obj_bound_any(obj) && !obj->active;
 160 }
 161
 162 int
 163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 164                             struct drm_file *file)
 165 {
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167         struct drm_i915_gem_get_aperture *args = data;
 168         struct drm_i915_gem_object *obj;
 169         size_t pinned;
 170
 171         pinned = 0;
 172         mutex_lock(&dev->struct_mutex);
 173         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 174                 if (i915_gem_obj_is_pinned(obj))
 175                         pinned += i915_gem_obj_ggtt_size(obj);
 176         mutex_unlock(&dev->struct_mutex);
 177
 178         args->aper_size = dev_priv->gtt.base.total;
 179         args->aper_available_size = args->aper_size - pinned;
 180
 181         return 0;
 182 }
 183
 184 static int
 185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 186 {
 187         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 188         char *vaddr = obj->phys_handle->vaddr;
 189         struct sg_table *st;
 190         struct scatterlist *sg;
 191         int i;
 192
 193         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 194                 return -EINVAL;
 195
 196         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 197                 struct page *page;
 198                 char *src;
 199
 200                 page = shmem_read_mapping_page(mapping, i);
 201                 if (IS_ERR(page))
 202                         return PTR_ERR(page);
 203
 204                 src = kmap_atomic(page);
 205                 memcpy(vaddr, src, PAGE_SIZE);
 206                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 207                 kunmap_atomic(src);
 208
 209                 page_cache_release(page);
 210                 vaddr += PAGE_SIZE;
 211         }
 212
 213         i915_gem_chipset_flush(obj->base.dev);
 214
 215         st = kmalloc(sizeof(*st), GFP_KERNEL);
 216         if (st == NULL)
 217                 return -ENOMEM;
 218
 219         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 220                 kfree(st);
 221                 return -ENOMEM;
 222         }
 223
 224         sg = st->sgl;
 225         sg->offset = 0;
 226         sg->length = obj->base.size;
 227
 228         sg_dma_address(sg) = obj->phys_handle->busaddr;
 229         sg_dma_len(sg) = obj->base.size;
 230
 231         obj->pages = st;
 232         obj->has_dma_mapping = true;
 233         return 0;
 234 }
 235
 236 static void
 237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 238 {
 239         int ret;
 240
 241         BUG_ON(obj->madv == __I915_MADV_PURGED);
 242
 243         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 244         if (ret) {
 245                 /* In the event of a disaster, abandon all caches and
 246                  * hope for the best.
 247                  */
 248                 WARN_ON(ret != -EIO);
 249                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 250         }
 251
 252         if (obj->madv == I915_MADV_DONTNEED)
 253                 obj->dirty = 0;
 254
 255         if (obj->dirty) {
 256                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 257                 char *vaddr = obj->phys_handle->vaddr;
 258                 int i;
 259
 260                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 261                         struct page *page;
 262                         char *dst;
 263
 264                         page = shmem_read_mapping_page(mapping, i);
 265                         if (IS_ERR(page))
 266                                 continue;
 267
 268                         dst = kmap_atomic(page);
 269                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 270                         memcpy(dst, vaddr, PAGE_SIZE);
 271                         kunmap_atomic(dst);
 272
 273                         set_page_dirty(page);
 274                         if (obj->madv == I915_MADV_WILLNEED)
 275                                 mark_page_accessed(page);
 276                         page_cache_release(page);
 277                         vaddr += PAGE_SIZE;
 278                 }
 279                 obj->dirty = 0;
 280         }
 281
 282         sg_free_table(obj->pages);
 283         kfree(obj->pages);
 284
 285         obj->has_dma_mapping = false;
 286 }
 287
 288 static void
 289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 290 {
 291         drm_pci_free(obj->base.dev, obj->phys_handle);
 292 }
 293
 294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 295         .get_pages = i915_gem_object_get_pages_phys,
 296         .put_pages = i915_gem_object_put_pages_phys,
 297         .release = i915_gem_object_release_phys,
 298 };
 299
 300 static int
 301 drop_pages(struct drm_i915_gem_object *obj)
 302 {
 303         struct i915_vma *vma, *next;
 304         int ret;
 305
 306         drm_gem_object_reference(&obj->base);
 307         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 308                 if (i915_vma_unbind(vma))
 309                         break;
 310
 311         ret = i915_gem_object_put_pages(obj);
 312         drm_gem_object_unreference(&obj->base);
 313
 314         return ret;
 315 }
 316
 317 int
 318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 319                             int align)
 320 {
 321         drm_dma_handle_t *phys;
 322         int ret;
 323
 324         if (obj->phys_handle) {
 325                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 326                         return -EBUSY;
 327
 328                 return 0;
 329         }
 330
 331         if (obj->madv != I915_MADV_WILLNEED)
 332                 return -EFAULT;
 333
 334         if (obj->base.filp == NULL)
 335                 return -EINVAL;
 336
 337         ret = drop_pages(obj);
 338         if (ret)
 339                 return ret;
 340
 341         /* create a new object */
 342         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 343         if (!phys)
 344                 return -ENOMEM;
 345
 346         obj->phys_handle = phys;
 347         obj->ops = &i915_gem_phys_ops;
 348
 349         return i915_gem_object_get_pages(obj);
 350 }
 351
 352 static int
 353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 354                      struct drm_i915_gem_pwrite *args,
 355                      struct drm_file *file_priv)
 356 {
 357         struct drm_device *dev = obj->base.dev;
 358         void *vaddr = obj->phys_handle->vaddr + args->offset;
 359         char __user *user_data = to_user_ptr(args->data_ptr);
 360         int ret;
 361
 362         /* We manually control the domain here and pretend that it
 363          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 364          */
 365         ret = i915_gem_object_wait_rendering(obj, false);
 366         if (ret)
 367                 return ret;
 368
 369         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 370                 unsigned long unwritten;
 371
 372                 /* The physical object once assigned is fixed for the lifetime
 373                  * of the obj, so we can safely drop the lock and continue
 374                  * to access vaddr.
 375                  */
 376                 mutex_unlock(&dev->struct_mutex);
 377                 unwritten = copy_from_user(vaddr, user_data, args->size);
 378                 mutex_lock(&dev->struct_mutex);
 379                 if (unwritten)
 380                         return -EFAULT;
 381         }
 382
 383         drm_clflush_virt_range(vaddr, args->size);
 384         i915_gem_chipset_flush(dev);
 385         return 0;
 386 }
 387
 388 void *i915_gem_object_alloc(struct drm_device *dev)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 392 }
 393
 394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 395 {
 396         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 397         kmem_cache_free(dev_priv->slab, obj);
 398 }
 399
 400 static int
 401 i915_gem_create(struct drm_file *file,
 402                 struct drm_device *dev,
 403                 uint64_t size,
 404                 uint32_t *handle_p)
 405 {
 406         struct drm_i915_gem_object *obj;
 407         int ret;
 408         u32 handle;
 409
 410         size = roundup(size, PAGE_SIZE);
 411         if (size == 0)
 412                 return -EINVAL;
 413
 414         /* Allocate the new object */
 415         obj = i915_gem_alloc_object(dev, size);
 416         if (obj == NULL)
 417                 return -ENOMEM;
 418
 419         ret = drm_gem_handle_create(file, &obj->base, &handle);
 420         /* drop reference from allocate - handle holds it now */
 421         drm_gem_object_unreference_unlocked(&obj->base);
 422         if (ret)
 423                 return ret;
 424
 425         *handle_p = handle;
 426         return 0;
 427 }
 428
 429 int
 430 i915_gem_dumb_create(struct drm_file *file,
 431                      struct drm_device *dev,
 432                      struct drm_mode_create_dumb *args)
 433 {
 434         /* have to work out size/pitch and return them */
 435         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 436         args->size = args->pitch * args->height;
 437         return i915_gem_create(file, dev,
 438                                args->size, &args->handle);
 439 }
 440
 441 /**
 442  * Creates a new mm object and returns a handle to it.
 443  */
 444 int
 445 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 446                       struct drm_file *file)
 447 {
 448         struct drm_i915_gem_create *args = data;
 449
 450         return i915_gem_create(file, dev,
 451                                args->size, &args->handle);
 452 }
 453
 454 static inline int
 455 __copy_to_user_swizzled(char __user *cpu_vaddr,
 456                         const char *gpu_vaddr, int gpu_offset,
 457                         int length)
 458 {
 459         int ret, cpu_offset = 0;
 460
 461         while (length > 0) {
 462                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 463                 int this_length = min(cacheline_end - gpu_offset, length);
 464                 int swizzled_gpu_offset = gpu_offset ^ 64;
 465
 466                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 467                                      gpu_vaddr + swizzled_gpu_offset,
 468                                      this_length);
 469                 if (ret)
 470                         return ret + length;
 471
 472                 cpu_offset += this_length;
 473                 gpu_offset += this_length;
 474                 length -= this_length;
 475         }
 476
 477         return 0;
 478 }
 479
 480 static inline int
 481 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 482                           const char __user *cpu_vaddr,
 483                           int length)
 484 {
 485         int ret, cpu_offset = 0;
 486
 487         while (length > 0) {
 488                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 489                 int this_length = min(cacheline_end - gpu_offset, length);
 490                 int swizzled_gpu_offset = gpu_offset ^ 64;
 491
 492                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 493                                        cpu_vaddr + cpu_offset,
 494                                        this_length);
 495                 if (ret)
 496                         return ret + length;
 497
 498                 cpu_offset += this_length;
 499                 gpu_offset += this_length;
 500                 length -= this_length;
 501         }
 502
 503         return 0;
 504 }
 505
 506 /*
 507  * Pins the specified object's pages and synchronizes the object with
 508  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 509  * flush the object from the CPU cache.
 510  */
 511 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 512                                     int *needs_clflush)
 513 {
 514         int ret;
 515
 516         *needs_clflush = 0;
 517
 518         if (!obj->base.filp)
 519                 return -EINVAL;
 520
 521         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 522                 /* If we're not in the cpu read domain, set ourself into the gtt
 523                  * read domain and manually flush cachelines (if required). This
 524                  * optimizes for the case when the gpu will dirty the data
 525                  * anyway again before the next pread happens. */
 526                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 527                                                         obj->cache_level);
 528                 ret = i915_gem_object_wait_rendering(obj, true);
 529                 if (ret)
 530                         return ret;
 531
 532                 i915_gem_object_retire(obj);
 533         }
 534
 535         ret = i915_gem_object_get_pages(obj);
 536         if (ret)
 537                 return ret;
 538
 539         i915_gem_object_pin_pages(obj);
 540
 541         return ret;
 542 }
 543
 544 /* Per-page copy function for the shmem pread fastpath.
 545  * Flushes invalid cachelines before reading the target if
 546  * needs_clflush is set. */
 547 static int
 548 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 549                  char __user *user_data,
 550                  bool page_do_bit17_swizzling, bool needs_clflush)
 551 {
 552         char *vaddr;
 553         int ret;
 554
 555         if (unlikely(page_do_bit17_swizzling))
 556                 return -EINVAL;
 557
 558         vaddr = kmap_atomic(page);
 559         if (needs_clflush)
 560                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 561                                        page_length);
 562         ret = __copy_to_user_inatomic(user_data,
 563                                       vaddr + shmem_page_offset,
 564                                       page_length);
 565         kunmap_atomic(vaddr);
 566
 567         return ret ? -EFAULT : 0;
 568 }
 569
 570 static void
 571 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 572                              bool swizzled)
 573 {
 574         if (unlikely(swizzled)) {
 575                 unsigned long start = (unsigned long) addr;
 576                 unsigned long end = (unsigned long) addr + length;
 577
 578                 /* For swizzling simply ensure that we always flush both
 579                  * channels. Lame, but simple and it works. Swizzled
 580                  * pwrite/pread is far from a hotpath - current userspace
 581                  * doesn't use it at all. */
 582                 start = round_down(start, 128);
 583                 end = round_up(end, 128);
 584
 585                 drm_clflush_virt_range((void *)start, end - start);
 586         } else {
 587                 drm_clflush_virt_range(addr, length);
 588         }
 589
 590 }
 591
 592 /* Only difference to the fast-path function is that this can handle bit17
 593  * and uses non-atomic copy and kmap functions. */
 594 static int
 595 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 596                  char __user *user_data,
 597                  bool page_do_bit17_swizzling, bool needs_clflush)
 598 {
 599         char *vaddr;
 600         int ret;
 601
 602         vaddr = kmap(page);
 603         if (needs_clflush)
 604                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 605                                              page_length,
 606                                              page_do_bit17_swizzling);
 607
 608         if (page_do_bit17_swizzling)
 609                 ret = __copy_to_user_swizzled(user_data,
 610                                               vaddr, shmem_page_offset,
 611                                               page_length);
 612         else
 613                 ret = __copy_to_user(user_data,
 614                                      vaddr + shmem_page_offset,
 615                                      page_length);
 616         kunmap(page);
 617
 618         return ret ? - EFAULT : 0;
 619 }
 620
 621 static int
 622 i915_gem_shmem_pread(struct drm_device *dev,
 623                      struct drm_i915_gem_object *obj,
 624                      struct drm_i915_gem_pread *args,
 625                      struct drm_file *file)
 626 {
 627         char __user *user_data;
 628         ssize_t remain;
 629         loff_t offset;
 630         int shmem_page_offset, page_length, ret = 0;
 631         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 632         int prefaulted = 0;
 633         int needs_clflush = 0;
 634         struct sg_page_iter sg_iter;
 635
 636         user_data = to_user_ptr(args->data_ptr);
 637         remain = args->size;
 638
 639         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 640
 641         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 642         if (ret)
 643                 return ret;
 644
 645         offset = args->offset;
 646
 647         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 648                          offset >> PAGE_SHIFT) {
 649                 struct page *page = sg_page_iter_page(&sg_iter);
 650
 651                 if (remain <= 0)
 652                         break;
 653
 654                 /* Operation in this page
 655                  *
 656                  * shmem_page_offset = offset within page in shmem file
 657                  * page_length = bytes to copy for this page
 658                  */
 659                 shmem_page_offset = offset_in_page(offset);
 660                 page_length = remain;
 661                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 662                         page_length = PAGE_SIZE - shmem_page_offset;
 663
 664                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 665                         (page_to_phys(page) & (1 << 17)) != 0;
 666
 667                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 668                                        user_data, page_do_bit17_swizzling,
 669                                        needs_clflush);
 670                 if (ret == 0)
 671                         goto next_page;
 672
 673                 mutex_unlock(&dev->struct_mutex);
 674
 675                 if (likely(!i915.prefault_disable) && !prefaulted) {
 676                         ret = fault_in_multipages_writeable(user_data, remain);
 677                         /* Userspace is tricking us, but we've already clobbered
 678                          * its pages with the prefault and promised to write the
 679                          * data up to the first fault. Hence ignore any errors
 680                          * and just continue. */
 681                         (void)ret;
 682                         prefaulted = 1;
 683                 }
 684
 685                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 686                                        user_data, page_do_bit17_swizzling,
 687                                        needs_clflush);
 688
 689                 mutex_lock(&dev->struct_mutex);
 690
 691                 if (ret)
 692                         goto out;
 693
 694 next_page:
 695                 remain -= page_length;
 696                 user_data += page_length;
 697                 offset += page_length;
 698         }
 699
 700 out:
 701         i915_gem_object_unpin_pages(obj);
 702
 703         return ret;
 704 }
 705
 706 /**
 707  * Reads data from the object referenced by handle.
 708  *
 709  * On error, the contents of *data are undefined.
 710  */
 711 int
 712 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 713                      struct drm_file *file)
 714 {
 715         struct drm_i915_gem_pread *args = data;
 716         struct drm_i915_gem_object *obj;
 717         int ret = 0;
 718
 719         if (args->size == 0)
 720                 return 0;
 721
 722         if (!access_ok(VERIFY_WRITE,
 723                        to_user_ptr(args->data_ptr),
 724                        args->size))
 725                 return -EFAULT;
 726
 727         ret = i915_mutex_lock_interruptible(dev);
 728         if (ret)
 729                 return ret;
 730
 731         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 732         if (&obj->base == NULL) {
 733                 ret = -ENOENT;
 734                 goto unlock;
 735         }
 736
 737         /* Bounds check source.  */
 738         if (args->offset > obj->base.size ||
 739             args->size > obj->base.size - args->offset) {
 740                 ret = -EINVAL;
 741                 goto out;
 742         }
 743
 744         /* prime objects have no backing filp to GEM pread/pwrite
 745          * pages from.
 746          */
 747         if (!obj->base.filp) {
 748                 ret = -EINVAL;
 749                 goto out;
 750         }
 751
 752         trace_i915_gem_object_pread(obj, args->offset, args->size);
 753
 754         ret = i915_gem_shmem_pread(dev, obj, args, file);
 755
 756 out:
 757         drm_gem_object_unreference(&obj->base);
 758 unlock:
 759         mutex_unlock(&dev->struct_mutex);
 760         return ret;
 761 }
 762
 763 /* This is the fast write path which cannot handle
 764  * page faults in the source data
 765  */
 766
 767 static inline int
 768 fast_user_write(struct io_mapping *mapping,
 769                 loff_t page_base, int page_offset,
 770                 char __user *user_data,
 771                 int length)
 772 {
 773         void __iomem *vaddr_atomic;
 774         void *vaddr;
 775         unsigned long unwritten;
 776
 777         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 778         /* We can use the cpu mem copy function because this is X86. */
 779         vaddr = (void __force*)vaddr_atomic + page_offset;
 780         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 781                                                       user_data, length);
 782         io_mapping_unmap_atomic(vaddr_atomic);
 783         return unwritten;
 784 }
 785
 786 /**
 787  * This is the fast pwrite path, where we copy the data directly from the
 788  * user into the GTT, uncached.
 789  */
 790 static int
 791 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 792                          struct drm_i915_gem_object *obj,
 793                          struct drm_i915_gem_pwrite *args,
 794                          struct drm_file *file)
 795 {
 796         struct drm_i915_private *dev_priv = dev->dev_private;
 797         ssize_t remain;
 798         loff_t offset, page_base;
 799         char __user *user_data;
 800         int page_offset, page_length, ret;
 801
 802         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 803         if (ret)
 804                 goto out;
 805
 806         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 807         if (ret)
 808                 goto out_unpin;
 809
 810         ret = i915_gem_object_put_fence(obj);
 811         if (ret)
 812                 goto out_unpin;
 813
 814         user_data = to_user_ptr(args->data_ptr);
 815         remain = args->size;
 816
 817         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 818
 819         while (remain > 0) {
 820                 /* Operation in this page
 821                  *
 822                  * page_base = page offset within aperture
 823                  * page_offset = offset within page
 824                  * page_length = bytes to copy for this page
 825                  */
 826                 page_base = offset & PAGE_MASK;
 827                 page_offset = offset_in_page(offset);
 828                 page_length = remain;
 829                 if ((page_offset + remain) > PAGE_SIZE)
 830                         page_length = PAGE_SIZE - page_offset;
 831
 832                 /* If we get a fault while copying data, then (presumably) our
 833                  * source page isn't available.  Return the error and we'll
 834                  * retry in the slow path.
 835                  */
 836                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 837                                     page_offset, user_data, page_length)) {
 838                         ret = -EFAULT;
 839                         goto out_unpin;
 840                 }
 841
 842                 remain -= page_length;
 843                 user_data += page_length;
 844                 offset += page_length;
 845         }
 846
 847 out_unpin:
 848         i915_gem_object_ggtt_unpin(obj);
 849 out:
 850         return ret;
 851 }
 852
 853 /* Per-page copy function for the shmem pwrite fastpath.
 854  * Flushes invalid cachelines before writing to the target if
 855  * needs_clflush_before is set and flushes out any written cachelines after
 856  * writing if needs_clflush is set. */
 857 static int
 858 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 859                   char __user *user_data,
 860                   bool page_do_bit17_swizzling,
 861                   bool needs_clflush_before,
 862                   bool needs_clflush_after)
 863 {
 864         char *vaddr;
 865         int ret;
 866
 867         if (unlikely(page_do_bit17_swizzling))
 868                 return -EINVAL;
 869
 870         vaddr = kmap_atomic(page);
 871         if (needs_clflush_before)
 872                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 873                                        page_length);
 874         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 875                                         user_data, page_length);
 876         if (needs_clflush_after)
 877                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 878                                        page_length);
 879         kunmap_atomic(vaddr);
 880
 881         return ret ? -EFAULT : 0;
 882 }
 883
 884 /* Only difference to the fast-path function is that this can handle bit17
 885  * and uses non-atomic copy and kmap functions. */
 886 static int
 887 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 888                   char __user *user_data,
 889                   bool page_do_bit17_swizzling,
 890                   bool needs_clflush_before,
 891                   bool needs_clflush_after)
 892 {
 893         char *vaddr;
 894         int ret;
 895
 896         vaddr = kmap(page);
 897         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 898                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 899                                              page_length,
 900                                              page_do_bit17_swizzling);
 901         if (page_do_bit17_swizzling)
 902                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 903                                                 user_data,
 904                                                 page_length);
 905         else
 906                 ret = __copy_from_user(vaddr + shmem_page_offset,
 907                                        user_data,
 908                                        page_length);
 909         if (needs_clflush_after)
 910                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 911                                              page_length,
 912                                              page_do_bit17_swizzling);
 913         kunmap(page);
 914
 915         return ret ? -EFAULT : 0;
 916 }
 917
 918 static int
 919 i915_gem_shmem_pwrite(struct drm_device *dev,
 920                       struct drm_i915_gem_object *obj,
 921                       struct drm_i915_gem_pwrite *args,
 922                       struct drm_file *file)
 923 {
 924         ssize_t remain;
 925         loff_t offset;
 926         char __user *user_data;
 927         int shmem_page_offset, page_length, ret = 0;
 928         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 929         int hit_slowpath = 0;
 930         int needs_clflush_after = 0;
 931         int needs_clflush_before = 0;
 932         struct sg_page_iter sg_iter;
 933
 934         user_data = to_user_ptr(args->data_ptr);
 935         remain = args->size;
 936
 937         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 938
 939         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 940                 /* If we're not in the cpu write domain, set ourself into the gtt
 941                  * write domain and manually flush cachelines (if required). This
 942                  * optimizes for the case when the gpu will use the data
 943                  * right away and we therefore have to clflush anyway. */
 944                 needs_clflush_after = cpu_write_needs_clflush(obj);
 945                 ret = i915_gem_object_wait_rendering(obj, false);
 946                 if (ret)
 947                         return ret;
 948
 949                 i915_gem_object_retire(obj);
 950         }
 951         /* Same trick applies to invalidate partially written cachelines read
 952          * before writing. */
 953         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 954                 needs_clflush_before =
 955                         !cpu_cache_is_coherent(dev, obj->cache_level);
 956
 957         ret = i915_gem_object_get_pages(obj);
 958         if (ret)
 959                 return ret;
 960
 961         i915_gem_object_pin_pages(obj);
 962
 963         offset = args->offset;
 964         obj->dirty = 1;
 965
 966         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 967                          offset >> PAGE_SHIFT) {
 968                 struct page *page = sg_page_iter_page(&sg_iter);
 969                 int partial_cacheline_write;
 970
 971                 if (remain <= 0)
 972                         break;
 973
 974                 /* Operation in this page
 975                  *
 976                  * shmem_page_offset = offset within page in shmem file
 977                  * page_length = bytes to copy for this page
 978                  */
 979                 shmem_page_offset = offset_in_page(offset);
 980
 981                 page_length = remain;
 982                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 983                         page_length = PAGE_SIZE - shmem_page_offset;
 984
 985                 /* If we don't overwrite a cacheline completely we need to be
 986                  * careful to have up-to-date data by first clflushing. Don't
 987                  * overcomplicate things and flush the entire patch. */
 988                 partial_cacheline_write = needs_clflush_before &&
 989                         ((shmem_page_offset | page_length)
 990                                 & (boot_cpu_data.x86_clflush_size - 1));
 991
 992                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 993                         (page_to_phys(page) & (1 << 17)) != 0;
 994
 995                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 996                                         user_data, page_do_bit17_swizzling,
 997                                         partial_cacheline_write,
 998                                         needs_clflush_after);
 999                 if (ret == 0)
1000                         goto next_page;
1001
1002                 hit_slowpath = 1;
1003                 mutex_unlock(&dev->struct_mutex);
1004                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1005                                         user_data, page_do_bit17_swizzling,
1006                                         partial_cacheline_write,
1007                                         needs_clflush_after);
1008
1009                 mutex_lock(&dev->struct_mutex);
1010
1011                 if (ret)
1012                         goto out;
1013
1014 next_page:
1015                 remain -= page_length;
1016                 user_data += page_length;
1017                 offset += page_length;
1018         }
1019
1020 out:
1021         i915_gem_object_unpin_pages(obj);
1022
1023         if (hit_slowpath) {
1024                 /*
1025                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1026                  * cachelines in-line while writing and the object moved
1027                  * out of the cpu write domain while we've dropped the lock.
1028                  */
1029                 if (!needs_clflush_after &&
1030                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1031                         if (i915_gem_clflush_object(obj, obj->pin_display))
1032                                 i915_gem_chipset_flush(dev);
1033                 }
1034         }
1035
1036         if (needs_clflush_after)
1037                 i915_gem_chipset_flush(dev);
1038
1039         return ret;
1040 }
1041
1042 /**
1043  * Writes data to the object referenced by handle.
1044  *
1045  * On error, the contents of the buffer that were to be modified are undefined.
1046  */
1047 int
1048 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1049                       struct drm_file *file)
1050 {
1051         struct drm_i915_gem_pwrite *args = data;
1052         struct drm_i915_gem_object *obj;
1053         int ret;
1054
1055         if (args->size == 0)
1056                 return 0;
1057
1058         if (!access_ok(VERIFY_READ,
1059                        to_user_ptr(args->data_ptr),
1060                        args->size))
1061                 return -EFAULT;
1062
1063         if (likely(!i915.prefault_disable)) {
1064                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1065                                                    args->size);
1066                 if (ret)
1067                         return -EFAULT;
1068         }
1069
1070         ret = i915_mutex_lock_interruptible(dev);
1071         if (ret)
1072                 return ret;
1073
1074         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1075         if (&obj->base == NULL) {
1076                 ret = -ENOENT;
1077                 goto unlock;
1078         }
1079
1080         /* Bounds check destination. */
1081         if (args->offset > obj->base.size ||
1082             args->size > obj->base.size - args->offset) {
1083                 ret = -EINVAL;
1084                 goto out;
1085         }
1086
1087         /* prime objects have no backing filp to GEM pread/pwrite
1088          * pages from.
1089          */
1090         if (!obj->base.filp) {
1091                 ret = -EINVAL;
1092                 goto out;
1093         }
1094
1095         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1096
1097         ret = -EFAULT;
1098         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099          * it would end up going through the fenced access, and we'll get
1100          * different detiling behavior between reading and writing.
1101          * pread/pwrite currently are reading and writing from the CPU
1102          * perspective, requiring manual detiling by the client.
1103          */
1104         if (obj->tiling_mode == I915_TILING_NONE &&
1105             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1106             cpu_write_needs_clflush(obj)) {
1107                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1108                 /* Note that the gtt paths might fail with non-page-backed user
1109                  * pointers (e.g. gtt mappings when moving data between
1110                  * textures). Fallback to the shmem path in that case. */
1111         }
1112
1113         if (ret == -EFAULT || ret == -ENOSPC) {
1114                 if (obj->phys_handle)
1115                         ret = i915_gem_phys_pwrite(obj, args, file);
1116                 else
1117                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1118         }
1119
1120 out:
1121         drm_gem_object_unreference(&obj->base);
1122 unlock:
1123         mutex_unlock(&dev->struct_mutex);
1124         return ret;
1125 }
1126
1127 int
1128 i915_gem_check_wedge(struct i915_gpu_error *error,
1129                      bool interruptible)
1130 {
1131         if (i915_reset_in_progress(error)) {
1132                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133                  * -EIO unconditionally for these. */
1134                 if (!interruptible)
1135                         return -EIO;
1136
1137                 /* Recovery complete, but the reset failed ... */
1138                 if (i915_terminally_wedged(error))
1139                         return -EIO;
1140
1141                 /*
1142                  * Check if GPU Reset is in progress - we need intel_ring_begin
1143                  * to work properly to reinit the hw state while the gpu is
1144                  * still marked as reset-in-progress. Handle this with a flag.
1145                  */
1146                 if (!error->reload_in_reset)
1147                         return -EAGAIN;
1148         }
1149
1150         return 0;
1151 }
1152
1153 /*
1154  * Compare seqno against outstanding lazy request. Emit a request if they are
1155  * equal.
1156  */
1157 int
1158 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1159 {
1160         int ret;
1161
1162         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1163
1164         ret = 0;
1165         if (seqno == ring->outstanding_lazy_seqno)
1166                 ret = i915_add_request(ring, NULL);
1167
1168         return ret;
1169 }
1170
1171 static void fake_irq(unsigned long data)
1172 {
1173         wake_up_process((struct task_struct *)data);
1174 }
1175
1176 static bool missed_irq(struct drm_i915_private *dev_priv,
1177                        struct intel_engine_cs *ring)
1178 {
1179         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1180 }
1181
1182 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1183 {
1184         if (file_priv == NULL)
1185                 return true;
1186
1187         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1188 }
1189
1190 /**
1191  * __i915_wait_seqno - wait until execution of seqno has finished
1192  * @ring: the ring expected to report seqno
1193  * @seqno: duh!
1194  * @reset_counter: reset sequence associated with the given seqno
1195  * @interruptible: do an interruptible wait (normally yes)
1196  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1197  *
1198  * Note: It is of utmost importance that the passed in seqno and reset_counter
1199  * values have been read by the caller in an smp safe manner. Where read-side
1200  * locks are involved, it is sufficient to read the reset_counter before
1201  * unlocking the lock that protects the seqno. For lockless tricks, the
1202  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1203  * inserted.
1204  *
1205  * Returns 0 if the seqno was found within the alloted time. Else returns the
1206  * errno with remaining time filled in timeout argument.
1207  */
1208 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1209                         unsigned reset_counter,
1210                         bool interruptible,
1211                         s64 *timeout,
1212                         struct drm_i915_file_private *file_priv)
1213 {
1214         struct drm_device *dev = ring->dev;
1215         struct drm_i915_private *dev_priv = dev->dev_private;
1216         const bool irq_test_in_progress =
1217                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1218         DEFINE_WAIT(wait);
1219         unsigned long timeout_expire;
1220         s64 before, now;
1221         int ret;
1222
1223         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1224
1225         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1226                 return 0;
1227
1228         timeout_expire = timeout ?
1229                 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1230
1231         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1232                 gen6_rps_boost(dev_priv);
1233                 if (file_priv)
1234                         mod_delayed_work(dev_priv->wq,
1235                                          &file_priv->mm.idle_work,
1236                                          msecs_to_jiffies(100));
1237         }
1238
1239         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1240                 return -ENODEV;
1241
1242         /* Record current time in case interrupted by signal, or wedged */
1243         trace_i915_gem_request_wait_begin(ring, seqno);
1244         before = ktime_get_raw_ns();
1245         for (;;) {
1246                 struct timer_list timer;
1247
1248                 prepare_to_wait(&ring->irq_queue, &wait,
1249                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1250
1251                 /* We need to check whether any gpu reset happened in between
1252                  * the caller grabbing the seqno and now ... */
1253                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1254                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1255                          * is truely gone. */
1256                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1257                         if (ret == 0)
1258                                 ret = -EAGAIN;
1259                         break;
1260                 }
1261
1262                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1263                         ret = 0;
1264                         break;
1265                 }
1266
1267                 if (interruptible && signal_pending(current)) {
1268                         ret = -ERESTARTSYS;
1269                         break;
1270                 }
1271
1272                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1273                         ret = -ETIME;
1274                         break;
1275                 }
1276
1277                 timer.function = NULL;
1278                 if (timeout || missed_irq(dev_priv, ring)) {
1279                         unsigned long expire;
1280
1281                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1282                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1283                         mod_timer(&timer, expire);
1284                 }
1285
1286                 io_schedule();
1287
1288                 if (timer.function) {
1289                         del_singleshot_timer_sync(&timer);
1290                         destroy_timer_on_stack(&timer);
1291                 }
1292         }
1293         now = ktime_get_raw_ns();
1294         trace_i915_gem_request_wait_end(ring, seqno);
1295
1296         if (!irq_test_in_progress)
1297                 ring->irq_put(ring);
1298
1299         finish_wait(&ring->irq_queue, &wait);
1300
1301         if (timeout) {
1302                 s64 tres = *timeout - (now - before);
1303
1304                 *timeout = tres < 0 ? 0 : tres;
1305
1306                 /*
1307                  * Apparently ktime isn't accurate enough and occasionally has a
1308                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1309                  * things up to make the test happy. We allow up to 1 jiffy.
1310                  *
1311                  * This is a regrssion from the timespec->ktime conversion.
1312                  */
1313                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1314                         *timeout = 0;
1315         }
1316
1317         return ret;
1318 }
1319
1320 /**
1321  * Waits for a sequence number to be signaled, and cleans up the
1322  * request and object lists appropriately for that event.
1323  */
1324 int
1325 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1326 {
1327         struct drm_device *dev = ring->dev;
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         bool interruptible = dev_priv->mm.interruptible;
1330         unsigned reset_counter;
1331         int ret;
1332
1333         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1334         BUG_ON(seqno == 0);
1335
1336         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1337         if (ret)
1338                 return ret;
1339
1340         ret = i915_gem_check_olr(ring, seqno);
1341         if (ret)
1342                 return ret;
1343
1344         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1345         return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
1346                                  NULL, NULL);
1347 }
1348
1349 static int
1350 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1351 {
1352         if (!obj->active)
1353                 return 0;
1354
1355         /* Manually manage the write flush as we may have not yet
1356          * retired the buffer.
1357          *
1358          * Note that the last_write_seqno is always the earlier of
1359          * the two (read/write) seqno, so if we haved successfully waited,
1360          * we know we have passed the last write.
1361          */
1362         obj->last_write_seqno = 0;
1363
1364         return 0;
1365 }
1366
1367 /**
1368  * Ensures that all rendering to the object has completed and the object is
1369  * safe to unbind from the GTT or access from the CPU.
1370  */
1371 static __must_check int
1372 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1373                                bool readonly)
1374 {
1375         struct intel_engine_cs *ring = obj->ring;
1376         u32 seqno;
1377         int ret;
1378
1379         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1380         if (seqno == 0)
1381                 return 0;
1382
1383         ret = i915_wait_seqno(ring, seqno);
1384         if (ret)
1385                 return ret;
1386
1387         return i915_gem_object_wait_rendering__tail(obj);
1388 }
1389
1390 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1391  * as the object state may change during this call.
1392  */
1393 static __must_check int
1394 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1395                                             struct drm_i915_file_private *file_priv,
1396                                             bool readonly)
1397 {
1398         struct drm_device *dev = obj->base.dev;
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         struct intel_engine_cs *ring = obj->ring;
1401         unsigned reset_counter;
1402         u32 seqno;
1403         int ret;
1404
1405         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1406         BUG_ON(!dev_priv->mm.interruptible);
1407
1408         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1409         if (seqno == 0)
1410                 return 0;
1411
1412         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1413         if (ret)
1414                 return ret;
1415
1416         ret = i915_gem_check_olr(ring, seqno);
1417         if (ret)
1418                 return ret;
1419
1420         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1421         mutex_unlock(&dev->struct_mutex);
1422         ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
1423                                 file_priv);
1424         mutex_lock(&dev->struct_mutex);
1425         if (ret)
1426                 return ret;
1427
1428         return i915_gem_object_wait_rendering__tail(obj);
1429 }
1430
1431 /**
1432  * Called when user space prepares to use an object with the CPU, either
1433  * through the mmap ioctl's mapping or a GTT mapping.
1434  */
1435 int
1436 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1437                           struct drm_file *file)
1438 {
1439         struct drm_i915_gem_set_domain *args = data;
1440         struct drm_i915_gem_object *obj;
1441         uint32_t read_domains = args->read_domains;
1442         uint32_t write_domain = args->write_domain;
1443         int ret;
1444
1445         /* Only handle setting domains to types used by the CPU. */
1446         if (write_domain & I915_GEM_GPU_DOMAINS)
1447                 return -EINVAL;
1448
1449         if (read_domains & I915_GEM_GPU_DOMAINS)
1450                 return -EINVAL;
1451
1452         /* Having something in the write domain implies it's in the read
1453          * domain, and only that read domain.  Enforce that in the request.
1454          */
1455         if (write_domain != 0 && read_domains != write_domain)
1456                 return -EINVAL;
1457
1458         ret = i915_mutex_lock_interruptible(dev);
1459         if (ret)
1460                 return ret;
1461
1462         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1463         if (&obj->base == NULL) {
1464                 ret = -ENOENT;
1465                 goto unlock;
1466         }
1467
1468         /* Try to flush the object off the GPU without holding the lock.
1469          * We will repeat the flush holding the lock in the normal manner
1470          * to catch cases where we are gazumped.
1471          */
1472         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1473                                                           file->driver_priv,
1474                                                           !write_domain);
1475         if (ret)
1476                 goto unref;
1477
1478         if (read_domains & I915_GEM_DOMAIN_GTT) {
1479                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1480
1481                 /* Silently promote "you're not bound, there was nothing to do"
1482                  * to success, since the client was just asking us to
1483                  * make sure everything was done.
1484                  */
1485                 if (ret == -EINVAL)
1486                         ret = 0;
1487         } else {
1488                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1489         }
1490
1491 unref:
1492         drm_gem_object_unreference(&obj->base);
1493 unlock:
1494         mutex_unlock(&dev->struct_mutex);
1495         return ret;
1496 }
1497
1498 /**
1499  * Called when user space has done writes to this buffer
1500  */
1501 int
1502 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1503                          struct drm_file *file)
1504 {
1505         struct drm_i915_gem_sw_finish *args = data;
1506         struct drm_i915_gem_object *obj;
1507         int ret = 0;
1508
1509         ret = i915_mutex_lock_interruptible(dev);
1510         if (ret)
1511                 return ret;
1512
1513         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1514         if (&obj->base == NULL) {
1515                 ret = -ENOENT;
1516                 goto unlock;
1517         }
1518
1519         /* Pinned buffers may be scanout, so flush the cache */
1520         if (obj->pin_display)
1521                 i915_gem_object_flush_cpu_write_domain(obj, true);
1522
1523         drm_gem_object_unreference(&obj->base);
1524 unlock:
1525         mutex_unlock(&dev->struct_mutex);
1526         return ret;
1527 }
1528
1529 /**
1530  * Maps the contents of an object, returning the address it is mapped
1531  * into.
1532  *
1533  * While the mapping holds a reference on the contents of the object, it doesn't
1534  * imply a ref on the object itself.
1535  *
1536  * IMPORTANT:
1537  *
1538  * DRM driver writers who look a this function as an example for how to do GEM
1539  * mmap support, please don't implement mmap support like here. The modern way
1540  * to implement DRM mmap support is with an mmap offset ioctl (like
1541  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1542  * That way debug tooling like valgrind will understand what's going on, hiding
1543  * the mmap call in a driver private ioctl will break that. The i915 driver only
1544  * does cpu mmaps this way because we didn't know better.
1545  */
1546 int
1547 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1548                     struct drm_file *file)
1549 {
1550         struct drm_i915_gem_mmap *args = data;
1551         struct drm_gem_object *obj;
1552         unsigned long addr;
1553
1554         obj = drm_gem_object_lookup(dev, file, args->handle);
1555         if (obj == NULL)
1556                 return -ENOENT;
1557
1558         /* prime objects have no backing filp to GEM mmap
1559          * pages from.
1560          */
1561         if (!obj->filp) {
1562                 drm_gem_object_unreference_unlocked(obj);
1563                 return -EINVAL;
1564         }
1565
1566         addr = vm_mmap(obj->filp, 0, args->size,
1567                        PROT_READ | PROT_WRITE, MAP_SHARED,
1568                        args->offset);
1569         drm_gem_object_unreference_unlocked(obj);
1570         if (IS_ERR((void *)addr))
1571                 return addr;
1572
1573         args->addr_ptr = (uint64_t) addr;
1574
1575         return 0;
1576 }
1577
1578 /**
1579  * i915_gem_fault - fault a page into the GTT
1580  * vma: VMA in question
1581  * vmf: fault info
1582  *
1583  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1584  * from userspace.  The fault handler takes care of binding the object to
1585  * the GTT (if needed), allocating and programming a fence register (again,
1586  * only if needed based on whether the old reg is still valid or the object
1587  * is tiled) and inserting a new PTE into the faulting process.
1588  *
1589  * Note that the faulting process may involve evicting existing objects
1590  * from the GTT and/or fence registers to make room.  So performance may
1591  * suffer if the GTT working set is large or there are few fence registers
1592  * left.
1593  */
1594 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1595 {
1596         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1597         struct drm_device *dev = obj->base.dev;
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         pgoff_t page_offset;
1600         unsigned long pfn;
1601         int ret = 0;
1602         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1603
1604         intel_runtime_pm_get(dev_priv);
1605
1606         /* We don't use vmf->pgoff since that has the fake offset */
1607         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1608                 PAGE_SHIFT;
1609
1610         ret = i915_mutex_lock_interruptible(dev);
1611         if (ret)
1612                 goto out;
1613
1614         trace_i915_gem_object_fault(obj, page_offset, true, write);
1615
1616         /* Try to flush the object off the GPU first without holding the lock.
1617          * Upon reacquiring the lock, we will perform our sanity checks and then
1618          * repeat the flush holding the lock in the normal manner to catch cases
1619          * where we are gazumped.
1620          */
1621         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1622         if (ret)
1623                 goto unlock;
1624
1625         /* Access to snoopable pages through the GTT is incoherent. */
1626         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1627                 ret = -EFAULT;
1628                 goto unlock;
1629         }
1630
1631         /* Now bind it into the GTT if needed */
1632         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1633         if (ret)
1634                 goto unlock;
1635
1636         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1637         if (ret)
1638                 goto unpin;
1639
1640         ret = i915_gem_object_get_fence(obj);
1641         if (ret)
1642                 goto unpin;
1643
1644         /* Finally, remap it using the new GTT offset */
1645         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1646         pfn >>= PAGE_SHIFT;
1647
1648         if (!obj->fault_mappable) {
1649                 unsigned long size = min_t(unsigned long,
1650                                            vma->vm_end - vma->vm_start,
1651                                            obj->base.size);
1652                 int i;
1653
1654                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1655                         ret = vm_insert_pfn(vma,
1656                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1657                                             pfn + i);
1658                         if (ret)
1659                                 break;
1660                 }
1661
1662                 obj->fault_mappable = true;
1663         } else
1664                 ret = vm_insert_pfn(vma,
1665                                     (unsigned long)vmf->virtual_address,
1666                                     pfn + page_offset);
1667 unpin:
1668         i915_gem_object_ggtt_unpin(obj);
1669 unlock:
1670         mutex_unlock(&dev->struct_mutex);
1671 out:
1672         switch (ret) {
1673         case -EIO:
1674                 /*
1675                  * We eat errors when the gpu is terminally wedged to avoid
1676                  * userspace unduly crashing (gl has no provisions for mmaps to
1677                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1678                  * and so needs to be reported.
1679                  */
1680                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1681                         ret = VM_FAULT_SIGBUS;
1682                         break;
1683                 }
1684         case -EAGAIN:
1685                 /*
1686                  * EAGAIN means the gpu is hung and we'll wait for the error
1687                  * handler to reset everything when re-faulting in
1688                  * i915_mutex_lock_interruptible.
1689                  */
1690         case 0:
1691         case -ERESTARTSYS:
1692         case -EINTR:
1693         case -EBUSY:
1694                 /*
1695                  * EBUSY is ok: this just means that another thread
1696                  * already did the job.
1697                  */
1698                 ret = VM_FAULT_NOPAGE;
1699                 break;
1700         case -ENOMEM:
1701                 ret = VM_FAULT_OOM;
1702                 break;
1703         case -ENOSPC:
1704         case -EFAULT:
1705                 ret = VM_FAULT_SIGBUS;
1706                 break;
1707         default:
1708                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1709                 ret = VM_FAULT_SIGBUS;
1710                 break;
1711         }
1712
1713         intel_runtime_pm_put(dev_priv);
1714         return ret;
1715 }
1716
1717 /**
1718  * i915_gem_release_mmap - remove physical page mappings
1719  * @obj: obj in question
1720  *
1721  * Preserve the reservation of the mmapping with the DRM core code, but
1722  * relinquish ownership of the pages back to the system.
1723  *
1724  * It is vital that we remove the page mapping if we have mapped a tiled
1725  * object through the GTT and then lose the fence register due to
1726  * resource pressure. Similarly if the object has been moved out of the
1727  * aperture, than pages mapped into userspace must be revoked. Removing the
1728  * mapping will then trigger a page fault on the next user access, allowing
1729  * fixup by i915_gem_fault().
1730  */
1731 void
1732 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1733 {
1734         if (!obj->fault_mappable)
1735                 return;
1736
1737         drm_vma_node_unmap(&obj->base.vma_node,
1738                            obj->base.dev->anon_inode->i_mapping);
1739         obj->fault_mappable = false;
1740 }
1741
1742 void
1743 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1744 {
1745         struct drm_i915_gem_object *obj;
1746
1747         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1748                 i915_gem_release_mmap(obj);
1749 }
1750
1751 uint32_t
1752 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1753 {
1754         uint32_t gtt_size;
1755
1756         if (INTEL_INFO(dev)->gen >= 4 ||
1757             tiling_mode == I915_TILING_NONE)
1758                 return size;
1759
1760         /* Previous chips need a power-of-two fence region when tiling */
1761         if (INTEL_INFO(dev)->gen == 3)
1762                 gtt_size = 1024*1024;
1763         else
1764                 gtt_size = 512*1024;
1765
1766         while (gtt_size < size)
1767                 gtt_size <<= 1;
1768
1769         return gtt_size;
1770 }
1771
1772 /**
1773  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1774  * @obj: object to check
1775  *
1776  * Return the required GTT alignment for an object, taking into account
1777  * potential fence register mapping.
1778  */
1779 uint32_t
1780 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1781                            int tiling_mode, bool fenced)
1782 {
1783         /*
1784          * Minimum alignment is 4k (GTT page size), but might be greater
1785          * if a fence register is needed for the object.
1786          */
1787         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1788             tiling_mode == I915_TILING_NONE)
1789                 return 4096;
1790
1791         /*
1792          * Previous chips need to be aligned to the size of the smallest
1793          * fence register that can contain the object.
1794          */
1795         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1796 }
1797
1798 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1799 {
1800         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1801         int ret;
1802
1803         if (drm_vma_node_has_offset(&obj->base.vma_node))
1804                 return 0;
1805
1806         dev_priv->mm.shrinker_no_lock_stealing = true;
1807
1808         ret = drm_gem_create_mmap_offset(&obj->base);
1809         if (ret != -ENOSPC)
1810                 goto out;
1811
1812         /* Badly fragmented mmap space? The only way we can recover
1813          * space is by destroying unwanted objects. We can't randomly release
1814          * mmap_offsets as userspace expects them to be persistent for the
1815          * lifetime of the objects. The closest we can is to release the
1816          * offsets on purgeable objects by truncating it and marking it purged,
1817          * which prevents userspace from ever using that object again.
1818          */
1819         i915_gem_shrink(dev_priv,
1820                         obj->base.size >> PAGE_SHIFT,
1821                         I915_SHRINK_BOUND |
1822                         I915_SHRINK_UNBOUND |
1823                         I915_SHRINK_PURGEABLE);
1824         ret = drm_gem_create_mmap_offset(&obj->base);
1825         if (ret != -ENOSPC)
1826                 goto out;
1827
1828         i915_gem_shrink_all(dev_priv);
1829         ret = drm_gem_create_mmap_offset(&obj->base);
1830 out:
1831         dev_priv->mm.shrinker_no_lock_stealing = false;
1832
1833         return ret;
1834 }
1835
1836 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1837 {
1838         drm_gem_free_mmap_offset(&obj->base);
1839 }
1840
1841 int
1842 i915_gem_mmap_gtt(struct drm_file *file,
1843                   struct drm_device *dev,
1844                   uint32_t handle,
1845                   uint64_t *offset)
1846 {
1847         struct drm_i915_private *dev_priv = dev->dev_private;
1848         struct drm_i915_gem_object *obj;
1849         int ret;
1850
1851         ret = i915_mutex_lock_interruptible(dev);
1852         if (ret)
1853                 return ret;
1854
1855         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1856         if (&obj->base == NULL) {
1857                 ret = -ENOENT;
1858                 goto unlock;
1859         }
1860
1861         if (obj->base.size > dev_priv->gtt.mappable_end) {
1862                 ret = -E2BIG;
1863                 goto out;
1864         }
1865
1866         if (obj->madv != I915_MADV_WILLNEED) {
1867                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1868                 ret = -EFAULT;
1869                 goto out;
1870         }
1871
1872         ret = i915_gem_object_create_mmap_offset(obj);
1873         if (ret)
1874                 goto out;
1875
1876         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1877
1878 out:
1879         drm_gem_object_unreference(&obj->base);
1880 unlock:
1881         mutex_unlock(&dev->struct_mutex);
1882         return ret;
1883 }
1884
1885 /**
1886  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1887  * @dev: DRM device
1888  * @data: GTT mapping ioctl data
1889  * @file: GEM object info
1890  *
1891  * Simply returns the fake offset to userspace so it can mmap it.
1892  * The mmap call will end up in drm_gem_mmap(), which will set things
1893  * up so we can get faults in the handler above.
1894  *
1895  * The fault handler will take care of binding the object into the GTT
1896  * (since it may have been evicted to make room for something), allocating
1897  * a fence register, and mapping the appropriate aperture address into
1898  * userspace.
1899  */
1900 int
1901 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1902                         struct drm_file *file)
1903 {
1904         struct drm_i915_gem_mmap_gtt *args = data;
1905
1906         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1907 }
1908
1909 static inline int
1910 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1911 {
1912         return obj->madv == I915_MADV_DONTNEED;
1913 }
1914
1915 /* Immediately discard the backing storage */
1916 static void
1917 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1918 {
1919         i915_gem_object_free_mmap_offset(obj);
1920
1921         if (obj->base.filp == NULL)
1922                 return;
1923
1924         /* Our goal here is to return as much of the memory as
1925          * is possible back to the system as we are called from OOM.
1926          * To do this we must instruct the shmfs to drop all of its
1927          * backing pages, *now*.
1928          */
1929         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1930         obj->madv = __I915_MADV_PURGED;
1931 }
1932
1933 /* Try to discard unwanted pages */
1934 static void
1935 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1936 {
1937         struct address_space *mapping;
1938
1939         switch (obj->madv) {
1940         case I915_MADV_DONTNEED:
1941                 i915_gem_object_truncate(obj);
1942         case __I915_MADV_PURGED:
1943                 return;
1944         }
1945
1946         if (obj->base.filp == NULL)
1947                 return;
1948
1949         mapping = file_inode(obj->base.filp)->i_mapping,
1950         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1951 }
1952
1953 static void
1954 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1955 {
1956         struct sg_page_iter sg_iter;
1957         int ret;
1958
1959         BUG_ON(obj->madv == __I915_MADV_PURGED);
1960
1961         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1962         if (ret) {
1963                 /* In the event of a disaster, abandon all caches and
1964                  * hope for the best.
1965                  */
1966                 WARN_ON(ret != -EIO);
1967                 i915_gem_clflush_object(obj, true);
1968                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1969         }
1970
1971         if (i915_gem_object_needs_bit17_swizzle(obj))
1972                 i915_gem_object_save_bit_17_swizzle(obj);
1973
1974         if (obj->madv == I915_MADV_DONTNEED)
1975                 obj->dirty = 0;
1976
1977         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1978                 struct page *page = sg_page_iter_page(&sg_iter);
1979
1980                 if (obj->dirty)
1981                         set_page_dirty(page);
1982
1983                 if (obj->madv == I915_MADV_WILLNEED)
1984                         mark_page_accessed(page);
1985
1986                 page_cache_release(page);
1987         }
1988         obj->dirty = 0;
1989
1990         sg_free_table(obj->pages);
1991         kfree(obj->pages);
1992 }
1993
1994 int
1995 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1996 {
1997         const struct drm_i915_gem_object_ops *ops = obj->ops;
1998
1999         if (obj->pages == NULL)
2000                 return 0;
2001
2002         if (obj->pages_pin_count)
2003                 return -EBUSY;
2004
2005         BUG_ON(i915_gem_obj_bound_any(obj));
2006
2007         /* ->put_pages might need to allocate memory for the bit17 swizzle
2008          * array, hence protect them from being reaped by removing them from gtt
2009          * lists early. */
2010         list_del(&obj->global_list);
2011
2012         ops->put_pages(obj);
2013         obj->pages = NULL;
2014
2015         i915_gem_object_invalidate(obj);
2016
2017         return 0;
2018 }
2019
2020 unsigned long
2021 i915_gem_shrink(struct drm_i915_private *dev_priv,
2022                 long target, unsigned flags)
2023 {
2024         const struct {
2025                 struct list_head *list;
2026                 unsigned int bit;
2027         } phases[] = {
2028                 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2029                 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2030                 { NULL, 0 },
2031         }, *phase;
2032         unsigned long count = 0;
2033
2034         /*
2035          * As we may completely rewrite the (un)bound list whilst unbinding
2036          * (due to retiring requests) we have to strictly process only
2037          * one element of the list at the time, and recheck the list
2038          * on every iteration.
2039          *
2040          * In particular, we must hold a reference whilst removing the
2041          * object as we may end up waiting for and/or retiring the objects.
2042          * This might release the final reference (held by the active list)
2043          * and result in the object being freed from under us. This is
2044          * similar to the precautions the eviction code must take whilst
2045          * removing objects.
2046          *
2047          * Also note that although these lists do not hold a reference to
2048          * the object we can safely grab one here: The final object
2049          * unreferencing and the bound_list are both protected by the
2050          * dev->struct_mutex and so we won't ever be able to observe an
2051          * object on the bound_list with a reference count equals 0.
2052          */
2053         for (phase = phases; phase->list; phase++) {
2054                 struct list_head still_in_list;
2055
2056                 if ((flags & phase->bit) == 0)
2057                         continue;
2058
2059                 INIT_LIST_HEAD(&still_in_list);
2060                 while (count < target && !list_empty(phase->list)) {
2061                         struct drm_i915_gem_object *obj;
2062                         struct i915_vma *vma, *v;
2063
2064                         obj = list_first_entry(phase->list,
2065                                                typeof(*obj), global_list);
2066                         list_move_tail(&obj->global_list, &still_in_list);
2067
2068                         if (flags & I915_SHRINK_PURGEABLE &&
2069                             !i915_gem_object_is_purgeable(obj))
2070                                 continue;
2071
2072                         drm_gem_object_reference(&obj->base);
2073
2074                         /* For the unbound phase, this should be a no-op! */
2075                         list_for_each_entry_safe(vma, v,
2076                                                  &obj->vma_list, vma_link)
2077                                 if (i915_vma_unbind(vma))
2078                                         break;
2079
2080                         if (i915_gem_object_put_pages(obj) == 0)
2081                                 count += obj->base.size >> PAGE_SHIFT;
2082
2083                         drm_gem_object_unreference(&obj->base);
2084                 }
2085                 list_splice(&still_in_list, phase->list);
2086         }
2087
2088         return count;
2089 }
2090
2091 static unsigned long
2092 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2093 {
2094         i915_gem_evict_everything(dev_priv->dev);
2095         return i915_gem_shrink(dev_priv, LONG_MAX,
2096                                I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2097 }
2098
2099 static int
2100 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2101 {
2102         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2103         int page_count, i;
2104         struct address_space *mapping;
2105         struct sg_table *st;
2106         struct scatterlist *sg;
2107         struct sg_page_iter sg_iter;
2108         struct page *page;
2109         unsigned long last_pfn = 0;     /* suppress gcc warning */
2110         gfp_t gfp;
2111
2112         /* Assert that the object is not currently in any GPU domain. As it
2113          * wasn't in the GTT, there shouldn't be any way it could have been in
2114          * a GPU cache
2115          */
2116         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2117         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2118
2119         st = kmalloc(sizeof(*st), GFP_KERNEL);
2120         if (st == NULL)
2121                 return -ENOMEM;
2122
2123         page_count = obj->base.size / PAGE_SIZE;
2124         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2125                 kfree(st);
2126                 return -ENOMEM;
2127         }
2128
2129         /* Get the list of pages out of our struct file.  They'll be pinned
2130          * at this point until we release them.
2131          *
2132          * Fail silently without starting the shrinker
2133          */
2134         mapping = file_inode(obj->base.filp)->i_mapping;
2135         gfp = mapping_gfp_mask(mapping);
2136         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2137         gfp &= ~(__GFP_IO | __GFP_WAIT);
2138         sg = st->sgl;
2139         st->nents = 0;
2140         for (i = 0; i < page_count; i++) {
2141                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2142                 if (IS_ERR(page)) {
2143                         i915_gem_shrink(dev_priv,
2144                                         page_count,
2145                                         I915_SHRINK_BOUND |
2146                                         I915_SHRINK_UNBOUND |
2147                                         I915_SHRINK_PURGEABLE);
2148                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2149                 }
2150                 if (IS_ERR(page)) {
2151                         /* We've tried hard to allocate the memory by reaping
2152                          * our own buffer, now let the real VM do its job and
2153                          * go down in flames if truly OOM.
2154                          */
2155                         i915_gem_shrink_all(dev_priv);
2156                         page = shmem_read_mapping_page(mapping, i);
2157                         if (IS_ERR(page))
2158                                 goto err_pages;
2159                 }
2160 #ifdef CONFIG_SWIOTLB
2161                 if (swiotlb_nr_tbl()) {
2162                         st->nents++;
2163                         sg_set_page(sg, page, PAGE_SIZE, 0);
2164                         sg = sg_next(sg);
2165                         continue;
2166                 }
2167 #endif
2168                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2169                         if (i)
2170                                 sg = sg_next(sg);
2171                         st->nents++;
2172                         sg_set_page(sg, page, PAGE_SIZE, 0);
2173                 } else {
2174                         sg->length += PAGE_SIZE;
2175                 }
2176                 last_pfn = page_to_pfn(page);
2177
2178                 /* Check that the i965g/gm workaround works. */
2179                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2180         }
2181 #ifdef CONFIG_SWIOTLB
2182         if (!swiotlb_nr_tbl())
2183 #endif
2184                 sg_mark_end(sg);
2185         obj->pages = st;
2186
2187         if (i915_gem_object_needs_bit17_swizzle(obj))
2188                 i915_gem_object_do_bit_17_swizzle(obj);
2189
2190         if (obj->tiling_mode != I915_TILING_NONE &&
2191             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2192                 i915_gem_object_pin_pages(obj);
2193
2194         return 0;
2195
2196 err_pages:
2197         sg_mark_end(sg);
2198         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2199                 page_cache_release(sg_page_iter_page(&sg_iter));
2200         sg_free_table(st);
2201         kfree(st);
2202
2203         /* shmemfs first checks if there is enough memory to allocate the page
2204          * and reports ENOSPC should there be insufficient, along with the usual
2205          * ENOMEM for a genuine allocation failure.
2206          *
2207          * We use ENOSPC in our driver to mean that we have run out of aperture
2208          * space and so want to translate the error from shmemfs back to our
2209          * usual understanding of ENOMEM.
2210          */
2211         if (PTR_ERR(page) == -ENOSPC)
2212                 return -ENOMEM;
2213         else
2214                 return PTR_ERR(page);
2215 }
2216
2217 /* Ensure that the associated pages are gathered from the backing storage
2218  * and pinned into our object. i915_gem_object_get_pages() may be called
2219  * multiple times before they are released by a single call to
2220  * i915_gem_object_put_pages() - once the pages are no longer referenced
2221  * either as a result of memory pressure (reaping pages under the shrinker)
2222  * or as the object is itself released.
2223  */
2224 int
2225 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2226 {
2227         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2228         const struct drm_i915_gem_object_ops *ops = obj->ops;
2229         int ret;
2230
2231         if (obj->pages)
2232                 return 0;
2233
2234         if (obj->madv != I915_MADV_WILLNEED) {
2235                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2236                 return -EFAULT;
2237         }
2238
2239         BUG_ON(obj->pages_pin_count);
2240
2241         ret = ops->get_pages(obj);
2242         if (ret)
2243                 return ret;
2244
2245         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2246         return 0;
2247 }
2248
2249 static void
2250 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2251                                struct intel_engine_cs *ring)
2252 {
2253         u32 seqno = intel_ring_get_seqno(ring);
2254
2255         BUG_ON(ring == NULL);
2256         if (obj->ring != ring && obj->last_write_seqno) {
2257                 /* Keep the seqno relative to the current ring */
2258                 obj->last_write_seqno = seqno;
2259         }
2260         obj->ring = ring;
2261
2262         /* Add a reference if we're newly entering the active list. */
2263         if (!obj->active) {
2264                 drm_gem_object_reference(&obj->base);
2265                 obj->active = 1;
2266         }
2267
2268         list_move_tail(&obj->ring_list, &ring->active_list);
2269
2270         obj->last_read_seqno = seqno;
2271 }
2272
2273 void i915_vma_move_to_active(struct i915_vma *vma,
2274                              struct intel_engine_cs *ring)
2275 {
2276         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2277         return i915_gem_object_move_to_active(vma->obj, ring);
2278 }
2279
2280 static void
2281 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2282 {
2283         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284         struct i915_address_space *vm;
2285         struct i915_vma *vma;
2286
2287         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2288         BUG_ON(!obj->active);
2289
2290         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2291                 vma = i915_gem_obj_to_vma(obj, vm);
2292                 if (vma && !list_empty(&vma->mm_list))
2293                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2294         }
2295
2296         intel_fb_obj_flush(obj, true);
2297
2298         list_del_init(&obj->ring_list);
2299         obj->ring = NULL;
2300
2301         obj->last_read_seqno = 0;
2302         obj->last_write_seqno = 0;
2303         obj->base.write_domain = 0;
2304
2305         obj->last_fenced_seqno = 0;
2306
2307         obj->active = 0;
2308         drm_gem_object_unreference(&obj->base);
2309
2310         WARN_ON(i915_verify_lists(dev));
2311 }
2312
2313 static void
2314 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2315 {
2316         struct intel_engine_cs *ring = obj->ring;
2317
2318         if (ring == NULL)
2319                 return;
2320
2321         if (i915_seqno_passed(ring->get_seqno(ring, true),
2322                               obj->last_read_seqno))
2323                 i915_gem_object_move_to_inactive(obj);
2324 }
2325
2326 static int
2327 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2328 {
2329         struct drm_i915_private *dev_priv = dev->dev_private;
2330         struct intel_engine_cs *ring;
2331         int ret, i, j;
2332
2333         /* Carefully retire all requests without writing to the rings */
2334         for_each_ring(ring, dev_priv, i) {
2335                 ret = intel_ring_idle(ring);
2336                 if (ret)
2337                         return ret;
2338         }
2339         i915_gem_retire_requests(dev);
2340
2341         /* Finally reset hw state */
2342         for_each_ring(ring, dev_priv, i) {
2343                 intel_ring_init_seqno(ring, seqno);
2344
2345                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2346                         ring->semaphore.sync_seqno[j] = 0;
2347         }
2348
2349         return 0;
2350 }
2351
2352 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2353 {
2354         struct drm_i915_private *dev_priv = dev->dev_private;
2355         int ret;
2356
2357         if (seqno == 0)
2358                 return -EINVAL;
2359
2360         /* HWS page needs to be set less than what we
2361          * will inject to ring
2362          */
2363         ret = i915_gem_init_seqno(dev, seqno - 1);
2364         if (ret)
2365                 return ret;
2366
2367         /* Carefully set the last_seqno value so that wrap
2368          * detection still works
2369          */
2370         dev_priv->next_seqno = seqno;
2371         dev_priv->last_seqno = seqno - 1;
2372         if (dev_priv->last_seqno == 0)
2373                 dev_priv->last_seqno--;
2374
2375         return 0;
2376 }
2377
2378 int
2379 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2380 {
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382
2383         /* reserve 0 for non-seqno */
2384         if (dev_priv->next_seqno == 0) {
2385                 int ret = i915_gem_init_seqno(dev, 0);
2386                 if (ret)
2387                         return ret;
2388
2389                 dev_priv->next_seqno = 1;
2390         }
2391
2392         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2393         return 0;
2394 }
2395
2396 int __i915_add_request(struct intel_engine_cs *ring,
2397                        struct drm_file *file,
2398                        struct drm_i915_gem_object *obj,
2399                        u32 *out_seqno)
2400 {
2401         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2402         struct drm_i915_gem_request *request;
2403         struct intel_ringbuffer *ringbuf;
2404         u32 request_ring_position, request_start;
2405         int ret;
2406
2407         request = ring->preallocated_lazy_request;
2408         if (WARN_ON(request == NULL))
2409                 return -ENOMEM;
2410
2411         if (i915.enable_execlists) {
2412                 struct intel_context *ctx = request->ctx;
2413                 ringbuf = ctx->engine[ring->id].ringbuf;
2414         } else
2415                 ringbuf = ring->buffer;
2416
2417         request_start = intel_ring_get_tail(ringbuf);
2418         /*
2419          * Emit any outstanding flushes - execbuf can fail to emit the flush
2420          * after having emitted the batchbuffer command. Hence we need to fix
2421          * things up similar to emitting the lazy request. The difference here
2422          * is that the flush _must_ happen before the next request, no matter
2423          * what.
2424          */
2425         if (i915.enable_execlists) {
2426                 ret = logical_ring_flush_all_caches(ringbuf);
2427                 if (ret)
2428                         return ret;
2429         } else {
2430                 ret = intel_ring_flush_all_caches(ring);
2431                 if (ret)
2432                         return ret;
2433         }
2434
2435         /* Record the position of the start of the request so that
2436          * should we detect the updated seqno part-way through the
2437          * GPU processing the request, we never over-estimate the
2438          * position of the head.
2439          */
2440         request_ring_position = intel_ring_get_tail(ringbuf);
2441
2442         if (i915.enable_execlists) {
2443                 ret = ring->emit_request(ringbuf);
2444                 if (ret)
2445                         return ret;
2446         } else {
2447                 ret = ring->add_request(ring);
2448                 if (ret)
2449                         return ret;
2450         }
2451
2452         request->seqno = intel_ring_get_seqno(ring);
2453         request->ring = ring;
2454         request->head = request_start;
2455         request->tail = request_ring_position;
2456
2457         /* Whilst this request exists, batch_obj will be on the
2458          * active_list, and so will hold the active reference. Only when this
2459          * request is retired will the the batch_obj be moved onto the
2460          * inactive_list and lose its active reference. Hence we do not need
2461          * to explicitly hold another reference here.
2462          */
2463         request->batch_obj = obj;
2464
2465         if (!i915.enable_execlists) {
2466                 /* Hold a reference to the current context so that we can inspect
2467                  * it later in case a hangcheck error event fires.
2468                  */
2469                 request->ctx = ring->last_context;
2470                 if (request->ctx)
2471                         i915_gem_context_reference(request->ctx);
2472         }
2473
2474         request->emitted_jiffies = jiffies;
2475         list_add_tail(&request->list, &ring->request_list);
2476         request->file_priv = NULL;
2477
2478         if (file) {
2479                 struct drm_i915_file_private *file_priv = file->driver_priv;
2480
2481                 spin_lock(&file_priv->mm.lock);
2482                 request->file_priv = file_priv;
2483                 list_add_tail(&request->client_list,
2484                               &file_priv->mm.request_list);
2485                 spin_unlock(&file_priv->mm.lock);
2486         }
2487
2488         trace_i915_gem_request_add(ring, request->seqno);
2489         ring->outstanding_lazy_seqno = 0;
2490         ring->preallocated_lazy_request = NULL;
2491
2492         i915_queue_hangcheck(ring->dev);
2493
2494         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2495         queue_delayed_work(dev_priv->wq,
2496                            &dev_priv->mm.retire_work,
2497                            round_jiffies_up_relative(HZ));
2498         intel_mark_busy(dev_priv->dev);
2499
2500         if (out_seqno)
2501                 *out_seqno = request->seqno;
2502         return 0;
2503 }
2504
2505 static inline void
2506 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2507 {
2508         struct drm_i915_file_private *file_priv = request->file_priv;
2509
2510         if (!file_priv)
2511                 return;
2512
2513         spin_lock(&file_priv->mm.lock);
2514         list_del(&request->client_list);
2515         request->file_priv = NULL;
2516         spin_unlock(&file_priv->mm.lock);
2517 }
2518
2519 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2520                                    const struct intel_context *ctx)
2521 {
2522         unsigned long elapsed;
2523
2524         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2525
2526         if (ctx->hang_stats.banned)
2527                 return true;
2528
2529         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2530                 if (!i915_gem_context_is_default(ctx)) {
2531                         DRM_DEBUG("context hanging too fast, banning!\n");
2532                         return true;
2533                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2534                         if (i915_stop_ring_allow_warn(dev_priv))
2535                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2536                         return true;
2537                 }
2538         }
2539
2540         return false;
2541 }
2542
2543 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2544                                   struct intel_context *ctx,
2545                                   const bool guilty)
2546 {
2547         struct i915_ctx_hang_stats *hs;
2548
2549         if (WARN_ON(!ctx))
2550                 return;
2551
2552         hs = &ctx->hang_stats;
2553
2554         if (guilty) {
2555                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2556                 hs->batch_active++;
2557                 hs->guilty_ts = get_seconds();
2558         } else {
2559                 hs->batch_pending++;
2560         }
2561 }
2562
2563 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2564 {
2565         struct intel_context *ctx = request->ctx;
2566
2567         list_del(&request->list);
2568         i915_gem_request_remove_from_client(request);
2569
2570         if (ctx) {
2571                 if (i915.enable_execlists) {
2572                         struct intel_engine_cs *ring = request->ring;
2573
2574                         if (ctx != ring->default_context)
2575                                 intel_lr_context_unpin(ring, ctx);
2576                 }
2577                 i915_gem_context_unreference(ctx);
2578         }
2579         kfree(request);
2580 }
2581
2582 struct drm_i915_gem_request *
2583 i915_gem_find_active_request(struct intel_engine_cs *ring)
2584 {
2585         struct drm_i915_gem_request *request;
2586         u32 completed_seqno;
2587
2588         completed_seqno = ring->get_seqno(ring, false);
2589
2590         list_for_each_entry(request, &ring->request_list, list) {
2591                 if (i915_seqno_passed(completed_seqno, request->seqno))
2592                         continue;
2593
2594                 return request;
2595         }
2596
2597         return NULL;
2598 }
2599
2600 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2601                                        struct intel_engine_cs *ring)
2602 {
2603         struct drm_i915_gem_request *request;
2604         bool ring_hung;
2605
2606         request = i915_gem_find_active_request(ring);
2607
2608         if (request == NULL)
2609                 return;
2610
2611         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2612
2613         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2614
2615         list_for_each_entry_continue(request, &ring->request_list, list)
2616                 i915_set_reset_status(dev_priv, request->ctx, false);
2617 }
2618
2619 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2620                                         struct intel_engine_cs *ring)
2621 {
2622         while (!list_empty(&ring->active_list)) {
2623                 struct drm_i915_gem_object *obj;
2624
2625                 obj = list_first_entry(&ring->active_list,
2626                                        struct drm_i915_gem_object,
2627                                        ring_list);
2628
2629                 i915_gem_object_move_to_inactive(obj);
2630         }
2631
2632         /*
2633          * Clear the execlists queue up before freeing the requests, as those
2634          * are the ones that keep the context and ringbuffer backing objects
2635          * pinned in place.
2636          */
2637         while (!list_empty(&ring->execlist_queue)) {
2638                 struct intel_ctx_submit_request *submit_req;
2639
2640                 submit_req = list_first_entry(&ring->execlist_queue,
2641                                 struct intel_ctx_submit_request,
2642                                 execlist_link);
2643                 list_del(&submit_req->execlist_link);
2644                 intel_runtime_pm_put(dev_priv);
2645                 i915_gem_context_unreference(submit_req->ctx);
2646                 kfree(submit_req);
2647         }
2648
2649         /*
2650          * We must free the requests after all the corresponding objects have
2651          * been moved off active lists. Which is the same order as the normal
2652          * retire_requests function does. This is important if object hold
2653          * implicit references on things like e.g. ppgtt address spaces through
2654          * the request.
2655          */
2656         while (!list_empty(&ring->request_list)) {
2657                 struct drm_i915_gem_request *request;
2658
2659                 request = list_first_entry(&ring->request_list,
2660                                            struct drm_i915_gem_request,
2661                                            list);
2662
2663                 i915_gem_free_request(request);
2664         }
2665
2666         /* These may not have been flush before the reset, do so now */
2667         kfree(ring->preallocated_lazy_request);
2668         ring->preallocated_lazy_request = NULL;
2669         ring->outstanding_lazy_seqno = 0;
2670 }
2671
2672 void i915_gem_restore_fences(struct drm_device *dev)
2673 {
2674         struct drm_i915_private *dev_priv = dev->dev_private;
2675         int i;
2676
2677         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2678                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2679
2680                 /*
2681                  * Commit delayed tiling changes if we have an object still
2682                  * attached to the fence, otherwise just clear the fence.
2683                  */
2684                 if (reg->obj) {
2685                         i915_gem_object_update_fence(reg->obj, reg,
2686                                                      reg->obj->tiling_mode);
2687                 } else {
2688                         i915_gem_write_fence(dev, i, NULL);
2689                 }
2690         }
2691 }
2692
2693 void i915_gem_reset(struct drm_device *dev)
2694 {
2695         struct drm_i915_private *dev_priv = dev->dev_private;
2696         struct intel_engine_cs *ring;
2697         int i;
2698
2699         /*
2700          * Before we free the objects from the requests, we need to inspect
2701          * them for finding the guilty party. As the requests only borrow
2702          * their reference to the objects, the inspection must be done first.
2703          */
2704         for_each_ring(ring, dev_priv, i)
2705                 i915_gem_reset_ring_status(dev_priv, ring);
2706
2707         for_each_ring(ring, dev_priv, i)
2708                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2709
2710         i915_gem_context_reset(dev);
2711
2712         i915_gem_restore_fences(dev);
2713 }
2714
2715 /**
2716  * This function clears the request list as sequence numbers are passed.
2717  */
2718 void
2719 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2720 {
2721         uint32_t seqno;
2722
2723         if (list_empty(&ring->request_list))
2724                 return;
2725
2726         WARN_ON(i915_verify_lists(ring->dev));
2727
2728         seqno = ring->get_seqno(ring, true);
2729
2730         /* Move any buffers on the active list that are no longer referenced
2731          * by the ringbuffer to the flushing/inactive lists as appropriate,
2732          * before we free the context associated with the requests.
2733          */
2734         while (!list_empty(&ring->active_list)) {
2735                 struct drm_i915_gem_object *obj;
2736
2737                 obj = list_first_entry(&ring->active_list,
2738                                       struct drm_i915_gem_object,
2739                                       ring_list);
2740
2741                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2742                         break;
2743
2744                 i915_gem_object_move_to_inactive(obj);
2745         }
2746
2747
2748         while (!list_empty(&ring->request_list)) {
2749                 struct drm_i915_gem_request *request;
2750                 struct intel_ringbuffer *ringbuf;
2751
2752                 request = list_first_entry(&ring->request_list,
2753                                            struct drm_i915_gem_request,
2754                                            list);
2755
2756                 if (!i915_seqno_passed(seqno, request->seqno))
2757                         break;
2758
2759                 trace_i915_gem_request_retire(ring, request->seqno);
2760
2761                 /* This is one of the few common intersection points
2762                  * between legacy ringbuffer submission and execlists:
2763                  * we need to tell them apart in order to find the correct
2764                  * ringbuffer to which the request belongs to.
2765                  */
2766                 if (i915.enable_execlists) {
2767                         struct intel_context *ctx = request->ctx;
2768                         ringbuf = ctx->engine[ring->id].ringbuf;
2769                 } else
2770                         ringbuf = ring->buffer;
2771
2772                 /* We know the GPU must have read the request to have
2773                  * sent us the seqno + interrupt, so use the position
2774                  * of tail of the request to update the last known position
2775                  * of the GPU head.
2776                  */
2777                 ringbuf->last_retired_head = request->tail;
2778
2779                 i915_gem_free_request(request);
2780         }
2781
2782         if (unlikely(ring->trace_irq_seqno &&
2783                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2784                 ring->irq_put(ring);
2785                 ring->trace_irq_seqno = 0;
2786         }
2787
2788         WARN_ON(i915_verify_lists(ring->dev));
2789 }
2790
2791 bool
2792 i915_gem_retire_requests(struct drm_device *dev)
2793 {
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         struct intel_engine_cs *ring;
2796         bool idle = true;
2797         int i;
2798
2799         for_each_ring(ring, dev_priv, i) {
2800                 i915_gem_retire_requests_ring(ring);
2801                 idle &= list_empty(&ring->request_list);
2802                 if (i915.enable_execlists) {
2803                         unsigned long flags;
2804
2805                         spin_lock_irqsave(&ring->execlist_lock, flags);
2806                         idle &= list_empty(&ring->execlist_queue);
2807                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2808
2809                         intel_execlists_retire_requests(ring);
2810                 }
2811         }
2812
2813         if (idle)
2814                 mod_delayed_work(dev_priv->wq,
2815                                    &dev_priv->mm.idle_work,
2816                                    msecs_to_jiffies(100));
2817
2818         return idle;
2819 }
2820
2821 static void
2822 i915_gem_retire_work_handler(struct work_struct *work)
2823 {
2824         struct drm_i915_private *dev_priv =
2825                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2826         struct drm_device *dev = dev_priv->dev;
2827         bool idle;
2828
2829         /* Come back later if the device is busy... */
2830         idle = false;
2831         if (mutex_trylock(&dev->struct_mutex)) {
2832                 idle = i915_gem_retire_requests(dev);
2833                 mutex_unlock(&dev->struct_mutex);
2834         }
2835         if (!idle)
2836                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2837                                    round_jiffies_up_relative(HZ));
2838 }
2839
2840 static void
2841 i915_gem_idle_work_handler(struct work_struct *work)
2842 {
2843         struct drm_i915_private *dev_priv =
2844                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2845
2846         intel_mark_idle(dev_priv->dev);
2847 }
2848
2849 /**
2850  * Ensures that an object will eventually get non-busy by flushing any required
2851  * write domains, emitting any outstanding lazy request and retiring and
2852  * completed requests.
2853  */
2854 static int
2855 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2856 {
2857         int ret;
2858
2859         if (obj->active) {
2860                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2861                 if (ret)
2862                         return ret;
2863
2864                 i915_gem_retire_requests_ring(obj->ring);
2865         }
2866
2867         return 0;
2868 }
2869
2870 /**
2871  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2872  * @DRM_IOCTL_ARGS: standard ioctl arguments
2873  *
2874  * Returns 0 if successful, else an error is returned with the remaining time in
2875  * the timeout parameter.
2876  *  -ETIME: object is still busy after timeout
2877  *  -ERESTARTSYS: signal interrupted the wait
2878  *  -ENONENT: object doesn't exist
2879  * Also possible, but rare:
2880  *  -EAGAIN: GPU wedged
2881  *  -ENOMEM: damn
2882  *  -ENODEV: Internal IRQ fail
2883  *  -E?: The add request failed
2884  *
2885  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2886  * non-zero timeout parameter the wait ioctl will wait for the given number of
2887  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2888  * without holding struct_mutex the object may become re-busied before this
2889  * function completes. A similar but shorter * race condition exists in the busy
2890  * ioctl
2891  */
2892 int
2893 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2894 {
2895         struct drm_i915_private *dev_priv = dev->dev_private;
2896         struct drm_i915_gem_wait *args = data;
2897         struct drm_i915_gem_object *obj;
2898         struct intel_engine_cs *ring = NULL;
2899         unsigned reset_counter;
2900         u32 seqno = 0;
2901         int ret = 0;
2902
2903         if (args->flags != 0)
2904                 return -EINVAL;
2905
2906         ret = i915_mutex_lock_interruptible(dev);
2907         if (ret)
2908                 return ret;
2909
2910         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2911         if (&obj->base == NULL) {
2912                 mutex_unlock(&dev->struct_mutex);
2913                 return -ENOENT;
2914         }
2915
2916         /* Need to make sure the object gets inactive eventually. */
2917         ret = i915_gem_object_flush_active(obj);
2918         if (ret)
2919                 goto out;
2920
2921         if (obj->active) {
2922                 seqno = obj->last_read_seqno;
2923                 ring = obj->ring;
2924         }
2925
2926         if (seqno == 0)
2927                  goto out;
2928
2929         /* Do this after OLR check to make sure we make forward progress polling
2930          * on this IOCTL with a timeout <=0 (like busy ioctl)
2931          */
2932         if (args->timeout_ns <= 0) {
2933                 ret = -ETIME;
2934                 goto out;
2935         }
2936
2937         drm_gem_object_unreference(&obj->base);
2938         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2939         mutex_unlock(&dev->struct_mutex);
2940
2941         return __i915_wait_seqno(ring, seqno, reset_counter, true,
2942                                  &args->timeout_ns, file->driver_priv);
2943
2944 out:
2945         drm_gem_object_unreference(&obj->base);
2946         mutex_unlock(&dev->struct_mutex);
2947         return ret;
2948 }
2949
2950 /**
2951  * i915_gem_object_sync - sync an object to a ring.
2952  *
2953  * @obj: object which may be in use on another ring.
2954  * @to: ring we wish to use the object on. May be NULL.
2955  *
2956  * This code is meant to abstract object synchronization with the GPU.
2957  * Calling with NULL implies synchronizing the object with the CPU
2958  * rather than a particular GPU ring.
2959  *
2960  * Returns 0 if successful, else propagates up the lower layer error.
2961  */
2962 int
2963 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2964                      struct intel_engine_cs *to)
2965 {
2966         struct intel_engine_cs *from = obj->ring;
2967         u32 seqno;
2968         int ret, idx;
2969
2970         if (from == NULL || to == from)
2971                 return 0;
2972
2973         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2974                 return i915_gem_object_wait_rendering(obj, false);
2975
2976         idx = intel_ring_sync_index(from, to);
2977
2978         seqno = obj->last_read_seqno;
2979         /* Optimization: Avoid semaphore sync when we are sure we already
2980          * waited for an object with higher seqno */
2981         if (seqno <= from->semaphore.sync_seqno[idx])
2982                 return 0;
2983
2984         ret = i915_gem_check_olr(obj->ring, seqno);
2985         if (ret)
2986                 return ret;
2987
2988         trace_i915_gem_ring_sync_to(from, to, seqno);
2989         ret = to->semaphore.sync_to(to, from, seqno);
2990         if (!ret)
2991                 /* We use last_read_seqno because sync_to()
2992                  * might have just caused seqno wrap under
2993                  * the radar.
2994                  */
2995                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2996
2997         return ret;
2998 }
2999
3000 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3001 {
3002         u32 old_write_domain, old_read_domains;
3003
3004         /* Force a pagefault for domain tracking on next user access */
3005         i915_gem_release_mmap(obj);
3006
3007         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3008                 return;
3009
3010         /* Wait for any direct GTT access to complete */
3011         mb();
3012
3013         old_read_domains = obj->base.read_domains;
3014         old_write_domain = obj->base.write_domain;
3015
3016         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3017         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3018
3019         trace_i915_gem_object_change_domain(obj,
3020                                             old_read_domains,
3021                                             old_write_domain);
3022 }
3023
3024 int i915_vma_unbind(struct i915_vma *vma)
3025 {
3026         struct drm_i915_gem_object *obj = vma->obj;
3027         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3028         int ret;
3029
3030         if (list_empty(&vma->vma_link))
3031                 return 0;
3032
3033         if (!drm_mm_node_allocated(&vma->node)) {
3034                 i915_gem_vma_destroy(vma);
3035                 return 0;
3036         }
3037
3038         if (vma->pin_count)
3039                 return -EBUSY;
3040
3041         BUG_ON(obj->pages == NULL);
3042
3043         ret = i915_gem_object_finish_gpu(obj);
3044         if (ret)
3045                 return ret;
3046         /* Continue on if we fail due to EIO, the GPU is hung so we
3047          * should be safe and we need to cleanup or else we might
3048          * cause memory corruption through use-after-free.
3049          */
3050
3051         /* Throw away the active reference before moving to the unbound list */
3052         i915_gem_object_retire(obj);
3053
3054         if (i915_is_ggtt(vma->vm)) {
3055                 i915_gem_object_finish_gtt(obj);
3056
3057                 /* release the fence reg _after_ flushing */
3058                 ret = i915_gem_object_put_fence(obj);
3059                 if (ret)
3060                         return ret;
3061         }
3062
3063         trace_i915_vma_unbind(vma);
3064
3065         vma->unbind_vma(vma);
3066
3067         list_del_init(&vma->mm_list);
3068         if (i915_is_ggtt(vma->vm))
3069                 obj->map_and_fenceable = false;
3070
3071         drm_mm_remove_node(&vma->node);
3072         i915_gem_vma_destroy(vma);
3073
3074         /* Since the unbound list is global, only move to that list if
3075          * no more VMAs exist. */
3076         if (list_empty(&obj->vma_list)) {
3077                 i915_gem_gtt_finish_object(obj);
3078                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3079         }
3080
3081         /* And finally now the object is completely decoupled from this vma,
3082          * we can drop its hold on the backing storage and allow it to be
3083          * reaped by the shrinker.
3084          */
3085         i915_gem_object_unpin_pages(obj);
3086
3087         return 0;
3088 }
3089
3090 int i915_gpu_idle(struct drm_device *dev)
3091 {
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         struct intel_engine_cs *ring;
3094         int ret, i;
3095
3096         /* Flush everything onto the inactive list. */
3097         for_each_ring(ring, dev_priv, i) {
3098                 if (!i915.enable_execlists) {
3099                         ret = i915_switch_context(ring, ring->default_context);
3100                         if (ret)
3101                                 return ret;
3102                 }
3103
3104                 ret = intel_ring_idle(ring);
3105                 if (ret)
3106                         return ret;
3107         }
3108
3109         return 0;
3110 }
3111
3112 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3113                                  struct drm_i915_gem_object *obj)
3114 {
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int fence_reg;
3117         int fence_pitch_shift;
3118
3119         if (INTEL_INFO(dev)->gen >= 6) {
3120                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3121                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3122         } else {
3123                 fence_reg = FENCE_REG_965_0;
3124                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3125         }
3126
3127         fence_reg += reg * 8;
3128
3129         /* To w/a incoherency with non-atomic 64-bit register updates,
3130          * we split the 64-bit update into two 32-bit writes. In order
3131          * for a partial fence not to be evaluated between writes, we
3132          * precede the update with write to turn off the fence register,
3133          * and only enable the fence as the last step.
3134          *
3135          * For extra levels of paranoia, we make sure each step lands
3136          * before applying the next step.
3137          */
3138         I915_WRITE(fence_reg, 0);
3139         POSTING_READ(fence_reg);
3140
3141         if (obj) {
3142                 u32 size = i915_gem_obj_ggtt_size(obj);
3143                 uint64_t val;
3144
3145                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3146                                  0xfffff000) << 32;
3147                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3148                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3149                 if (obj->tiling_mode == I915_TILING_Y)
3150                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3151                 val |= I965_FENCE_REG_VALID;
3152
3153                 I915_WRITE(fence_reg + 4, val >> 32);
3154                 POSTING_READ(fence_reg + 4);
3155
3156                 I915_WRITE(fence_reg + 0, val);
3157                 POSTING_READ(fence_reg);
3158         } else {
3159                 I915_WRITE(fence_reg + 4, 0);
3160                 POSTING_READ(fence_reg + 4);
3161         }
3162 }
3163
3164 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3165                                  struct drm_i915_gem_object *obj)
3166 {
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168         u32 val;
3169
3170         if (obj) {
3171                 u32 size = i915_gem_obj_ggtt_size(obj);
3172                 int pitch_val;
3173                 int tile_width;
3174
3175                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3176                      (size & -size) != size ||
3177                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3178                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3179                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3180
3181                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3182                         tile_width = 128;
3183                 else
3184                         tile_width = 512;
3185
3186                 /* Note: pitch better be a power of two tile widths */
3187                 pitch_val = obj->stride / tile_width;
3188                 pitch_val = ffs(pitch_val) - 1;
3189
3190                 val = i915_gem_obj_ggtt_offset(obj);
3191                 if (obj->tiling_mode == I915_TILING_Y)
3192                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3193                 val |= I915_FENCE_SIZE_BITS(size);
3194                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3195                 val |= I830_FENCE_REG_VALID;
3196         } else
3197                 val = 0;
3198
3199         if (reg < 8)
3200                 reg = FENCE_REG_830_0 + reg * 4;
3201         else
3202                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3203
3204         I915_WRITE(reg, val);
3205         POSTING_READ(reg);
3206 }
3207
3208 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3209                                 struct drm_i915_gem_object *obj)
3210 {
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         uint32_t val;
3213
3214         if (obj) {
3215                 u32 size = i915_gem_obj_ggtt_size(obj);
3216                 uint32_t pitch_val;
3217
3218                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3219                      (size & -size) != size ||
3220                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3221                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3222                      i915_gem_obj_ggtt_offset(obj), size);
3223
3224                 pitch_val = obj->stride / 128;
3225                 pitch_val = ffs(pitch_val) - 1;
3226
3227                 val = i915_gem_obj_ggtt_offset(obj);
3228                 if (obj->tiling_mode == I915_TILING_Y)
3229                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3230                 val |= I830_FENCE_SIZE_BITS(size);
3231                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3232                 val |= I830_FENCE_REG_VALID;
3233         } else
3234                 val = 0;
3235
3236         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3237         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3238 }
3239
3240 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3241 {
3242         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3243 }
3244
3245 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3246                                  struct drm_i915_gem_object *obj)
3247 {
3248         struct drm_i915_private *dev_priv = dev->dev_private;
3249
3250         /* Ensure that all CPU reads are completed before installing a fence
3251          * and all writes before removing the fence.
3252          */
3253         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3254                 mb();
3255
3256         WARN(obj && (!obj->stride || !obj->tiling_mode),
3257              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3258              obj->stride, obj->tiling_mode);
3259
3260         switch (INTEL_INFO(dev)->gen) {
3261         case 9:
3262         case 8:
3263         case 7:
3264         case 6:
3265         case 5:
3266         case 4: i965_write_fence_reg(dev, reg, obj); break;
3267         case 3: i915_write_fence_reg(dev, reg, obj); break;
3268         case 2: i830_write_fence_reg(dev, reg, obj); break;
3269         default: BUG();
3270         }
3271
3272         /* And similarly be paranoid that no direct access to this region
3273          * is reordered to before the fence is installed.
3274          */
3275         if (i915_gem_object_needs_mb(obj))
3276                 mb();
3277 }
3278
3279 static inline int fence_number(struct drm_i915_private *dev_priv,
3280                                struct drm_i915_fence_reg *fence)
3281 {
3282         return fence - dev_priv->fence_regs;
3283 }
3284
3285 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3286                                          struct drm_i915_fence_reg *fence,
3287                                          bool enable)
3288 {
3289         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3290         int reg = fence_number(dev_priv, fence);
3291
3292         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3293
3294         if (enable) {
3295                 obj->fence_reg = reg;
3296                 fence->obj = obj;
3297                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3298         } else {
3299                 obj->fence_reg = I915_FENCE_REG_NONE;
3300                 fence->obj = NULL;
3301                 list_del_init(&fence->lru_list);
3302         }
3303         obj->fence_dirty = false;
3304 }
3305
3306 static int
3307 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3308 {
3309         if (obj->last_fenced_seqno) {
3310                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3311                 if (ret)
3312                         return ret;
3313
3314                 obj->last_fenced_seqno = 0;
3315         }
3316
3317         return 0;
3318 }
3319
3320 int
3321 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3322 {
3323         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3324         struct drm_i915_fence_reg *fence;
3325         int ret;
3326
3327         ret = i915_gem_object_wait_fence(obj);
3328         if (ret)
3329                 return ret;
3330
3331         if (obj->fence_reg == I915_FENCE_REG_NONE)
3332                 return 0;
3333
3334         fence = &dev_priv->fence_regs[obj->fence_reg];
3335
3336         if (WARN_ON(fence->pin_count))
3337                 return -EBUSY;
3338
3339         i915_gem_object_fence_lost(obj);
3340         i915_gem_object_update_fence(obj, fence, false);
3341
3342         return 0;
3343 }
3344
3345 static struct drm_i915_fence_reg *
3346 i915_find_fence_reg(struct drm_device *dev)
3347 {
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct drm_i915_fence_reg *reg, *avail;
3350         int i;
3351
3352         /* First try to find a free reg */
3353         avail = NULL;
3354         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3355                 reg = &dev_priv->fence_regs[i];
3356                 if (!reg->obj)
3357                         return reg;
3358
3359                 if (!reg->pin_count)
3360                         avail = reg;
3361         }
3362
3363         if (avail == NULL)
3364                 goto deadlock;
3365
3366         /* None available, try to steal one or wait for a user to finish */
3367         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3368                 if (reg->pin_count)
3369                         continue;
3370
3371                 return reg;
3372         }
3373
3374 deadlock:
3375         /* Wait for completion of pending flips which consume fences */
3376         if (intel_has_pending_fb_unpin(dev))
3377                 return ERR_PTR(-EAGAIN);
3378
3379         return ERR_PTR(-EDEADLK);
3380 }
3381
3382 /**
3383  * i915_gem_object_get_fence - set up fencing for an object
3384  * @obj: object to map through a fence reg
3385  *
3386  * When mapping objects through the GTT, userspace wants to be able to write
3387  * to them without having to worry about swizzling if the object is tiled.
3388  * This function walks the fence regs looking for a free one for @obj,
3389  * stealing one if it can't find any.
3390  *
3391  * It then sets up the reg based on the object's properties: address, pitch
3392  * and tiling format.
3393  *
3394  * For an untiled surface, this removes any existing fence.
3395  */
3396 int
3397 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3398 {
3399         struct drm_device *dev = obj->base.dev;
3400         struct drm_i915_private *dev_priv = dev->dev_private;
3401         bool enable = obj->tiling_mode != I915_TILING_NONE;
3402         struct drm_i915_fence_reg *reg;
3403         int ret;
3404
3405         /* Have we updated the tiling parameters upon the object and so
3406          * will need to serialise the write to the associated fence register?
3407          */
3408         if (obj->fence_dirty) {
3409                 ret = i915_gem_object_wait_fence(obj);
3410                 if (ret)
3411                         return ret;
3412         }
3413
3414         /* Just update our place in the LRU if our fence is getting reused. */
3415         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3416                 reg = &dev_priv->fence_regs[obj->fence_reg];
3417                 if (!obj->fence_dirty) {
3418                         list_move_tail(&reg->lru_list,
3419                                        &dev_priv->mm.fence_list);
3420                         return 0;
3421                 }
3422         } else if (enable) {
3423                 if (WARN_ON(!obj->map_and_fenceable))
3424                         return -EINVAL;
3425
3426                 reg = i915_find_fence_reg(dev);
3427                 if (IS_ERR(reg))
3428                         return PTR_ERR(reg);
3429
3430                 if (reg->obj) {
3431                         struct drm_i915_gem_object *old = reg->obj;
3432
3433                         ret = i915_gem_object_wait_fence(old);
3434                         if (ret)
3435                                 return ret;
3436
3437                         i915_gem_object_fence_lost(old);
3438                 }
3439         } else
3440                 return 0;
3441
3442         i915_gem_object_update_fence(obj, reg, enable);
3443
3444         return 0;
3445 }
3446
3447 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3448                                      unsigned long cache_level)
3449 {
3450         struct drm_mm_node *gtt_space = &vma->node;
3451         struct drm_mm_node *other;
3452
3453         /*
3454          * On some machines we have to be careful when putting differing types
3455          * of snoopable memory together to avoid the prefetcher crossing memory
3456          * domains and dying. During vm initialisation, we decide whether or not
3457          * these constraints apply and set the drm_mm.color_adjust
3458          * appropriately.
3459          */
3460         if (vma->vm->mm.color_adjust == NULL)
3461                 return true;
3462
3463         if (!drm_mm_node_allocated(gtt_space))
3464                 return true;
3465
3466         if (list_empty(&gtt_space->node_list))
3467                 return true;
3468
3469         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3470         if (other->allocated && !other->hole_follows && other->color != cache_level)
3471                 return false;
3472
3473         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3474         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3475                 return false;
3476
3477         return true;
3478 }
3479
3480 /**
3481  * Finds free space in the GTT aperture and binds the object there.
3482  */
3483 static struct i915_vma *
3484 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3485                            struct i915_address_space *vm,
3486                            unsigned alignment,
3487                            uint64_t flags)
3488 {
3489         struct drm_device *dev = obj->base.dev;
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         u32 size, fence_size, fence_alignment, unfenced_alignment;
3492         unsigned long start =
3493                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3494         unsigned long end =
3495                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3496         struct i915_vma *vma;
3497         int ret;
3498
3499         fence_size = i915_gem_get_gtt_size(dev,
3500                                            obj->base.size,
3501                                            obj->tiling_mode);
3502         fence_alignment = i915_gem_get_gtt_alignment(dev,
3503                                                      obj->base.size,
3504                                                      obj->tiling_mode, true);
3505         unfenced_alignment =
3506                 i915_gem_get_gtt_alignment(dev,
3507                                            obj->base.size,
3508                                            obj->tiling_mode, false);
3509
3510         if (alignment == 0)
3511                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3512                                                 unfenced_alignment;
3513         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3514                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3515                 return ERR_PTR(-EINVAL);
3516         }
3517
3518         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3519
3520         /* If the object is bigger than the entire aperture, reject it early
3521          * before evicting everything in a vain attempt to find space.
3522          */
3523         if (obj->base.size > end) {
3524                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3525                           obj->base.size,
3526                           flags & PIN_MAPPABLE ? "mappable" : "total",
3527                           end);
3528                 return ERR_PTR(-E2BIG);
3529         }
3530
3531         ret = i915_gem_object_get_pages(obj);
3532         if (ret)
3533                 return ERR_PTR(ret);
3534
3535         i915_gem_object_pin_pages(obj);
3536
3537         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3538         if (IS_ERR(vma))
3539                 goto err_unpin;
3540
3541 search_free:
3542         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3543                                                   size, alignment,
3544                                                   obj->cache_level,
3545                                                   start, end,
3546                                                   DRM_MM_SEARCH_DEFAULT,
3547                                                   DRM_MM_CREATE_DEFAULT);
3548         if (ret) {
3549                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3550                                                obj->cache_level,
3551                                                start, end,
3552                                                flags);
3553                 if (ret == 0)
3554                         goto search_free;
3555
3556                 goto err_free_vma;
3557         }
3558         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3559                 ret = -EINVAL;
3560                 goto err_remove_node;
3561         }
3562
3563         ret = i915_gem_gtt_prepare_object(obj);
3564         if (ret)
3565                 goto err_remove_node;
3566
3567         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3568         list_add_tail(&vma->mm_list, &vm->inactive_list);
3569
3570         trace_i915_vma_bind(vma, flags);
3571         vma->bind_vma(vma, obj->cache_level,
3572                       flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3573
3574         return vma;
3575
3576 err_remove_node:
3577         drm_mm_remove_node(&vma->node);
3578 err_free_vma:
3579         i915_gem_vma_destroy(vma);
3580         vma = ERR_PTR(ret);
3581 err_unpin:
3582         i915_gem_object_unpin_pages(obj);
3583         return vma;
3584 }
3585
3586 bool
3587 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3588                         bool force)
3589 {
3590         /* If we don't have a page list set up, then we're not pinned
3591          * to GPU, and we can ignore the cache flush because it'll happen
3592          * again at bind time.
3593          */
3594         if (obj->pages == NULL)
3595                 return false;
3596
3597         /*
3598          * Stolen memory is always coherent with the GPU as it is explicitly
3599          * marked as wc by the system, or the system is cache-coherent.
3600          */
3601         if (obj->stolen || obj->phys_handle)
3602                 return false;
3603
3604         /* If the GPU is snooping the contents of the CPU cache,
3605          * we do not need to manually clear the CPU cache lines.  However,
3606          * the caches are only snooped when the render cache is
3607          * flushed/invalidated.  As we always have to emit invalidations
3608          * and flushes when moving into and out of the RENDER domain, correct
3609          * snooping behaviour occurs naturally as the result of our domain
3610          * tracking.
3611          */
3612         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3613                 return false;
3614
3615         trace_i915_gem_object_clflush(obj);
3616         drm_clflush_sg(obj->pages);
3617
3618         return true;
3619 }
3620
3621 /** Flushes the GTT write domain for the object if it's dirty. */
3622 static void
3623 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3624 {
3625         uint32_t old_write_domain;
3626
3627         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3628                 return;
3629
3630         /* No actual flushing is required for the GTT write domain.  Writes
3631          * to it immediately go to main memory as far as we know, so there's
3632          * no chipset flush.  It also doesn't land in render cache.
3633          *
3634          * However, we do have to enforce the order so that all writes through
3635          * the GTT land before any writes to the device, such as updates to
3636          * the GATT itself.
3637          */
3638         wmb();
3639
3640         old_write_domain = obj->base.write_domain;
3641         obj->base.write_domain = 0;
3642
3643         intel_fb_obj_flush(obj, false);
3644
3645         trace_i915_gem_object_change_domain(obj,
3646                                             obj->base.read_domains,
3647                                             old_write_domain);
3648 }
3649
3650 /** Flushes the CPU write domain for the object if it's dirty. */
3651 static void
3652 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3653                                        bool force)
3654 {
3655         uint32_t old_write_domain;
3656
3657         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3658                 return;
3659
3660         if (i915_gem_clflush_object(obj, force))
3661                 i915_gem_chipset_flush(obj->base.dev);
3662
3663         old_write_domain = obj->base.write_domain;
3664         obj->base.write_domain = 0;
3665
3666         intel_fb_obj_flush(obj, false);
3667
3668         trace_i915_gem_object_change_domain(obj,
3669                                             obj->base.read_domains,
3670                                             old_write_domain);
3671 }
3672
3673 /**
3674  * Moves a single object to the GTT read, and possibly write domain.
3675  *
3676  * This function returns when the move is complete, including waiting on
3677  * flushes to occur.
3678  */
3679 int
3680 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3681 {
3682         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3683         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3684         uint32_t old_write_domain, old_read_domains;
3685         int ret;
3686
3687         /* Not valid to be called on unbound objects. */
3688         if (vma == NULL)
3689                 return -EINVAL;
3690
3691         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3692                 return 0;
3693
3694         ret = i915_gem_object_wait_rendering(obj, !write);
3695         if (ret)
3696                 return ret;
3697
3698         i915_gem_object_retire(obj);
3699         i915_gem_object_flush_cpu_write_domain(obj, false);
3700
3701         /* Serialise direct access to this object with the barriers for
3702          * coherent writes from the GPU, by effectively invalidating the
3703          * GTT domain upon first access.
3704          */
3705         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3706                 mb();
3707
3708         old_write_domain = obj->base.write_domain;
3709         old_read_domains = obj->base.read_domains;
3710
3711         /* It should now be out of any other write domains, and we can update
3712          * the domain values for our changes.
3713          */
3714         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3715         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3716         if (write) {
3717                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3718                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3719                 obj->dirty = 1;
3720         }
3721
3722         if (write)
3723                 intel_fb_obj_invalidate(obj, NULL);
3724
3725         trace_i915_gem_object_change_domain(obj,
3726                                             old_read_domains,
3727                                             old_write_domain);
3728
3729         /* And bump the LRU for this access */
3730         if (i915_gem_object_is_inactive(obj))
3731                 list_move_tail(&vma->mm_list,
3732                                &dev_priv->gtt.base.inactive_list);
3733
3734         return 0;
3735 }
3736
3737 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3738                                     enum i915_cache_level cache_level)
3739 {
3740         struct drm_device *dev = obj->base.dev;
3741         struct i915_vma *vma, *next;
3742         int ret;
3743
3744         if (obj->cache_level == cache_level)
3745                 return 0;
3746
3747         if (i915_gem_obj_is_pinned(obj)) {
3748                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3749                 return -EBUSY;
3750         }
3751
3752         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3753                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3754                         ret = i915_vma_unbind(vma);
3755                         if (ret)
3756                                 return ret;
3757                 }
3758         }
3759
3760         if (i915_gem_obj_bound_any(obj)) {
3761                 ret = i915_gem_object_finish_gpu(obj);
3762                 if (ret)
3763                         return ret;
3764
3765                 i915_gem_object_finish_gtt(obj);
3766
3767                 /* Before SandyBridge, you could not use tiling or fence
3768                  * registers with snooped memory, so relinquish any fences
3769                  * currently pointing to our region in the aperture.
3770                  */
3771                 if (INTEL_INFO(dev)->gen < 6) {
3772                         ret = i915_gem_object_put_fence(obj);
3773                         if (ret)
3774                                 return ret;
3775                 }
3776
3777                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3778                         if (drm_mm_node_allocated(&vma->node))
3779                                 vma->bind_vma(vma, cache_level,
3780                                                 vma->bound & GLOBAL_BIND);
3781         }
3782
3783         list_for_each_entry(vma, &obj->vma_list, vma_link)
3784                 vma->node.color = cache_level;
3785         obj->cache_level = cache_level;
3786
3787         if (cpu_write_needs_clflush(obj)) {
3788                 u32 old_read_domains, old_write_domain;
3789
3790                 /* If we're coming from LLC cached, then we haven't
3791                  * actually been tracking whether the data is in the
3792                  * CPU cache or not, since we only allow one bit set
3793                  * in obj->write_domain and have been skipping the clflushes.
3794                  * Just set it to the CPU cache for now.
3795                  */
3796                 i915_gem_object_retire(obj);
3797                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3798
3799                 old_read_domains = obj->base.read_domains;
3800                 old_write_domain = obj->base.write_domain;
3801
3802                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3803                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3804
3805                 trace_i915_gem_object_change_domain(obj,
3806                                                     old_read_domains,
3807                                                     old_write_domain);
3808         }
3809
3810         return 0;
3811 }
3812
3813 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3814                                struct drm_file *file)
3815 {
3816         struct drm_i915_gem_caching *args = data;
3817         struct drm_i915_gem_object *obj;
3818         int ret;
3819
3820         ret = i915_mutex_lock_interruptible(dev);
3821         if (ret)
3822                 return ret;
3823
3824         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3825         if (&obj->base == NULL) {
3826                 ret = -ENOENT;
3827                 goto unlock;
3828         }
3829
3830         switch (obj->cache_level) {
3831         case I915_CACHE_LLC:
3832         case I915_CACHE_L3_LLC:
3833                 args->caching = I915_CACHING_CACHED;
3834                 break;
3835
3836         case I915_CACHE_WT:
3837                 args->caching = I915_CACHING_DISPLAY;
3838                 break;
3839
3840         default:
3841                 args->caching = I915_CACHING_NONE;
3842                 break;
3843         }
3844
3845         drm_gem_object_unreference(&obj->base);
3846 unlock:
3847         mutex_unlock(&dev->struct_mutex);
3848         return ret;
3849 }
3850
3851 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3852                                struct drm_file *file)
3853 {
3854         struct drm_i915_gem_caching *args = data;
3855         struct drm_i915_gem_object *obj;
3856         enum i915_cache_level level;
3857         int ret;
3858
3859         switch (args->caching) {
3860         case I915_CACHING_NONE:
3861                 level = I915_CACHE_NONE;
3862                 break;
3863         case I915_CACHING_CACHED:
3864                 level = I915_CACHE_LLC;
3865                 break;
3866         case I915_CACHING_DISPLAY:
3867                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3868                 break;
3869         default:
3870                 return -EINVAL;
3871         }
3872
3873         ret = i915_mutex_lock_interruptible(dev);
3874         if (ret)
3875                 return ret;
3876
3877         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3878         if (&obj->base == NULL) {
3879                 ret = -ENOENT;
3880                 goto unlock;
3881         }
3882
3883         ret = i915_gem_object_set_cache_level(obj, level);
3884
3885         drm_gem_object_unreference(&obj->base);
3886 unlock:
3887         mutex_unlock(&dev->struct_mutex);
3888         return ret;
3889 }
3890
3891 static bool is_pin_display(struct drm_i915_gem_object *obj)
3892 {
3893         struct i915_vma *vma;
3894
3895         vma = i915_gem_obj_to_ggtt(obj);
3896         if (!vma)
3897                 return false;
3898
3899         /* There are 3 sources that pin objects:
3900          *   1. The display engine (scanouts, sprites, cursors);
3901          *   2. Reservations for execbuffer;
3902          *   3. The user.
3903          *
3904          * We can ignore reservations as we hold the struct_mutex and
3905          * are only called outside of the reservation path.  The user
3906          * can only increment pin_count once, and so if after
3907          * subtracting the potential reference by the user, any pin_count
3908          * remains, it must be due to another use by the display engine.
3909          */
3910         return vma->pin_count - !!obj->user_pin_count;
3911 }
3912
3913 /*
3914  * Prepare buffer for display plane (scanout, cursors, etc).
3915  * Can be called from an uninterruptible phase (modesetting) and allows
3916  * any flushes to be pipelined (for pageflips).
3917  */
3918 int
3919 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3920                                      u32 alignment,
3921                                      struct intel_engine_cs *pipelined)
3922 {
3923         u32 old_read_domains, old_write_domain;
3924         bool was_pin_display;
3925         int ret;
3926
3927         if (pipelined != obj->ring) {
3928                 ret = i915_gem_object_sync(obj, pipelined);
3929                 if (ret)
3930                         return ret;
3931         }
3932
3933         /* Mark the pin_display early so that we account for the
3934          * display coherency whilst setting up the cache domains.
3935          */
3936         was_pin_display = obj->pin_display;
3937         obj->pin_display = true;
3938
3939         /* The display engine is not coherent with the LLC cache on gen6.  As
3940          * a result, we make sure that the pinning that is about to occur is
3941          * done with uncached PTEs. This is lowest common denominator for all
3942          * chipsets.
3943          *
3944          * However for gen6+, we could do better by using the GFDT bit instead
3945          * of uncaching, which would allow us to flush all the LLC-cached data
3946          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3947          */
3948         ret = i915_gem_object_set_cache_level(obj,
3949                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3950         if (ret)
3951                 goto err_unpin_display;
3952
3953         /* As the user may map the buffer once pinned in the display plane
3954          * (e.g. libkms for the bootup splash), we have to ensure that we
3955          * always use map_and_fenceable for all scanout buffers.
3956          */
3957         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3958         if (ret)
3959                 goto err_unpin_display;
3960
3961         i915_gem_object_flush_cpu_write_domain(obj, true);
3962
3963         old_write_domain = obj->base.write_domain;
3964         old_read_domains = obj->base.read_domains;
3965
3966         /* It should now be out of any other write domains, and we can update
3967          * the domain values for our changes.
3968          */
3969         obj->base.write_domain = 0;
3970         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3971
3972         trace_i915_gem_object_change_domain(obj,
3973                                             old_read_domains,
3974                                             old_write_domain);
3975
3976         return 0;
3977
3978 err_unpin_display:
3979         WARN_ON(was_pin_display != is_pin_display(obj));
3980         obj->pin_display = was_pin_display;
3981         return ret;
3982 }
3983
3984 void
3985 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3986 {
3987         i915_gem_object_ggtt_unpin(obj);
3988         obj->pin_display = is_pin_display(obj);
3989 }
3990
3991 int
3992 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3993 {
3994         int ret;
3995
3996         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3997                 return 0;
3998
3999         ret = i915_gem_object_wait_rendering(obj, false);
4000         if (ret)
4001                 return ret;
4002
4003         /* Ensure that we invalidate the GPU's caches and TLBs. */
4004         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4005         return 0;
4006 }
4007
4008 /**
4009  * Moves a single object to the CPU read, and possibly write domain.
4010  *
4011  * This function returns when the move is complete, including waiting on
4012  * flushes to occur.
4013  */
4014 int
4015 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4016 {
4017         uint32_t old_write_domain, old_read_domains;
4018         int ret;
4019
4020         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4021                 return 0;
4022
4023         ret = i915_gem_object_wait_rendering(obj, !write);
4024         if (ret)
4025                 return ret;
4026
4027         i915_gem_object_retire(obj);
4028         i915_gem_object_flush_gtt_write_domain(obj);
4029
4030         old_write_domain = obj->base.write_domain;
4031         old_read_domains = obj->base.read_domains;
4032
4033         /* Flush the CPU cache if it's still invalid. */
4034         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4035                 i915_gem_clflush_object(obj, false);
4036
4037                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4038         }
4039
4040         /* It should now be out of any other write domains, and we can update
4041          * the domain values for our changes.
4042          */
4043         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4044
4045         /* If we're writing through the CPU, then the GPU read domains will
4046          * need to be invalidated at next use.
4047          */
4048         if (write) {
4049                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4050                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4051         }
4052
4053         if (write)
4054                 intel_fb_obj_invalidate(obj, NULL);
4055
4056         trace_i915_gem_object_change_domain(obj,
4057                                             old_read_domains,
4058                                             old_write_domain);
4059
4060         return 0;
4061 }
4062
4063 /* Throttle our rendering by waiting until the ring has completed our requests
4064  * emitted over 20 msec ago.
4065  *
4066  * Note that if we were to use the current jiffies each time around the loop,
4067  * we wouldn't escape the function with any frames outstanding if the time to
4068  * render a frame was over 20ms.
4069  *
4070  * This should get us reasonable parallelism between CPU and GPU but also
4071  * relatively low latency when blocking on a particular request to finish.
4072  */
4073 static int
4074 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4075 {
4076         struct drm_i915_private *dev_priv = dev->dev_private;
4077         struct drm_i915_file_private *file_priv = file->driver_priv;
4078         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4079         struct drm_i915_gem_request *request;
4080         struct intel_engine_cs *ring = NULL;
4081         unsigned reset_counter;
4082         u32 seqno = 0;
4083         int ret;
4084
4085         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4086         if (ret)
4087                 return ret;
4088
4089         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4090         if (ret)
4091                 return ret;
4092
4093         spin_lock(&file_priv->mm.lock);
4094         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4095                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4096                         break;
4097
4098                 ring = request->ring;
4099                 seqno = request->seqno;
4100         }
4101         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4102         spin_unlock(&file_priv->mm.lock);
4103
4104         if (seqno == 0)
4105                 return 0;
4106
4107         ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4108         if (ret == 0)
4109                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4110
4111         return ret;
4112 }
4113
4114 static bool
4115 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4116 {
4117         struct drm_i915_gem_object *obj = vma->obj;
4118
4119         if (alignment &&
4120             vma->node.start & (alignment - 1))
4121                 return true;
4122
4123         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4124                 return true;
4125
4126         if (flags & PIN_OFFSET_BIAS &&
4127             vma->node.start < (flags & PIN_OFFSET_MASK))
4128                 return true;
4129
4130         return false;
4131 }
4132
4133 int
4134 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4135                     struct i915_address_space *vm,
4136                     uint32_t alignment,
4137                     uint64_t flags)
4138 {
4139         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4140         struct i915_vma *vma;
4141         unsigned bound;
4142         int ret;
4143
4144         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4145                 return -ENODEV;
4146
4147         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4148                 return -EINVAL;
4149
4150         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4151                 return -EINVAL;
4152
4153         vma = i915_gem_obj_to_vma(obj, vm);
4154         if (vma) {
4155                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4156                         return -EBUSY;
4157
4158                 if (i915_vma_misplaced(vma, alignment, flags)) {
4159                         WARN(vma->pin_count,
4160                              "bo is already pinned with incorrect alignment:"
4161                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4162                              " obj->map_and_fenceable=%d\n",
4163                              i915_gem_obj_offset(obj, vm), alignment,
4164                              !!(flags & PIN_MAPPABLE),
4165                              obj->map_and_fenceable);
4166                         ret = i915_vma_unbind(vma);
4167                         if (ret)
4168                                 return ret;
4169
4170                         vma = NULL;
4171                 }
4172         }
4173
4174         bound = vma ? vma->bound : 0;
4175         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4176                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4177                 if (IS_ERR(vma))
4178                         return PTR_ERR(vma);
4179         }
4180
4181         if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4182                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4183
4184         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4185                 bool mappable, fenceable;
4186                 u32 fence_size, fence_alignment;
4187
4188                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4189                                                    obj->base.size,
4190                                                    obj->tiling_mode);
4191                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4192                                                              obj->base.size,
4193                                                              obj->tiling_mode,
4194                                                              true);
4195
4196                 fenceable = (vma->node.size == fence_size &&
4197                              (vma->node.start & (fence_alignment - 1)) == 0);
4198
4199                 mappable = (vma->node.start + obj->base.size <=
4200                             dev_priv->gtt.mappable_end);
4201
4202                 obj->map_and_fenceable = mappable && fenceable;
4203         }
4204
4205         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4206
4207         vma->pin_count++;
4208         if (flags & PIN_MAPPABLE)
4209                 obj->pin_mappable |= true;
4210
4211         return 0;
4212 }
4213
4214 void
4215 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4216 {
4217         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4218
4219         BUG_ON(!vma);
4220         BUG_ON(vma->pin_count == 0);
4221         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4222
4223         if (--vma->pin_count == 0)
4224                 obj->pin_mappable = false;
4225 }
4226
4227 bool
4228 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4229 {
4230         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4231                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4232                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4233
4234                 WARN_ON(!ggtt_vma ||
4235                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4236                         ggtt_vma->pin_count);
4237                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4238                 return true;
4239         } else
4240                 return false;
4241 }
4242
4243 void
4244 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4245 {
4246         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4247                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4248                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4249                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4250         }
4251 }
4252
4253 int
4254 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4255                    struct drm_file *file)
4256 {
4257         struct drm_i915_gem_pin *args = data;
4258         struct drm_i915_gem_object *obj;
4259         int ret;
4260
4261         if (drm_core_check_feature(dev, DRIVER_MODESET))
4262                 return -ENODEV;
4263
4264         ret = i915_mutex_lock_interruptible(dev);
4265         if (ret)
4266                 return ret;
4267
4268         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4269         if (&obj->base == NULL) {
4270                 ret = -ENOENT;
4271                 goto unlock;
4272         }
4273
4274         if (obj->madv != I915_MADV_WILLNEED) {
4275                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4276                 ret = -EFAULT;
4277                 goto out;
4278         }
4279
4280         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4281                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4282                           args->handle);
4283                 ret = -EINVAL;
4284                 goto out;
4285         }
4286
4287         if (obj->user_pin_count == ULONG_MAX) {
4288                 ret = -EBUSY;
4289                 goto out;
4290         }
4291
4292         if (obj->user_pin_count == 0) {
4293                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4294                 if (ret)
4295                         goto out;
4296         }
4297
4298         obj->user_pin_count++;
4299         obj->pin_filp = file;
4300
4301         args->offset = i915_gem_obj_ggtt_offset(obj);
4302 out:
4303         drm_gem_object_unreference(&obj->base);
4304 unlock:
4305         mutex_unlock(&dev->struct_mutex);
4306         return ret;
4307 }
4308
4309 int
4310 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4311                      struct drm_file *file)
4312 {
4313         struct drm_i915_gem_pin *args = data;
4314         struct drm_i915_gem_object *obj;
4315         int ret;
4316
4317         if (drm_core_check_feature(dev, DRIVER_MODESET))
4318                 return -ENODEV;
4319
4320         ret = i915_mutex_lock_interruptible(dev);
4321         if (ret)
4322                 return ret;
4323
4324         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4325         if (&obj->base == NULL) {
4326                 ret = -ENOENT;
4327                 goto unlock;
4328         }
4329
4330         if (obj->pin_filp != file) {
4331                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4332                           args->handle);
4333                 ret = -EINVAL;
4334                 goto out;
4335         }
4336         obj->user_pin_count--;
4337         if (obj->user_pin_count == 0) {
4338                 obj->pin_filp = NULL;
4339                 i915_gem_object_ggtt_unpin(obj);
4340         }
4341
4342 out:
4343         drm_gem_object_unreference(&obj->base);
4344 unlock:
4345         mutex_unlock(&dev->struct_mutex);
4346         return ret;
4347 }
4348
4349 int
4350 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4351                     struct drm_file *file)
4352 {
4353         struct drm_i915_gem_busy *args = data;
4354         struct drm_i915_gem_object *obj;
4355         int ret;
4356
4357         ret = i915_mutex_lock_interruptible(dev);
4358         if (ret)
4359                 return ret;
4360
4361         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4362         if (&obj->base == NULL) {
4363                 ret = -ENOENT;
4364                 goto unlock;
4365         }
4366
4367         /* Count all active objects as busy, even if they are currently not used
4368          * by the gpu. Users of this interface expect objects to eventually
4369          * become non-busy without any further actions, therefore emit any
4370          * necessary flushes here.
4371          */
4372         ret = i915_gem_object_flush_active(obj);
4373
4374         args->busy = obj->active;
4375         if (obj->ring) {
4376                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4377                 args->busy |= intel_ring_flag(obj->ring) << 16;
4378         }
4379
4380         drm_gem_object_unreference(&obj->base);
4381 unlock:
4382         mutex_unlock(&dev->struct_mutex);
4383         return ret;
4384 }
4385
4386 int
4387 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4388                         struct drm_file *file_priv)
4389 {
4390         return i915_gem_ring_throttle(dev, file_priv);
4391 }
4392
4393 int
4394 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4395                        struct drm_file *file_priv)
4396 {
4397         struct drm_i915_private *dev_priv = dev->dev_private;
4398         struct drm_i915_gem_madvise *args = data;
4399         struct drm_i915_gem_object *obj;
4400         int ret;
4401
4402         switch (args->madv) {
4403         case I915_MADV_DONTNEED:
4404         case I915_MADV_WILLNEED:
4405             break;
4406         default:
4407             return -EINVAL;
4408         }
4409
4410         ret = i915_mutex_lock_interruptible(dev);
4411         if (ret)
4412                 return ret;
4413
4414         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4415         if (&obj->base == NULL) {
4416                 ret = -ENOENT;
4417                 goto unlock;
4418         }
4419
4420         if (i915_gem_obj_is_pinned(obj)) {
4421                 ret = -EINVAL;
4422                 goto out;
4423         }
4424
4425         if (obj->pages &&
4426             obj->tiling_mode != I915_TILING_NONE &&
4427             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4428                 if (obj->madv == I915_MADV_WILLNEED)
4429                         i915_gem_object_unpin_pages(obj);
4430                 if (args->madv == I915_MADV_WILLNEED)
4431                         i915_gem_object_pin_pages(obj);
4432         }
4433
4434         if (obj->madv != __I915_MADV_PURGED)
4435                 obj->madv = args->madv;
4436
4437         /* if the object is no longer attached, discard its backing storage */
4438         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4439                 i915_gem_object_truncate(obj);
4440
4441         args->retained = obj->madv != __I915_MADV_PURGED;
4442
4443 out:
4444         drm_gem_object_unreference(&obj->base);
4445 unlock:
4446         mutex_unlock(&dev->struct_mutex);
4447         return ret;
4448 }
4449
4450 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4451                           const struct drm_i915_gem_object_ops *ops)
4452 {
4453         INIT_LIST_HEAD(&obj->global_list);
4454         INIT_LIST_HEAD(&obj->ring_list);
4455         INIT_LIST_HEAD(&obj->obj_exec_link);
4456         INIT_LIST_HEAD(&obj->vma_list);
4457
4458         obj->ops = ops;
4459
4460         obj->fence_reg = I915_FENCE_REG_NONE;
4461         obj->madv = I915_MADV_WILLNEED;
4462
4463         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4464 }
4465
4466 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4467         .get_pages = i915_gem_object_get_pages_gtt,
4468         .put_pages = i915_gem_object_put_pages_gtt,
4469 };
4470
4471 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4472                                                   size_t size)
4473 {
4474         struct drm_i915_gem_object *obj;
4475         struct address_space *mapping;
4476         gfp_t mask;
4477
4478         obj = i915_gem_object_alloc(dev);
4479         if (obj == NULL)
4480                 return NULL;
4481
4482         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4483                 i915_gem_object_free(obj);
4484                 return NULL;
4485         }
4486
4487         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4488         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4489                 /* 965gm cannot relocate objects above 4GiB. */
4490                 mask &= ~__GFP_HIGHMEM;
4491                 mask |= __GFP_DMA32;
4492         }
4493
4494         mapping = file_inode(obj->base.filp)->i_mapping;
4495         mapping_set_gfp_mask(mapping, mask);
4496
4497         i915_gem_object_init(obj, &i915_gem_object_ops);
4498
4499         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4500         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4501
4502         if (HAS_LLC(dev)) {
4503                 /* On some devices, we can have the GPU use the LLC (the CPU
4504                  * cache) for about a 10% performance improvement
4505                  * compared to uncached.  Graphics requests other than
4506                  * display scanout are coherent with the CPU in
4507                  * accessing this cache.  This means in this mode we
4508                  * don't need to clflush on the CPU side, and on the
4509                  * GPU side we only need to flush internal caches to
4510                  * get data visible to the CPU.
4511                  *
4512                  * However, we maintain the display planes as UC, and so
4513                  * need to rebind when first used as such.
4514                  */
4515                 obj->cache_level = I915_CACHE_LLC;
4516         } else
4517                 obj->cache_level = I915_CACHE_NONE;
4518
4519         trace_i915_gem_object_create(obj);
4520
4521         return obj;
4522 }
4523
4524 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4525 {
4526         /* If we are the last user of the backing storage (be it shmemfs
4527          * pages or stolen etc), we know that the pages are going to be
4528          * immediately released. In this case, we can then skip copying
4529          * back the contents from the GPU.
4530          */
4531
4532         if (obj->madv != I915_MADV_WILLNEED)
4533                 return false;
4534
4535         if (obj->base.filp == NULL)
4536                 return true;
4537
4538         /* At first glance, this looks racy, but then again so would be
4539          * userspace racing mmap against close. However, the first external
4540          * reference to the filp can only be obtained through the
4541          * i915_gem_mmap_ioctl() which safeguards us against the user
4542          * acquiring such a reference whilst we are in the middle of
4543          * freeing the object.
4544          */
4545         return atomic_long_read(&obj->base.filp->f_count) == 1;
4546 }
4547
4548 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4549 {
4550         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4551         struct drm_device *dev = obj->base.dev;
4552         struct drm_i915_private *dev_priv = dev->dev_private;
4553         struct i915_vma *vma, *next;
4554
4555         intel_runtime_pm_get(dev_priv);
4556
4557         trace_i915_gem_object_destroy(obj);
4558
4559         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4560                 int ret;
4561
4562                 vma->pin_count = 0;
4563                 ret = i915_vma_unbind(vma);
4564                 if (WARN_ON(ret == -ERESTARTSYS)) {
4565                         bool was_interruptible;
4566
4567                         was_interruptible = dev_priv->mm.interruptible;
4568                         dev_priv->mm.interruptible = false;
4569
4570                         WARN_ON(i915_vma_unbind(vma));
4571
4572                         dev_priv->mm.interruptible = was_interruptible;
4573                 }
4574         }
4575
4576         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4577          * before progressing. */
4578         if (obj->stolen)
4579                 i915_gem_object_unpin_pages(obj);
4580
4581         WARN_ON(obj->frontbuffer_bits);
4582
4583         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4584             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4585             obj->tiling_mode != I915_TILING_NONE)
4586                 i915_gem_object_unpin_pages(obj);
4587
4588         if (WARN_ON(obj->pages_pin_count))
4589                 obj->pages_pin_count = 0;
4590         if (discard_backing_storage(obj))
4591                 obj->madv = I915_MADV_DONTNEED;
4592         i915_gem_object_put_pages(obj);
4593         i915_gem_object_free_mmap_offset(obj);
4594
4595         BUG_ON(obj->pages);
4596
4597         if (obj->base.import_attach)
4598                 drm_prime_gem_destroy(&obj->base, NULL);
4599
4600         if (obj->ops->release)
4601                 obj->ops->release(obj);
4602
4603         drm_gem_object_release(&obj->base);
4604         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4605
4606         kfree(obj->bit_17);
4607         i915_gem_object_free(obj);
4608
4609         intel_runtime_pm_put(dev_priv);
4610 }
4611
4612 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4613                                      struct i915_address_space *vm)
4614 {
4615         struct i915_vma *vma;
4616         list_for_each_entry(vma, &obj->vma_list, vma_link)
4617                 if (vma->vm == vm)
4618                         return vma;
4619
4620         return NULL;
4621 }
4622
4623 void i915_gem_vma_destroy(struct i915_vma *vma)
4624 {
4625         struct i915_address_space *vm = NULL;
4626         WARN_ON(vma->node.allocated);
4627
4628         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4629         if (!list_empty(&vma->exec_list))
4630                 return;
4631
4632         vm = vma->vm;
4633
4634         if (!i915_is_ggtt(vm))
4635                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4636
4637         list_del(&vma->vma_link);
4638
4639         kfree(vma);
4640 }
4641
4642 static void
4643 i915_gem_stop_ringbuffers(struct drm_device *dev)
4644 {
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         struct intel_engine_cs *ring;
4647         int i;
4648
4649         for_each_ring(ring, dev_priv, i)
4650                 dev_priv->gt.stop_ring(ring);
4651 }
4652
4653 int
4654 i915_gem_suspend(struct drm_device *dev)
4655 {
4656         struct drm_i915_private *dev_priv = dev->dev_private;
4657         int ret = 0;
4658
4659         mutex_lock(&dev->struct_mutex);
4660         ret = i915_gpu_idle(dev);
4661         if (ret)
4662                 goto err;
4663
4664         i915_gem_retire_requests(dev);
4665
4666         /* Under UMS, be paranoid and evict. */
4667         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4668                 i915_gem_evict_everything(dev);
4669
4670         i915_gem_stop_ringbuffers(dev);
4671         mutex_unlock(&dev->struct_mutex);
4672
4673         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4674         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4675         flush_delayed_work(&dev_priv->mm.idle_work);
4676
4677         return 0;
4678
4679 err:
4680         mutex_unlock(&dev->struct_mutex);
4681         return ret;
4682 }
4683
4684 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4685 {
4686         struct drm_device *dev = ring->dev;
4687         struct drm_i915_private *dev_priv = dev->dev_private;
4688         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4689         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4690         int i, ret;
4691
4692         if (!HAS_L3_DPF(dev) || !remap_info)
4693                 return 0;
4694
4695         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4696         if (ret)
4697                 return ret;
4698
4699         /*
4700          * Note: We do not worry about the concurrent register cacheline hang
4701          * here because no other code should access these registers other than
4702          * at initialization time.
4703          */
4704         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4705                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4706                 intel_ring_emit(ring, reg_base + i);
4707                 intel_ring_emit(ring, remap_info[i/4]);
4708         }
4709
4710         intel_ring_advance(ring);
4711
4712         return ret;
4713 }
4714
4715 void i915_gem_init_swizzling(struct drm_device *dev)
4716 {
4717         struct drm_i915_private *dev_priv = dev->dev_private;
4718
4719         if (INTEL_INFO(dev)->gen < 5 ||
4720             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4721                 return;
4722
4723         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4724                                  DISP_TILE_SURFACE_SWIZZLING);
4725
4726         if (IS_GEN5(dev))
4727                 return;
4728
4729         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4730         if (IS_GEN6(dev))
4731                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4732         else if (IS_GEN7(dev))
4733                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4734         else if (IS_GEN8(dev))
4735                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4736         else
4737                 BUG();
4738 }
4739
4740 static bool
4741 intel_enable_blt(struct drm_device *dev)
4742 {
4743         if (!HAS_BLT(dev))
4744                 return false;
4745
4746         /* The blitter was dysfunctional on early prototypes */
4747         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4748                 DRM_INFO("BLT not supported on this pre-production hardware;"
4749                          " graphics performance will be degraded.\n");
4750                 return false;
4751         }
4752
4753         return true;
4754 }
4755
4756 static void init_unused_ring(struct drm_device *dev, u32 base)
4757 {
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759
4760         I915_WRITE(RING_CTL(base), 0);
4761         I915_WRITE(RING_HEAD(base), 0);
4762         I915_WRITE(RING_TAIL(base), 0);
4763         I915_WRITE(RING_START(base), 0);
4764 }
4765
4766 static void init_unused_rings(struct drm_device *dev)
4767 {
4768         if (IS_I830(dev)) {
4769                 init_unused_ring(dev, PRB1_BASE);
4770                 init_unused_ring(dev, SRB0_BASE);
4771                 init_unused_ring(dev, SRB1_BASE);
4772                 init_unused_ring(dev, SRB2_BASE);
4773                 init_unused_ring(dev, SRB3_BASE);
4774         } else if (IS_GEN2(dev)) {
4775                 init_unused_ring(dev, SRB0_BASE);
4776                 init_unused_ring(dev, SRB1_BASE);
4777         } else if (IS_GEN3(dev)) {
4778                 init_unused_ring(dev, PRB1_BASE);
4779                 init_unused_ring(dev, PRB2_BASE);
4780         }
4781 }
4782
4783 int i915_gem_init_rings(struct drm_device *dev)
4784 {
4785         struct drm_i915_private *dev_priv = dev->dev_private;
4786         int ret;
4787
4788         /*
4789          * At least 830 can leave some of the unused rings
4790          * "active" (ie. head != tail) after resume which
4791          * will prevent c3 entry. Makes sure all unused rings
4792          * are totally idle.
4793          */
4794         init_unused_rings(dev);
4795
4796         ret = intel_init_render_ring_buffer(dev);
4797         if (ret)
4798                 return ret;
4799
4800         if (HAS_BSD(dev)) {
4801                 ret = intel_init_bsd_ring_buffer(dev);
4802                 if (ret)
4803                         goto cleanup_render_ring;
4804         }
4805
4806         if (intel_enable_blt(dev)) {
4807                 ret = intel_init_blt_ring_buffer(dev);
4808                 if (ret)
4809                         goto cleanup_bsd_ring;
4810         }
4811
4812         if (HAS_VEBOX(dev)) {
4813                 ret = intel_init_vebox_ring_buffer(dev);
4814                 if (ret)
4815                         goto cleanup_blt_ring;
4816         }
4817
4818         if (HAS_BSD2(dev)) {
4819                 ret = intel_init_bsd2_ring_buffer(dev);
4820                 if (ret)
4821                         goto cleanup_vebox_ring;
4822         }
4823
4824         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4825         if (ret)
4826                 goto cleanup_bsd2_ring;
4827
4828         return 0;
4829
4830 cleanup_bsd2_ring:
4831         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4832 cleanup_vebox_ring:
4833         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4834 cleanup_blt_ring:
4835         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4836 cleanup_bsd_ring:
4837         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4838 cleanup_render_ring:
4839         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4840
4841         return ret;
4842 }
4843
4844 int
4845 i915_gem_init_hw(struct drm_device *dev)
4846 {
4847         struct drm_i915_private *dev_priv = dev->dev_private;
4848         int ret, i;
4849
4850         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4851                 return -EIO;
4852
4853         if (dev_priv->ellc_size)
4854                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4855
4856         if (IS_HASWELL(dev))
4857                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4858                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4859
4860         if (HAS_PCH_NOP(dev)) {
4861                 if (IS_IVYBRIDGE(dev)) {
4862                         u32 temp = I915_READ(GEN7_MSG_CTL);
4863                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4864                         I915_WRITE(GEN7_MSG_CTL, temp);
4865                 } else if (INTEL_INFO(dev)->gen >= 7) {
4866                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4867                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4868                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4869                 }
4870         }
4871
4872         i915_gem_init_swizzling(dev);
4873
4874         ret = dev_priv->gt.init_rings(dev);
4875         if (ret)
4876                 return ret;
4877
4878         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4879                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4880
4881         /*
4882          * XXX: Contexts should only be initialized once. Doing a switch to the
4883          * default context switch however is something we'd like to do after
4884          * reset or thaw (the latter may not actually be necessary for HW, but
4885          * goes with our code better). Context switching requires rings (for
4886          * the do_switch), but before enabling PPGTT. So don't move this.
4887          */
4888         ret = i915_gem_context_enable(dev_priv);
4889         if (ret && ret != -EIO) {
4890                 DRM_ERROR("Context enable failed %d\n", ret);
4891                 i915_gem_cleanup_ringbuffer(dev);
4892
4893                 return ret;
4894         }
4895
4896         ret = i915_ppgtt_init_hw(dev);
4897         if (ret && ret != -EIO) {
4898                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4899                 i915_gem_cleanup_ringbuffer(dev);
4900         }
4901
4902         return ret;
4903 }
4904
4905 int i915_gem_init(struct drm_device *dev)
4906 {
4907         struct drm_i915_private *dev_priv = dev->dev_private;
4908         int ret;
4909
4910         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4911                         i915.enable_execlists);
4912
4913         mutex_lock(&dev->struct_mutex);
4914
4915         if (IS_VALLEYVIEW(dev)) {
4916                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4917                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4918                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4919                               VLV_GTLC_ALLOWWAKEACK), 10))
4920                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4921         }
4922
4923         if (!i915.enable_execlists) {
4924                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4925                 dev_priv->gt.init_rings = i915_gem_init_rings;
4926                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4927                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4928         } else {
4929                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4930                 dev_priv->gt.init_rings = intel_logical_rings_init;
4931                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4932                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4933         }
4934
4935         ret = i915_gem_init_userptr(dev);
4936         if (ret) {
4937                 mutex_unlock(&dev->struct_mutex);
4938                 return ret;
4939         }
4940
4941         i915_gem_init_global_gtt(dev);
4942
4943         ret = i915_gem_context_init(dev);
4944         if (ret) {
4945                 mutex_unlock(&dev->struct_mutex);
4946                 return ret;
4947         }
4948
4949         ret = i915_gem_init_hw(dev);
4950         if (ret == -EIO) {
4951                 /* Allow ring initialisation to fail by marking the GPU as
4952                  * wedged. But we only want to do this where the GPU is angry,
4953                  * for all other failure, such as an allocation failure, bail.
4954                  */
4955                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4956                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4957                 ret = 0;
4958         }
4959         mutex_unlock(&dev->struct_mutex);
4960
4961         return ret;
4962 }
4963
4964 void
4965 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4966 {
4967         struct drm_i915_private *dev_priv = dev->dev_private;
4968         struct intel_engine_cs *ring;
4969         int i;
4970
4971         for_each_ring(ring, dev_priv, i)
4972                 dev_priv->gt.cleanup_ring(ring);
4973 }
4974
4975 static void
4976 init_ring_lists(struct intel_engine_cs *ring)
4977 {
4978         INIT_LIST_HEAD(&ring->active_list);
4979         INIT_LIST_HEAD(&ring->request_list);
4980 }
4981
4982 void i915_init_vm(struct drm_i915_private *dev_priv,
4983                   struct i915_address_space *vm)
4984 {
4985         if (!i915_is_ggtt(vm))
4986                 drm_mm_init(&vm->mm, vm->start, vm->total);
4987         vm->dev = dev_priv->dev;
4988         INIT_LIST_HEAD(&vm->active_list);
4989         INIT_LIST_HEAD(&vm->inactive_list);
4990         INIT_LIST_HEAD(&vm->global_link);
4991         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4992 }
4993
4994 void
4995 i915_gem_load(struct drm_device *dev)
4996 {
4997         struct drm_i915_private *dev_priv = dev->dev_private;
4998         int i;
4999
5000         dev_priv->slab =
5001                 kmem_cache_create("i915_gem_object",
5002                                   sizeof(struct drm_i915_gem_object), 0,
5003                                   SLAB_HWCACHE_ALIGN,
5004                                   NULL);
5005
5006         INIT_LIST_HEAD(&dev_priv->vm_list);
5007         i915_init_vm(dev_priv, &dev_priv->gtt.base);
5008
5009         INIT_LIST_HEAD(&dev_priv->context_list);
5010         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5011         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5012         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5013         for (i = 0; i < I915_NUM_RINGS; i++)
5014                 init_ring_lists(&dev_priv->ring[i]);
5015         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5016                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5017         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5018                           i915_gem_retire_work_handler);
5019         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5020                           i915_gem_idle_work_handler);
5021         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5022
5023         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5024         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5025                 I915_WRITE(MI_ARB_STATE,
5026                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5027         }
5028
5029         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5030
5031         /* Old X drivers will take 0-2 for front, back, depth buffers */
5032         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5033                 dev_priv->fence_reg_start = 3;
5034
5035         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5036                 dev_priv->num_fence_regs = 32;
5037         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5038                 dev_priv->num_fence_regs = 16;
5039         else
5040                 dev_priv->num_fence_regs = 8;
5041
5042         /* Initialize fence registers to zero */
5043         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5044         i915_gem_restore_fences(dev);
5045
5046         i915_gem_detect_bit_6_swizzle(dev);
5047         init_waitqueue_head(&dev_priv->pending_flip_queue);
5048
5049         dev_priv->mm.interruptible = true;
5050
5051         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5052         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5053         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5054         register_shrinker(&dev_priv->mm.shrinker);
5055
5056         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5057         register_oom_notifier(&dev_priv->mm.oom_notifier);
5058
5059         mutex_init(&dev_priv->fb_tracking.lock);
5060 }
5061
5062 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5063 {
5064         struct drm_i915_file_private *file_priv = file->driver_priv;
5065
5066         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5067
5068         /* Clean up our request list when the client is going away, so that
5069          * later retire_requests won't dereference our soon-to-be-gone
5070          * file_priv.
5071          */
5072         spin_lock(&file_priv->mm.lock);
5073         while (!list_empty(&file_priv->mm.request_list)) {
5074                 struct drm_i915_gem_request *request;
5075
5076                 request = list_first_entry(&file_priv->mm.request_list,
5077                                            struct drm_i915_gem_request,
5078                                            client_list);
5079                 list_del(&request->client_list);
5080                 request->file_priv = NULL;
5081         }
5082         spin_unlock(&file_priv->mm.lock);
5083 }
5084
5085 static void
5086 i915_gem_file_idle_work_handler(struct work_struct *work)
5087 {
5088         struct drm_i915_file_private *file_priv =
5089                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5090
5091         atomic_set(&file_priv->rps_wait_boost, false);
5092 }
5093
5094 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5095 {
5096         struct drm_i915_file_private *file_priv;
5097         int ret;
5098
5099         DRM_DEBUG_DRIVER("\n");
5100
5101         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5102         if (!file_priv)
5103                 return -ENOMEM;
5104
5105         file->driver_priv = file_priv;
5106         file_priv->dev_priv = dev->dev_private;
5107         file_priv->file = file;
5108
5109         spin_lock_init(&file_priv->mm.lock);
5110         INIT_LIST_HEAD(&file_priv->mm.request_list);
5111         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5112                           i915_gem_file_idle_work_handler);
5113
5114         ret = i915_gem_context_open(dev, file);
5115         if (ret)
5116                 kfree(file_priv);
5117
5118         return ret;
5119 }
5120
5121 /**
5122  * i915_gem_track_fb - update frontbuffer tracking
5123  * old: current GEM buffer for the frontbuffer slots
5124  * new: new GEM buffer for the frontbuffer slots
5125  * frontbuffer_bits: bitmask of frontbuffer slots
5126  *
5127  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5128  * from @old and setting them in @new. Both @old and @new can be NULL.
5129  */
5130 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5131                        struct drm_i915_gem_object *new,
5132                        unsigned frontbuffer_bits)
5133 {
5134         if (old) {
5135                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5136                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5137                 old->frontbuffer_bits &= ~frontbuffer_bits;
5138         }
5139
5140         if (new) {
5141                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5142                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5143                 new->frontbuffer_bits |= frontbuffer_bits;
5144         }
5145 }
5146
5147 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5148 {
5149         if (!mutex_is_locked(mutex))
5150                 return false;
5151
5152 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5153         return mutex->owner == task;
5154 #else
5155         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5156         return false;
5157 #endif
5158 }
5159
5160 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5161 {
5162         if (!mutex_trylock(&dev->struct_mutex)) {
5163                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5164                         return false;
5165
5166                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5167                         return false;
5168
5169                 *unlock = false;
5170         } else
5171                 *unlock = true;
5172
5173         return true;
5174 }
5175
5176 static int num_vma_bound(struct drm_i915_gem_object *obj)
5177 {
5178         struct i915_vma *vma;
5179         int count = 0;
5180
5181         list_for_each_entry(vma, &obj->vma_list, vma_link)
5182                 if (drm_mm_node_allocated(&vma->node))
5183                         count++;
5184
5185         return count;
5186 }
5187
5188 static unsigned long
5189 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5190 {
5191         struct drm_i915_private *dev_priv =
5192                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5193         struct drm_device *dev = dev_priv->dev;
5194         struct drm_i915_gem_object *obj;
5195         unsigned long count;
5196         bool unlock;
5197
5198         if (!i915_gem_shrinker_lock(dev, &unlock))
5199                 return 0;
5200
5201         count = 0;
5202         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5203                 if (obj->pages_pin_count == 0)
5204                         count += obj->base.size >> PAGE_SHIFT;
5205
5206         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5207                 if (!i915_gem_obj_is_pinned(obj) &&
5208                     obj->pages_pin_count == num_vma_bound(obj))
5209                         count += obj->base.size >> PAGE_SHIFT;
5210         }
5211
5212         if (unlock)
5213                 mutex_unlock(&dev->struct_mutex);
5214
5215         return count;
5216 }
5217
5218 /* All the new VM stuff */
5219 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5220                                   struct i915_address_space *vm)
5221 {
5222         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5223         struct i915_vma *vma;
5224
5225         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5226
5227         list_for_each_entry(vma, &o->vma_list, vma_link) {
5228                 if (vma->vm == vm)
5229                         return vma->node.start;
5230
5231         }
5232         WARN(1, "%s vma for this object not found.\n",
5233              i915_is_ggtt(vm) ? "global" : "ppgtt");
5234         return -1;
5235 }
5236
5237 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5238                         struct i915_address_space *vm)
5239 {
5240         struct i915_vma *vma;
5241
5242         list_for_each_entry(vma, &o->vma_list, vma_link)
5243                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5244                         return true;
5245
5246         return false;
5247 }
5248
5249 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5250 {
5251         struct i915_vma *vma;
5252
5253         list_for_each_entry(vma, &o->vma_list, vma_link)
5254                 if (drm_mm_node_allocated(&vma->node))
5255                         return true;
5256
5257         return false;
5258 }
5259
5260 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5261                                 struct i915_address_space *vm)
5262 {
5263         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5264         struct i915_vma *vma;
5265
5266         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5267
5268         BUG_ON(list_empty(&o->vma_list));
5269
5270         list_for_each_entry(vma, &o->vma_list, vma_link)
5271                 if (vma->vm == vm)
5272                         return vma->node.size;
5273
5274         return 0;
5275 }
5276
5277 static unsigned long
5278 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5279 {
5280         struct drm_i915_private *dev_priv =
5281                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5282         struct drm_device *dev = dev_priv->dev;
5283         unsigned long freed;
5284         bool unlock;
5285
5286         if (!i915_gem_shrinker_lock(dev, &unlock))
5287                 return SHRINK_STOP;
5288
5289         freed = i915_gem_shrink(dev_priv,
5290                                 sc->nr_to_scan,
5291                                 I915_SHRINK_BOUND |
5292                                 I915_SHRINK_UNBOUND |
5293                                 I915_SHRINK_PURGEABLE);
5294         if (freed < sc->nr_to_scan)
5295                 freed += i915_gem_shrink(dev_priv,
5296                                          sc->nr_to_scan - freed,
5297                                          I915_SHRINK_BOUND |
5298                                          I915_SHRINK_UNBOUND);
5299         if (unlock)
5300                 mutex_unlock(&dev->struct_mutex);
5301
5302         return freed;
5303 }
5304
5305 static int
5306 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5307 {
5308         struct drm_i915_private *dev_priv =
5309                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5310         struct drm_device *dev = dev_priv->dev;
5311         struct drm_i915_gem_object *obj;
5312         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5313         unsigned long pinned, bound, unbound, freed_pages;
5314         bool was_interruptible;
5315         bool unlock;
5316
5317         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5318                 schedule_timeout_killable(1);
5319                 if (fatal_signal_pending(current))
5320                         return NOTIFY_DONE;
5321         }
5322         if (timeout == 0) {
5323                 pr_err("Unable to purge GPU memory due lock contention.\n");
5324                 return NOTIFY_DONE;
5325         }
5326
5327         was_interruptible = dev_priv->mm.interruptible;
5328         dev_priv->mm.interruptible = false;
5329
5330         freed_pages = i915_gem_shrink_all(dev_priv);
5331
5332         dev_priv->mm.interruptible = was_interruptible;
5333
5334         /* Because we may be allocating inside our own driver, we cannot
5335          * assert that there are no objects with pinned pages that are not
5336          * being pointed to by hardware.
5337          */
5338         unbound = bound = pinned = 0;
5339         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5340                 if (!obj->base.filp) /* not backed by a freeable object */
5341                         continue;
5342
5343                 if (obj->pages_pin_count)
5344                         pinned += obj->base.size;
5345                 else
5346                         unbound += obj->base.size;
5347         }
5348         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5349                 if (!obj->base.filp)
5350                         continue;
5351
5352                 if (obj->pages_pin_count)
5353                         pinned += obj->base.size;
5354                 else
5355                         bound += obj->base.size;
5356         }
5357
5358         if (unlock)
5359                 mutex_unlock(&dev->struct_mutex);
5360
5361         if (freed_pages || unbound || bound)
5362                 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5363                         freed_pages << PAGE_SHIFT, pinned);
5364         if (unbound || bound)
5365                 pr_err("%lu and %lu bytes still available in the "
5366                        "bound and unbound GPU page lists.\n",
5367                        bound, unbound);
5368
5369         *(unsigned long *)ptr += freed_pages;
5370         return NOTIFY_DONE;
5371 }
5372
5373 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5374 {
5375         struct i915_vma *vma;
5376
5377         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5378         if (vma->vm != i915_obj_to_ggtt(obj))
5379                 return NULL;
5380
5381         return vma;
5382 }