drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  64
  65 static bool cpu_cache_is_coherent(struct drm_device *dev,
  66                                   enum i915_cache_level level)
  67 {
  68         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  69 }
  70
  71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  72 {
  73         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  74                 return true;
  75
  76         return obj->pin_display;
  77 }
  78
  79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  80 {
  81         if (obj->tiling_mode)
  82                 i915_gem_release_mmap(obj);
  83
  84         /* As we do not have an associated fence register, we will force
  85          * a tiling change if we ever need to acquire one.
  86          */
  87         obj->fence_dirty = false;
  88         obj->fence_reg = I915_FENCE_REG_NONE;
  89 }
  90
  91 /* some bookkeeping */
  92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  93                                   size_t size)
  94 {
  95         spin_lock(&dev_priv->mm.object_stat_lock);
  96         dev_priv->mm.object_count++;
  97         dev_priv->mm.object_memory += size;
  98         spin_unlock(&dev_priv->mm.object_stat_lock);
  99 }
 100
 101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 102                                      size_t size)
 103 {
 104         spin_lock(&dev_priv->mm.object_stat_lock);
 105         dev_priv->mm.object_count--;
 106         dev_priv->mm.object_memory -= size;
 107         spin_unlock(&dev_priv->mm.object_stat_lock);
 108 }
 109
 110 static int
 111 i915_gem_wait_for_error(struct i915_gpu_error *error)
 112 {
 113         int ret;
 114
 115 #define EXIT_COND (!i915_reset_in_progress(error) || \
 116                    i915_terminally_wedged(error))
 117         if (EXIT_COND)
 118                 return 0;
 119
 120         /*
 121          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 122          * userspace. If it takes that long something really bad is going on and
 123          * we should simply try to bail out and fail as gracefully as possible.
 124          */
 125         ret = wait_event_interruptible_timeout(error->reset_queue,
 126                                                EXIT_COND,
 127                                                10*HZ);
 128         if (ret == 0) {
 129                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 130                 return -EIO;
 131         } else if (ret < 0) {
 132                 return ret;
 133         }
 134 #undef EXIT_COND
 135
 136         return 0;
 137 }
 138
 139 int i915_mutex_lock_interruptible(struct drm_device *dev)
 140 {
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         int ret;
 143
 144         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 145         if (ret)
 146                 return ret;
 147
 148         ret = mutex_lock_interruptible(&dev->struct_mutex);
 149         if (ret)
 150                 return ret;
 151
 152         WARN_ON(i915_verify_lists(dev));
 153         return 0;
 154 }
 155
 156 static inline bool
 157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 158 {
 159         return i915_gem_obj_bound_any(obj) && !obj->active;
 160 }
 161
 162 int
 163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 164                             struct drm_file *file)
 165 {
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167         struct drm_i915_gem_get_aperture *args = data;
 168         struct drm_i915_gem_object *obj;
 169         size_t pinned;
 170
 171         pinned = 0;
 172         mutex_lock(&dev->struct_mutex);
 173         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 174                 if (i915_gem_obj_is_pinned(obj))
 175                         pinned += i915_gem_obj_ggtt_size(obj);
 176         mutex_unlock(&dev->struct_mutex);
 177
 178         args->aper_size = dev_priv->gtt.base.total;
 179         args->aper_available_size = args->aper_size - pinned;
 180
 181         return 0;
 182 }
 183
 184 static int
 185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 186 {
 187         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 188         char *vaddr = obj->phys_handle->vaddr;
 189         struct sg_table *st;
 190         struct scatterlist *sg;
 191         int i;
 192
 193         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 194                 return -EINVAL;
 195
 196         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 197                 struct page *page;
 198                 char *src;
 199
 200                 page = shmem_read_mapping_page(mapping, i);
 201                 if (IS_ERR(page))
 202                         return PTR_ERR(page);
 203
 204                 src = kmap_atomic(page);
 205                 memcpy(vaddr, src, PAGE_SIZE);
 206                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 207                 kunmap_atomic(src);
 208
 209                 page_cache_release(page);
 210                 vaddr += PAGE_SIZE;
 211         }
 212
 213         i915_gem_chipset_flush(obj->base.dev);
 214
 215         st = kmalloc(sizeof(*st), GFP_KERNEL);
 216         if (st == NULL)
 217                 return -ENOMEM;
 218
 219         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 220                 kfree(st);
 221                 return -ENOMEM;
 222         }
 223
 224         sg = st->sgl;
 225         sg->offset = 0;
 226         sg->length = obj->base.size;
 227
 228         sg_dma_address(sg) = obj->phys_handle->busaddr;
 229         sg_dma_len(sg) = obj->base.size;
 230
 231         obj->pages = st;
 232         obj->has_dma_mapping = true;
 233         return 0;
 234 }
 235
 236 static void
 237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 238 {
 239         int ret;
 240
 241         BUG_ON(obj->madv == __I915_MADV_PURGED);
 242
 243         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 244         if (ret) {
 245                 /* In the event of a disaster, abandon all caches and
 246                  * hope for the best.
 247                  */
 248                 WARN_ON(ret != -EIO);
 249                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 250         }
 251
 252         if (obj->madv == I915_MADV_DONTNEED)
 253                 obj->dirty = 0;
 254
 255         if (obj->dirty) {
 256                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 257                 char *vaddr = obj->phys_handle->vaddr;
 258                 int i;
 259
 260                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 261                         struct page *page;
 262                         char *dst;
 263
 264                         page = shmem_read_mapping_page(mapping, i);
 265                         if (IS_ERR(page))
 266                                 continue;
 267
 268                         dst = kmap_atomic(page);
 269                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 270                         memcpy(dst, vaddr, PAGE_SIZE);
 271                         kunmap_atomic(dst);
 272
 273                         set_page_dirty(page);
 274                         if (obj->madv == I915_MADV_WILLNEED)
 275                                 mark_page_accessed(page);
 276                         page_cache_release(page);
 277                         vaddr += PAGE_SIZE;
 278                 }
 279                 obj->dirty = 0;
 280         }
 281
 282         sg_free_table(obj->pages);
 283         kfree(obj->pages);
 284
 285         obj->has_dma_mapping = false;
 286 }
 287
 288 static void
 289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 290 {
 291         drm_pci_free(obj->base.dev, obj->phys_handle);
 292 }
 293
 294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 295         .get_pages = i915_gem_object_get_pages_phys,
 296         .put_pages = i915_gem_object_put_pages_phys,
 297         .release = i915_gem_object_release_phys,
 298 };
 299
 300 static int
 301 drop_pages(struct drm_i915_gem_object *obj)
 302 {
 303         struct i915_vma *vma, *next;
 304         int ret;
 305
 306         drm_gem_object_reference(&obj->base);
 307         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 308                 if (i915_vma_unbind(vma))
 309                         break;
 310
 311         ret = i915_gem_object_put_pages(obj);
 312         drm_gem_object_unreference(&obj->base);
 313
 314         return ret;
 315 }
 316
 317 int
 318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 319                             int align)
 320 {
 321         drm_dma_handle_t *phys;
 322         int ret;
 323
 324         if (obj->phys_handle) {
 325                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 326                         return -EBUSY;
 327
 328                 return 0;
 329         }
 330
 331         if (obj->madv != I915_MADV_WILLNEED)
 332                 return -EFAULT;
 333
 334         if (obj->base.filp == NULL)
 335                 return -EINVAL;
 336
 337         ret = drop_pages(obj);
 338         if (ret)
 339                 return ret;
 340
 341         /* create a new object */
 342         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 343         if (!phys)
 344                 return -ENOMEM;
 345
 346         obj->phys_handle = phys;
 347         obj->ops = &i915_gem_phys_ops;
 348
 349         return i915_gem_object_get_pages(obj);
 350 }
 351
 352 static int
 353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 354                      struct drm_i915_gem_pwrite *args,
 355                      struct drm_file *file_priv)
 356 {
 357         struct drm_device *dev = obj->base.dev;
 358         void *vaddr = obj->phys_handle->vaddr + args->offset;
 359         char __user *user_data = to_user_ptr(args->data_ptr);
 360         int ret;
 361
 362         /* We manually control the domain here and pretend that it
 363          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 364          */
 365         ret = i915_gem_object_wait_rendering(obj, false);
 366         if (ret)
 367                 return ret;
 368
 369         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 370                 unsigned long unwritten;
 371
 372                 /* The physical object once assigned is fixed for the lifetime
 373                  * of the obj, so we can safely drop the lock and continue
 374                  * to access vaddr.
 375                  */
 376                 mutex_unlock(&dev->struct_mutex);
 377                 unwritten = copy_from_user(vaddr, user_data, args->size);
 378                 mutex_lock(&dev->struct_mutex);
 379                 if (unwritten)
 380                         return -EFAULT;
 381         }
 382
 383         drm_clflush_virt_range(vaddr, args->size);
 384         i915_gem_chipset_flush(dev);
 385         return 0;
 386 }
 387
 388 void *i915_gem_object_alloc(struct drm_device *dev)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 392 }
 393
 394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 395 {
 396         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 397         kmem_cache_free(dev_priv->slab, obj);
 398 }
 399
 400 static int
 401 i915_gem_create(struct drm_file *file,
 402                 struct drm_device *dev,
 403                 uint64_t size,
 404                 bool dumb,
 405                 uint32_t *handle_p)
 406 {
 407         struct drm_i915_gem_object *obj;
 408         int ret;
 409         u32 handle;
 410
 411         size = roundup(size, PAGE_SIZE);
 412         if (size == 0)
 413                 return -EINVAL;
 414
 415         /* Allocate the new object */
 416         obj = i915_gem_alloc_object(dev, size);
 417         if (obj == NULL)
 418                 return -ENOMEM;
 419
 420         obj->base.dumb = dumb;
 421         ret = drm_gem_handle_create(file, &obj->base, &handle);
 422         /* drop reference from allocate - handle holds it now */
 423         drm_gem_object_unreference_unlocked(&obj->base);
 424         if (ret)
 425                 return ret;
 426
 427         *handle_p = handle;
 428         return 0;
 429 }
 430
 431 int
 432 i915_gem_dumb_create(struct drm_file *file,
 433                      struct drm_device *dev,
 434                      struct drm_mode_create_dumb *args)
 435 {
 436         /* have to work out size/pitch and return them */
 437         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 438         args->size = args->pitch * args->height;
 439         return i915_gem_create(file, dev,
 440                                args->size, true, &args->handle);
 441 }
 442
 443 /**
 444  * Creates a new mm object and returns a handle to it.
 445  */
 446 int
 447 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 448                       struct drm_file *file)
 449 {
 450         struct drm_i915_gem_create *args = data;
 451
 452         return i915_gem_create(file, dev,
 453                                args->size, false, &args->handle);
 454 }
 455
 456 static inline int
 457 __copy_to_user_swizzled(char __user *cpu_vaddr,
 458                         const char *gpu_vaddr, int gpu_offset,
 459                         int length)
 460 {
 461         int ret, cpu_offset = 0;
 462
 463         while (length > 0) {
 464                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 465                 int this_length = min(cacheline_end - gpu_offset, length);
 466                 int swizzled_gpu_offset = gpu_offset ^ 64;
 467
 468                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 469                                      gpu_vaddr + swizzled_gpu_offset,
 470                                      this_length);
 471                 if (ret)
 472                         return ret + length;
 473
 474                 cpu_offset += this_length;
 475                 gpu_offset += this_length;
 476                 length -= this_length;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static inline int
 483 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 484                           const char __user *cpu_vaddr,
 485                           int length)
 486 {
 487         int ret, cpu_offset = 0;
 488
 489         while (length > 0) {
 490                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 491                 int this_length = min(cacheline_end - gpu_offset, length);
 492                 int swizzled_gpu_offset = gpu_offset ^ 64;
 493
 494                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 495                                        cpu_vaddr + cpu_offset,
 496                                        this_length);
 497                 if (ret)
 498                         return ret + length;
 499
 500                 cpu_offset += this_length;
 501                 gpu_offset += this_length;
 502                 length -= this_length;
 503         }
 504
 505         return 0;
 506 }
 507
 508 /*
 509  * Pins the specified object's pages and synchronizes the object with
 510  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 511  * flush the object from the CPU cache.
 512  */
 513 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 514                                     int *needs_clflush)
 515 {
 516         int ret;
 517
 518         *needs_clflush = 0;
 519
 520         if (!obj->base.filp)
 521                 return -EINVAL;
 522
 523         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 524                 /* If we're not in the cpu read domain, set ourself into the gtt
 525                  * read domain and manually flush cachelines (if required). This
 526                  * optimizes for the case when the gpu will dirty the data
 527                  * anyway again before the next pread happens. */
 528                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 529                                                         obj->cache_level);
 530                 ret = i915_gem_object_wait_rendering(obj, true);
 531                 if (ret)
 532                         return ret;
 533
 534                 i915_gem_object_retire(obj);
 535         }
 536
 537         ret = i915_gem_object_get_pages(obj);
 538         if (ret)
 539                 return ret;
 540
 541         i915_gem_object_pin_pages(obj);
 542
 543         return ret;
 544 }
 545
 546 /* Per-page copy function for the shmem pread fastpath.
 547  * Flushes invalid cachelines before reading the target if
 548  * needs_clflush is set. */
 549 static int
 550 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 551                  char __user *user_data,
 552                  bool page_do_bit17_swizzling, bool needs_clflush)
 553 {
 554         char *vaddr;
 555         int ret;
 556
 557         if (unlikely(page_do_bit17_swizzling))
 558                 return -EINVAL;
 559
 560         vaddr = kmap_atomic(page);
 561         if (needs_clflush)
 562                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 563                                        page_length);
 564         ret = __copy_to_user_inatomic(user_data,
 565                                       vaddr + shmem_page_offset,
 566                                       page_length);
 567         kunmap_atomic(vaddr);
 568
 569         return ret ? -EFAULT : 0;
 570 }
 571
 572 static void
 573 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 574                              bool swizzled)
 575 {
 576         if (unlikely(swizzled)) {
 577                 unsigned long start = (unsigned long) addr;
 578                 unsigned long end = (unsigned long) addr + length;
 579
 580                 /* For swizzling simply ensure that we always flush both
 581                  * channels. Lame, but simple and it works. Swizzled
 582                  * pwrite/pread is far from a hotpath - current userspace
 583                  * doesn't use it at all. */
 584                 start = round_down(start, 128);
 585                 end = round_up(end, 128);
 586
 587                 drm_clflush_virt_range((void *)start, end - start);
 588         } else {
 589                 drm_clflush_virt_range(addr, length);
 590         }
 591
 592 }
 593
 594 /* Only difference to the fast-path function is that this can handle bit17
 595  * and uses non-atomic copy and kmap functions. */
 596 static int
 597 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 598                  char __user *user_data,
 599                  bool page_do_bit17_swizzling, bool needs_clflush)
 600 {
 601         char *vaddr;
 602         int ret;
 603
 604         vaddr = kmap(page);
 605         if (needs_clflush)
 606                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 607                                              page_length,
 608                                              page_do_bit17_swizzling);
 609
 610         if (page_do_bit17_swizzling)
 611                 ret = __copy_to_user_swizzled(user_data,
 612                                               vaddr, shmem_page_offset,
 613                                               page_length);
 614         else
 615                 ret = __copy_to_user(user_data,
 616                                      vaddr + shmem_page_offset,
 617                                      page_length);
 618         kunmap(page);
 619
 620         return ret ? - EFAULT : 0;
 621 }
 622
 623 static int
 624 i915_gem_shmem_pread(struct drm_device *dev,
 625                      struct drm_i915_gem_object *obj,
 626                      struct drm_i915_gem_pread *args,
 627                      struct drm_file *file)
 628 {
 629         char __user *user_data;
 630         ssize_t remain;
 631         loff_t offset;
 632         int shmem_page_offset, page_length, ret = 0;
 633         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 634         int prefaulted = 0;
 635         int needs_clflush = 0;
 636         struct sg_page_iter sg_iter;
 637
 638         user_data = to_user_ptr(args->data_ptr);
 639         remain = args->size;
 640
 641         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 642
 643         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 644         if (ret)
 645                 return ret;
 646
 647         offset = args->offset;
 648
 649         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 650                          offset >> PAGE_SHIFT) {
 651                 struct page *page = sg_page_iter_page(&sg_iter);
 652
 653                 if (remain <= 0)
 654                         break;
 655
 656                 /* Operation in this page
 657                  *
 658                  * shmem_page_offset = offset within page in shmem file
 659                  * page_length = bytes to copy for this page
 660                  */
 661                 shmem_page_offset = offset_in_page(offset);
 662                 page_length = remain;
 663                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 664                         page_length = PAGE_SIZE - shmem_page_offset;
 665
 666                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 667                         (page_to_phys(page) & (1 << 17)) != 0;
 668
 669                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 670                                        user_data, page_do_bit17_swizzling,
 671                                        needs_clflush);
 672                 if (ret == 0)
 673                         goto next_page;
 674
 675                 mutex_unlock(&dev->struct_mutex);
 676
 677                 if (likely(!i915.prefault_disable) && !prefaulted) {
 678                         ret = fault_in_multipages_writeable(user_data, remain);
 679                         /* Userspace is tricking us, but we've already clobbered
 680                          * its pages with the prefault and promised to write the
 681                          * data up to the first fault. Hence ignore any errors
 682                          * and just continue. */
 683                         (void)ret;
 684                         prefaulted = 1;
 685                 }
 686
 687                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 688                                        user_data, page_do_bit17_swizzling,
 689                                        needs_clflush);
 690
 691                 mutex_lock(&dev->struct_mutex);
 692
 693                 if (ret)
 694                         goto out;
 695
 696 next_page:
 697                 remain -= page_length;
 698                 user_data += page_length;
 699                 offset += page_length;
 700         }
 701
 702 out:
 703         i915_gem_object_unpin_pages(obj);
 704
 705         return ret;
 706 }
 707
 708 /**
 709  * Reads data from the object referenced by handle.
 710  *
 711  * On error, the contents of *data are undefined.
 712  */
 713 int
 714 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 715                      struct drm_file *file)
 716 {
 717         struct drm_i915_gem_pread *args = data;
 718         struct drm_i915_gem_object *obj;
 719         int ret = 0;
 720
 721         if (args->size == 0)
 722                 return 0;
 723
 724         if (!access_ok(VERIFY_WRITE,
 725                        to_user_ptr(args->data_ptr),
 726                        args->size))
 727                 return -EFAULT;
 728
 729         ret = i915_mutex_lock_interruptible(dev);
 730         if (ret)
 731                 return ret;
 732
 733         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 734         if (&obj->base == NULL) {
 735                 ret = -ENOENT;
 736                 goto unlock;
 737         }
 738
 739         /* Bounds check source.  */
 740         if (args->offset > obj->base.size ||
 741             args->size > obj->base.size - args->offset) {
 742                 ret = -EINVAL;
 743                 goto out;
 744         }
 745
 746         /* prime objects have no backing filp to GEM pread/pwrite
 747          * pages from.
 748          */
 749         if (!obj->base.filp) {
 750                 ret = -EINVAL;
 751                 goto out;
 752         }
 753
 754         trace_i915_gem_object_pread(obj, args->offset, args->size);
 755
 756         ret = i915_gem_shmem_pread(dev, obj, args, file);
 757
 758 out:
 759         drm_gem_object_unreference(&obj->base);
 760 unlock:
 761         mutex_unlock(&dev->struct_mutex);
 762         return ret;
 763 }
 764
 765 /* This is the fast write path which cannot handle
 766  * page faults in the source data
 767  */
 768
 769 static inline int
 770 fast_user_write(struct io_mapping *mapping,
 771                 loff_t page_base, int page_offset,
 772                 char __user *user_data,
 773                 int length)
 774 {
 775         void __iomem *vaddr_atomic;
 776         void *vaddr;
 777         unsigned long unwritten;
 778
 779         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 780         /* We can use the cpu mem copy function because this is X86. */
 781         vaddr = (void __force*)vaddr_atomic + page_offset;
 782         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 783                                                       user_data, length);
 784         io_mapping_unmap_atomic(vaddr_atomic);
 785         return unwritten;
 786 }
 787
 788 /**
 789  * This is the fast pwrite path, where we copy the data directly from the
 790  * user into the GTT, uncached.
 791  */
 792 static int
 793 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 794                          struct drm_i915_gem_object *obj,
 795                          struct drm_i915_gem_pwrite *args,
 796                          struct drm_file *file)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         ssize_t remain;
 800         loff_t offset, page_base;
 801         char __user *user_data;
 802         int page_offset, page_length, ret;
 803
 804         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 805         if (ret)
 806                 goto out;
 807
 808         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 809         if (ret)
 810                 goto out_unpin;
 811
 812         ret = i915_gem_object_put_fence(obj);
 813         if (ret)
 814                 goto out_unpin;
 815
 816         user_data = to_user_ptr(args->data_ptr);
 817         remain = args->size;
 818
 819         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 820
 821         while (remain > 0) {
 822                 /* Operation in this page
 823                  *
 824                  * page_base = page offset within aperture
 825                  * page_offset = offset within page
 826                  * page_length = bytes to copy for this page
 827                  */
 828                 page_base = offset & PAGE_MASK;
 829                 page_offset = offset_in_page(offset);
 830                 page_length = remain;
 831                 if ((page_offset + remain) > PAGE_SIZE)
 832                         page_length = PAGE_SIZE - page_offset;
 833
 834                 /* If we get a fault while copying data, then (presumably) our
 835                  * source page isn't available.  Return the error and we'll
 836                  * retry in the slow path.
 837                  */
 838                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 839                                     page_offset, user_data, page_length)) {
 840                         ret = -EFAULT;
 841                         goto out_unpin;
 842                 }
 843
 844                 remain -= page_length;
 845                 user_data += page_length;
 846                 offset += page_length;
 847         }
 848
 849 out_unpin:
 850         i915_gem_object_ggtt_unpin(obj);
 851 out:
 852         return ret;
 853 }
 854
 855 /* Per-page copy function for the shmem pwrite fastpath.
 856  * Flushes invalid cachelines before writing to the target if
 857  * needs_clflush_before is set and flushes out any written cachelines after
 858  * writing if needs_clflush is set. */
 859 static int
 860 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 861                   char __user *user_data,
 862                   bool page_do_bit17_swizzling,
 863                   bool needs_clflush_before,
 864                   bool needs_clflush_after)
 865 {
 866         char *vaddr;
 867         int ret;
 868
 869         if (unlikely(page_do_bit17_swizzling))
 870                 return -EINVAL;
 871
 872         vaddr = kmap_atomic(page);
 873         if (needs_clflush_before)
 874                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 875                                        page_length);
 876         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 877                                         user_data, page_length);
 878         if (needs_clflush_after)
 879                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 880                                        page_length);
 881         kunmap_atomic(vaddr);
 882
 883         return ret ? -EFAULT : 0;
 884 }
 885
 886 /* Only difference to the fast-path function is that this can handle bit17
 887  * and uses non-atomic copy and kmap functions. */
 888 static int
 889 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 890                   char __user *user_data,
 891                   bool page_do_bit17_swizzling,
 892                   bool needs_clflush_before,
 893                   bool needs_clflush_after)
 894 {
 895         char *vaddr;
 896         int ret;
 897
 898         vaddr = kmap(page);
 899         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 900                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 901                                              page_length,
 902                                              page_do_bit17_swizzling);
 903         if (page_do_bit17_swizzling)
 904                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 905                                                 user_data,
 906                                                 page_length);
 907         else
 908                 ret = __copy_from_user(vaddr + shmem_page_offset,
 909                                        user_data,
 910                                        page_length);
 911         if (needs_clflush_after)
 912                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 913                                              page_length,
 914                                              page_do_bit17_swizzling);
 915         kunmap(page);
 916
 917         return ret ? -EFAULT : 0;
 918 }
 919
 920 static int
 921 i915_gem_shmem_pwrite(struct drm_device *dev,
 922                       struct drm_i915_gem_object *obj,
 923                       struct drm_i915_gem_pwrite *args,
 924                       struct drm_file *file)
 925 {
 926         ssize_t remain;
 927         loff_t offset;
 928         char __user *user_data;
 929         int shmem_page_offset, page_length, ret = 0;
 930         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 931         int hit_slowpath = 0;
 932         int needs_clflush_after = 0;
 933         int needs_clflush_before = 0;
 934         struct sg_page_iter sg_iter;
 935
 936         user_data = to_user_ptr(args->data_ptr);
 937         remain = args->size;
 938
 939         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 940
 941         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 942                 /* If we're not in the cpu write domain, set ourself into the gtt
 943                  * write domain and manually flush cachelines (if required). This
 944                  * optimizes for the case when the gpu will use the data
 945                  * right away and we therefore have to clflush anyway. */
 946                 needs_clflush_after = cpu_write_needs_clflush(obj);
 947                 ret = i915_gem_object_wait_rendering(obj, false);
 948                 if (ret)
 949                         return ret;
 950
 951                 i915_gem_object_retire(obj);
 952         }
 953         /* Same trick applies to invalidate partially written cachelines read
 954          * before writing. */
 955         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 956                 needs_clflush_before =
 957                         !cpu_cache_is_coherent(dev, obj->cache_level);
 958
 959         ret = i915_gem_object_get_pages(obj);
 960         if (ret)
 961                 return ret;
 962
 963         i915_gem_object_pin_pages(obj);
 964
 965         offset = args->offset;
 966         obj->dirty = 1;
 967
 968         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 969                          offset >> PAGE_SHIFT) {
 970                 struct page *page = sg_page_iter_page(&sg_iter);
 971                 int partial_cacheline_write;
 972
 973                 if (remain <= 0)
 974                         break;
 975
 976                 /* Operation in this page
 977                  *
 978                  * shmem_page_offset = offset within page in shmem file
 979                  * page_length = bytes to copy for this page
 980                  */
 981                 shmem_page_offset = offset_in_page(offset);
 982
 983                 page_length = remain;
 984                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 985                         page_length = PAGE_SIZE - shmem_page_offset;
 986
 987                 /* If we don't overwrite a cacheline completely we need to be
 988                  * careful to have up-to-date data by first clflushing. Don't
 989                  * overcomplicate things and flush the entire patch. */
 990                 partial_cacheline_write = needs_clflush_before &&
 991                         ((shmem_page_offset | page_length)
 992                                 & (boot_cpu_data.x86_clflush_size - 1));
 993
 994                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 995                         (page_to_phys(page) & (1 << 17)) != 0;
 996
 997                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 998                                         user_data, page_do_bit17_swizzling,
 999                                         partial_cacheline_write,
1000                                         needs_clflush_after);
1001                 if (ret == 0)
1002                         goto next_page;
1003
1004                 hit_slowpath = 1;
1005                 mutex_unlock(&dev->struct_mutex);
1006                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1007                                         user_data, page_do_bit17_swizzling,
1008                                         partial_cacheline_write,
1009                                         needs_clflush_after);
1010
1011                 mutex_lock(&dev->struct_mutex);
1012
1013                 if (ret)
1014                         goto out;
1015
1016 next_page:
1017                 remain -= page_length;
1018                 user_data += page_length;
1019                 offset += page_length;
1020         }
1021
1022 out:
1023         i915_gem_object_unpin_pages(obj);
1024
1025         if (hit_slowpath) {
1026                 /*
1027                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1028                  * cachelines in-line while writing and the object moved
1029                  * out of the cpu write domain while we've dropped the lock.
1030                  */
1031                 if (!needs_clflush_after &&
1032                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1033                         if (i915_gem_clflush_object(obj, obj->pin_display))
1034                                 i915_gem_chipset_flush(dev);
1035                 }
1036         }
1037
1038         if (needs_clflush_after)
1039                 i915_gem_chipset_flush(dev);
1040
1041         return ret;
1042 }
1043
1044 /**
1045  * Writes data to the object referenced by handle.
1046  *
1047  * On error, the contents of the buffer that were to be modified are undefined.
1048  */
1049 int
1050 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1051                       struct drm_file *file)
1052 {
1053         struct drm_i915_gem_pwrite *args = data;
1054         struct drm_i915_gem_object *obj;
1055         int ret;
1056
1057         if (args->size == 0)
1058                 return 0;
1059
1060         if (!access_ok(VERIFY_READ,
1061                        to_user_ptr(args->data_ptr),
1062                        args->size))
1063                 return -EFAULT;
1064
1065         if (likely(!i915.prefault_disable)) {
1066                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1067                                                    args->size);
1068                 if (ret)
1069                         return -EFAULT;
1070         }
1071
1072         ret = i915_mutex_lock_interruptible(dev);
1073         if (ret)
1074                 return ret;
1075
1076         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1077         if (&obj->base == NULL) {
1078                 ret = -ENOENT;
1079                 goto unlock;
1080         }
1081
1082         /* Bounds check destination. */
1083         if (args->offset > obj->base.size ||
1084             args->size > obj->base.size - args->offset) {
1085                 ret = -EINVAL;
1086                 goto out;
1087         }
1088
1089         /* prime objects have no backing filp to GEM pread/pwrite
1090          * pages from.
1091          */
1092         if (!obj->base.filp) {
1093                 ret = -EINVAL;
1094                 goto out;
1095         }
1096
1097         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1098
1099         ret = -EFAULT;
1100         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1101          * it would end up going through the fenced access, and we'll get
1102          * different detiling behavior between reading and writing.
1103          * pread/pwrite currently are reading and writing from the CPU
1104          * perspective, requiring manual detiling by the client.
1105          */
1106         if (obj->tiling_mode == I915_TILING_NONE &&
1107             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1108             cpu_write_needs_clflush(obj)) {
1109                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1110                 /* Note that the gtt paths might fail with non-page-backed user
1111                  * pointers (e.g. gtt mappings when moving data between
1112                  * textures). Fallback to the shmem path in that case. */
1113         }
1114
1115         if (ret == -EFAULT || ret == -ENOSPC) {
1116                 if (obj->phys_handle)
1117                         ret = i915_gem_phys_pwrite(obj, args, file);
1118                 else
1119                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1120         }
1121
1122 out:
1123         drm_gem_object_unreference(&obj->base);
1124 unlock:
1125         mutex_unlock(&dev->struct_mutex);
1126         return ret;
1127 }
1128
1129 int
1130 i915_gem_check_wedge(struct i915_gpu_error *error,
1131                      bool interruptible)
1132 {
1133         if (i915_reset_in_progress(error)) {
1134                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1135                  * -EIO unconditionally for these. */
1136                 if (!interruptible)
1137                         return -EIO;
1138
1139                 /* Recovery complete, but the reset failed ... */
1140                 if (i915_terminally_wedged(error))
1141                         return -EIO;
1142
1143                 /*
1144                  * Check if GPU Reset is in progress - we need intel_ring_begin
1145                  * to work properly to reinit the hw state while the gpu is
1146                  * still marked as reset-in-progress. Handle this with a flag.
1147                  */
1148                 if (!error->reload_in_reset)
1149                         return -EAGAIN;
1150         }
1151
1152         return 0;
1153 }
1154
1155 /*
1156  * Compare arbitrary request against outstanding lazy request. Emit on match.
1157  */
1158 int
1159 i915_gem_check_olr(struct drm_i915_gem_request *req)
1160 {
1161         int ret;
1162
1163         WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1164
1165         ret = 0;
1166         if (req == req->ring->outstanding_lazy_request)
1167                 ret = i915_add_request(req->ring);
1168
1169         return ret;
1170 }
1171
1172 static void fake_irq(unsigned long data)
1173 {
1174         wake_up_process((struct task_struct *)data);
1175 }
1176
1177 static bool missed_irq(struct drm_i915_private *dev_priv,
1178                        struct intel_engine_cs *ring)
1179 {
1180         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1181 }
1182
1183 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1184 {
1185         if (file_priv == NULL)
1186                 return true;
1187
1188         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1189 }
1190
1191 /**
1192  * __i915_wait_request - wait until execution of request has finished
1193  * @req: duh!
1194  * @reset_counter: reset sequence associated with the given request
1195  * @interruptible: do an interruptible wait (normally yes)
1196  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1197  *
1198  * Note: It is of utmost importance that the passed in seqno and reset_counter
1199  * values have been read by the caller in an smp safe manner. Where read-side
1200  * locks are involved, it is sufficient to read the reset_counter before
1201  * unlocking the lock that protects the seqno. For lockless tricks, the
1202  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1203  * inserted.
1204  *
1205  * Returns 0 if the request was found within the alloted time. Else returns the
1206  * errno with remaining time filled in timeout argument.
1207  */
1208 int __i915_wait_request(struct drm_i915_gem_request *req,
1209                         unsigned reset_counter,
1210                         bool interruptible,
1211                         s64 *timeout,
1212                         struct drm_i915_file_private *file_priv)
1213 {
1214         struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1215         struct drm_device *dev = ring->dev;
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         const bool irq_test_in_progress =
1218                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1219         DEFINE_WAIT(wait);
1220         unsigned long timeout_expire;
1221         s64 before, now;
1222         int ret;
1223
1224         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1225
1226         if (i915_gem_request_completed(req, true))
1227                 return 0;
1228
1229         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1230
1231         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1232                 gen6_rps_boost(dev_priv);
1233                 if (file_priv)
1234                         mod_delayed_work(dev_priv->wq,
1235                                          &file_priv->mm.idle_work,
1236                                          msecs_to_jiffies(100));
1237         }
1238
1239         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1240                 return -ENODEV;
1241
1242         /* Record current time in case interrupted by signal, or wedged */
1243         trace_i915_gem_request_wait_begin(req);
1244         before = ktime_get_raw_ns();
1245         for (;;) {
1246                 struct timer_list timer;
1247
1248                 prepare_to_wait(&ring->irq_queue, &wait,
1249                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1250
1251                 /* We need to check whether any gpu reset happened in between
1252                  * the caller grabbing the seqno and now ... */
1253                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1254                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1255                          * is truely gone. */
1256                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1257                         if (ret == 0)
1258                                 ret = -EAGAIN;
1259                         break;
1260                 }
1261
1262                 if (i915_gem_request_completed(req, false)) {
1263                         ret = 0;
1264                         break;
1265                 }
1266
1267                 if (interruptible && signal_pending(current)) {
1268                         ret = -ERESTARTSYS;
1269                         break;
1270                 }
1271
1272                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1273                         ret = -ETIME;
1274                         break;
1275                 }
1276
1277                 timer.function = NULL;
1278                 if (timeout || missed_irq(dev_priv, ring)) {
1279                         unsigned long expire;
1280
1281                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1282                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1283                         mod_timer(&timer, expire);
1284                 }
1285
1286                 io_schedule();
1287
1288                 if (timer.function) {
1289                         del_singleshot_timer_sync(&timer);
1290                         destroy_timer_on_stack(&timer);
1291                 }
1292         }
1293         now = ktime_get_raw_ns();
1294         trace_i915_gem_request_wait_end(req);
1295
1296         if (!irq_test_in_progress)
1297                 ring->irq_put(ring);
1298
1299         finish_wait(&ring->irq_queue, &wait);
1300
1301         if (timeout) {
1302                 s64 tres = *timeout - (now - before);
1303
1304                 *timeout = tres < 0 ? 0 : tres;
1305         }
1306
1307         return ret;
1308 }
1309
1310 /**
1311  * Waits for a request to be signaled, and cleans up the
1312  * request and object lists appropriately for that event.
1313  */
1314 int
1315 i915_wait_request(struct drm_i915_gem_request *req)
1316 {
1317         struct drm_device *dev;
1318         struct drm_i915_private *dev_priv;
1319         bool interruptible;
1320         unsigned reset_counter;
1321         int ret;
1322
1323         BUG_ON(req == NULL);
1324
1325         dev = req->ring->dev;
1326         dev_priv = dev->dev_private;
1327         interruptible = dev_priv->mm.interruptible;
1328
1329         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1330
1331         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1332         if (ret)
1333                 return ret;
1334
1335         ret = i915_gem_check_olr(req);
1336         if (ret)
1337                 return ret;
1338
1339         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1340         i915_gem_request_reference(req);
1341         ret = __i915_wait_request(req, reset_counter,
1342                                   interruptible, NULL, NULL);
1343         i915_gem_request_unreference(req);
1344         return ret;
1345 }
1346
1347 static int
1348 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1349 {
1350         if (!obj->active)
1351                 return 0;
1352
1353         /* Manually manage the write flush as we may have not yet
1354          * retired the buffer.
1355          *
1356          * Note that the last_write_req is always the earlier of
1357          * the two (read/write) requests, so if we haved successfully waited,
1358          * we know we have passed the last write.
1359          */
1360         i915_gem_request_assign(&obj->last_write_req, NULL);
1361
1362         return 0;
1363 }
1364
1365 /**
1366  * Ensures that all rendering to the object has completed and the object is
1367  * safe to unbind from the GTT or access from the CPU.
1368  */
1369 static __must_check int
1370 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1371                                bool readonly)
1372 {
1373         struct drm_i915_gem_request *req;
1374         int ret;
1375
1376         req = readonly ? obj->last_write_req : obj->last_read_req;
1377         if (!req)
1378                 return 0;
1379
1380         ret = i915_wait_request(req);
1381         if (ret)
1382                 return ret;
1383
1384         return i915_gem_object_wait_rendering__tail(obj);
1385 }
1386
1387 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1388  * as the object state may change during this call.
1389  */
1390 static __must_check int
1391 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1392                                             struct drm_i915_file_private *file_priv,
1393                                             bool readonly)
1394 {
1395         struct drm_i915_gem_request *req;
1396         struct drm_device *dev = obj->base.dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         unsigned reset_counter;
1399         int ret;
1400
1401         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1402         BUG_ON(!dev_priv->mm.interruptible);
1403
1404         req = readonly ? obj->last_write_req : obj->last_read_req;
1405         if (!req)
1406                 return 0;
1407
1408         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1409         if (ret)
1410                 return ret;
1411
1412         ret = i915_gem_check_olr(req);
1413         if (ret)
1414                 return ret;
1415
1416         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1417         i915_gem_request_reference(req);
1418         mutex_unlock(&dev->struct_mutex);
1419         ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1420         mutex_lock(&dev->struct_mutex);
1421         i915_gem_request_unreference(req);
1422         if (ret)
1423                 return ret;
1424
1425         return i915_gem_object_wait_rendering__tail(obj);
1426 }
1427
1428 /**
1429  * Called when user space prepares to use an object with the CPU, either
1430  * through the mmap ioctl's mapping or a GTT mapping.
1431  */
1432 int
1433 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1434                           struct drm_file *file)
1435 {
1436         struct drm_i915_gem_set_domain *args = data;
1437         struct drm_i915_gem_object *obj;
1438         uint32_t read_domains = args->read_domains;
1439         uint32_t write_domain = args->write_domain;
1440         int ret;
1441
1442         /* Only handle setting domains to types used by the CPU. */
1443         if (write_domain & I915_GEM_GPU_DOMAINS)
1444                 return -EINVAL;
1445
1446         if (read_domains & I915_GEM_GPU_DOMAINS)
1447                 return -EINVAL;
1448
1449         /* Having something in the write domain implies it's in the read
1450          * domain, and only that read domain.  Enforce that in the request.
1451          */
1452         if (write_domain != 0 && read_domains != write_domain)
1453                 return -EINVAL;
1454
1455         ret = i915_mutex_lock_interruptible(dev);
1456         if (ret)
1457                 return ret;
1458
1459         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1460         if (&obj->base == NULL) {
1461                 ret = -ENOENT;
1462                 goto unlock;
1463         }
1464
1465         /* Try to flush the object off the GPU without holding the lock.
1466          * We will repeat the flush holding the lock in the normal manner
1467          * to catch cases where we are gazumped.
1468          */
1469         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1470                                                           file->driver_priv,
1471                                                           !write_domain);
1472         if (ret)
1473                 goto unref;
1474
1475         if (read_domains & I915_GEM_DOMAIN_GTT) {
1476                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1477
1478                 /* Silently promote "you're not bound, there was nothing to do"
1479                  * to success, since the client was just asking us to
1480                  * make sure everything was done.
1481                  */
1482                 if (ret == -EINVAL)
1483                         ret = 0;
1484         } else {
1485                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1486         }
1487
1488 unref:
1489         drm_gem_object_unreference(&obj->base);
1490 unlock:
1491         mutex_unlock(&dev->struct_mutex);
1492         return ret;
1493 }
1494
1495 /**
1496  * Called when user space has done writes to this buffer
1497  */
1498 int
1499 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1500                          struct drm_file *file)
1501 {
1502         struct drm_i915_gem_sw_finish *args = data;
1503         struct drm_i915_gem_object *obj;
1504         int ret = 0;
1505
1506         ret = i915_mutex_lock_interruptible(dev);
1507         if (ret)
1508                 return ret;
1509
1510         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1511         if (&obj->base == NULL) {
1512                 ret = -ENOENT;
1513                 goto unlock;
1514         }
1515
1516         /* Pinned buffers may be scanout, so flush the cache */
1517         if (obj->pin_display)
1518                 i915_gem_object_flush_cpu_write_domain(obj, true);
1519
1520         drm_gem_object_unreference(&obj->base);
1521 unlock:
1522         mutex_unlock(&dev->struct_mutex);
1523         return ret;
1524 }
1525
1526 /**
1527  * Maps the contents of an object, returning the address it is mapped
1528  * into.
1529  *
1530  * While the mapping holds a reference on the contents of the object, it doesn't
1531  * imply a ref on the object itself.
1532  *
1533  * IMPORTANT:
1534  *
1535  * DRM driver writers who look a this function as an example for how to do GEM
1536  * mmap support, please don't implement mmap support like here. The modern way
1537  * to implement DRM mmap support is with an mmap offset ioctl (like
1538  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539  * That way debug tooling like valgrind will understand what's going on, hiding
1540  * the mmap call in a driver private ioctl will break that. The i915 driver only
1541  * does cpu mmaps this way because we didn't know better.
1542  */
1543 int
1544 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1545                     struct drm_file *file)
1546 {
1547         struct drm_i915_gem_mmap *args = data;
1548         struct drm_gem_object *obj;
1549         unsigned long addr;
1550
1551         obj = drm_gem_object_lookup(dev, file, args->handle);
1552         if (obj == NULL)
1553                 return -ENOENT;
1554
1555         /* prime objects have no backing filp to GEM mmap
1556          * pages from.
1557          */
1558         if (!obj->filp) {
1559                 drm_gem_object_unreference_unlocked(obj);
1560                 return -EINVAL;
1561         }
1562
1563         addr = vm_mmap(obj->filp, 0, args->size,
1564                        PROT_READ | PROT_WRITE, MAP_SHARED,
1565                        args->offset);
1566         drm_gem_object_unreference_unlocked(obj);
1567         if (IS_ERR((void *)addr))
1568                 return addr;
1569
1570         args->addr_ptr = (uint64_t) addr;
1571
1572         return 0;
1573 }
1574
1575 /**
1576  * i915_gem_fault - fault a page into the GTT
1577  * vma: VMA in question
1578  * vmf: fault info
1579  *
1580  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1581  * from userspace.  The fault handler takes care of binding the object to
1582  * the GTT (if needed), allocating and programming a fence register (again,
1583  * only if needed based on whether the old reg is still valid or the object
1584  * is tiled) and inserting a new PTE into the faulting process.
1585  *
1586  * Note that the faulting process may involve evicting existing objects
1587  * from the GTT and/or fence registers to make room.  So performance may
1588  * suffer if the GTT working set is large or there are few fence registers
1589  * left.
1590  */
1591 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1592 {
1593         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1594         struct drm_device *dev = obj->base.dev;
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596         pgoff_t page_offset;
1597         unsigned long pfn;
1598         int ret = 0;
1599         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1600
1601         intel_runtime_pm_get(dev_priv);
1602
1603         /* We don't use vmf->pgoff since that has the fake offset */
1604         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1605                 PAGE_SHIFT;
1606
1607         ret = i915_mutex_lock_interruptible(dev);
1608         if (ret)
1609                 goto out;
1610
1611         trace_i915_gem_object_fault(obj, page_offset, true, write);
1612
1613         /* Try to flush the object off the GPU first without holding the lock.
1614          * Upon reacquiring the lock, we will perform our sanity checks and then
1615          * repeat the flush holding the lock in the normal manner to catch cases
1616          * where we are gazumped.
1617          */
1618         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1619         if (ret)
1620                 goto unlock;
1621
1622         /* Access to snoopable pages through the GTT is incoherent. */
1623         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1624                 ret = -EFAULT;
1625                 goto unlock;
1626         }
1627
1628         /* Now bind it into the GTT if needed */
1629         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1630         if (ret)
1631                 goto unlock;
1632
1633         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1634         if (ret)
1635                 goto unpin;
1636
1637         ret = i915_gem_object_get_fence(obj);
1638         if (ret)
1639                 goto unpin;
1640
1641         /* Finally, remap it using the new GTT offset */
1642         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1643         pfn >>= PAGE_SHIFT;
1644
1645         if (!obj->fault_mappable) {
1646                 unsigned long size = min_t(unsigned long,
1647                                            vma->vm_end - vma->vm_start,
1648                                            obj->base.size);
1649                 int i;
1650
1651                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1652                         ret = vm_insert_pfn(vma,
1653                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1654                                             pfn + i);
1655                         if (ret)
1656                                 break;
1657                 }
1658
1659                 obj->fault_mappable = true;
1660         } else
1661                 ret = vm_insert_pfn(vma,
1662                                     (unsigned long)vmf->virtual_address,
1663                                     pfn + page_offset);
1664 unpin:
1665         i915_gem_object_ggtt_unpin(obj);
1666 unlock:
1667         mutex_unlock(&dev->struct_mutex);
1668 out:
1669         switch (ret) {
1670         case -EIO:
1671                 /*
1672                  * We eat errors when the gpu is terminally wedged to avoid
1673                  * userspace unduly crashing (gl has no provisions for mmaps to
1674                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1675                  * and so needs to be reported.
1676                  */
1677                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1678                         ret = VM_FAULT_SIGBUS;
1679                         break;
1680                 }
1681         case -EAGAIN:
1682                 /*
1683                  * EAGAIN means the gpu is hung and we'll wait for the error
1684                  * handler to reset everything when re-faulting in
1685                  * i915_mutex_lock_interruptible.
1686                  */
1687         case 0:
1688         case -ERESTARTSYS:
1689         case -EINTR:
1690         case -EBUSY:
1691                 /*
1692                  * EBUSY is ok: this just means that another thread
1693                  * already did the job.
1694                  */
1695                 ret = VM_FAULT_NOPAGE;
1696                 break;
1697         case -ENOMEM:
1698                 ret = VM_FAULT_OOM;
1699                 break;
1700         case -ENOSPC:
1701         case -EFAULT:
1702                 ret = VM_FAULT_SIGBUS;
1703                 break;
1704         default:
1705                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1706                 ret = VM_FAULT_SIGBUS;
1707                 break;
1708         }
1709
1710         intel_runtime_pm_put(dev_priv);
1711         return ret;
1712 }
1713
1714 /**
1715  * i915_gem_release_mmap - remove physical page mappings
1716  * @obj: obj in question
1717  *
1718  * Preserve the reservation of the mmapping with the DRM core code, but
1719  * relinquish ownership of the pages back to the system.
1720  *
1721  * It is vital that we remove the page mapping if we have mapped a tiled
1722  * object through the GTT and then lose the fence register due to
1723  * resource pressure. Similarly if the object has been moved out of the
1724  * aperture, than pages mapped into userspace must be revoked. Removing the
1725  * mapping will then trigger a page fault on the next user access, allowing
1726  * fixup by i915_gem_fault().
1727  */
1728 void
1729 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1730 {
1731         if (!obj->fault_mappable)
1732                 return;
1733
1734         drm_vma_node_unmap(&obj->base.vma_node,
1735                            obj->base.dev->anon_inode->i_mapping);
1736         obj->fault_mappable = false;
1737 }
1738
1739 void
1740 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1741 {
1742         struct drm_i915_gem_object *obj;
1743
1744         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1745                 i915_gem_release_mmap(obj);
1746 }
1747
1748 uint32_t
1749 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1750 {
1751         uint32_t gtt_size;
1752
1753         if (INTEL_INFO(dev)->gen >= 4 ||
1754             tiling_mode == I915_TILING_NONE)
1755                 return size;
1756
1757         /* Previous chips need a power-of-two fence region when tiling */
1758         if (INTEL_INFO(dev)->gen == 3)
1759                 gtt_size = 1024*1024;
1760         else
1761                 gtt_size = 512*1024;
1762
1763         while (gtt_size < size)
1764                 gtt_size <<= 1;
1765
1766         return gtt_size;
1767 }
1768
1769 /**
1770  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1771  * @obj: object to check
1772  *
1773  * Return the required GTT alignment for an object, taking into account
1774  * potential fence register mapping.
1775  */
1776 uint32_t
1777 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1778                            int tiling_mode, bool fenced)
1779 {
1780         /*
1781          * Minimum alignment is 4k (GTT page size), but might be greater
1782          * if a fence register is needed for the object.
1783          */
1784         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1785             tiling_mode == I915_TILING_NONE)
1786                 return 4096;
1787
1788         /*
1789          * Previous chips need to be aligned to the size of the smallest
1790          * fence register that can contain the object.
1791          */
1792         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1793 }
1794
1795 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1796 {
1797         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1798         int ret;
1799
1800         if (drm_vma_node_has_offset(&obj->base.vma_node))
1801                 return 0;
1802
1803         dev_priv->mm.shrinker_no_lock_stealing = true;
1804
1805         ret = drm_gem_create_mmap_offset(&obj->base);
1806         if (ret != -ENOSPC)
1807                 goto out;
1808
1809         /* Badly fragmented mmap space? The only way we can recover
1810          * space is by destroying unwanted objects. We can't randomly release
1811          * mmap_offsets as userspace expects them to be persistent for the
1812          * lifetime of the objects. The closest we can is to release the
1813          * offsets on purgeable objects by truncating it and marking it purged,
1814          * which prevents userspace from ever using that object again.
1815          */
1816         i915_gem_shrink(dev_priv,
1817                         obj->base.size >> PAGE_SHIFT,
1818                         I915_SHRINK_BOUND |
1819                         I915_SHRINK_UNBOUND |
1820                         I915_SHRINK_PURGEABLE);
1821         ret = drm_gem_create_mmap_offset(&obj->base);
1822         if (ret != -ENOSPC)
1823                 goto out;
1824
1825         i915_gem_shrink_all(dev_priv);
1826         ret = drm_gem_create_mmap_offset(&obj->base);
1827 out:
1828         dev_priv->mm.shrinker_no_lock_stealing = false;
1829
1830         return ret;
1831 }
1832
1833 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1834 {
1835         drm_gem_free_mmap_offset(&obj->base);
1836 }
1837
1838 static int
1839 i915_gem_mmap_gtt(struct drm_file *file,
1840                   struct drm_device *dev,
1841                   uint32_t handle, bool dumb,
1842                   uint64_t *offset)
1843 {
1844         struct drm_i915_private *dev_priv = dev->dev_private;
1845         struct drm_i915_gem_object *obj;
1846         int ret;
1847
1848         ret = i915_mutex_lock_interruptible(dev);
1849         if (ret)
1850                 return ret;
1851
1852         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1853         if (&obj->base == NULL) {
1854                 ret = -ENOENT;
1855                 goto unlock;
1856         }
1857
1858         /*
1859          * We don't allow dumb mmaps on objects created using another
1860          * interface.
1861          */
1862         WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
1863                   "Illegal dumb map of accelerated buffer.\n");
1864
1865         if (obj->base.size > dev_priv->gtt.mappable_end) {
1866                 ret = -E2BIG;
1867                 goto out;
1868         }
1869
1870         if (obj->madv != I915_MADV_WILLNEED) {
1871                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1872                 ret = -EFAULT;
1873                 goto out;
1874         }
1875
1876         ret = i915_gem_object_create_mmap_offset(obj);
1877         if (ret)
1878                 goto out;
1879
1880         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1881
1882 out:
1883         drm_gem_object_unreference(&obj->base);
1884 unlock:
1885         mutex_unlock(&dev->struct_mutex);
1886         return ret;
1887 }
1888
1889 int
1890 i915_gem_dumb_map_offset(struct drm_file *file,
1891                          struct drm_device *dev,
1892                          uint32_t handle,
1893                          uint64_t *offset)
1894 {
1895         return i915_gem_mmap_gtt(file, dev, handle, true, offset);
1896 }
1897
1898 /**
1899  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1900  * @dev: DRM device
1901  * @data: GTT mapping ioctl data
1902  * @file: GEM object info
1903  *
1904  * Simply returns the fake offset to userspace so it can mmap it.
1905  * The mmap call will end up in drm_gem_mmap(), which will set things
1906  * up so we can get faults in the handler above.
1907  *
1908  * The fault handler will take care of binding the object into the GTT
1909  * (since it may have been evicted to make room for something), allocating
1910  * a fence register, and mapping the appropriate aperture address into
1911  * userspace.
1912  */
1913 int
1914 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1915                         struct drm_file *file)
1916 {
1917         struct drm_i915_gem_mmap_gtt *args = data;
1918
1919         return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
1920 }
1921
1922 static inline int
1923 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1924 {
1925         return obj->madv == I915_MADV_DONTNEED;
1926 }
1927
1928 /* Immediately discard the backing storage */
1929 static void
1930 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1931 {
1932         i915_gem_object_free_mmap_offset(obj);
1933
1934         if (obj->base.filp == NULL)
1935                 return;
1936
1937         /* Our goal here is to return as much of the memory as
1938          * is possible back to the system as we are called from OOM.
1939          * To do this we must instruct the shmfs to drop all of its
1940          * backing pages, *now*.
1941          */
1942         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1943         obj->madv = __I915_MADV_PURGED;
1944 }
1945
1946 /* Try to discard unwanted pages */
1947 static void
1948 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1949 {
1950         struct address_space *mapping;
1951
1952         switch (obj->madv) {
1953         case I915_MADV_DONTNEED:
1954                 i915_gem_object_truncate(obj);
1955         case __I915_MADV_PURGED:
1956                 return;
1957         }
1958
1959         if (obj->base.filp == NULL)
1960                 return;
1961
1962         mapping = file_inode(obj->base.filp)->i_mapping,
1963         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1964 }
1965
1966 static void
1967 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1968 {
1969         struct sg_page_iter sg_iter;
1970         int ret;
1971
1972         BUG_ON(obj->madv == __I915_MADV_PURGED);
1973
1974         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1975         if (ret) {
1976                 /* In the event of a disaster, abandon all caches and
1977                  * hope for the best.
1978                  */
1979                 WARN_ON(ret != -EIO);
1980                 i915_gem_clflush_object(obj, true);
1981                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1982         }
1983
1984         if (i915_gem_object_needs_bit17_swizzle(obj))
1985                 i915_gem_object_save_bit_17_swizzle(obj);
1986
1987         if (obj->madv == I915_MADV_DONTNEED)
1988                 obj->dirty = 0;
1989
1990         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1991                 struct page *page = sg_page_iter_page(&sg_iter);
1992
1993                 if (obj->dirty)
1994                         set_page_dirty(page);
1995
1996                 if (obj->madv == I915_MADV_WILLNEED)
1997                         mark_page_accessed(page);
1998
1999                 page_cache_release(page);
2000         }
2001         obj->dirty = 0;
2002
2003         sg_free_table(obj->pages);
2004         kfree(obj->pages);
2005 }
2006
2007 int
2008 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2009 {
2010         const struct drm_i915_gem_object_ops *ops = obj->ops;
2011
2012         if (obj->pages == NULL)
2013                 return 0;
2014
2015         if (obj->pages_pin_count)
2016                 return -EBUSY;
2017
2018         BUG_ON(i915_gem_obj_bound_any(obj));
2019
2020         /* ->put_pages might need to allocate memory for the bit17 swizzle
2021          * array, hence protect them from being reaped by removing them from gtt
2022          * lists early. */
2023         list_del(&obj->global_list);
2024
2025         ops->put_pages(obj);
2026         obj->pages = NULL;
2027
2028         i915_gem_object_invalidate(obj);
2029
2030         return 0;
2031 }
2032
2033 unsigned long
2034 i915_gem_shrink(struct drm_i915_private *dev_priv,
2035                 long target, unsigned flags)
2036 {
2037         const struct {
2038                 struct list_head *list;
2039                 unsigned int bit;
2040         } phases[] = {
2041                 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2042                 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2043                 { NULL, 0 },
2044         }, *phase;
2045         unsigned long count = 0;
2046
2047         /*
2048          * As we may completely rewrite the (un)bound list whilst unbinding
2049          * (due to retiring requests) we have to strictly process only
2050          * one element of the list at the time, and recheck the list
2051          * on every iteration.
2052          *
2053          * In particular, we must hold a reference whilst removing the
2054          * object as we may end up waiting for and/or retiring the objects.
2055          * This might release the final reference (held by the active list)
2056          * and result in the object being freed from under us. This is
2057          * similar to the precautions the eviction code must take whilst
2058          * removing objects.
2059          *
2060          * Also note that although these lists do not hold a reference to
2061          * the object we can safely grab one here: The final object
2062          * unreferencing and the bound_list are both protected by the
2063          * dev->struct_mutex and so we won't ever be able to observe an
2064          * object on the bound_list with a reference count equals 0.
2065          */
2066         for (phase = phases; phase->list; phase++) {
2067                 struct list_head still_in_list;
2068
2069                 if ((flags & phase->bit) == 0)
2070                         continue;
2071
2072                 INIT_LIST_HEAD(&still_in_list);
2073                 while (count < target && !list_empty(phase->list)) {
2074                         struct drm_i915_gem_object *obj;
2075                         struct i915_vma *vma, *v;
2076
2077                         obj = list_first_entry(phase->list,
2078                                                typeof(*obj), global_list);
2079                         list_move_tail(&obj->global_list, &still_in_list);
2080
2081                         if (flags & I915_SHRINK_PURGEABLE &&
2082                             !i915_gem_object_is_purgeable(obj))
2083                                 continue;
2084
2085                         drm_gem_object_reference(&obj->base);
2086
2087                         /* For the unbound phase, this should be a no-op! */
2088                         list_for_each_entry_safe(vma, v,
2089                                                  &obj->vma_list, vma_link)
2090                                 if (i915_vma_unbind(vma))
2091                                         break;
2092
2093                         if (i915_gem_object_put_pages(obj) == 0)
2094                                 count += obj->base.size >> PAGE_SHIFT;
2095
2096                         drm_gem_object_unreference(&obj->base);
2097                 }
2098                 list_splice(&still_in_list, phase->list);
2099         }
2100
2101         return count;
2102 }
2103
2104 static unsigned long
2105 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2106 {
2107         i915_gem_evict_everything(dev_priv->dev);
2108         return i915_gem_shrink(dev_priv, LONG_MAX,
2109                                I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2110 }
2111
2112 static int
2113 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2114 {
2115         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2116         int page_count, i;
2117         struct address_space *mapping;
2118         struct sg_table *st;
2119         struct scatterlist *sg;
2120         struct sg_page_iter sg_iter;
2121         struct page *page;
2122         unsigned long last_pfn = 0;     /* suppress gcc warning */
2123         gfp_t gfp;
2124
2125         /* Assert that the object is not currently in any GPU domain. As it
2126          * wasn't in the GTT, there shouldn't be any way it could have been in
2127          * a GPU cache
2128          */
2129         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2130         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2131
2132         st = kmalloc(sizeof(*st), GFP_KERNEL);
2133         if (st == NULL)
2134                 return -ENOMEM;
2135
2136         page_count = obj->base.size / PAGE_SIZE;
2137         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2138                 kfree(st);
2139                 return -ENOMEM;
2140         }
2141
2142         /* Get the list of pages out of our struct file.  They'll be pinned
2143          * at this point until we release them.
2144          *
2145          * Fail silently without starting the shrinker
2146          */
2147         mapping = file_inode(obj->base.filp)->i_mapping;
2148         gfp = mapping_gfp_mask(mapping);
2149         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2150         gfp &= ~(__GFP_IO | __GFP_WAIT);
2151         sg = st->sgl;
2152         st->nents = 0;
2153         for (i = 0; i < page_count; i++) {
2154                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2155                 if (IS_ERR(page)) {
2156                         i915_gem_shrink(dev_priv,
2157                                         page_count,
2158                                         I915_SHRINK_BOUND |
2159                                         I915_SHRINK_UNBOUND |
2160                                         I915_SHRINK_PURGEABLE);
2161                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2162                 }
2163                 if (IS_ERR(page)) {
2164                         /* We've tried hard to allocate the memory by reaping
2165                          * our own buffer, now let the real VM do its job and
2166                          * go down in flames if truly OOM.
2167                          */
2168                         i915_gem_shrink_all(dev_priv);
2169                         page = shmem_read_mapping_page(mapping, i);
2170                         if (IS_ERR(page))
2171                                 goto err_pages;
2172                 }
2173 #ifdef CONFIG_SWIOTLB
2174                 if (swiotlb_nr_tbl()) {
2175                         st->nents++;
2176                         sg_set_page(sg, page, PAGE_SIZE, 0);
2177                         sg = sg_next(sg);
2178                         continue;
2179                 }
2180 #endif
2181                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2182                         if (i)
2183                                 sg = sg_next(sg);
2184                         st->nents++;
2185                         sg_set_page(sg, page, PAGE_SIZE, 0);
2186                 } else {
2187                         sg->length += PAGE_SIZE;
2188                 }
2189                 last_pfn = page_to_pfn(page);
2190
2191                 /* Check that the i965g/gm workaround works. */
2192                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2193         }
2194 #ifdef CONFIG_SWIOTLB
2195         if (!swiotlb_nr_tbl())
2196 #endif
2197                 sg_mark_end(sg);
2198         obj->pages = st;
2199
2200         if (i915_gem_object_needs_bit17_swizzle(obj))
2201                 i915_gem_object_do_bit_17_swizzle(obj);
2202
2203         if (obj->tiling_mode != I915_TILING_NONE &&
2204             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2205                 i915_gem_object_pin_pages(obj);
2206
2207         return 0;
2208
2209 err_pages:
2210         sg_mark_end(sg);
2211         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2212                 page_cache_release(sg_page_iter_page(&sg_iter));
2213         sg_free_table(st);
2214         kfree(st);
2215
2216         /* shmemfs first checks if there is enough memory to allocate the page
2217          * and reports ENOSPC should there be insufficient, along with the usual
2218          * ENOMEM for a genuine allocation failure.
2219          *
2220          * We use ENOSPC in our driver to mean that we have run out of aperture
2221          * space and so want to translate the error from shmemfs back to our
2222          * usual understanding of ENOMEM.
2223          */
2224         if (PTR_ERR(page) == -ENOSPC)
2225                 return -ENOMEM;
2226         else
2227                 return PTR_ERR(page);
2228 }
2229
2230 /* Ensure that the associated pages are gathered from the backing storage
2231  * and pinned into our object. i915_gem_object_get_pages() may be called
2232  * multiple times before they are released by a single call to
2233  * i915_gem_object_put_pages() - once the pages are no longer referenced
2234  * either as a result of memory pressure (reaping pages under the shrinker)
2235  * or as the object is itself released.
2236  */
2237 int
2238 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2239 {
2240         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241         const struct drm_i915_gem_object_ops *ops = obj->ops;
2242         int ret;
2243
2244         if (obj->pages)
2245                 return 0;
2246
2247         if (obj->madv != I915_MADV_WILLNEED) {
2248                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2249                 return -EFAULT;
2250         }
2251
2252         BUG_ON(obj->pages_pin_count);
2253
2254         ret = ops->get_pages(obj);
2255         if (ret)
2256                 return ret;
2257
2258         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2259         return 0;
2260 }
2261
2262 static void
2263 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2264                                struct intel_engine_cs *ring)
2265 {
2266         struct drm_i915_gem_request *req;
2267         struct intel_engine_cs *old_ring;
2268
2269         BUG_ON(ring == NULL);
2270
2271         req = intel_ring_get_request(ring);
2272         old_ring = i915_gem_request_get_ring(obj->last_read_req);
2273
2274         if (old_ring != ring && obj->last_write_req) {
2275                 /* Keep the request relative to the current ring */
2276                 i915_gem_request_assign(&obj->last_write_req, req);
2277         }
2278
2279         /* Add a reference if we're newly entering the active list. */
2280         if (!obj->active) {
2281                 drm_gem_object_reference(&obj->base);
2282                 obj->active = 1;
2283         }
2284
2285         list_move_tail(&obj->ring_list, &ring->active_list);
2286
2287         i915_gem_request_assign(&obj->last_read_req, req);
2288 }
2289
2290 void i915_vma_move_to_active(struct i915_vma *vma,
2291                              struct intel_engine_cs *ring)
2292 {
2293         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2294         return i915_gem_object_move_to_active(vma->obj, ring);
2295 }
2296
2297 static void
2298 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2299 {
2300         struct i915_vma *vma;
2301
2302         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2303         BUG_ON(!obj->active);
2304
2305         list_for_each_entry(vma, &obj->vma_list, vma_link) {
2306                 if (!list_empty(&vma->mm_list))
2307                         list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2308         }
2309
2310         intel_fb_obj_flush(obj, true);
2311
2312         list_del_init(&obj->ring_list);
2313
2314         i915_gem_request_assign(&obj->last_read_req, NULL);
2315         i915_gem_request_assign(&obj->last_write_req, NULL);
2316         obj->base.write_domain = 0;
2317
2318         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2319
2320         obj->active = 0;
2321         drm_gem_object_unreference(&obj->base);
2322
2323         WARN_ON(i915_verify_lists(dev));
2324 }
2325
2326 static void
2327 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2328 {
2329         if (obj->last_read_req == NULL)
2330                 return;
2331
2332         if (i915_gem_request_completed(obj->last_read_req, true))
2333                 i915_gem_object_move_to_inactive(obj);
2334 }
2335
2336 static int
2337 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2338 {
2339         struct drm_i915_private *dev_priv = dev->dev_private;
2340         struct intel_engine_cs *ring;
2341         int ret, i, j;
2342
2343         /* Carefully retire all requests without writing to the rings */
2344         for_each_ring(ring, dev_priv, i) {
2345                 ret = intel_ring_idle(ring);
2346                 if (ret)
2347                         return ret;
2348         }
2349         i915_gem_retire_requests(dev);
2350
2351         /* Finally reset hw state */
2352         for_each_ring(ring, dev_priv, i) {
2353                 intel_ring_init_seqno(ring, seqno);
2354
2355                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2356                         ring->semaphore.sync_seqno[j] = 0;
2357         }
2358
2359         return 0;
2360 }
2361
2362 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2363 {
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         int ret;
2366
2367         if (seqno == 0)
2368                 return -EINVAL;
2369
2370         /* HWS page needs to be set less than what we
2371          * will inject to ring
2372          */
2373         ret = i915_gem_init_seqno(dev, seqno - 1);
2374         if (ret)
2375                 return ret;
2376
2377         /* Carefully set the last_seqno value so that wrap
2378          * detection still works
2379          */
2380         dev_priv->next_seqno = seqno;
2381         dev_priv->last_seqno = seqno - 1;
2382         if (dev_priv->last_seqno == 0)
2383                 dev_priv->last_seqno--;
2384
2385         return 0;
2386 }
2387
2388 int
2389 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2390 {
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392
2393         /* reserve 0 for non-seqno */
2394         if (dev_priv->next_seqno == 0) {
2395                 int ret = i915_gem_init_seqno(dev, 0);
2396                 if (ret)
2397                         return ret;
2398
2399                 dev_priv->next_seqno = 1;
2400         }
2401
2402         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2403         return 0;
2404 }
2405
2406 int __i915_add_request(struct intel_engine_cs *ring,
2407                        struct drm_file *file,
2408                        struct drm_i915_gem_object *obj)
2409 {
2410         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2411         struct drm_i915_gem_request *request;
2412         struct intel_ringbuffer *ringbuf;
2413         u32 request_ring_position, request_start;
2414         int ret;
2415
2416         request = ring->outstanding_lazy_request;
2417         if (WARN_ON(request == NULL))
2418                 return -ENOMEM;
2419
2420         if (i915.enable_execlists) {
2421                 struct intel_context *ctx = request->ctx;
2422                 ringbuf = ctx->engine[ring->id].ringbuf;
2423         } else
2424                 ringbuf = ring->buffer;
2425
2426         request_start = intel_ring_get_tail(ringbuf);
2427         /*
2428          * Emit any outstanding flushes - execbuf can fail to emit the flush
2429          * after having emitted the batchbuffer command. Hence we need to fix
2430          * things up similar to emitting the lazy request. The difference here
2431          * is that the flush _must_ happen before the next request, no matter
2432          * what.
2433          */
2434         if (i915.enable_execlists) {
2435                 ret = logical_ring_flush_all_caches(ringbuf);
2436                 if (ret)
2437                         return ret;
2438         } else {
2439                 ret = intel_ring_flush_all_caches(ring);
2440                 if (ret)
2441                         return ret;
2442         }
2443
2444         /* Record the position of the start of the request so that
2445          * should we detect the updated seqno part-way through the
2446          * GPU processing the request, we never over-estimate the
2447          * position of the head.
2448          */
2449         request_ring_position = intel_ring_get_tail(ringbuf);
2450
2451         if (i915.enable_execlists) {
2452                 ret = ring->emit_request(ringbuf);
2453                 if (ret)
2454                         return ret;
2455         } else {
2456                 ret = ring->add_request(ring);
2457                 if (ret)
2458                         return ret;
2459         }
2460
2461         request->head = request_start;
2462         request->tail = request_ring_position;
2463
2464         /* Whilst this request exists, batch_obj will be on the
2465          * active_list, and so will hold the active reference. Only when this
2466          * request is retired will the the batch_obj be moved onto the
2467          * inactive_list and lose its active reference. Hence we do not need
2468          * to explicitly hold another reference here.
2469          */
2470         request->batch_obj = obj;
2471
2472         if (!i915.enable_execlists) {
2473                 /* Hold a reference to the current context so that we can inspect
2474                  * it later in case a hangcheck error event fires.
2475                  */
2476                 request->ctx = ring->last_context;
2477                 if (request->ctx)
2478                         i915_gem_context_reference(request->ctx);
2479         }
2480
2481         request->emitted_jiffies = jiffies;
2482         list_add_tail(&request->list, &ring->request_list);
2483         request->file_priv = NULL;
2484
2485         if (file) {
2486                 struct drm_i915_file_private *file_priv = file->driver_priv;
2487
2488                 spin_lock(&file_priv->mm.lock);
2489                 request->file_priv = file_priv;
2490                 list_add_tail(&request->client_list,
2491                               &file_priv->mm.request_list);
2492                 spin_unlock(&file_priv->mm.lock);
2493         }
2494
2495         trace_i915_gem_request_add(request);
2496         ring->outstanding_lazy_request = NULL;
2497
2498         i915_queue_hangcheck(ring->dev);
2499
2500         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2501         queue_delayed_work(dev_priv->wq,
2502                            &dev_priv->mm.retire_work,
2503                            round_jiffies_up_relative(HZ));
2504         intel_mark_busy(dev_priv->dev);
2505
2506         return 0;
2507 }
2508
2509 static inline void
2510 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2511 {
2512         struct drm_i915_file_private *file_priv = request->file_priv;
2513
2514         if (!file_priv)
2515                 return;
2516
2517         spin_lock(&file_priv->mm.lock);
2518         list_del(&request->client_list);
2519         request->file_priv = NULL;
2520         spin_unlock(&file_priv->mm.lock);
2521 }
2522
2523 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2524                                    const struct intel_context *ctx)
2525 {
2526         unsigned long elapsed;
2527
2528         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2529
2530         if (ctx->hang_stats.banned)
2531                 return true;
2532
2533         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2534                 if (!i915_gem_context_is_default(ctx)) {
2535                         DRM_DEBUG("context hanging too fast, banning!\n");
2536                         return true;
2537                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2538                         if (i915_stop_ring_allow_warn(dev_priv))
2539                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2540                         return true;
2541                 }
2542         }
2543
2544         return false;
2545 }
2546
2547 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2548                                   struct intel_context *ctx,
2549                                   const bool guilty)
2550 {
2551         struct i915_ctx_hang_stats *hs;
2552
2553         if (WARN_ON(!ctx))
2554                 return;
2555
2556         hs = &ctx->hang_stats;
2557
2558         if (guilty) {
2559                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2560                 hs->batch_active++;
2561                 hs->guilty_ts = get_seconds();
2562         } else {
2563                 hs->batch_pending++;
2564         }
2565 }
2566
2567 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2568 {
2569         list_del(&request->list);
2570         i915_gem_request_remove_from_client(request);
2571
2572         i915_gem_request_unreference(request);
2573 }
2574
2575 void i915_gem_request_free(struct kref *req_ref)
2576 {
2577         struct drm_i915_gem_request *req = container_of(req_ref,
2578                                                  typeof(*req), ref);
2579         struct intel_context *ctx = req->ctx;
2580
2581         if (ctx) {
2582                 if (i915.enable_execlists) {
2583                         struct intel_engine_cs *ring = req->ring;
2584
2585                         if (ctx != ring->default_context)
2586                                 intel_lr_context_unpin(ring, ctx);
2587                 }
2588
2589                 i915_gem_context_unreference(ctx);
2590         }
2591
2592         kfree(req);
2593 }
2594
2595 struct drm_i915_gem_request *
2596 i915_gem_find_active_request(struct intel_engine_cs *ring)
2597 {
2598         struct drm_i915_gem_request *request;
2599
2600         list_for_each_entry(request, &ring->request_list, list) {
2601                 if (i915_gem_request_completed(request, false))
2602                         continue;
2603
2604                 return request;
2605         }
2606
2607         return NULL;
2608 }
2609
2610 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2611                                        struct intel_engine_cs *ring)
2612 {
2613         struct drm_i915_gem_request *request;
2614         bool ring_hung;
2615
2616         request = i915_gem_find_active_request(ring);
2617
2618         if (request == NULL)
2619                 return;
2620
2621         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2622
2623         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2624
2625         list_for_each_entry_continue(request, &ring->request_list, list)
2626                 i915_set_reset_status(dev_priv, request->ctx, false);
2627 }
2628
2629 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2630                                         struct intel_engine_cs *ring)
2631 {
2632         while (!list_empty(&ring->active_list)) {
2633                 struct drm_i915_gem_object *obj;
2634
2635                 obj = list_first_entry(&ring->active_list,
2636                                        struct drm_i915_gem_object,
2637                                        ring_list);
2638
2639                 i915_gem_object_move_to_inactive(obj);
2640         }
2641
2642         /*
2643          * Clear the execlists queue up before freeing the requests, as those
2644          * are the ones that keep the context and ringbuffer backing objects
2645          * pinned in place.
2646          */
2647         while (!list_empty(&ring->execlist_queue)) {
2648                 struct intel_ctx_submit_request *submit_req;
2649
2650                 submit_req = list_first_entry(&ring->execlist_queue,
2651                                 struct intel_ctx_submit_request,
2652                                 execlist_link);
2653                 list_del(&submit_req->execlist_link);
2654                 intel_runtime_pm_put(dev_priv);
2655                 i915_gem_context_unreference(submit_req->ctx);
2656                 kfree(submit_req);
2657         }
2658
2659         /*
2660          * We must free the requests after all the corresponding objects have
2661          * been moved off active lists. Which is the same order as the normal
2662          * retire_requests function does. This is important if object hold
2663          * implicit references on things like e.g. ppgtt address spaces through
2664          * the request.
2665          */
2666         while (!list_empty(&ring->request_list)) {
2667                 struct drm_i915_gem_request *request;
2668
2669                 request = list_first_entry(&ring->request_list,
2670                                            struct drm_i915_gem_request,
2671                                            list);
2672
2673                 i915_gem_free_request(request);
2674         }
2675
2676         /* This may not have been flushed before the reset, so clean it now */
2677         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2678 }
2679
2680 void i915_gem_restore_fences(struct drm_device *dev)
2681 {
2682         struct drm_i915_private *dev_priv = dev->dev_private;
2683         int i;
2684
2685         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2686                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2687
2688                 /*
2689                  * Commit delayed tiling changes if we have an object still
2690                  * attached to the fence, otherwise just clear the fence.
2691                  */
2692                 if (reg->obj) {
2693                         i915_gem_object_update_fence(reg->obj, reg,
2694                                                      reg->obj->tiling_mode);
2695                 } else {
2696                         i915_gem_write_fence(dev, i, NULL);
2697                 }
2698         }
2699 }
2700
2701 void i915_gem_reset(struct drm_device *dev)
2702 {
2703         struct drm_i915_private *dev_priv = dev->dev_private;
2704         struct intel_engine_cs *ring;
2705         int i;
2706
2707         /*
2708          * Before we free the objects from the requests, we need to inspect
2709          * them for finding the guilty party. As the requests only borrow
2710          * their reference to the objects, the inspection must be done first.
2711          */
2712         for_each_ring(ring, dev_priv, i)
2713                 i915_gem_reset_ring_status(dev_priv, ring);
2714
2715         for_each_ring(ring, dev_priv, i)
2716                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2717
2718         i915_gem_context_reset(dev);
2719
2720         i915_gem_restore_fences(dev);
2721 }
2722
2723 /**
2724  * This function clears the request list as sequence numbers are passed.
2725  */
2726 void
2727 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2728 {
2729         if (list_empty(&ring->request_list))
2730                 return;
2731
2732         WARN_ON(i915_verify_lists(ring->dev));
2733
2734         /* Move any buffers on the active list that are no longer referenced
2735          * by the ringbuffer to the flushing/inactive lists as appropriate,
2736          * before we free the context associated with the requests.
2737          */
2738         while (!list_empty(&ring->active_list)) {
2739                 struct drm_i915_gem_object *obj;
2740
2741                 obj = list_first_entry(&ring->active_list,
2742                                       struct drm_i915_gem_object,
2743                                       ring_list);
2744
2745                 if (!i915_gem_request_completed(obj->last_read_req, true))
2746                         break;
2747
2748                 i915_gem_object_move_to_inactive(obj);
2749         }
2750
2751
2752         while (!list_empty(&ring->request_list)) {
2753                 struct drm_i915_gem_request *request;
2754                 struct intel_ringbuffer *ringbuf;
2755
2756                 request = list_first_entry(&ring->request_list,
2757                                            struct drm_i915_gem_request,
2758                                            list);
2759
2760                 if (!i915_gem_request_completed(request, true))
2761                         break;
2762
2763                 trace_i915_gem_request_retire(request);
2764
2765                 /* This is one of the few common intersection points
2766                  * between legacy ringbuffer submission and execlists:
2767                  * we need to tell them apart in order to find the correct
2768                  * ringbuffer to which the request belongs to.
2769                  */
2770                 if (i915.enable_execlists) {
2771                         struct intel_context *ctx = request->ctx;
2772                         ringbuf = ctx->engine[ring->id].ringbuf;
2773                 } else
2774                         ringbuf = ring->buffer;
2775
2776                 /* We know the GPU must have read the request to have
2777                  * sent us the seqno + interrupt, so use the position
2778                  * of tail of the request to update the last known position
2779                  * of the GPU head.
2780                  */
2781                 ringbuf->last_retired_head = request->tail;
2782
2783                 i915_gem_free_request(request);
2784         }
2785
2786         if (unlikely(ring->trace_irq_req &&
2787                      i915_gem_request_completed(ring->trace_irq_req, true))) {
2788                 ring->irq_put(ring);
2789                 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2790         }
2791
2792         WARN_ON(i915_verify_lists(ring->dev));
2793 }
2794
2795 bool
2796 i915_gem_retire_requests(struct drm_device *dev)
2797 {
2798         struct drm_i915_private *dev_priv = dev->dev_private;
2799         struct intel_engine_cs *ring;
2800         bool idle = true;
2801         int i;
2802
2803         for_each_ring(ring, dev_priv, i) {
2804                 i915_gem_retire_requests_ring(ring);
2805                 idle &= list_empty(&ring->request_list);
2806                 if (i915.enable_execlists) {
2807                         unsigned long flags;
2808
2809                         spin_lock_irqsave(&ring->execlist_lock, flags);
2810                         idle &= list_empty(&ring->execlist_queue);
2811                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2812
2813                         intel_execlists_retire_requests(ring);
2814                 }
2815         }
2816
2817         if (idle)
2818                 mod_delayed_work(dev_priv->wq,
2819                                    &dev_priv->mm.idle_work,
2820                                    msecs_to_jiffies(100));
2821
2822         return idle;
2823 }
2824
2825 static void
2826 i915_gem_retire_work_handler(struct work_struct *work)
2827 {
2828         struct drm_i915_private *dev_priv =
2829                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2830         struct drm_device *dev = dev_priv->dev;
2831         bool idle;
2832
2833         /* Come back later if the device is busy... */
2834         idle = false;
2835         if (mutex_trylock(&dev->struct_mutex)) {
2836                 idle = i915_gem_retire_requests(dev);
2837                 mutex_unlock(&dev->struct_mutex);
2838         }
2839         if (!idle)
2840                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2841                                    round_jiffies_up_relative(HZ));
2842 }
2843
2844 static void
2845 i915_gem_idle_work_handler(struct work_struct *work)
2846 {
2847         struct drm_i915_private *dev_priv =
2848                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2849
2850         intel_mark_idle(dev_priv->dev);
2851 }
2852
2853 /**
2854  * Ensures that an object will eventually get non-busy by flushing any required
2855  * write domains, emitting any outstanding lazy request and retiring and
2856  * completed requests.
2857  */
2858 static int
2859 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2860 {
2861         struct intel_engine_cs *ring;
2862         int ret;
2863
2864         if (obj->active) {
2865                 ring = i915_gem_request_get_ring(obj->last_read_req);
2866
2867                 ret = i915_gem_check_olr(obj->last_read_req);
2868                 if (ret)
2869                         return ret;
2870
2871                 i915_gem_retire_requests_ring(ring);
2872         }
2873
2874         return 0;
2875 }
2876
2877 /**
2878  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2879  * @DRM_IOCTL_ARGS: standard ioctl arguments
2880  *
2881  * Returns 0 if successful, else an error is returned with the remaining time in
2882  * the timeout parameter.
2883  *  -ETIME: object is still busy after timeout
2884  *  -ERESTARTSYS: signal interrupted the wait
2885  *  -ENONENT: object doesn't exist
2886  * Also possible, but rare:
2887  *  -EAGAIN: GPU wedged
2888  *  -ENOMEM: damn
2889  *  -ENODEV: Internal IRQ fail
2890  *  -E?: The add request failed
2891  *
2892  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2893  * non-zero timeout parameter the wait ioctl will wait for the given number of
2894  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2895  * without holding struct_mutex the object may become re-busied before this
2896  * function completes. A similar but shorter * race condition exists in the busy
2897  * ioctl
2898  */
2899 int
2900 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2901 {
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903         struct drm_i915_gem_wait *args = data;
2904         struct drm_i915_gem_object *obj;
2905         struct drm_i915_gem_request *req;
2906         unsigned reset_counter;
2907         int ret = 0;
2908
2909         if (args->flags != 0)
2910                 return -EINVAL;
2911
2912         ret = i915_mutex_lock_interruptible(dev);
2913         if (ret)
2914                 return ret;
2915
2916         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2917         if (&obj->base == NULL) {
2918                 mutex_unlock(&dev->struct_mutex);
2919                 return -ENOENT;
2920         }
2921
2922         /* Need to make sure the object gets inactive eventually. */
2923         ret = i915_gem_object_flush_active(obj);
2924         if (ret)
2925                 goto out;
2926
2927         if (!obj->active || !obj->last_read_req)
2928                 goto out;
2929
2930         req = obj->last_read_req;
2931
2932         /* Do this after OLR check to make sure we make forward progress polling
2933          * on this IOCTL with a timeout <=0 (like busy ioctl)
2934          */
2935         if (args->timeout_ns <= 0) {
2936                 ret = -ETIME;
2937                 goto out;
2938         }
2939
2940         drm_gem_object_unreference(&obj->base);
2941         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2942         i915_gem_request_reference(req);
2943         mutex_unlock(&dev->struct_mutex);
2944
2945         ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2946                                   file->driver_priv);
2947         mutex_lock(&dev->struct_mutex);
2948         i915_gem_request_unreference(req);
2949         mutex_unlock(&dev->struct_mutex);
2950         return ret;
2951
2952 out:
2953         drm_gem_object_unreference(&obj->base);
2954         mutex_unlock(&dev->struct_mutex);
2955         return ret;
2956 }
2957
2958 /**
2959  * i915_gem_object_sync - sync an object to a ring.
2960  *
2961  * @obj: object which may be in use on another ring.
2962  * @to: ring we wish to use the object on. May be NULL.
2963  *
2964  * This code is meant to abstract object synchronization with the GPU.
2965  * Calling with NULL implies synchronizing the object with the CPU
2966  * rather than a particular GPU ring.
2967  *
2968  * Returns 0 if successful, else propagates up the lower layer error.
2969  */
2970 int
2971 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2972                      struct intel_engine_cs *to)
2973 {
2974         struct intel_engine_cs *from;
2975         u32 seqno;
2976         int ret, idx;
2977
2978         from = i915_gem_request_get_ring(obj->last_read_req);
2979
2980         if (from == NULL || to == from)
2981                 return 0;
2982
2983         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2984                 return i915_gem_object_wait_rendering(obj, false);
2985
2986         idx = intel_ring_sync_index(from, to);
2987
2988         seqno = i915_gem_request_get_seqno(obj->last_read_req);
2989         /* Optimization: Avoid semaphore sync when we are sure we already
2990          * waited for an object with higher seqno */
2991         if (seqno <= from->semaphore.sync_seqno[idx])
2992                 return 0;
2993
2994         ret = i915_gem_check_olr(obj->last_read_req);
2995         if (ret)
2996                 return ret;
2997
2998         trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
2999         ret = to->semaphore.sync_to(to, from, seqno);
3000         if (!ret)
3001                 /* We use last_read_req because sync_to()
3002                  * might have just caused seqno wrap under
3003                  * the radar.
3004                  */
3005                 from->semaphore.sync_seqno[idx] =
3006                                 i915_gem_request_get_seqno(obj->last_read_req);
3007
3008         return ret;
3009 }
3010
3011 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3012 {
3013         u32 old_write_domain, old_read_domains;
3014
3015         /* Force a pagefault for domain tracking on next user access */
3016         i915_gem_release_mmap(obj);
3017
3018         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3019                 return;
3020
3021         /* Wait for any direct GTT access to complete */
3022         mb();
3023
3024         old_read_domains = obj->base.read_domains;
3025         old_write_domain = obj->base.write_domain;
3026
3027         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3028         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3029
3030         trace_i915_gem_object_change_domain(obj,
3031                                             old_read_domains,
3032                                             old_write_domain);
3033 }
3034
3035 int i915_vma_unbind(struct i915_vma *vma)
3036 {
3037         struct drm_i915_gem_object *obj = vma->obj;
3038         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3039         int ret;
3040
3041         if (list_empty(&vma->vma_link))
3042                 return 0;
3043
3044         if (!drm_mm_node_allocated(&vma->node)) {
3045                 i915_gem_vma_destroy(vma);
3046                 return 0;
3047         }
3048
3049         if (vma->pin_count)
3050                 return -EBUSY;
3051
3052         BUG_ON(obj->pages == NULL);
3053
3054         ret = i915_gem_object_finish_gpu(obj);
3055         if (ret)
3056                 return ret;
3057         /* Continue on if we fail due to EIO, the GPU is hung so we
3058          * should be safe and we need to cleanup or else we might
3059          * cause memory corruption through use-after-free.
3060          */
3061
3062         if (i915_is_ggtt(vma->vm) &&
3063             vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3064                 i915_gem_object_finish_gtt(obj);
3065
3066                 /* release the fence reg _after_ flushing */
3067                 ret = i915_gem_object_put_fence(obj);
3068                 if (ret)
3069                         return ret;
3070         }
3071
3072         trace_i915_vma_unbind(vma);
3073
3074         vma->unbind_vma(vma);
3075
3076         list_del_init(&vma->mm_list);
3077         if (i915_is_ggtt(vma->vm)) {
3078                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3079                         obj->map_and_fenceable = false;
3080                 } else if (vma->ggtt_view.pages) {
3081                         sg_free_table(vma->ggtt_view.pages);
3082                         kfree(vma->ggtt_view.pages);
3083                         vma->ggtt_view.pages = NULL;
3084                 }
3085         }
3086
3087         drm_mm_remove_node(&vma->node);
3088         i915_gem_vma_destroy(vma);
3089
3090         /* Since the unbound list is global, only move to that list if
3091          * no more VMAs exist. */
3092         if (list_empty(&obj->vma_list)) {
3093                 /* Throw away the active reference before
3094                  * moving to the unbound list. */
3095                 i915_gem_object_retire(obj);
3096
3097                 i915_gem_gtt_finish_object(obj);
3098                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3099         }
3100
3101         /* And finally now the object is completely decoupled from this vma,
3102          * we can drop its hold on the backing storage and allow it to be
3103          * reaped by the shrinker.
3104          */
3105         i915_gem_object_unpin_pages(obj);
3106
3107         return 0;
3108 }
3109
3110 int i915_gpu_idle(struct drm_device *dev)
3111 {
3112         struct drm_i915_private *dev_priv = dev->dev_private;
3113         struct intel_engine_cs *ring;
3114         int ret, i;
3115
3116         /* Flush everything onto the inactive list. */
3117         for_each_ring(ring, dev_priv, i) {
3118                 if (!i915.enable_execlists) {
3119                         ret = i915_switch_context(ring, ring->default_context);
3120                         if (ret)
3121                                 return ret;
3122                 }
3123
3124                 ret = intel_ring_idle(ring);
3125                 if (ret)
3126                         return ret;
3127         }
3128
3129         return 0;
3130 }
3131
3132 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3133                                  struct drm_i915_gem_object *obj)
3134 {
3135         struct drm_i915_private *dev_priv = dev->dev_private;
3136         int fence_reg;
3137         int fence_pitch_shift;
3138
3139         if (INTEL_INFO(dev)->gen >= 6) {
3140                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3141                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3142         } else {
3143                 fence_reg = FENCE_REG_965_0;
3144                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3145         }
3146
3147         fence_reg += reg * 8;
3148
3149         /* To w/a incoherency with non-atomic 64-bit register updates,
3150          * we split the 64-bit update into two 32-bit writes. In order
3151          * for a partial fence not to be evaluated between writes, we
3152          * precede the update with write to turn off the fence register,
3153          * and only enable the fence as the last step.
3154          *
3155          * For extra levels of paranoia, we make sure each step lands
3156          * before applying the next step.
3157          */
3158         I915_WRITE(fence_reg, 0);
3159         POSTING_READ(fence_reg);
3160
3161         if (obj) {
3162                 u32 size = i915_gem_obj_ggtt_size(obj);
3163                 uint64_t val;
3164
3165                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3166                                  0xfffff000) << 32;
3167                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3168                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3169                 if (obj->tiling_mode == I915_TILING_Y)
3170                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3171                 val |= I965_FENCE_REG_VALID;
3172
3173                 I915_WRITE(fence_reg + 4, val >> 32);
3174                 POSTING_READ(fence_reg + 4);
3175
3176                 I915_WRITE(fence_reg + 0, val);
3177                 POSTING_READ(fence_reg);
3178         } else {
3179                 I915_WRITE(fence_reg + 4, 0);
3180                 POSTING_READ(fence_reg + 4);
3181         }
3182 }
3183
3184 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3185                                  struct drm_i915_gem_object *obj)
3186 {
3187         struct drm_i915_private *dev_priv = dev->dev_private;
3188         u32 val;
3189
3190         if (obj) {
3191                 u32 size = i915_gem_obj_ggtt_size(obj);
3192                 int pitch_val;
3193                 int tile_width;
3194
3195                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3196                      (size & -size) != size ||
3197                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3198                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3199                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3200
3201                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3202                         tile_width = 128;
3203                 else
3204                         tile_width = 512;
3205
3206                 /* Note: pitch better be a power of two tile widths */
3207                 pitch_val = obj->stride / tile_width;
3208                 pitch_val = ffs(pitch_val) - 1;
3209
3210                 val = i915_gem_obj_ggtt_offset(obj);
3211                 if (obj->tiling_mode == I915_TILING_Y)
3212                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3213                 val |= I915_FENCE_SIZE_BITS(size);
3214                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3215                 val |= I830_FENCE_REG_VALID;
3216         } else
3217                 val = 0;
3218
3219         if (reg < 8)
3220                 reg = FENCE_REG_830_0 + reg * 4;
3221         else
3222                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3223
3224         I915_WRITE(reg, val);
3225         POSTING_READ(reg);
3226 }
3227
3228 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3229                                 struct drm_i915_gem_object *obj)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         uint32_t val;
3233
3234         if (obj) {
3235                 u32 size = i915_gem_obj_ggtt_size(obj);
3236                 uint32_t pitch_val;
3237
3238                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3239                      (size & -size) != size ||
3240                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3241                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3242                      i915_gem_obj_ggtt_offset(obj), size);
3243
3244                 pitch_val = obj->stride / 128;
3245                 pitch_val = ffs(pitch_val) - 1;
3246
3247                 val = i915_gem_obj_ggtt_offset(obj);
3248                 if (obj->tiling_mode == I915_TILING_Y)
3249                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3250                 val |= I830_FENCE_SIZE_BITS(size);
3251                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3252                 val |= I830_FENCE_REG_VALID;
3253         } else
3254                 val = 0;
3255
3256         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3257         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3258 }
3259
3260 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3261 {
3262         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3263 }
3264
3265 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3266                                  struct drm_i915_gem_object *obj)
3267 {
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269
3270         /* Ensure that all CPU reads are completed before installing a fence
3271          * and all writes before removing the fence.
3272          */
3273         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3274                 mb();
3275
3276         WARN(obj && (!obj->stride || !obj->tiling_mode),
3277              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3278              obj->stride, obj->tiling_mode);
3279
3280         if (IS_GEN2(dev))
3281                 i830_write_fence_reg(dev, reg, obj);
3282         else if (IS_GEN3(dev))
3283                 i915_write_fence_reg(dev, reg, obj);
3284         else if (INTEL_INFO(dev)->gen >= 4)
3285                 i965_write_fence_reg(dev, reg, obj);
3286
3287         /* And similarly be paranoid that no direct access to this region
3288          * is reordered to before the fence is installed.
3289          */
3290         if (i915_gem_object_needs_mb(obj))
3291                 mb();
3292 }
3293
3294 static inline int fence_number(struct drm_i915_private *dev_priv,
3295                                struct drm_i915_fence_reg *fence)
3296 {
3297         return fence - dev_priv->fence_regs;
3298 }
3299
3300 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3301                                          struct drm_i915_fence_reg *fence,
3302                                          bool enable)
3303 {
3304         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3305         int reg = fence_number(dev_priv, fence);
3306
3307         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3308
3309         if (enable) {
3310                 obj->fence_reg = reg;
3311                 fence->obj = obj;
3312                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3313         } else {
3314                 obj->fence_reg = I915_FENCE_REG_NONE;
3315                 fence->obj = NULL;
3316                 list_del_init(&fence->lru_list);
3317         }
3318         obj->fence_dirty = false;
3319 }
3320
3321 static int
3322 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3323 {
3324         if (obj->last_fenced_req) {
3325                 int ret = i915_wait_request(obj->last_fenced_req);
3326                 if (ret)
3327                         return ret;
3328
3329                 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3330         }
3331
3332         return 0;
3333 }
3334
3335 int
3336 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3337 {
3338         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3339         struct drm_i915_fence_reg *fence;
3340         int ret;
3341
3342         ret = i915_gem_object_wait_fence(obj);
3343         if (ret)
3344                 return ret;
3345
3346         if (obj->fence_reg == I915_FENCE_REG_NONE)
3347                 return 0;
3348
3349         fence = &dev_priv->fence_regs[obj->fence_reg];
3350
3351         if (WARN_ON(fence->pin_count))
3352                 return -EBUSY;
3353
3354         i915_gem_object_fence_lost(obj);
3355         i915_gem_object_update_fence(obj, fence, false);
3356
3357         return 0;
3358 }
3359
3360 static struct drm_i915_fence_reg *
3361 i915_find_fence_reg(struct drm_device *dev)
3362 {
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct drm_i915_fence_reg *reg, *avail;
3365         int i;
3366
3367         /* First try to find a free reg */
3368         avail = NULL;
3369         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3370                 reg = &dev_priv->fence_regs[i];
3371                 if (!reg->obj)
3372                         return reg;
3373
3374                 if (!reg->pin_count)
3375                         avail = reg;
3376         }
3377
3378         if (avail == NULL)
3379                 goto deadlock;
3380
3381         /* None available, try to steal one or wait for a user to finish */
3382         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3383                 if (reg->pin_count)
3384                         continue;
3385
3386                 return reg;
3387         }
3388
3389 deadlock:
3390         /* Wait for completion of pending flips which consume fences */
3391         if (intel_has_pending_fb_unpin(dev))
3392                 return ERR_PTR(-EAGAIN);
3393
3394         return ERR_PTR(-EDEADLK);
3395 }
3396
3397 /**
3398  * i915_gem_object_get_fence - set up fencing for an object
3399  * @obj: object to map through a fence reg
3400  *
3401  * When mapping objects through the GTT, userspace wants to be able to write
3402  * to them without having to worry about swizzling if the object is tiled.
3403  * This function walks the fence regs looking for a free one for @obj,
3404  * stealing one if it can't find any.
3405  *
3406  * It then sets up the reg based on the object's properties: address, pitch
3407  * and tiling format.
3408  *
3409  * For an untiled surface, this removes any existing fence.
3410  */
3411 int
3412 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3413 {
3414         struct drm_device *dev = obj->base.dev;
3415         struct drm_i915_private *dev_priv = dev->dev_private;
3416         bool enable = obj->tiling_mode != I915_TILING_NONE;
3417         struct drm_i915_fence_reg *reg;
3418         int ret;
3419
3420         /* Have we updated the tiling parameters upon the object and so
3421          * will need to serialise the write to the associated fence register?
3422          */
3423         if (obj->fence_dirty) {
3424                 ret = i915_gem_object_wait_fence(obj);
3425                 if (ret)
3426                         return ret;
3427         }
3428
3429         /* Just update our place in the LRU if our fence is getting reused. */
3430         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3431                 reg = &dev_priv->fence_regs[obj->fence_reg];
3432                 if (!obj->fence_dirty) {
3433                         list_move_tail(&reg->lru_list,
3434                                        &dev_priv->mm.fence_list);
3435                         return 0;
3436                 }
3437         } else if (enable) {
3438                 if (WARN_ON(!obj->map_and_fenceable))
3439                         return -EINVAL;
3440
3441                 reg = i915_find_fence_reg(dev);
3442                 if (IS_ERR(reg))
3443                         return PTR_ERR(reg);
3444
3445                 if (reg->obj) {
3446                         struct drm_i915_gem_object *old = reg->obj;
3447
3448                         ret = i915_gem_object_wait_fence(old);
3449                         if (ret)
3450                                 return ret;
3451
3452                         i915_gem_object_fence_lost(old);
3453                 }
3454         } else
3455                 return 0;
3456
3457         i915_gem_object_update_fence(obj, reg, enable);
3458
3459         return 0;
3460 }
3461
3462 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3463                                      unsigned long cache_level)
3464 {
3465         struct drm_mm_node *gtt_space = &vma->node;
3466         struct drm_mm_node *other;
3467
3468         /*
3469          * On some machines we have to be careful when putting differing types
3470          * of snoopable memory together to avoid the prefetcher crossing memory
3471          * domains and dying. During vm initialisation, we decide whether or not
3472          * these constraints apply and set the drm_mm.color_adjust
3473          * appropriately.
3474          */
3475         if (vma->vm->mm.color_adjust == NULL)
3476                 return true;
3477
3478         if (!drm_mm_node_allocated(gtt_space))
3479                 return true;
3480
3481         if (list_empty(&gtt_space->node_list))
3482                 return true;
3483
3484         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3485         if (other->allocated && !other->hole_follows && other->color != cache_level)
3486                 return false;
3487
3488         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3489         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3490                 return false;
3491
3492         return true;
3493 }
3494
3495 /**
3496  * Finds free space in the GTT aperture and binds the object there.
3497  */
3498 static struct i915_vma *
3499 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3500                            struct i915_address_space *vm,
3501                            unsigned alignment,
3502                            uint64_t flags,
3503                            const struct i915_ggtt_view *view)
3504 {
3505         struct drm_device *dev = obj->base.dev;
3506         struct drm_i915_private *dev_priv = dev->dev_private;
3507         u32 size, fence_size, fence_alignment, unfenced_alignment;
3508         unsigned long start =
3509                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3510         unsigned long end =
3511                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3512         struct i915_vma *vma;
3513         int ret;
3514
3515         fence_size = i915_gem_get_gtt_size(dev,
3516                                            obj->base.size,
3517                                            obj->tiling_mode);
3518         fence_alignment = i915_gem_get_gtt_alignment(dev,
3519                                                      obj->base.size,
3520                                                      obj->tiling_mode, true);
3521         unfenced_alignment =
3522                 i915_gem_get_gtt_alignment(dev,
3523                                            obj->base.size,
3524                                            obj->tiling_mode, false);
3525
3526         if (alignment == 0)
3527                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3528                                                 unfenced_alignment;
3529         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3530                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3531                 return ERR_PTR(-EINVAL);
3532         }
3533
3534         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3535
3536         /* If the object is bigger than the entire aperture, reject it early
3537          * before evicting everything in a vain attempt to find space.
3538          */
3539         if (obj->base.size > end) {
3540                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3541                           obj->base.size,
3542                           flags & PIN_MAPPABLE ? "mappable" : "total",
3543                           end);
3544                 return ERR_PTR(-E2BIG);
3545         }
3546
3547         ret = i915_gem_object_get_pages(obj);
3548         if (ret)
3549                 return ERR_PTR(ret);
3550
3551         i915_gem_object_pin_pages(obj);
3552
3553         vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view);
3554         if (IS_ERR(vma))
3555                 goto err_unpin;
3556
3557 search_free:
3558         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3559                                                   size, alignment,
3560                                                   obj->cache_level,
3561                                                   start, end,
3562                                                   DRM_MM_SEARCH_DEFAULT,
3563                                                   DRM_MM_CREATE_DEFAULT);
3564         if (ret) {
3565                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3566                                                obj->cache_level,
3567                                                start, end,
3568                                                flags);
3569                 if (ret == 0)
3570                         goto search_free;
3571
3572                 goto err_free_vma;
3573         }
3574         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3575                 ret = -EINVAL;
3576                 goto err_remove_node;
3577         }
3578
3579         ret = i915_gem_gtt_prepare_object(obj);
3580         if (ret)
3581                 goto err_remove_node;
3582
3583         trace_i915_vma_bind(vma, flags);
3584         ret = i915_vma_bind(vma, obj->cache_level,
3585                             flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3586         if (ret)
3587                 goto err_finish_gtt;
3588
3589         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3590         list_add_tail(&vma->mm_list, &vm->inactive_list);
3591
3592         return vma;
3593
3594 err_finish_gtt:
3595         i915_gem_gtt_finish_object(obj);
3596 err_remove_node:
3597         drm_mm_remove_node(&vma->node);
3598 err_free_vma:
3599         i915_gem_vma_destroy(vma);
3600         vma = ERR_PTR(ret);
3601 err_unpin:
3602         i915_gem_object_unpin_pages(obj);
3603         return vma;
3604 }
3605
3606 bool
3607 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3608                         bool force)
3609 {
3610         /* If we don't have a page list set up, then we're not pinned
3611          * to GPU, and we can ignore the cache flush because it'll happen
3612          * again at bind time.
3613          */
3614         if (obj->pages == NULL)
3615                 return false;
3616
3617         /*
3618          * Stolen memory is always coherent with the GPU as it is explicitly
3619          * marked as wc by the system, or the system is cache-coherent.
3620          */
3621         if (obj->stolen || obj->phys_handle)
3622                 return false;
3623
3624         /* If the GPU is snooping the contents of the CPU cache,
3625          * we do not need to manually clear the CPU cache lines.  However,
3626          * the caches are only snooped when the render cache is
3627          * flushed/invalidated.  As we always have to emit invalidations
3628          * and flushes when moving into and out of the RENDER domain, correct
3629          * snooping behaviour occurs naturally as the result of our domain
3630          * tracking.
3631          */
3632         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3633                 return false;
3634
3635         trace_i915_gem_object_clflush(obj);
3636         drm_clflush_sg(obj->pages);
3637
3638         return true;
3639 }
3640
3641 /** Flushes the GTT write domain for the object if it's dirty. */
3642 static void
3643 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3644 {
3645         uint32_t old_write_domain;
3646
3647         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3648                 return;
3649
3650         /* No actual flushing is required for the GTT write domain.  Writes
3651          * to it immediately go to main memory as far as we know, so there's
3652          * no chipset flush.  It also doesn't land in render cache.
3653          *
3654          * However, we do have to enforce the order so that all writes through
3655          * the GTT land before any writes to the device, such as updates to
3656          * the GATT itself.
3657          */
3658         wmb();
3659
3660         old_write_domain = obj->base.write_domain;
3661         obj->base.write_domain = 0;
3662
3663         intel_fb_obj_flush(obj, false);
3664
3665         trace_i915_gem_object_change_domain(obj,
3666                                             obj->base.read_domains,
3667                                             old_write_domain);
3668 }
3669
3670 /** Flushes the CPU write domain for the object if it's dirty. */
3671 static void
3672 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3673                                        bool force)
3674 {
3675         uint32_t old_write_domain;
3676
3677         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3678                 return;
3679
3680         if (i915_gem_clflush_object(obj, force))
3681                 i915_gem_chipset_flush(obj->base.dev);
3682
3683         old_write_domain = obj->base.write_domain;
3684         obj->base.write_domain = 0;
3685
3686         intel_fb_obj_flush(obj, false);
3687
3688         trace_i915_gem_object_change_domain(obj,
3689                                             obj->base.read_domains,
3690                                             old_write_domain);
3691 }
3692
3693 /**
3694  * Moves a single object to the GTT read, and possibly write domain.
3695  *
3696  * This function returns when the move is complete, including waiting on
3697  * flushes to occur.
3698  */
3699 int
3700 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3701 {
3702         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3703         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3704         uint32_t old_write_domain, old_read_domains;
3705         int ret;
3706
3707         /* Not valid to be called on unbound objects. */
3708         if (vma == NULL)
3709                 return -EINVAL;
3710
3711         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3712                 return 0;
3713
3714         ret = i915_gem_object_wait_rendering(obj, !write);
3715         if (ret)
3716                 return ret;
3717
3718         i915_gem_object_retire(obj);
3719         i915_gem_object_flush_cpu_write_domain(obj, false);
3720
3721         /* Serialise direct access to this object with the barriers for
3722          * coherent writes from the GPU, by effectively invalidating the
3723          * GTT domain upon first access.
3724          */
3725         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3726                 mb();
3727
3728         old_write_domain = obj->base.write_domain;
3729         old_read_domains = obj->base.read_domains;
3730
3731         /* It should now be out of any other write domains, and we can update
3732          * the domain values for our changes.
3733          */
3734         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3735         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3736         if (write) {
3737                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3738                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3739                 obj->dirty = 1;
3740         }
3741
3742         if (write)
3743                 intel_fb_obj_invalidate(obj, NULL);
3744
3745         trace_i915_gem_object_change_domain(obj,
3746                                             old_read_domains,
3747                                             old_write_domain);
3748
3749         /* And bump the LRU for this access */
3750         if (i915_gem_object_is_inactive(obj))
3751                 list_move_tail(&vma->mm_list,
3752                                &dev_priv->gtt.base.inactive_list);
3753
3754         return 0;
3755 }
3756
3757 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3758                                     enum i915_cache_level cache_level)
3759 {
3760         struct drm_device *dev = obj->base.dev;
3761         struct i915_vma *vma, *next;
3762         int ret;
3763
3764         if (obj->cache_level == cache_level)
3765                 return 0;
3766
3767         if (i915_gem_obj_is_pinned(obj)) {
3768                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3769                 return -EBUSY;
3770         }
3771
3772         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3773                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3774                         ret = i915_vma_unbind(vma);
3775                         if (ret)
3776                                 return ret;
3777                 }
3778         }
3779
3780         if (i915_gem_obj_bound_any(obj)) {
3781                 ret = i915_gem_object_finish_gpu(obj);
3782                 if (ret)
3783                         return ret;
3784
3785                 i915_gem_object_finish_gtt(obj);
3786
3787                 /* Before SandyBridge, you could not use tiling or fence
3788                  * registers with snooped memory, so relinquish any fences
3789                  * currently pointing to our region in the aperture.
3790                  */
3791                 if (INTEL_INFO(dev)->gen < 6) {
3792                         ret = i915_gem_object_put_fence(obj);
3793                         if (ret)
3794                                 return ret;
3795                 }
3796
3797                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3798                         if (drm_mm_node_allocated(&vma->node)) {
3799                                 ret = i915_vma_bind(vma, cache_level,
3800                                                     vma->bound & GLOBAL_BIND);
3801                                 if (ret)
3802                                         return ret;
3803                         }
3804         }
3805
3806         list_for_each_entry(vma, &obj->vma_list, vma_link)
3807                 vma->node.color = cache_level;
3808         obj->cache_level = cache_level;
3809
3810         if (cpu_write_needs_clflush(obj)) {
3811                 u32 old_read_domains, old_write_domain;
3812
3813                 /* If we're coming from LLC cached, then we haven't
3814                  * actually been tracking whether the data is in the
3815                  * CPU cache or not, since we only allow one bit set
3816                  * in obj->write_domain and have been skipping the clflushes.
3817                  * Just set it to the CPU cache for now.
3818                  */
3819                 i915_gem_object_retire(obj);
3820                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3821
3822                 old_read_domains = obj->base.read_domains;
3823                 old_write_domain = obj->base.write_domain;
3824
3825                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3826                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3827
3828                 trace_i915_gem_object_change_domain(obj,
3829                                                     old_read_domains,
3830                                                     old_write_domain);
3831         }
3832
3833         return 0;
3834 }
3835
3836 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3837                                struct drm_file *file)
3838 {
3839         struct drm_i915_gem_caching *args = data;
3840         struct drm_i915_gem_object *obj;
3841         int ret;
3842
3843         ret = i915_mutex_lock_interruptible(dev);
3844         if (ret)
3845                 return ret;
3846
3847         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3848         if (&obj->base == NULL) {
3849                 ret = -ENOENT;
3850                 goto unlock;
3851         }
3852
3853         switch (obj->cache_level) {
3854         case I915_CACHE_LLC:
3855         case I915_CACHE_L3_LLC:
3856                 args->caching = I915_CACHING_CACHED;
3857                 break;
3858
3859         case I915_CACHE_WT:
3860                 args->caching = I915_CACHING_DISPLAY;
3861                 break;
3862
3863         default:
3864                 args->caching = I915_CACHING_NONE;
3865                 break;
3866         }
3867
3868         drm_gem_object_unreference(&obj->base);
3869 unlock:
3870         mutex_unlock(&dev->struct_mutex);
3871         return ret;
3872 }
3873
3874 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3875                                struct drm_file *file)
3876 {
3877         struct drm_i915_gem_caching *args = data;
3878         struct drm_i915_gem_object *obj;
3879         enum i915_cache_level level;
3880         int ret;
3881
3882         switch (args->caching) {
3883         case I915_CACHING_NONE:
3884                 level = I915_CACHE_NONE;
3885                 break;
3886         case I915_CACHING_CACHED:
3887                 level = I915_CACHE_LLC;
3888                 break;
3889         case I915_CACHING_DISPLAY:
3890                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3891                 break;
3892         default:
3893                 return -EINVAL;
3894         }
3895
3896         ret = i915_mutex_lock_interruptible(dev);
3897         if (ret)
3898                 return ret;
3899
3900         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3901         if (&obj->base == NULL) {
3902                 ret = -ENOENT;
3903                 goto unlock;
3904         }
3905
3906         ret = i915_gem_object_set_cache_level(obj, level);
3907
3908         drm_gem_object_unreference(&obj->base);
3909 unlock:
3910         mutex_unlock(&dev->struct_mutex);
3911         return ret;
3912 }
3913
3914 static bool is_pin_display(struct drm_i915_gem_object *obj)
3915 {
3916         struct i915_vma *vma;
3917
3918         vma = i915_gem_obj_to_ggtt(obj);
3919         if (!vma)
3920                 return false;
3921
3922         /* There are 2 sources that pin objects:
3923          *   1. The display engine (scanouts, sprites, cursors);
3924          *   2. Reservations for execbuffer;
3925          *
3926          * We can ignore reservations as we hold the struct_mutex and
3927          * are only called outside of the reservation path.
3928          */
3929         return vma->pin_count;
3930 }
3931
3932 /*
3933  * Prepare buffer for display plane (scanout, cursors, etc).
3934  * Can be called from an uninterruptible phase (modesetting) and allows
3935  * any flushes to be pipelined (for pageflips).
3936  */
3937 int
3938 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3939                                      u32 alignment,
3940                                      struct intel_engine_cs *pipelined)
3941 {
3942         u32 old_read_domains, old_write_domain;
3943         bool was_pin_display;
3944         int ret;
3945
3946         if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3947                 ret = i915_gem_object_sync(obj, pipelined);
3948                 if (ret)
3949                         return ret;
3950         }
3951
3952         /* Mark the pin_display early so that we account for the
3953          * display coherency whilst setting up the cache domains.
3954          */
3955         was_pin_display = obj->pin_display;
3956         obj->pin_display = true;
3957
3958         /* The display engine is not coherent with the LLC cache on gen6.  As
3959          * a result, we make sure that the pinning that is about to occur is
3960          * done with uncached PTEs. This is lowest common denominator for all
3961          * chipsets.
3962          *
3963          * However for gen6+, we could do better by using the GFDT bit instead
3964          * of uncaching, which would allow us to flush all the LLC-cached data
3965          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3966          */
3967         ret = i915_gem_object_set_cache_level(obj,
3968                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3969         if (ret)
3970                 goto err_unpin_display;
3971
3972         /* As the user may map the buffer once pinned in the display plane
3973          * (e.g. libkms for the bootup splash), we have to ensure that we
3974          * always use map_and_fenceable for all scanout buffers.
3975          */
3976         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3977         if (ret)
3978                 goto err_unpin_display;
3979
3980         i915_gem_object_flush_cpu_write_domain(obj, true);
3981
3982         old_write_domain = obj->base.write_domain;
3983         old_read_domains = obj->base.read_domains;
3984
3985         /* It should now be out of any other write domains, and we can update
3986          * the domain values for our changes.
3987          */
3988         obj->base.write_domain = 0;
3989         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3990
3991         trace_i915_gem_object_change_domain(obj,
3992                                             old_read_domains,
3993                                             old_write_domain);
3994
3995         return 0;
3996
3997 err_unpin_display:
3998         WARN_ON(was_pin_display != is_pin_display(obj));
3999         obj->pin_display = was_pin_display;
4000         return ret;
4001 }
4002
4003 void
4004 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4005 {
4006         i915_gem_object_ggtt_unpin(obj);
4007         obj->pin_display = is_pin_display(obj);
4008 }
4009
4010 int
4011 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4012 {
4013         int ret;
4014
4015         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4016                 return 0;
4017
4018         ret = i915_gem_object_wait_rendering(obj, false);
4019         if (ret)
4020                 return ret;
4021
4022         /* Ensure that we invalidate the GPU's caches and TLBs. */
4023         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4024         return 0;
4025 }
4026
4027 /**
4028  * Moves a single object to the CPU read, and possibly write domain.
4029  *
4030  * This function returns when the move is complete, including waiting on
4031  * flushes to occur.
4032  */
4033 int
4034 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4035 {
4036         uint32_t old_write_domain, old_read_domains;
4037         int ret;
4038
4039         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4040                 return 0;
4041
4042         ret = i915_gem_object_wait_rendering(obj, !write);
4043         if (ret)
4044                 return ret;
4045
4046         i915_gem_object_retire(obj);
4047         i915_gem_object_flush_gtt_write_domain(obj);
4048
4049         old_write_domain = obj->base.write_domain;
4050         old_read_domains = obj->base.read_domains;
4051
4052         /* Flush the CPU cache if it's still invalid. */
4053         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4054                 i915_gem_clflush_object(obj, false);
4055
4056                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4057         }
4058
4059         /* It should now be out of any other write domains, and we can update
4060          * the domain values for our changes.
4061          */
4062         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4063
4064         /* If we're writing through the CPU, then the GPU read domains will
4065          * need to be invalidated at next use.
4066          */
4067         if (write) {
4068                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4069                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4070         }
4071
4072         if (write)
4073                 intel_fb_obj_invalidate(obj, NULL);
4074
4075         trace_i915_gem_object_change_domain(obj,
4076                                             old_read_domains,
4077                                             old_write_domain);
4078
4079         return 0;
4080 }
4081
4082 /* Throttle our rendering by waiting until the ring has completed our requests
4083  * emitted over 20 msec ago.
4084  *
4085  * Note that if we were to use the current jiffies each time around the loop,
4086  * we wouldn't escape the function with any frames outstanding if the time to
4087  * render a frame was over 20ms.
4088  *
4089  * This should get us reasonable parallelism between CPU and GPU but also
4090  * relatively low latency when blocking on a particular request to finish.
4091  */
4092 static int
4093 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4094 {
4095         struct drm_i915_private *dev_priv = dev->dev_private;
4096         struct drm_i915_file_private *file_priv = file->driver_priv;
4097         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4098         struct drm_i915_gem_request *request, *target = NULL;
4099         unsigned reset_counter;
4100         int ret;
4101
4102         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4103         if (ret)
4104                 return ret;
4105
4106         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4107         if (ret)
4108                 return ret;
4109
4110         spin_lock(&file_priv->mm.lock);
4111         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4112                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4113                         break;
4114
4115                 target = request;
4116         }
4117         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4118         if (target)
4119                 i915_gem_request_reference(target);
4120         spin_unlock(&file_priv->mm.lock);
4121
4122         if (target == NULL)
4123                 return 0;
4124
4125         ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4126         if (ret == 0)
4127                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4128
4129         mutex_lock(&dev->struct_mutex);
4130         i915_gem_request_unreference(target);
4131         mutex_unlock(&dev->struct_mutex);
4132
4133         return ret;
4134 }
4135
4136 static bool
4137 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4138 {
4139         struct drm_i915_gem_object *obj = vma->obj;
4140
4141         if (alignment &&
4142             vma->node.start & (alignment - 1))
4143                 return true;
4144
4145         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4146                 return true;
4147
4148         if (flags & PIN_OFFSET_BIAS &&
4149             vma->node.start < (flags & PIN_OFFSET_MASK))
4150                 return true;
4151
4152         return false;
4153 }
4154
4155 int
4156 i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
4157                          struct i915_address_space *vm,
4158                          uint32_t alignment,
4159                          uint64_t flags,
4160                          const struct i915_ggtt_view *view)
4161 {
4162         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4163         struct i915_vma *vma;
4164         unsigned bound;
4165         int ret;
4166
4167         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4168                 return -ENODEV;
4169
4170         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4171                 return -EINVAL;
4172
4173         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4174                 return -EINVAL;
4175
4176         vma = i915_gem_obj_to_vma_view(obj, vm, view);
4177         if (vma) {
4178                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4179                         return -EBUSY;
4180
4181                 if (i915_vma_misplaced(vma, alignment, flags)) {
4182                         WARN(vma->pin_count,
4183                              "bo is already pinned with incorrect alignment:"
4184                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4185                              " obj->map_and_fenceable=%d\n",
4186                              i915_gem_obj_offset_view(obj, vm, view->type),
4187                              alignment,
4188                              !!(flags & PIN_MAPPABLE),
4189                              obj->map_and_fenceable);
4190                         ret = i915_vma_unbind(vma);
4191                         if (ret)
4192                                 return ret;
4193
4194                         vma = NULL;
4195                 }
4196         }
4197
4198         bound = vma ? vma->bound : 0;
4199         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4200                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment,
4201                                                  flags, view);
4202                 if (IS_ERR(vma))
4203                         return PTR_ERR(vma);
4204         }
4205
4206         if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) {
4207                 ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
4208                 if (ret)
4209                         return ret;
4210         }
4211
4212         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4213                 bool mappable, fenceable;
4214                 u32 fence_size, fence_alignment;
4215
4216                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4217                                                    obj->base.size,
4218                                                    obj->tiling_mode);
4219                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4220                                                              obj->base.size,
4221                                                              obj->tiling_mode,
4222                                                              true);
4223
4224                 fenceable = (vma->node.size == fence_size &&
4225                              (vma->node.start & (fence_alignment - 1)) == 0);
4226
4227                 mappable = (vma->node.start + obj->base.size <=
4228                             dev_priv->gtt.mappable_end);
4229
4230                 obj->map_and_fenceable = mappable && fenceable;
4231         }
4232
4233         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4234
4235         vma->pin_count++;
4236         if (flags & PIN_MAPPABLE)
4237                 obj->pin_mappable |= true;
4238
4239         return 0;
4240 }
4241
4242 void
4243 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4244 {
4245         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4246
4247         BUG_ON(!vma);
4248         BUG_ON(vma->pin_count == 0);
4249         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4250
4251         if (--vma->pin_count == 0)
4252                 obj->pin_mappable = false;
4253 }
4254
4255 bool
4256 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4257 {
4258         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4259                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4260                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4261
4262                 WARN_ON(!ggtt_vma ||
4263                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4264                         ggtt_vma->pin_count);
4265                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4266                 return true;
4267         } else
4268                 return false;
4269 }
4270
4271 void
4272 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4273 {
4274         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4275                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4276                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4277                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4278         }
4279 }
4280
4281 int
4282 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4283                     struct drm_file *file)
4284 {
4285         struct drm_i915_gem_busy *args = data;
4286         struct drm_i915_gem_object *obj;
4287         int ret;
4288
4289         ret = i915_mutex_lock_interruptible(dev);
4290         if (ret)
4291                 return ret;
4292
4293         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4294         if (&obj->base == NULL) {
4295                 ret = -ENOENT;
4296                 goto unlock;
4297         }
4298
4299         /* Count all active objects as busy, even if they are currently not used
4300          * by the gpu. Users of this interface expect objects to eventually
4301          * become non-busy without any further actions, therefore emit any
4302          * necessary flushes here.
4303          */
4304         ret = i915_gem_object_flush_active(obj);
4305
4306         args->busy = obj->active;
4307         if (obj->last_read_req) {
4308                 struct intel_engine_cs *ring;
4309                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4310                 ring = i915_gem_request_get_ring(obj->last_read_req);
4311                 args->busy |= intel_ring_flag(ring) << 16;
4312         }
4313
4314         drm_gem_object_unreference(&obj->base);
4315 unlock:
4316         mutex_unlock(&dev->struct_mutex);
4317         return ret;
4318 }
4319
4320 int
4321 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4322                         struct drm_file *file_priv)
4323 {
4324         return i915_gem_ring_throttle(dev, file_priv);
4325 }
4326
4327 int
4328 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4329                        struct drm_file *file_priv)
4330 {
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         struct drm_i915_gem_madvise *args = data;
4333         struct drm_i915_gem_object *obj;
4334         int ret;
4335
4336         switch (args->madv) {
4337         case I915_MADV_DONTNEED:
4338         case I915_MADV_WILLNEED:
4339             break;
4340         default:
4341             return -EINVAL;
4342         }
4343
4344         ret = i915_mutex_lock_interruptible(dev);
4345         if (ret)
4346                 return ret;
4347
4348         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4349         if (&obj->base == NULL) {
4350                 ret = -ENOENT;
4351                 goto unlock;
4352         }
4353
4354         if (i915_gem_obj_is_pinned(obj)) {
4355                 ret = -EINVAL;
4356                 goto out;
4357         }
4358
4359         if (obj->pages &&
4360             obj->tiling_mode != I915_TILING_NONE &&
4361             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4362                 if (obj->madv == I915_MADV_WILLNEED)
4363                         i915_gem_object_unpin_pages(obj);
4364                 if (args->madv == I915_MADV_WILLNEED)
4365                         i915_gem_object_pin_pages(obj);
4366         }
4367
4368         if (obj->madv != __I915_MADV_PURGED)
4369                 obj->madv = args->madv;
4370
4371         /* if the object is no longer attached, discard its backing storage */
4372         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4373                 i915_gem_object_truncate(obj);
4374
4375         args->retained = obj->madv != __I915_MADV_PURGED;
4376
4377 out:
4378         drm_gem_object_unreference(&obj->base);
4379 unlock:
4380         mutex_unlock(&dev->struct_mutex);
4381         return ret;
4382 }
4383
4384 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4385                           const struct drm_i915_gem_object_ops *ops)
4386 {
4387         INIT_LIST_HEAD(&obj->global_list);
4388         INIT_LIST_HEAD(&obj->ring_list);
4389         INIT_LIST_HEAD(&obj->obj_exec_link);
4390         INIT_LIST_HEAD(&obj->vma_list);
4391         INIT_LIST_HEAD(&obj->batch_pool_list);
4392
4393         obj->ops = ops;
4394
4395         obj->fence_reg = I915_FENCE_REG_NONE;
4396         obj->madv = I915_MADV_WILLNEED;
4397
4398         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4399 }
4400
4401 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4402         .get_pages = i915_gem_object_get_pages_gtt,
4403         .put_pages = i915_gem_object_put_pages_gtt,
4404 };
4405
4406 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4407                                                   size_t size)
4408 {
4409         struct drm_i915_gem_object *obj;
4410         struct address_space *mapping;
4411         gfp_t mask;
4412
4413         obj = i915_gem_object_alloc(dev);
4414         if (obj == NULL)
4415                 return NULL;
4416
4417         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4418                 i915_gem_object_free(obj);
4419                 return NULL;
4420         }
4421
4422         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4423         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4424                 /* 965gm cannot relocate objects above 4GiB. */
4425                 mask &= ~__GFP_HIGHMEM;
4426                 mask |= __GFP_DMA32;
4427         }
4428
4429         mapping = file_inode(obj->base.filp)->i_mapping;
4430         mapping_set_gfp_mask(mapping, mask);
4431
4432         i915_gem_object_init(obj, &i915_gem_object_ops);
4433
4434         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4435         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4436
4437         if (HAS_LLC(dev)) {
4438                 /* On some devices, we can have the GPU use the LLC (the CPU
4439                  * cache) for about a 10% performance improvement
4440                  * compared to uncached.  Graphics requests other than
4441                  * display scanout are coherent with the CPU in
4442                  * accessing this cache.  This means in this mode we
4443                  * don't need to clflush on the CPU side, and on the
4444                  * GPU side we only need to flush internal caches to
4445                  * get data visible to the CPU.
4446                  *
4447                  * However, we maintain the display planes as UC, and so
4448                  * need to rebind when first used as such.
4449                  */
4450                 obj->cache_level = I915_CACHE_LLC;
4451         } else
4452                 obj->cache_level = I915_CACHE_NONE;
4453
4454         trace_i915_gem_object_create(obj);
4455
4456         return obj;
4457 }
4458
4459 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4460 {
4461         /* If we are the last user of the backing storage (be it shmemfs
4462          * pages or stolen etc), we know that the pages are going to be
4463          * immediately released. In this case, we can then skip copying
4464          * back the contents from the GPU.
4465          */
4466
4467         if (obj->madv != I915_MADV_WILLNEED)
4468                 return false;
4469
4470         if (obj->base.filp == NULL)
4471                 return true;
4472
4473         /* At first glance, this looks racy, but then again so would be
4474          * userspace racing mmap against close. However, the first external
4475          * reference to the filp can only be obtained through the
4476          * i915_gem_mmap_ioctl() which safeguards us against the user
4477          * acquiring such a reference whilst we are in the middle of
4478          * freeing the object.
4479          */
4480         return atomic_long_read(&obj->base.filp->f_count) == 1;
4481 }
4482
4483 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4484 {
4485         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4486         struct drm_device *dev = obj->base.dev;
4487         struct drm_i915_private *dev_priv = dev->dev_private;
4488         struct i915_vma *vma, *next;
4489
4490         intel_runtime_pm_get(dev_priv);
4491
4492         trace_i915_gem_object_destroy(obj);
4493
4494         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4495                 int ret;
4496
4497                 vma->pin_count = 0;
4498                 ret = i915_vma_unbind(vma);
4499                 if (WARN_ON(ret == -ERESTARTSYS)) {
4500                         bool was_interruptible;
4501
4502                         was_interruptible = dev_priv->mm.interruptible;
4503                         dev_priv->mm.interruptible = false;
4504
4505                         WARN_ON(i915_vma_unbind(vma));
4506
4507                         dev_priv->mm.interruptible = was_interruptible;
4508                 }
4509         }
4510
4511         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4512          * before progressing. */
4513         if (obj->stolen)
4514                 i915_gem_object_unpin_pages(obj);
4515
4516         WARN_ON(obj->frontbuffer_bits);
4517
4518         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4519             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4520             obj->tiling_mode != I915_TILING_NONE)
4521                 i915_gem_object_unpin_pages(obj);
4522
4523         if (WARN_ON(obj->pages_pin_count))
4524                 obj->pages_pin_count = 0;
4525         if (discard_backing_storage(obj))
4526                 obj->madv = I915_MADV_DONTNEED;
4527         i915_gem_object_put_pages(obj);
4528         i915_gem_object_free_mmap_offset(obj);
4529
4530         BUG_ON(obj->pages);
4531
4532         if (obj->base.import_attach)
4533                 drm_prime_gem_destroy(&obj->base, NULL);
4534
4535         if (obj->ops->release)
4536                 obj->ops->release(obj);
4537
4538         drm_gem_object_release(&obj->base);
4539         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4540
4541         kfree(obj->bit_17);
4542         i915_gem_object_free(obj);
4543
4544         intel_runtime_pm_put(dev_priv);
4545 }
4546
4547 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
4548                                           struct i915_address_space *vm,
4549                                           const struct i915_ggtt_view *view)
4550 {
4551         struct i915_vma *vma;
4552         list_for_each_entry(vma, &obj->vma_list, vma_link)
4553                 if (vma->vm == vm && vma->ggtt_view.type == view->type)
4554                         return vma;
4555
4556         return NULL;
4557 }
4558
4559 void i915_gem_vma_destroy(struct i915_vma *vma)
4560 {
4561         struct i915_address_space *vm = NULL;
4562         WARN_ON(vma->node.allocated);
4563
4564         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4565         if (!list_empty(&vma->exec_list))
4566                 return;
4567
4568         vm = vma->vm;
4569
4570         if (!i915_is_ggtt(vm))
4571                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4572
4573         list_del(&vma->vma_link);
4574
4575         kfree(vma);
4576 }
4577
4578 static void
4579 i915_gem_stop_ringbuffers(struct drm_device *dev)
4580 {
4581         struct drm_i915_private *dev_priv = dev->dev_private;
4582         struct intel_engine_cs *ring;
4583         int i;
4584
4585         for_each_ring(ring, dev_priv, i)
4586                 dev_priv->gt.stop_ring(ring);
4587 }
4588
4589 int
4590 i915_gem_suspend(struct drm_device *dev)
4591 {
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593         int ret = 0;
4594
4595         mutex_lock(&dev->struct_mutex);
4596         ret = i915_gpu_idle(dev);
4597         if (ret)
4598                 goto err;
4599
4600         i915_gem_retire_requests(dev);
4601
4602         /* Under UMS, be paranoid and evict. */
4603         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4604                 i915_gem_evict_everything(dev);
4605
4606         i915_gem_stop_ringbuffers(dev);
4607         mutex_unlock(&dev->struct_mutex);
4608
4609         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4610         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4611         flush_delayed_work(&dev_priv->mm.idle_work);
4612
4613         /* Assert that we sucessfully flushed all the work and
4614          * reset the GPU back to its idle, low power state.
4615          */
4616         WARN_ON(dev_priv->mm.busy);
4617
4618         return 0;
4619
4620 err:
4621         mutex_unlock(&dev->struct_mutex);
4622         return ret;
4623 }
4624
4625 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4626 {
4627         struct drm_device *dev = ring->dev;
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4630         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4631         int i, ret;
4632
4633         if (!HAS_L3_DPF(dev) || !remap_info)
4634                 return 0;
4635
4636         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4637         if (ret)
4638                 return ret;
4639
4640         /*
4641          * Note: We do not worry about the concurrent register cacheline hang
4642          * here because no other code should access these registers other than
4643          * at initialization time.
4644          */
4645         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4646                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4647                 intel_ring_emit(ring, reg_base + i);
4648                 intel_ring_emit(ring, remap_info[i/4]);
4649         }
4650
4651         intel_ring_advance(ring);
4652
4653         return ret;
4654 }
4655
4656 void i915_gem_init_swizzling(struct drm_device *dev)
4657 {
4658         struct drm_i915_private *dev_priv = dev->dev_private;
4659
4660         if (INTEL_INFO(dev)->gen < 5 ||
4661             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4662                 return;
4663
4664         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4665                                  DISP_TILE_SURFACE_SWIZZLING);
4666
4667         if (IS_GEN5(dev))
4668                 return;
4669
4670         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4671         if (IS_GEN6(dev))
4672                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4673         else if (IS_GEN7(dev))
4674                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4675         else if (IS_GEN8(dev))
4676                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4677         else
4678                 BUG();
4679 }
4680
4681 static bool
4682 intel_enable_blt(struct drm_device *dev)
4683 {
4684         if (!HAS_BLT(dev))
4685                 return false;
4686
4687         /* The blitter was dysfunctional on early prototypes */
4688         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4689                 DRM_INFO("BLT not supported on this pre-production hardware;"
4690                          " graphics performance will be degraded.\n");
4691                 return false;
4692         }
4693
4694         return true;
4695 }
4696
4697 static void init_unused_ring(struct drm_device *dev, u32 base)
4698 {
4699         struct drm_i915_private *dev_priv = dev->dev_private;
4700
4701         I915_WRITE(RING_CTL(base), 0);
4702         I915_WRITE(RING_HEAD(base), 0);
4703         I915_WRITE(RING_TAIL(base), 0);
4704         I915_WRITE(RING_START(base), 0);
4705 }
4706
4707 static void init_unused_rings(struct drm_device *dev)
4708 {
4709         if (IS_I830(dev)) {
4710                 init_unused_ring(dev, PRB1_BASE);
4711                 init_unused_ring(dev, SRB0_BASE);
4712                 init_unused_ring(dev, SRB1_BASE);
4713                 init_unused_ring(dev, SRB2_BASE);
4714                 init_unused_ring(dev, SRB3_BASE);
4715         } else if (IS_GEN2(dev)) {
4716                 init_unused_ring(dev, SRB0_BASE);
4717                 init_unused_ring(dev, SRB1_BASE);
4718         } else if (IS_GEN3(dev)) {
4719                 init_unused_ring(dev, PRB1_BASE);
4720                 init_unused_ring(dev, PRB2_BASE);
4721         }
4722 }
4723
4724 int i915_gem_init_rings(struct drm_device *dev)
4725 {
4726         struct drm_i915_private *dev_priv = dev->dev_private;
4727         int ret;
4728
4729         ret = intel_init_render_ring_buffer(dev);
4730         if (ret)
4731                 return ret;
4732
4733         if (HAS_BSD(dev)) {
4734                 ret = intel_init_bsd_ring_buffer(dev);
4735                 if (ret)
4736                         goto cleanup_render_ring;
4737         }
4738
4739         if (intel_enable_blt(dev)) {
4740                 ret = intel_init_blt_ring_buffer(dev);
4741                 if (ret)
4742                         goto cleanup_bsd_ring;
4743         }
4744
4745         if (HAS_VEBOX(dev)) {
4746                 ret = intel_init_vebox_ring_buffer(dev);
4747                 if (ret)
4748                         goto cleanup_blt_ring;
4749         }
4750
4751         if (HAS_BSD2(dev)) {
4752                 ret = intel_init_bsd2_ring_buffer(dev);
4753                 if (ret)
4754                         goto cleanup_vebox_ring;
4755         }
4756
4757         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4758         if (ret)
4759                 goto cleanup_bsd2_ring;
4760
4761         return 0;
4762
4763 cleanup_bsd2_ring:
4764         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4765 cleanup_vebox_ring:
4766         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4767 cleanup_blt_ring:
4768         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4769 cleanup_bsd_ring:
4770         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4771 cleanup_render_ring:
4772         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4773
4774         return ret;
4775 }
4776
4777 int
4778 i915_gem_init_hw(struct drm_device *dev)
4779 {
4780         struct drm_i915_private *dev_priv = dev->dev_private;
4781         struct intel_engine_cs *ring;
4782         int ret, i;
4783
4784         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4785                 return -EIO;
4786
4787         if (dev_priv->ellc_size)
4788                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4789
4790         if (IS_HASWELL(dev))
4791                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4792                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4793
4794         if (HAS_PCH_NOP(dev)) {
4795                 if (IS_IVYBRIDGE(dev)) {
4796                         u32 temp = I915_READ(GEN7_MSG_CTL);
4797                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4798                         I915_WRITE(GEN7_MSG_CTL, temp);
4799                 } else if (INTEL_INFO(dev)->gen >= 7) {
4800                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4801                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4802                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4803                 }
4804         }
4805
4806         i915_gem_init_swizzling(dev);
4807
4808         /*
4809          * At least 830 can leave some of the unused rings
4810          * "active" (ie. head != tail) after resume which
4811          * will prevent c3 entry. Makes sure all unused rings
4812          * are totally idle.
4813          */
4814         init_unused_rings(dev);
4815
4816         for_each_ring(ring, dev_priv, i) {
4817                 ret = ring->init_hw(ring);
4818                 if (ret)
4819                         return ret;
4820         }
4821
4822         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4823                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4824
4825         /*
4826          * XXX: Contexts should only be initialized once. Doing a switch to the
4827          * default context switch however is something we'd like to do after
4828          * reset or thaw (the latter may not actually be necessary for HW, but
4829          * goes with our code better). Context switching requires rings (for
4830          * the do_switch), but before enabling PPGTT. So don't move this.
4831          */
4832         ret = i915_gem_context_enable(dev_priv);
4833         if (ret && ret != -EIO) {
4834                 DRM_ERROR("Context enable failed %d\n", ret);
4835                 i915_gem_cleanup_ringbuffer(dev);
4836
4837                 return ret;
4838         }
4839
4840         ret = i915_ppgtt_init_hw(dev);
4841         if (ret && ret != -EIO) {
4842                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4843                 i915_gem_cleanup_ringbuffer(dev);
4844         }
4845
4846         return ret;
4847 }
4848
4849 int i915_gem_init(struct drm_device *dev)
4850 {
4851         struct drm_i915_private *dev_priv = dev->dev_private;
4852         int ret;
4853
4854         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4855                         i915.enable_execlists);
4856
4857         mutex_lock(&dev->struct_mutex);
4858
4859         if (IS_VALLEYVIEW(dev)) {
4860                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4861                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4862                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4863                               VLV_GTLC_ALLOWWAKEACK), 10))
4864                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4865         }
4866
4867         if (!i915.enable_execlists) {
4868                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4869                 dev_priv->gt.init_rings = i915_gem_init_rings;
4870                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4871                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4872         } else {
4873                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4874                 dev_priv->gt.init_rings = intel_logical_rings_init;
4875                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4876                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4877         }
4878
4879         ret = i915_gem_init_userptr(dev);
4880         if (ret)
4881                 goto out_unlock;
4882
4883         i915_gem_init_global_gtt(dev);
4884
4885         ret = i915_gem_context_init(dev);
4886         if (ret)
4887                 goto out_unlock;
4888
4889         ret = dev_priv->gt.init_rings(dev);
4890         if (ret)
4891                 goto out_unlock;
4892
4893         ret = i915_gem_init_hw(dev);
4894         if (ret == -EIO) {
4895                 /* Allow ring initialisation to fail by marking the GPU as
4896                  * wedged. But we only want to do this where the GPU is angry,
4897                  * for all other failure, such as an allocation failure, bail.
4898                  */
4899                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4900                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4901                 ret = 0;
4902         }
4903
4904 out_unlock:
4905         mutex_unlock(&dev->struct_mutex);
4906
4907         return ret;
4908 }
4909
4910 void
4911 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4912 {
4913         struct drm_i915_private *dev_priv = dev->dev_private;
4914         struct intel_engine_cs *ring;
4915         int i;
4916
4917         for_each_ring(ring, dev_priv, i)
4918                 dev_priv->gt.cleanup_ring(ring);
4919 }
4920
4921 static void
4922 init_ring_lists(struct intel_engine_cs *ring)
4923 {
4924         INIT_LIST_HEAD(&ring->active_list);
4925         INIT_LIST_HEAD(&ring->request_list);
4926 }
4927
4928 void i915_init_vm(struct drm_i915_private *dev_priv,
4929                   struct i915_address_space *vm)
4930 {
4931         if (!i915_is_ggtt(vm))
4932                 drm_mm_init(&vm->mm, vm->start, vm->total);
4933         vm->dev = dev_priv->dev;
4934         INIT_LIST_HEAD(&vm->active_list);
4935         INIT_LIST_HEAD(&vm->inactive_list);
4936         INIT_LIST_HEAD(&vm->global_link);
4937         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4938 }
4939
4940 void
4941 i915_gem_load(struct drm_device *dev)
4942 {
4943         struct drm_i915_private *dev_priv = dev->dev_private;
4944         int i;
4945
4946         dev_priv->slab =
4947                 kmem_cache_create("i915_gem_object",
4948                                   sizeof(struct drm_i915_gem_object), 0,
4949                                   SLAB_HWCACHE_ALIGN,
4950                                   NULL);
4951
4952         INIT_LIST_HEAD(&dev_priv->vm_list);
4953         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4954
4955         INIT_LIST_HEAD(&dev_priv->context_list);
4956         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4957         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4958         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4959         for (i = 0; i < I915_NUM_RINGS; i++)
4960                 init_ring_lists(&dev_priv->ring[i]);
4961         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4962                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4963         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4964                           i915_gem_retire_work_handler);
4965         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4966                           i915_gem_idle_work_handler);
4967         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4968
4969         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4970         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4971                 I915_WRITE(MI_ARB_STATE,
4972                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4973         }
4974
4975         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4976
4977         /* Old X drivers will take 0-2 for front, back, depth buffers */
4978         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4979                 dev_priv->fence_reg_start = 3;
4980
4981         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4982                 dev_priv->num_fence_regs = 32;
4983         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4984                 dev_priv->num_fence_regs = 16;
4985         else
4986                 dev_priv->num_fence_regs = 8;
4987
4988         /* Initialize fence registers to zero */
4989         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4990         i915_gem_restore_fences(dev);
4991
4992         i915_gem_detect_bit_6_swizzle(dev);
4993         init_waitqueue_head(&dev_priv->pending_flip_queue);
4994
4995         dev_priv->mm.interruptible = true;
4996
4997         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4998         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4999         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5000         register_shrinker(&dev_priv->mm.shrinker);
5001
5002         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5003         register_oom_notifier(&dev_priv->mm.oom_notifier);
5004
5005         i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool);
5006
5007         mutex_init(&dev_priv->fb_tracking.lock);
5008 }
5009
5010 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5011 {
5012         struct drm_i915_file_private *file_priv = file->driver_priv;
5013
5014         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5015
5016         /* Clean up our request list when the client is going away, so that
5017          * later retire_requests won't dereference our soon-to-be-gone
5018          * file_priv.
5019          */
5020         spin_lock(&file_priv->mm.lock);
5021         while (!list_empty(&file_priv->mm.request_list)) {
5022                 struct drm_i915_gem_request *request;
5023
5024                 request = list_first_entry(&file_priv->mm.request_list,
5025                                            struct drm_i915_gem_request,
5026                                            client_list);
5027                 list_del(&request->client_list);
5028                 request->file_priv = NULL;
5029         }
5030         spin_unlock(&file_priv->mm.lock);
5031 }
5032
5033 static void
5034 i915_gem_file_idle_work_handler(struct work_struct *work)
5035 {
5036         struct drm_i915_file_private *file_priv =
5037                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5038
5039         atomic_set(&file_priv->rps_wait_boost, false);
5040 }
5041
5042 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5043 {
5044         struct drm_i915_file_private *file_priv;
5045         int ret;
5046
5047         DRM_DEBUG_DRIVER("\n");
5048
5049         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5050         if (!file_priv)
5051                 return -ENOMEM;
5052
5053         file->driver_priv = file_priv;
5054         file_priv->dev_priv = dev->dev_private;
5055         file_priv->file = file;
5056
5057         spin_lock_init(&file_priv->mm.lock);
5058         INIT_LIST_HEAD(&file_priv->mm.request_list);
5059         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5060                           i915_gem_file_idle_work_handler);
5061
5062         ret = i915_gem_context_open(dev, file);
5063         if (ret)
5064                 kfree(file_priv);
5065
5066         return ret;
5067 }
5068
5069 /**
5070  * i915_gem_track_fb - update frontbuffer tracking
5071  * old: current GEM buffer for the frontbuffer slots
5072  * new: new GEM buffer for the frontbuffer slots
5073  * frontbuffer_bits: bitmask of frontbuffer slots
5074  *
5075  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5076  * from @old and setting them in @new. Both @old and @new can be NULL.
5077  */
5078 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5079                        struct drm_i915_gem_object *new,
5080                        unsigned frontbuffer_bits)
5081 {
5082         if (old) {
5083                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5084                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5085                 old->frontbuffer_bits &= ~frontbuffer_bits;
5086         }
5087
5088         if (new) {
5089                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5090                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5091                 new->frontbuffer_bits |= frontbuffer_bits;
5092         }
5093 }
5094
5095 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5096 {
5097         if (!mutex_is_locked(mutex))
5098                 return false;
5099
5100 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5101         return mutex->owner == task;
5102 #else
5103         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5104         return false;
5105 #endif
5106 }
5107
5108 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5109 {
5110         if (!mutex_trylock(&dev->struct_mutex)) {
5111                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5112                         return false;
5113
5114                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5115                         return false;
5116
5117                 *unlock = false;
5118         } else
5119                 *unlock = true;
5120
5121         return true;
5122 }
5123
5124 static int num_vma_bound(struct drm_i915_gem_object *obj)
5125 {
5126         struct i915_vma *vma;
5127         int count = 0;
5128
5129         list_for_each_entry(vma, &obj->vma_list, vma_link)
5130                 if (drm_mm_node_allocated(&vma->node))
5131                         count++;
5132
5133         return count;
5134 }
5135
5136 static unsigned long
5137 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5138 {
5139         struct drm_i915_private *dev_priv =
5140                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5141         struct drm_device *dev = dev_priv->dev;
5142         struct drm_i915_gem_object *obj;
5143         unsigned long count;
5144         bool unlock;
5145
5146         if (!i915_gem_shrinker_lock(dev, &unlock))
5147                 return 0;
5148
5149         count = 0;
5150         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5151                 if (obj->pages_pin_count == 0)
5152                         count += obj->base.size >> PAGE_SHIFT;
5153
5154         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5155                 if (!i915_gem_obj_is_pinned(obj) &&
5156                     obj->pages_pin_count == num_vma_bound(obj))
5157                         count += obj->base.size >> PAGE_SHIFT;
5158         }
5159
5160         if (unlock)
5161                 mutex_unlock(&dev->struct_mutex);
5162
5163         return count;
5164 }
5165
5166 /* All the new VM stuff */
5167 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
5168                                        struct i915_address_space *vm,
5169                                        enum i915_ggtt_view_type view)
5170 {
5171         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5172         struct i915_vma *vma;
5173
5174         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5175
5176         list_for_each_entry(vma, &o->vma_list, vma_link) {
5177                 if (vma->vm == vm && vma->ggtt_view.type == view)
5178                         return vma->node.start;
5179
5180         }
5181         WARN(1, "%s vma for this object not found.\n",
5182              i915_is_ggtt(vm) ? "global" : "ppgtt");
5183         return -1;
5184 }
5185
5186 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
5187                              struct i915_address_space *vm,
5188                              enum i915_ggtt_view_type view)
5189 {
5190         struct i915_vma *vma;
5191
5192         list_for_each_entry(vma, &o->vma_list, vma_link)
5193                 if (vma->vm == vm &&
5194                     vma->ggtt_view.type == view &&
5195                     drm_mm_node_allocated(&vma->node))
5196                         return true;
5197
5198         return false;
5199 }
5200
5201 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5202 {
5203         struct i915_vma *vma;
5204
5205         list_for_each_entry(vma, &o->vma_list, vma_link)
5206                 if (drm_mm_node_allocated(&vma->node))
5207                         return true;
5208
5209         return false;
5210 }
5211
5212 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5213                                 struct i915_address_space *vm)
5214 {
5215         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5216         struct i915_vma *vma;
5217
5218         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5219
5220         BUG_ON(list_empty(&o->vma_list));
5221
5222         list_for_each_entry(vma, &o->vma_list, vma_link)
5223                 if (vma->vm == vm)
5224                         return vma->node.size;
5225
5226         return 0;
5227 }
5228
5229 static unsigned long
5230 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5231 {
5232         struct drm_i915_private *dev_priv =
5233                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5234         struct drm_device *dev = dev_priv->dev;
5235         unsigned long freed;
5236         bool unlock;
5237
5238         if (!i915_gem_shrinker_lock(dev, &unlock))
5239                 return SHRINK_STOP;
5240
5241         freed = i915_gem_shrink(dev_priv,
5242                                 sc->nr_to_scan,
5243                                 I915_SHRINK_BOUND |
5244                                 I915_SHRINK_UNBOUND |
5245                                 I915_SHRINK_PURGEABLE);
5246         if (freed < sc->nr_to_scan)
5247                 freed += i915_gem_shrink(dev_priv,
5248                                          sc->nr_to_scan - freed,
5249                                          I915_SHRINK_BOUND |
5250                                          I915_SHRINK_UNBOUND);
5251         if (unlock)
5252                 mutex_unlock(&dev->struct_mutex);
5253
5254         return freed;
5255 }
5256
5257 static int
5258 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5259 {
5260         struct drm_i915_private *dev_priv =
5261                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5262         struct drm_device *dev = dev_priv->dev;
5263         struct drm_i915_gem_object *obj;
5264         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5265         unsigned long pinned, bound, unbound, freed_pages;
5266         bool was_interruptible;
5267         bool unlock;
5268
5269         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5270                 schedule_timeout_killable(1);
5271                 if (fatal_signal_pending(current))
5272                         return NOTIFY_DONE;
5273         }
5274         if (timeout == 0) {
5275                 pr_err("Unable to purge GPU memory due lock contention.\n");
5276                 return NOTIFY_DONE;
5277         }
5278
5279         was_interruptible = dev_priv->mm.interruptible;
5280         dev_priv->mm.interruptible = false;
5281
5282         freed_pages = i915_gem_shrink_all(dev_priv);
5283
5284         dev_priv->mm.interruptible = was_interruptible;
5285
5286         /* Because we may be allocating inside our own driver, we cannot
5287          * assert that there are no objects with pinned pages that are not
5288          * being pointed to by hardware.
5289          */
5290         unbound = bound = pinned = 0;
5291         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5292                 if (!obj->base.filp) /* not backed by a freeable object */
5293                         continue;
5294
5295                 if (obj->pages_pin_count)
5296                         pinned += obj->base.size;
5297                 else
5298                         unbound += obj->base.size;
5299         }
5300         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5301                 if (!obj->base.filp)
5302                         continue;
5303
5304                 if (obj->pages_pin_count)
5305                         pinned += obj->base.size;
5306                 else
5307                         bound += obj->base.size;
5308         }
5309
5310         if (unlock)
5311                 mutex_unlock(&dev->struct_mutex);
5312
5313         if (freed_pages || unbound || bound)
5314                 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5315                         freed_pages << PAGE_SHIFT, pinned);
5316         if (unbound || bound)
5317                 pr_err("%lu and %lu bytes still available in the "
5318                        "bound and unbound GPU page lists.\n",
5319                        bound, unbound);
5320
5321         *(unsigned long *)ptr += freed_pages;
5322         return NOTIFY_DONE;
5323 }
5324
5325 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5326 {
5327         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5328         struct i915_vma *vma;
5329
5330         list_for_each_entry(vma, &obj->vma_list, vma_link)
5331                 if (vma->vm == ggtt &&
5332                     vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5333                         return vma;
5334
5335         return NULL;
5336 }