drivers/infiniband/hw/cxgb4/t4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __T4_H__
  32 #define __T4_H__
  33
  34 #include "t4_hw.h"
  35 #include "t4_regs.h"
  36 #include "t4_values.h"
  37 #include "t4_msg.h"
  38 #include "t4fw_ri_api.h"
  39
  40 #define T4_MAX_NUM_PD 65536
  41 #define T4_MAX_MR_SIZE (~0ULL)
  42 #define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
  43 #define T4_STAG_UNSET 0xffffffff
  44 #define T4_FW_MAJ 0
  45 #define PCIE_MA_SYNC_A 0x30b4
  46
  47 struct t4_status_page {
  48         __be32 rsvd1;   /* flit 0 - hw owns */
  49         __be16 rsvd2;
  50         __be16 qid;
  51         __be16 cidx;
  52         __be16 pidx;
  53         u8 qp_err;      /* flit 1 - sw owns */
  54         u8 db_off;
  55         u8 pad;
  56         u16 host_wq_pidx;
  57         u16 host_cidx;
  58         u16 host_pidx;
  59 };
  60
  61 #define T4_EQ_ENTRY_SIZE 64
  62
  63 #define T4_SQ_NUM_SLOTS 5
  64 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
  65 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
  66                         sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
  67 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
  68                         sizeof(struct fw_ri_immd)))
  69 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
  70                         sizeof(struct fw_ri_rdma_write_wr) - \
  71                         sizeof(struct fw_ri_immd)))
  72 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
  73                         sizeof(struct fw_ri_rdma_write_wr) - \
  74                         sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
  75 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
  76                         sizeof(struct fw_ri_immd)) & ~31UL)
  77 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
  78 #define T4_MAX_FR_DSGL 1024
  79 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
  80
  81 static inline int t4_max_fr_depth(int use_dsgl)
  82 {
  83         return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
  84 }
  85
  86 #define T4_RQ_NUM_SLOTS 2
  87 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
  88 #define T4_MAX_RECV_SGE 4
  89
  90 union t4_wr {
  91         struct fw_ri_res_wr res;
  92         struct fw_ri_wr ri;
  93         struct fw_ri_rdma_write_wr write;
  94         struct fw_ri_send_wr send;
  95         struct fw_ri_rdma_read_wr read;
  96         struct fw_ri_bind_mw_wr bind;
  97         struct fw_ri_fr_nsmr_wr fr;
  98         struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
  99         struct fw_ri_inv_lstag_wr inv;
 100         struct t4_status_page status;
 101         __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
 102 };
 103
 104 union t4_recv_wr {
 105         struct fw_ri_recv_wr recv;
 106         struct t4_status_page status;
 107         __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
 108 };
 109
 110 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
 111                                enum fw_wr_opcodes opcode, u8 flags, u8 len16)
 112 {
 113         wqe->send.opcode = (u8)opcode;
 114         wqe->send.flags = flags;
 115         wqe->send.wrid = wrid;
 116         wqe->send.r1[0] = 0;
 117         wqe->send.r1[1] = 0;
 118         wqe->send.r1[2] = 0;
 119         wqe->send.len16 = len16;
 120 }
 121
 122 /* CQE/AE status codes */
 123 #define T4_ERR_SUCCESS                     0x0
 124 #define T4_ERR_STAG                        0x1  /* STAG invalid: either the */
 125                                                 /* STAG is offlimt, being 0, */
 126                                                 /* or STAG_key mismatch */
 127 #define T4_ERR_PDID                        0x2  /* PDID mismatch */
 128 #define T4_ERR_QPID                        0x3  /* QPID mismatch */
 129 #define T4_ERR_ACCESS                      0x4  /* Invalid access right */
 130 #define T4_ERR_WRAP                        0x5  /* Wrap error */
 131 #define T4_ERR_BOUND                       0x6  /* base and bounds voilation */
 132 #define T4_ERR_INVALIDATE_SHARED_MR        0x7  /* attempt to invalidate a  */
 133                                                 /* shared memory region */
 134 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8  /* attempt to invalidate a  */
 135                                                 /* shared memory region */
 136 #define T4_ERR_ECC                         0x9  /* ECC error detected */
 137 #define T4_ERR_ECC_PSTAG                   0xA  /* ECC error detected when  */
 138                                                 /* reading PSTAG for a MW  */
 139                                                 /* Invalidate */
 140 #define T4_ERR_PBL_ADDR_BOUND              0xB  /* pbl addr out of bounds:  */
 141                                                 /* software error */
 142 #define T4_ERR_SWFLUSH                     0xC  /* SW FLUSHED */
 143 #define T4_ERR_CRC                         0x10 /* CRC error */
 144 #define T4_ERR_MARKER                      0x11 /* Marker error */
 145 #define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
 146 #define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
 147 #define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
 148 #define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
 149 #define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
 150 #define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
 151 #define T4_ERR_MSN                         0x18 /* MSN error */
 152 #define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
 153 #define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
 154                                                 /* or READ_REQ */
 155 #define T4_ERR_MSN_GAP                     0x1B
 156 #define T4_ERR_MSN_RANGE                   0x1C
 157 #define T4_ERR_IRD_OVERFLOW                0x1D
 158 #define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
 159                                                 /* software error */
 160 #define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
 161                                                 /* mismatch) */
 162 /*
 163  * CQE defs
 164  */
 165 struct t4_cqe {
 166         __be32 header;
 167         __be32 len;
 168         union {
 169                 struct {
 170                         __be32 stag;
 171                         __be32 msn;
 172                 } rcqe;
 173                 struct {
 174                         u32 stag;
 175                         u16 nada2;
 176                         u16 cidx;
 177                 } scqe;
 178                 struct {
 179                         __be32 wrid_hi;
 180                         __be32 wrid_low;
 181                 } gen;
 182         } u;
 183         __be64 reserved;
 184         __be64 bits_type_ts;
 185 };
 186
 187 /* macros for flit 0 of the cqe */
 188
 189 #define CQE_QPID_S        12
 190 #define CQE_QPID_M        0xFFFFF
 191 #define CQE_QPID_G(x)     ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
 192 #define CQE_QPID_V(x)     ((x)<<CQE_QPID_S)
 193
 194 #define CQE_SWCQE_S       11
 195 #define CQE_SWCQE_M       0x1
 196 #define CQE_SWCQE_G(x)    ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
 197 #define CQE_SWCQE_V(x)    ((x)<<CQE_SWCQE_S)
 198
 199 #define CQE_STATUS_S      5
 200 #define CQE_STATUS_M      0x1F
 201 #define CQE_STATUS_G(x)   ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
 202 #define CQE_STATUS_V(x)   ((x)<<CQE_STATUS_S)
 203
 204 #define CQE_TYPE_S        4
 205 #define CQE_TYPE_M        0x1
 206 #define CQE_TYPE_G(x)     ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
 207 #define CQE_TYPE_V(x)     ((x)<<CQE_TYPE_S)
 208
 209 #define CQE_OPCODE_S      0
 210 #define CQE_OPCODE_M      0xF
 211 #define CQE_OPCODE_G(x)   ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
 212 #define CQE_OPCODE_V(x)   ((x)<<CQE_OPCODE_S)
 213
 214 #define SW_CQE(x)         (CQE_SWCQE_G(be32_to_cpu((x)->header)))
 215 #define CQE_QPID(x)       (CQE_QPID_G(be32_to_cpu((x)->header)))
 216 #define CQE_TYPE(x)       (CQE_TYPE_G(be32_to_cpu((x)->header)))
 217 #define SQ_TYPE(x)        (CQE_TYPE((x)))
 218 #define RQ_TYPE(x)        (!CQE_TYPE((x)))
 219 #define CQE_STATUS(x)     (CQE_STATUS_G(be32_to_cpu((x)->header)))
 220 #define CQE_OPCODE(x)     (CQE_OPCODE_G(be32_to_cpu((x)->header)))
 221
 222 #define CQE_SEND_OPCODE(x)( \
 223         (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
 224         (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
 225         (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
 226         (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
 227
 228 #define CQE_LEN(x)        (be32_to_cpu((x)->len))
 229
 230 /* used for RQ completion processing */
 231 #define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
 232 #define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))
 233
 234 /* used for SQ completion processing */
 235 #define CQE_WRID_SQ_IDX(x)      ((x)->u.scqe.cidx)
 236 #define CQE_WRID_FR_STAG(x)     (be32_to_cpu((x)->u.scqe.stag))
 237
 238 /* generic accessor macros */
 239 #define CQE_WRID_HI(x)          (be32_to_cpu((x)->u.gen.wrid_hi))
 240 #define CQE_WRID_LOW(x)         (be32_to_cpu((x)->u.gen.wrid_low))
 241
 242 /* macros for flit 3 of the cqe */
 243 #define CQE_GENBIT_S    63
 244 #define CQE_GENBIT_M    0x1
 245 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
 246 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
 247
 248 #define CQE_OVFBIT_S    62
 249 #define CQE_OVFBIT_M    0x1
 250 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
 251
 252 #define CQE_IQTYPE_S    60
 253 #define CQE_IQTYPE_M    0x3
 254 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
 255
 256 #define CQE_TS_M        0x0fffffffffffffffULL
 257 #define CQE_TS_G(x)     ((x) & CQE_TS_M)
 258
 259 #define CQE_OVFBIT(x)   ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
 260 #define CQE_GENBIT(x)   ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
 261 #define CQE_TS(x)       (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
 262
 263 struct t4_swsqe {
 264         u64                     wr_id;
 265         struct t4_cqe           cqe;
 266         int                     read_len;
 267         int                     opcode;
 268         int                     complete;
 269         int                     signaled;
 270         u16                     idx;
 271         int                     flushed;
 272         struct timespec         host_ts;
 273         u64                     sge_ts;
 274 };
 275
 276 static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
 277 {
 278 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
 279         return pgprot_writecombine(prot);
 280 #else
 281         return pgprot_noncached(prot);
 282 #endif
 283 }
 284
 285 enum {
 286         T4_SQ_ONCHIP = (1<<0),
 287 };
 288
 289 struct t4_sq {
 290         union t4_wr *queue;
 291         dma_addr_t dma_addr;
 292         DEFINE_DMA_UNMAP_ADDR(mapping);
 293         unsigned long phys_addr;
 294         struct t4_swsqe *sw_sq;
 295         struct t4_swsqe *oldest_read;
 296         void __iomem *bar2_va;
 297         u64 bar2_pa;
 298         size_t memsize;
 299         u32 bar2_qid;
 300         u32 qid;
 301         u16 in_use;
 302         u16 size;
 303         u16 cidx;
 304         u16 pidx;
 305         u16 wq_pidx;
 306         u16 wq_pidx_inc;
 307         u16 flags;
 308         short flush_cidx;
 309 };
 310
 311 struct t4_swrqe {
 312         u64 wr_id;
 313         struct timespec host_ts;
 314         u64 sge_ts;
 315 };
 316
 317 struct t4_rq {
 318         union  t4_recv_wr *queue;
 319         dma_addr_t dma_addr;
 320         DEFINE_DMA_UNMAP_ADDR(mapping);
 321         struct t4_swrqe *sw_rq;
 322         void __iomem *bar2_va;
 323         u64 bar2_pa;
 324         size_t memsize;
 325         u32 bar2_qid;
 326         u32 qid;
 327         u32 msn;
 328         u32 rqt_hwaddr;
 329         u16 rqt_size;
 330         u16 in_use;
 331         u16 size;
 332         u16 cidx;
 333         u16 pidx;
 334         u16 wq_pidx;
 335         u16 wq_pidx_inc;
 336 };
 337
 338 struct t4_wq {
 339         struct t4_sq sq;
 340         struct t4_rq rq;
 341         void __iomem *db;
 342         struct c4iw_rdev *rdev;
 343         int flushed;
 344 };
 345
 346 static inline int t4_rqes_posted(struct t4_wq *wq)
 347 {
 348         return wq->rq.in_use;
 349 }
 350
 351 static inline int t4_rq_empty(struct t4_wq *wq)
 352 {
 353         return wq->rq.in_use == 0;
 354 }
 355
 356 static inline int t4_rq_full(struct t4_wq *wq)
 357 {
 358         return wq->rq.in_use == (wq->rq.size - 1);
 359 }
 360
 361 static inline u32 t4_rq_avail(struct t4_wq *wq)
 362 {
 363         return wq->rq.size - 1 - wq->rq.in_use;
 364 }
 365
 366 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
 367 {
 368         wq->rq.in_use++;
 369         if (++wq->rq.pidx == wq->rq.size)
 370                 wq->rq.pidx = 0;
 371         wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 372         if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
 373                 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
 374 }
 375
 376 static inline void t4_rq_consume(struct t4_wq *wq)
 377 {
 378         wq->rq.in_use--;
 379         wq->rq.msn++;
 380         if (++wq->rq.cidx == wq->rq.size)
 381                 wq->rq.cidx = 0;
 382 }
 383
 384 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
 385 {
 386         return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
 387 }
 388
 389 static inline u16 t4_rq_wq_size(struct t4_wq *wq)
 390 {
 391                 return wq->rq.size * T4_RQ_NUM_SLOTS;
 392 }
 393
 394 static inline int t4_sq_onchip(struct t4_sq *sq)
 395 {
 396         return sq->flags & T4_SQ_ONCHIP;
 397 }
 398
 399 static inline int t4_sq_empty(struct t4_wq *wq)
 400 {
 401         return wq->sq.in_use == 0;
 402 }
 403
 404 static inline int t4_sq_full(struct t4_wq *wq)
 405 {
 406         return wq->sq.in_use == (wq->sq.size - 1);
 407 }
 408
 409 static inline u32 t4_sq_avail(struct t4_wq *wq)
 410 {
 411         return wq->sq.size - 1 - wq->sq.in_use;
 412 }
 413
 414 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
 415 {
 416         wq->sq.in_use++;
 417         if (++wq->sq.pidx == wq->sq.size)
 418                 wq->sq.pidx = 0;
 419         wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 420         if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
 421                 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
 422 }
 423
 424 static inline void t4_sq_consume(struct t4_wq *wq)
 425 {
 426         BUG_ON(wq->sq.in_use < 1);
 427         if (wq->sq.cidx == wq->sq.flush_cidx)
 428                 wq->sq.flush_cidx = -1;
 429         wq->sq.in_use--;
 430         if (++wq->sq.cidx == wq->sq.size)
 431                 wq->sq.cidx = 0;
 432 }
 433
 434 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
 435 {
 436         return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
 437 }
 438
 439 static inline u16 t4_sq_wq_size(struct t4_wq *wq)
 440 {
 441                 return wq->sq.size * T4_SQ_NUM_SLOTS;
 442 }
 443
 444 /* This function copies 64 byte coalesced work request to memory
 445  * mapped BAR2 space. For coalesced WRs, the SGE fetches data
 446  * from the FIFO instead of from Host.
 447  */
 448 static inline void pio_copy(u64 __iomem *dst, u64 *src)
 449 {
 450         int count = 8;
 451
 452         while (count) {
 453                 writeq(*src, dst);
 454                 src++;
 455                 dst++;
 456                 count--;
 457         }
 458 }
 459
 460 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
 461 {
 462
 463         /* Flush host queue memory writes. */
 464         wmb();
 465         if (wq->sq.bar2_va) {
 466                 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
 467                         PDBG("%s: WC wq->sq.pidx = %d\n",
 468                              __func__, wq->sq.pidx);
 469                         pio_copy((u64 __iomem *)
 470                                  (wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
 471                                  (u64 *)wqe);
 472                 } else {
 473                         PDBG("%s: DB wq->sq.pidx = %d\n",
 474                              __func__, wq->sq.pidx);
 475                         writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
 476                                wq->sq.bar2_va + SGE_UDB_KDOORBELL);
 477                 }
 478
 479                 /* Flush user doorbell area writes. */
 480                 wmb();
 481                 return;
 482         }
 483         writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
 484 }
 485
 486 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc,
 487                                  union t4_recv_wr *wqe)
 488 {
 489
 490         /* Flush host queue memory writes. */
 491         wmb();
 492         if (wq->rq.bar2_va) {
 493                 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
 494                         PDBG("%s: WC wq->rq.pidx = %d\n",
 495                              __func__, wq->rq.pidx);
 496                         pio_copy((u64 __iomem *)
 497                                  (wq->rq.bar2_va + SGE_UDB_WCDOORBELL),
 498                                  (void *)wqe);
 499                 } else {
 500                         PDBG("%s: DB wq->rq.pidx = %d\n",
 501                              __func__, wq->rq.pidx);
 502                         writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
 503                                wq->rq.bar2_va + SGE_UDB_KDOORBELL);
 504                 }
 505
 506                 /* Flush user doorbell area writes. */
 507                 wmb();
 508                 return;
 509         }
 510         writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
 511 }
 512
 513 static inline int t4_wq_in_error(struct t4_wq *wq)
 514 {
 515         return wq->rq.queue[wq->rq.size].status.qp_err;
 516 }
 517
 518 static inline void t4_set_wq_in_error(struct t4_wq *wq)
 519 {
 520         wq->rq.queue[wq->rq.size].status.qp_err = 1;
 521 }
 522
 523 static inline void t4_disable_wq_db(struct t4_wq *wq)
 524 {
 525         wq->rq.queue[wq->rq.size].status.db_off = 1;
 526 }
 527
 528 static inline void t4_enable_wq_db(struct t4_wq *wq)
 529 {
 530         wq->rq.queue[wq->rq.size].status.db_off = 0;
 531 }
 532
 533 static inline int t4_wq_db_enabled(struct t4_wq *wq)
 534 {
 535         return !wq->rq.queue[wq->rq.size].status.db_off;
 536 }
 537
 538 enum t4_cq_flags {
 539         CQ_ARMED        = 1,
 540 };
 541
 542 struct t4_cq {
 543         struct t4_cqe *queue;
 544         dma_addr_t dma_addr;
 545         DEFINE_DMA_UNMAP_ADDR(mapping);
 546         struct t4_cqe *sw_queue;
 547         void __iomem *gts;
 548         void __iomem *bar2_va;
 549         u64 bar2_pa;
 550         u32 bar2_qid;
 551         struct c4iw_rdev *rdev;
 552         size_t memsize;
 553         __be64 bits_type_ts;
 554         u32 cqid;
 555         u32 qid_mask;
 556         int vector;
 557         u16 size; /* including status page */
 558         u16 cidx;
 559         u16 sw_pidx;
 560         u16 sw_cidx;
 561         u16 sw_in_use;
 562         u16 cidx_inc;
 563         u8 gen;
 564         u8 error;
 565         unsigned long flags;
 566 };
 567
 568 static inline void write_gts(struct t4_cq *cq, u32 val)
 569 {
 570         if (cq->bar2_va)
 571                 writel(val | INGRESSQID_V(cq->bar2_qid),
 572                        cq->bar2_va + SGE_UDB_GTS);
 573         else
 574                 writel(val | INGRESSQID_V(cq->cqid), cq->gts);
 575 }
 576
 577 static inline int t4_clear_cq_armed(struct t4_cq *cq)
 578 {
 579         return test_and_clear_bit(CQ_ARMED, &cq->flags);
 580 }
 581
 582 static inline int t4_arm_cq(struct t4_cq *cq, int se)
 583 {
 584         u32 val;
 585
 586         set_bit(CQ_ARMED, &cq->flags);
 587         while (cq->cidx_inc > CIDXINC_M) {
 588                 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7);
 589                 write_gts(cq, val);
 590                 cq->cidx_inc -= CIDXINC_M;
 591         }
 592         val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6);
 593         write_gts(cq, val);
 594         cq->cidx_inc = 0;
 595         return 0;
 596 }
 597
 598 static inline void t4_swcq_produce(struct t4_cq *cq)
 599 {
 600         cq->sw_in_use++;
 601         if (cq->sw_in_use == cq->size) {
 602                 PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
 603                 cq->error = 1;
 604                 BUG_ON(1);
 605         }
 606         if (++cq->sw_pidx == cq->size)
 607                 cq->sw_pidx = 0;
 608 }
 609
 610 static inline void t4_swcq_consume(struct t4_cq *cq)
 611 {
 612         BUG_ON(cq->sw_in_use < 1);
 613         cq->sw_in_use--;
 614         if (++cq->sw_cidx == cq->size)
 615                 cq->sw_cidx = 0;
 616 }
 617
 618 static inline void t4_hwcq_consume(struct t4_cq *cq)
 619 {
 620         cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
 621         if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
 622                 u32 val;
 623
 624                 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7);
 625                 write_gts(cq, val);
 626                 cq->cidx_inc = 0;
 627         }
 628         if (++cq->cidx == cq->size) {
 629                 cq->cidx = 0;
 630                 cq->gen ^= 1;
 631         }
 632 }
 633
 634 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
 635 {
 636         return (CQE_GENBIT(cqe) == cq->gen);
 637 }
 638
 639 static inline int t4_cq_notempty(struct t4_cq *cq)
 640 {
 641         return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
 642 }
 643
 644 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
 645 {
 646         int ret;
 647         u16 prev_cidx;
 648
 649         if (cq->cidx == 0)
 650                 prev_cidx = cq->size - 1;
 651         else
 652                 prev_cidx = cq->cidx - 1;
 653
 654         if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
 655                 ret = -EOVERFLOW;
 656                 cq->error = 1;
 657                 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
 658                 BUG_ON(1);
 659         } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
 660
 661                 /* Ensure CQE is flushed to memory */
 662                 rmb();
 663                 *cqe = &cq->queue[cq->cidx];
 664                 ret = 0;
 665         } else
 666                 ret = -ENODATA;
 667         return ret;
 668 }
 669
 670 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
 671 {
 672         if (cq->sw_in_use == cq->size) {
 673                 PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
 674                 cq->error = 1;
 675                 BUG_ON(1);
 676                 return NULL;
 677         }
 678         if (cq->sw_in_use)
 679                 return &cq->sw_queue[cq->sw_cidx];
 680         return NULL;
 681 }
 682
 683 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
 684 {
 685         int ret = 0;
 686
 687         if (cq->error)
 688                 ret = -ENODATA;
 689         else if (cq->sw_in_use)
 690                 *cqe = &cq->sw_queue[cq->sw_cidx];
 691         else
 692                 ret = t4_next_hw_cqe(cq, cqe);
 693         return ret;
 694 }
 695
 696 static inline int t4_cq_in_error(struct t4_cq *cq)
 697 {
 698         return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
 699 }
 700
 701 static inline void t4_set_cq_in_error(struct t4_cq *cq)
 702 {
 703         ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
 704 }
 705 #endif
 706
 707 struct t4_dev_status_page {
 708         u8 db_off;
 709         u8 pad1;
 710         u16 pad2;
 711         u32 pad3;
 712         u64 qp_start;
 713         u64 qp_size;
 714         u64 cq_start;
 715         u64 cq_size;
 716 };