drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/vxlan.h>
  49 #include <net/checksum.h>
  50 #include <net/ip6_checksum.h>
  51 #include <linux/workqueue.h>
  52 #include <linux/crc32.h>
  53 #include <linux/crc32c.h>
  54 #include <linux/prefetch.h>
  55 #include <linux/zlib.h>
  56 #include <linux/io.h>
  57 #include <linux/semaphore.h>
  58 #include <linux/stringify.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "bnx2x.h"
  62 #include "bnx2x_init.h"
  63 #include "bnx2x_init_ops.h"
  64 #include "bnx2x_cmn.h"
  65 #include "bnx2x_vfpf.h"
  66 #include "bnx2x_dcb.h"
  67 #include "bnx2x_sp.h"
  68 #include <linux/firmware.h>
  69 #include "bnx2x_fw_file_hdr.h"
  70 /* FW files */
  71 #define FW_FILE_VERSION                                 \
  72         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  74         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  75         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  76 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  78 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  97
  98 int bnx2x_num_queues;
  99 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 100 MODULE_PARM_DESC(num_queues,
 101                  " Set number of queues (default is as a number of CPUs)");
 102
 103 static int disable_tpa;
 104 module_param(disable_tpa, int, S_IRUGO);
 105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 106
 107 static int int_mode;
 108 module_param(int_mode, int, S_IRUGO);
 109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 110                                 "(1 INT#x; 2 MSI)");
 111
 112 static int dropless_fc;
 113 module_param(dropless_fc, int, S_IRUGO);
 114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 115
 116 static int mrrs = -1;
 117 module_param(mrrs, int, S_IRUGO);
 118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 119
 120 static int debug;
 121 module_param(debug, int, S_IRUGO);
 122 MODULE_PARM_DESC(debug, " Default debug msglevel");
 123
 124 static struct workqueue_struct *bnx2x_wq;
 125 struct workqueue_struct *bnx2x_iov_wq;
 126
 127 struct bnx2x_mac_vals {
 128         u32 xmac_addr;
 129         u32 xmac_val;
 130         u32 emac_addr;
 131         u32 emac_val;
 132         u32 umac_addr;
 133         u32 umac_val;
 134         u32 bmac_addr;
 135         u32 bmac_val[2];
 136 };
 137
 138 enum bnx2x_board_type {
 139         BCM57710 = 0,
 140         BCM57711,
 141         BCM57711E,
 142         BCM57712,
 143         BCM57712_MF,
 144         BCM57712_VF,
 145         BCM57800,
 146         BCM57800_MF,
 147         BCM57800_VF,
 148         BCM57810,
 149         BCM57810_MF,
 150         BCM57810_VF,
 151         BCM57840_4_10,
 152         BCM57840_2_20,
 153         BCM57840_MF,
 154         BCM57840_VF,
 155         BCM57811,
 156         BCM57811_MF,
 157         BCM57840_O,
 158         BCM57840_MFO,
 159         BCM57811_VF
 160 };
 161
 162 /* indexed by board_type, above */
 163 static struct {
 164         char *name;
 165 } board_info[] = {
 166         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 167         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 168         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 169         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 170         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 171         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 173         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 174         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 176         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 177         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 178         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 179         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 180         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 181         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 182         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 183         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 184         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 185         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 186         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 187 };
 188
 189 #ifndef PCI_DEVICE_ID_NX2_57710
 190 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711
 193 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57711E
 196 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712
 199 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 202 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 205 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800
 208 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 211 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 214 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810
 217 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 220 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_O
 223 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 226 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 229 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 232 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 235 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 238 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 241 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811
 244 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 247 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 248 #endif
 249 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 250 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 251 #endif
 252
 253 static const struct pci_device_id bnx2x_pci_tbl[] = {
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 275         { 0 }
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 279
 280 /* Global resources for unloading a previously loaded device */
 281 #define BNX2X_PREV_WAIT_NEEDED 1
 282 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 283 static LIST_HEAD(bnx2x_prev_list);
 284
 285 /* Forward declaration */
 286 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 287 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 289
 290 /****************************************************************************
 291 * General service functions
 292 ****************************************************************************/
 293
 294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 295
 296 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 297                                        u32 addr, dma_addr_t mapping)
 298 {
 299         REG_WR(bp,  addr, U64_LO(mapping));
 300         REG_WR(bp,  addr + 4, U64_HI(mapping));
 301 }
 302
 303 static void storm_memset_spq_addr(struct bnx2x *bp,
 304                                   dma_addr_t mapping, u16 abs_fid)
 305 {
 306         u32 addr = XSEM_REG_FAST_MEMORY +
 307                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 308
 309         __storm_memset_dma_mapping(bp, addr, mapping);
 310 }
 311
 312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 313                                   u16 pf_id)
 314 {
 315         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323 }
 324
 325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 326                                  u8 enable)
 327 {
 328         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336 }
 337
 338 static void storm_memset_eq_data(struct bnx2x *bp,
 339                                  struct event_ring_data *eq_data,
 340                                 u16 pfid)
 341 {
 342         size_t size = sizeof(struct event_ring_data);
 343
 344         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 345
 346         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 347 }
 348
 349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 350                                  u16 pfid)
 351 {
 352         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 353         REG_WR16(bp, addr, eq_prod);
 354 }
 355
 356 /* used only at init
 357  * locking is done by mcp
 358  */
 359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 360 {
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 364                                PCICFG_VENDOR_ID_OFFSET);
 365 }
 366
 367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 368 {
 369         u32 val;
 370
 371         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 372         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 374                                PCICFG_VENDOR_ID_OFFSET);
 375
 376         return val;
 377 }
 378
 379 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 380 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 381 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 382 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 383 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 384
 385 static void bnx2x_dp_dmae(struct bnx2x *bp,
 386                           struct dmae_command *dmae, int msglvl)
 387 {
 388         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 389         int i;
 390
 391         switch (dmae->opcode & DMAE_COMMAND_DST) {
 392         case DMAE_CMD_DST_PCI:
 393                 if (src_type == DMAE_CMD_SRC_PCI)
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 else
 402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 403                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 405                            dmae->opcode, dmae->src_addr_lo >> 2,
 406                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 408                            dmae->comp_val);
 409                 break;
 410         case DMAE_CMD_DST_GRC:
 411                 if (src_type == DMAE_CMD_SRC_PCI)
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 else
 420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 421                            "src [%08x], len [%d*4], dst [%08x]\n"
 422                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 423                            dmae->opcode, dmae->src_addr_lo >> 2,
 424                            dmae->len, dmae->dst_addr_lo >> 2,
 425                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 426                            dmae->comp_val);
 427                 break;
 428         default:
 429                 if (src_type == DMAE_CMD_SRC_PCI)
 430                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 431                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 432                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 433                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 434                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 435                            dmae->comp_val);
 436                 else
 437                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 438                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 439                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 440                            dmae->opcode, dmae->src_addr_lo >> 2,
 441                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 442                            dmae->comp_val);
 443                 break;
 444         }
 445
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 447                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 448                    i, *(((u32 *)dmae) + i));
 449 }
 450
 451 /* copy command into DMAE command memory and set DMAE command go */
 452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 453 {
 454         u32 cmd_offset;
 455         int i;
 456
 457         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 458         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 459                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 460         }
 461         REG_WR(bp, dmae_reg_go_c[idx], 1);
 462 }
 463
 464 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 465 {
 466         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 467                            DMAE_CMD_C_ENABLE);
 468 }
 469
 470 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 471 {
 472         return opcode & ~DMAE_CMD_SRC_RESET;
 473 }
 474
 475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 476                              bool with_comp, u8 comp_type)
 477 {
 478         u32 opcode = 0;
 479
 480         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 481                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 482
 483         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 484
 485         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 486         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 487                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 488         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 489
 490 #ifdef __BIG_ENDIAN
 491         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 492 #else
 493         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 494 #endif
 495         if (with_comp)
 496                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 497         return opcode;
 498 }
 499
 500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 501                                       struct dmae_command *dmae,
 502                                       u8 src_type, u8 dst_type)
 503 {
 504         memset(dmae, 0, sizeof(struct dmae_command));
 505
 506         /* set the opcode */
 507         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 508                                          true, DMAE_COMP_PCI);
 509
 510         /* fill in the completion parameters */
 511         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 512         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 513         dmae->comp_val = DMAE_COMP_VAL;
 514 }
 515
 516 /* issue a dmae command over the init-channel and wait for completion */
 517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 518                                u32 *comp)
 519 {
 520         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 521         int rc = 0;
 522
 523         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 524
 525         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 526          * as long as this code is called both from syscall context and
 527          * from ndo_set_rx_mode() flow that may be called from BH.
 528          */
 529
 530         spin_lock_bh(&bp->dmae_lock);
 531
 532         /* reset completion */
 533         *comp = 0;
 534
 535         /* post the command on the channel used for initializations */
 536         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 537
 538         /* wait for completion */
 539         udelay(5);
 540         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 541
 542                 if (!cnt ||
 543                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 544                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 545                         BNX2X_ERR("DMAE timeout!\n");
 546                         rc = DMAE_TIMEOUT;
 547                         goto unlock;
 548                 }
 549                 cnt--;
 550                 udelay(50);
 551         }
 552         if (*comp & DMAE_PCI_ERR_FLAG) {
 553                 BNX2X_ERR("DMAE PCI error!\n");
 554                 rc = DMAE_PCI_ERROR;
 555         }
 556
 557 unlock:
 558
 559         spin_unlock_bh(&bp->dmae_lock);
 560
 561         return rc;
 562 }
 563
 564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 565                       u32 len32)
 566 {
 567         int rc;
 568         struct dmae_command dmae;
 569
 570         if (!bp->dmae_ready) {
 571                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 572
 573                 if (CHIP_IS_E1(bp))
 574                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 575                 else
 576                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 577                 return;
 578         }
 579
 580         /* set opcode and fixed command fields */
 581         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 582
 583         /* fill in addresses and len */
 584         dmae.src_addr_lo = U64_LO(dma_addr);
 585         dmae.src_addr_hi = U64_HI(dma_addr);
 586         dmae.dst_addr_lo = dst_addr >> 2;
 587         dmae.dst_addr_hi = 0;
 588         dmae.len = len32;
 589
 590         /* issue the command and wait for completion */
 591         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 592         if (rc) {
 593                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 594 #ifdef BNX2X_STOP_ON_ERROR
 595                 bnx2x_panic();
 596 #endif
 597         }
 598 }
 599
 600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 601 {
 602         int rc;
 603         struct dmae_command dmae;
 604
 605         if (!bp->dmae_ready) {
 606                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 607                 int i;
 608
 609                 if (CHIP_IS_E1(bp))
 610                         for (i = 0; i < len32; i++)
 611                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 612                 else
 613                         for (i = 0; i < len32; i++)
 614                                 data[i] = REG_RD(bp, src_addr + i*4);
 615
 616                 return;
 617         }
 618
 619         /* set opcode and fixed command fields */
 620         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 621
 622         /* fill in addresses and len */
 623         dmae.src_addr_lo = src_addr >> 2;
 624         dmae.src_addr_hi = 0;
 625         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 626         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 627         dmae.len = len32;
 628
 629         /* issue the command and wait for completion */
 630         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 631         if (rc) {
 632                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 633 #ifdef BNX2X_STOP_ON_ERROR
 634                 bnx2x_panic();
 635 #endif
 636         }
 637 }
 638
 639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 640                                       u32 addr, u32 len)
 641 {
 642         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 643         int offset = 0;
 644
 645         while (len > dmae_wr_max) {
 646                 bnx2x_write_dmae(bp, phys_addr + offset,
 647                                  addr + offset, dmae_wr_max);
 648                 offset += dmae_wr_max * 4;
 649                 len -= dmae_wr_max;
 650         }
 651
 652         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 653 }
 654
 655 enum storms {
 656            XSTORM,
 657            TSTORM,
 658            CSTORM,
 659            USTORM,
 660            MAX_STORMS
 661 };
 662
 663 #define STORMS_NUM 4
 664 #define REGS_IN_ENTRY 4
 665
 666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 667                                               enum storms storm,
 668                                               int entry)
 669 {
 670         switch (storm) {
 671         case XSTORM:
 672                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 673         case TSTORM:
 674                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 675         case CSTORM:
 676                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 677         case USTORM:
 678                 return USTORM_ASSERT_LIST_OFFSET(entry);
 679         case MAX_STORMS:
 680         default:
 681                 BNX2X_ERR("unknown storm\n");
 682         }
 683         return -EINVAL;
 684 }
 685
 686 static int bnx2x_mc_assert(struct bnx2x *bp)
 687 {
 688         char last_idx;
 689         int i, j, rc = 0;
 690         enum storms storm;
 691         u32 regs[REGS_IN_ENTRY];
 692         u32 bar_storm_intmem[STORMS_NUM] = {
 693                 BAR_XSTRORM_INTMEM,
 694                 BAR_TSTRORM_INTMEM,
 695                 BAR_CSTRORM_INTMEM,
 696                 BAR_USTRORM_INTMEM
 697         };
 698         u32 storm_assert_list_index[STORMS_NUM] = {
 699                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 USTORM_ASSERT_LIST_INDEX_OFFSET
 703         };
 704         char *storms_string[STORMS_NUM] = {
 705                 "XSTORM",
 706                 "TSTORM",
 707                 "CSTORM",
 708                 "USTORM"
 709         };
 710
 711         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 712                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 713                                    storm_assert_list_index[storm]);
 714                 if (last_idx)
 715                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 716                                   storms_string[storm], last_idx);
 717
 718                 /* print the asserts */
 719                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720                         /* read a single assert entry */
 721                         for (j = 0; j < REGS_IN_ENTRY; j++)
 722                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 723                                           bnx2x_get_assert_list_entry(bp,
 724                                                                       storm,
 725                                                                       i) +
 726                                           sizeof(u32) * j);
 727
 728                         /* log entry if it contains a valid assert */
 729                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 730                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 731                                           storms_string[storm], i, regs[3],
 732                                           regs[2], regs[1], regs[0]);
 733                                 rc++;
 734                         } else {
 735                                 break;
 736                         }
 737                 }
 738         }
 739
 740         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 741                   CHIP_IS_E1(bp) ? "everest1" :
 742                   CHIP_IS_E1H(bp) ? "everest1h" :
 743                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 744                   BCM_5710_FW_MAJOR_VERSION,
 745                   BCM_5710_FW_MINOR_VERSION,
 746                   BCM_5710_FW_REVISION_VERSION);
 747
 748         return rc;
 749 }
 750
 751 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 752 #define SCRATCH_BUFFER_SIZE(bp) \
 753         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 754
 755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 756 {
 757         u32 addr, val;
 758         u32 mark, offset;
 759         __be32 data[9];
 760         int word;
 761         u32 trace_shmem_base;
 762         if (BP_NOMCP(bp)) {
 763                 BNX2X_ERR("NO MCP - can not dump\n");
 764                 return;
 765         }
 766         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 767                 (bp->common.bc_ver & 0xff0000) >> 16,
 768                 (bp->common.bc_ver & 0xff00) >> 8,
 769                 (bp->common.bc_ver & 0xff));
 770
 771         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 772         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 773                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 774
 775         if (BP_PATH(bp) == 0)
 776                 trace_shmem_base = bp->common.shmem_base;
 777         else
 778                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 779
 780         /* sanity */
 781         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 782             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 783                                 SCRATCH_BUFFER_SIZE(bp)) {
 784                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 785                           trace_shmem_base);
 786                 return;
 787         }
 788
 789         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 790
 791         /* validate TRCB signature */
 792         mark = REG_RD(bp, addr);
 793         if (mark != MFW_TRACE_SIGNATURE) {
 794                 BNX2X_ERR("Trace buffer signature is missing.");
 795                 return ;
 796         }
 797
 798         /* read cyclic buffer pointer */
 799         addr += 4;
 800         mark = REG_RD(bp, addr);
 801         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 802         if (mark >= trace_shmem_base || mark < addr + 4) {
 803                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 804                 return;
 805         }
 806         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 807
 808         printk("%s", lvl);
 809
 810         /* dump buffer after the mark */
 811         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 812                 for (word = 0; word < 8; word++)
 813                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 814                 data[8] = 0x0;
 815                 pr_cont("%s", (char *)data);
 816         }
 817
 818         /* dump buffer before the mark */
 819         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825         printk("%s" "end of fw dump\n", lvl);
 826 }
 827
 828 static void bnx2x_fw_dump(struct bnx2x *bp)
 829 {
 830         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 831 }
 832
 833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 834 {
 835         int port = BP_PORT(bp);
 836         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 837         u32 val = REG_RD(bp, addr);
 838
 839         /* in E1 we must use only PCI configuration space to disable
 840          * MSI/MSIX capability
 841          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 842          */
 843         if (CHIP_IS_E1(bp)) {
 844                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 845                  * Use mask register to prevent from HC sending interrupts
 846                  * after we exit the function
 847                  */
 848                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 849
 850                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 851                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 852                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 853         } else
 854                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 855                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 858
 859         DP(NETIF_MSG_IFDOWN,
 860            "write %x to HC %d (addr 0x%x)\n",
 861            val, port, addr);
 862
 863         /* flush all outstanding writes */
 864         mmiowb();
 865
 866         REG_WR(bp, addr, val);
 867         if (REG_RD(bp, addr) != val)
 868                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 869 }
 870
 871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 872 {
 873         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 874
 875         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 876                  IGU_PF_CONF_INT_LINE_EN |
 877                  IGU_PF_CONF_ATTN_BIT_EN);
 878
 879         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 880
 881         /* flush all outstanding writes */
 882         mmiowb();
 883
 884         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 885         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 886                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 887 }
 888
 889 static void bnx2x_int_disable(struct bnx2x *bp)
 890 {
 891         if (bp->common.int_block == INT_BLOCK_HC)
 892                 bnx2x_hc_int_disable(bp);
 893         else
 894                 bnx2x_igu_int_disable(bp);
 895 }
 896
 897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 898 {
 899         int i;
 900         u16 j;
 901         struct hc_sp_status_block_data sp_sb_data;
 902         int func = BP_FUNC(bp);
 903 #ifdef BNX2X_STOP_ON_ERROR
 904         u16 start = 0, end = 0;
 905         u8 cos;
 906 #endif
 907         if (IS_PF(bp) && disable_int)
 908                 bnx2x_int_disable(bp);
 909
 910         bp->stats_state = STATS_STATE_DISABLED;
 911         bp->eth_stats.unrecoverable_error++;
 912         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 913
 914         BNX2X_ERR("begin crash dump -----------------\n");
 915
 916         /* Indices */
 917         /* Common */
 918         if (IS_PF(bp)) {
 919                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 920                 int data_size, cstorm_offset;
 921
 922                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 923                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 924                           bp->spq_prod_idx, bp->stats_counter);
 925                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 926                           def_sb->atten_status_block.attn_bits,
 927                           def_sb->atten_status_block.attn_bits_ack,
 928                           def_sb->atten_status_block.status_block_id,
 929                           def_sb->atten_status_block.attn_bits_index);
 930                 BNX2X_ERR("     def (");
 931                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 932                         pr_cont("0x%x%s",
 933                                 def_sb->sp_sb.index_values[i],
 934                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 935
 936                 data_size = sizeof(struct hc_sp_status_block_data) /
 937                             sizeof(u32);
 938                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 939                 for (i = 0; i < data_size; i++)
 940                         *((u32 *)&sp_sb_data + i) =
 941                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 942                                            i * sizeof(u32));
 943
 944                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 945                         sp_sb_data.igu_sb_id,
 946                         sp_sb_data.igu_seg_id,
 947                         sp_sb_data.p_func.pf_id,
 948                         sp_sb_data.p_func.vnic_id,
 949                         sp_sb_data.p_func.vf_id,
 950                         sp_sb_data.p_func.vf_valid,
 951                         sp_sb_data.state);
 952         }
 953
 954         for_each_eth_queue(bp, i) {
 955                 struct bnx2x_fastpath *fp = &bp->fp[i];
 956                 int loop;
 957                 struct hc_status_block_data_e2 sb_data_e2;
 958                 struct hc_status_block_data_e1x sb_data_e1x;
 959                 struct hc_status_block_sm  *hc_sm_p =
 960                         CHIP_IS_E1x(bp) ?
 961                         sb_data_e1x.common.state_machine :
 962                         sb_data_e2.common.state_machine;
 963                 struct hc_index_data *hc_index_p =
 964                         CHIP_IS_E1x(bp) ?
 965                         sb_data_e1x.index_data :
 966                         sb_data_e2.index_data;
 967                 u8 data_size, cos;
 968                 u32 *sb_data_p;
 969                 struct bnx2x_fp_txdata txdata;
 970
 971                 if (!bp->fp)
 972                         break;
 973
 974                 if (!fp->rx_cons_sb)
 975                         continue;
 976
 977                 /* Rx */
 978                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 979                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 980                           fp->rx_comp_prod,
 981                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 982                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 983                           fp->rx_sge_prod, fp->last_max_sge,
 984                           le16_to_cpu(fp->fp_hc_idx));
 985
 986                 /* Tx */
 987                 for_each_cos_in_tx_queue(fp, cos)
 988                 {
 989                         if (!fp->txdata_ptr[cos])
 990                                 break;
 991
 992                         txdata = *fp->txdata_ptr[cos];
 993
 994                         if (!txdata.tx_cons_sb)
 995                                 continue;
 996
 997                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 998                                   i, txdata.tx_pkt_prod,
 999                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1000                                   txdata.tx_bd_cons,
1001                                   le16_to_cpu(*txdata.tx_cons_sb));
1002                 }
1003
1004                 loop = CHIP_IS_E1x(bp) ?
1005                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1006
1007                 /* host sb data */
1008
1009                 if (IS_FCOE_FP(fp))
1010                         continue;
1011
1012                 BNX2X_ERR("     run indexes (");
1013                 for (j = 0; j < HC_SB_MAX_SM; j++)
1014                         pr_cont("0x%x%s",
1015                                fp->sb_running_index[j],
1016                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1017
1018                 BNX2X_ERR("     indexes (");
1019                 for (j = 0; j < loop; j++)
1020                         pr_cont("0x%x%s",
1021                                fp->sb_index_values[j],
1022                                (j == loop - 1) ? ")" : " ");
1023
1024                 /* VF cannot access FW refelection for status block */
1025                 if (IS_VF(bp))
1026                         continue;
1027
1028                 /* fw sb data */
1029                 data_size = CHIP_IS_E1x(bp) ?
1030                         sizeof(struct hc_status_block_data_e1x) :
1031                         sizeof(struct hc_status_block_data_e2);
1032                 data_size /= sizeof(u32);
1033                 sb_data_p = CHIP_IS_E1x(bp) ?
1034                         (u32 *)&sb_data_e1x :
1035                         (u32 *)&sb_data_e2;
1036                 /* copy sb data in here */
1037                 for (j = 0; j < data_size; j++)
1038                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1039                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1040                                 j * sizeof(u32));
1041
1042                 if (!CHIP_IS_E1x(bp)) {
1043                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1044                                 sb_data_e2.common.p_func.pf_id,
1045                                 sb_data_e2.common.p_func.vf_id,
1046                                 sb_data_e2.common.p_func.vf_valid,
1047                                 sb_data_e2.common.p_func.vnic_id,
1048                                 sb_data_e2.common.same_igu_sb_1b,
1049                                 sb_data_e2.common.state);
1050                 } else {
1051                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1052                                 sb_data_e1x.common.p_func.pf_id,
1053                                 sb_data_e1x.common.p_func.vf_id,
1054                                 sb_data_e1x.common.p_func.vf_valid,
1055                                 sb_data_e1x.common.p_func.vnic_id,
1056                                 sb_data_e1x.common.same_igu_sb_1b,
1057                                 sb_data_e1x.common.state);
1058                 }
1059
1060                 /* SB_SMs data */
1061                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1062                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1063                                 j, hc_sm_p[j].__flags,
1064                                 hc_sm_p[j].igu_sb_id,
1065                                 hc_sm_p[j].igu_seg_id,
1066                                 hc_sm_p[j].time_to_expire,
1067                                 hc_sm_p[j].timer_value);
1068                 }
1069
1070                 /* Indices data */
1071                 for (j = 0; j < loop; j++) {
1072                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1073                                hc_index_p[j].flags,
1074                                hc_index_p[j].timeout);
1075                 }
1076         }
1077
1078 #ifdef BNX2X_STOP_ON_ERROR
1079         if (IS_PF(bp)) {
1080                 /* event queue */
1081                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1082                 for (i = 0; i < NUM_EQ_DESC; i++) {
1083                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1084
1085                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1086                                   i, bp->eq_ring[i].message.opcode,
1087                                   bp->eq_ring[i].message.error);
1088                         BNX2X_ERR("data: %x %x %x\n",
1089                                   data[0], data[1], data[2]);
1090                 }
1091         }
1092
1093         /* Rings */
1094         /* Rx */
1095         for_each_valid_rx_queue(bp, i) {
1096                 struct bnx2x_fastpath *fp = &bp->fp[i];
1097
1098                 if (!bp->fp)
1099                         break;
1100
1101                 if (!fp->rx_cons_sb)
1102                         continue;
1103
1104                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1106                 for (j = start; j != end; j = RX_BD(j + 1)) {
1107                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1109
1110                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1111                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1112                 }
1113
1114                 start = RX_SGE(fp->rx_sge_prod);
1115                 end = RX_SGE(fp->last_max_sge);
1116                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1117                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1119
1120                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1121                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1122                 }
1123
1124                 start = RCQ_BD(fp->rx_comp_cons - 10);
1125                 end = RCQ_BD(fp->rx_comp_cons + 503);
1126                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1127                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1128
1129                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1131                 }
1132         }
1133
1134         /* Tx */
1135         for_each_valid_tx_queue(bp, i) {
1136                 struct bnx2x_fastpath *fp = &bp->fp[i];
1137
1138                 if (!bp->fp)
1139                         break;
1140
1141                 for_each_cos_in_tx_queue(fp, cos) {
1142                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1143
1144                         if (!fp->txdata_ptr[cos])
1145                                 break;
1146
1147                         if (!txdata->tx_cons_sb)
1148                                 continue;
1149
1150                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1151                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1152                         for (j = start; j != end; j = TX_BD(j + 1)) {
1153                                 struct sw_tx_bd *sw_bd =
1154                                         &txdata->tx_buf_ring[j];
1155
1156                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1157                                           i, cos, j, sw_bd->skb,
1158                                           sw_bd->first_bd);
1159                         }
1160
1161                         start = TX_BD(txdata->tx_bd_cons - 10);
1162                         end = TX_BD(txdata->tx_bd_cons + 254);
1163                         for (j = start; j != end; j = TX_BD(j + 1)) {
1164                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1165
1166                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1167                                           i, cos, j, tx_bd[0], tx_bd[1],
1168                                           tx_bd[2], tx_bd[3]);
1169                         }
1170                 }
1171         }
1172 #endif
1173         if (IS_PF(bp)) {
1174                 bnx2x_fw_dump(bp);
1175                 bnx2x_mc_assert(bp);
1176         }
1177         BNX2X_ERR("end crash dump -----------------\n");
1178 }
1179
1180 /*
1181  * FLR Support for E2
1182  *
1183  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1184  * initialization.
1185  */
1186 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1187 #define FLR_WAIT_INTERVAL       50      /* usec */
1188 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1189
1190 struct pbf_pN_buf_regs {
1191         int pN;
1192         u32 init_crd;
1193         u32 crd;
1194         u32 crd_freed;
1195 };
1196
1197 struct pbf_pN_cmd_regs {
1198         int pN;
1199         u32 lines_occup;
1200         u32 lines_freed;
1201 };
1202
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1204                                      struct pbf_pN_buf_regs *regs,
1205                                      u32 poll_count)
1206 {
1207         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1208         u32 cur_cnt = poll_count;
1209
1210         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1211         crd = crd_start = REG_RD(bp, regs->crd);
1212         init_crd = REG_RD(bp, regs->init_crd);
1213
1214         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1215         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1216         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1217
1218         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1219                (init_crd - crd_start))) {
1220                 if (cur_cnt--) {
1221                         udelay(FLR_WAIT_INTERVAL);
1222                         crd = REG_RD(bp, regs->crd);
1223                         crd_freed = REG_RD(bp, regs->crd_freed);
1224                 } else {
1225                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1226                            regs->pN);
1227                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1228                            regs->pN, crd);
1229                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1230                            regs->pN, crd_freed);
1231                         break;
1232                 }
1233         }
1234         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1235            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1236 }
1237
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1239                                      struct pbf_pN_cmd_regs *regs,
1240                                      u32 poll_count)
1241 {
1242         u32 occup, to_free, freed, freed_start;
1243         u32 cur_cnt = poll_count;
1244
1245         occup = to_free = REG_RD(bp, regs->lines_occup);
1246         freed = freed_start = REG_RD(bp, regs->lines_freed);
1247
1248         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1249         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1250
1251         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1252                 if (cur_cnt--) {
1253                         udelay(FLR_WAIT_INTERVAL);
1254                         occup = REG_RD(bp, regs->lines_occup);
1255                         freed = REG_RD(bp, regs->lines_freed);
1256                 } else {
1257                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1258                            regs->pN);
1259                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1260                            regs->pN, occup);
1261                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1262                            regs->pN, freed);
1263                         break;
1264                 }
1265         }
1266         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1267            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1268 }
1269
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1271                                     u32 expected, u32 poll_count)
1272 {
1273         u32 cur_cnt = poll_count;
1274         u32 val;
1275
1276         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1277                 udelay(FLR_WAIT_INTERVAL);
1278
1279         return val;
1280 }
1281
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1283                                     char *msg, u32 poll_cnt)
1284 {
1285         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1286         if (val != 0) {
1287                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1288                 return 1;
1289         }
1290         return 0;
1291 }
1292
1293 /* Common routines with VF FLR cleanup */
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1295 {
1296         /* adjust polling timeout */
1297         if (CHIP_REV_IS_EMUL(bp))
1298                 return FLR_POLL_CNT * 2000;
1299
1300         if (CHIP_REV_IS_FPGA(bp))
1301                 return FLR_POLL_CNT * 120;
1302
1303         return FLR_POLL_CNT;
1304 }
1305
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1307 {
1308         struct pbf_pN_cmd_regs cmd_regs[] = {
1309                 {0, (CHIP_IS_E3B0(bp)) ?
1310                         PBF_REG_TQ_OCCUPANCY_Q0 :
1311                         PBF_REG_P0_TQ_OCCUPANCY,
1312                     (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1314                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1315                 {1, (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_OCCUPANCY_Q1 :
1317                         PBF_REG_P1_TQ_OCCUPANCY,
1318                     (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1320                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1321                 {4, (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1323                         PBF_REG_P4_TQ_OCCUPANCY,
1324                     (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1326                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1327         };
1328
1329         struct pbf_pN_buf_regs buf_regs[] = {
1330                 {0, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_INIT_CRD_Q0 :
1332                         PBF_REG_P0_INIT_CRD ,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_CREDIT_Q0 :
1335                         PBF_REG_P0_CREDIT,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1338                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1339                 {1, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q1 :
1341                         PBF_REG_P1_INIT_CRD,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q1 :
1344                         PBF_REG_P1_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1347                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1348                 {4, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_LB_Q :
1350                         PBF_REG_P4_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_LB_Q :
1353                         PBF_REG_P4_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1356                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1357         };
1358
1359         int i;
1360
1361         /* Verify the command queues are flushed P0, P1, P4 */
1362         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1363                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1364
1365         /* Verify the transmission buffers are flushed P0, P1, P4 */
1366         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1367                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1368 }
1369
1370 #define OP_GEN_PARAM(param) \
1371         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1372
1373 #define OP_GEN_TYPE(type) \
1374         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1375
1376 #define OP_GEN_AGG_VECT(index) \
1377         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1378
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1380 {
1381         u32 op_gen_command = 0;
1382         u32 comp_addr = BAR_CSTRORM_INTMEM +
1383                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1384         int ret = 0;
1385
1386         if (REG_RD(bp, comp_addr)) {
1387                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1388                 return 1;
1389         }
1390
1391         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1392         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1393         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1394         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1395
1396         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1397         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1398
1399         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1400                 BNX2X_ERR("FW final cleanup did not succeed\n");
1401                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1402                    (REG_RD(bp, comp_addr)));
1403                 bnx2x_panic();
1404                 return 1;
1405         }
1406         /* Zero completion for next FLR */
1407         REG_WR(bp, comp_addr, 0);
1408
1409         return ret;
1410 }
1411
1412 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1413 {
1414         u16 status;
1415
1416         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1417         return status & PCI_EXP_DEVSTA_TRPND;
1418 }
1419
1420 /* PF FLR specific routines
1421 */
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1423 {
1424         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1427                         "CFC PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430
1431         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         DORQ_REG_PF_USAGE_CNT,
1434                         "DQ PF usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437
1438         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1439         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1441                         "QM PF usage counter timed out",
1442                         poll_cnt))
1443                 return 1;
1444
1445         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1446         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1448                         "Timers VNIC usage counter timed out",
1449                         poll_cnt))
1450                 return 1;
1451         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1453                         "Timers NUM_SCANS usage counter timed out",
1454                         poll_cnt))
1455                 return 1;
1456
1457         /* Wait DMAE PF usage counter to zero */
1458         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1460                         "DMAE command register timed out",
1461                         poll_cnt))
1462                 return 1;
1463
1464         return 0;
1465 }
1466
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1468 {
1469         u32 val;
1470
1471         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1472         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1473
1474         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1475         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1478         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1485
1486         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1487         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1494            val);
1495 }
1496
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1498 {
1499         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1500
1501         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1502
1503         /* Re-enable PF target read access */
1504         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1505
1506         /* Poll HW usage counters */
1507         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1508         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1509                 return -EBUSY;
1510
1511         /* Zero the igu 'trailing edge' and 'leading edge' */
1512
1513         /* Send the FW cleanup command */
1514         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1515                 return -EBUSY;
1516
1517         /* ATC cleanup */
1518
1519         /* Verify TX hw is flushed */
1520         bnx2x_tx_hw_flushed(bp, poll_cnt);
1521
1522         /* Wait 100ms (not adjusted according to platform) */
1523         msleep(100);
1524
1525         /* Verify no pending pci transactions */
1526         if (bnx2x_is_pcie_pending(bp->pdev))
1527                 BNX2X_ERR("PCIE Transactions still pending\n");
1528
1529         /* Debug */
1530         bnx2x_hw_enable_status(bp);
1531
1532         /*
1533          * Master enable - Due to WB DMAE writes performed before this
1534          * register is re-initialized as part of the regular function init
1535          */
1536         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1537
1538         return 0;
1539 }
1540
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1542 {
1543         int port = BP_PORT(bp);
1544         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1545         u32 val = REG_RD(bp, addr);
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         if (msix) {
1551                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1552                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1553                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1554                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1555                 if (single_msix)
1556                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1557         } else if (msi) {
1558                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1559                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1560                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1562         } else {
1563                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1564                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1565                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567
1568                 if (!CHIP_IS_E1(bp)) {
1569                         DP(NETIF_MSG_IFUP,
1570                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1571
1572                         REG_WR(bp, addr, val);
1573
1574                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1575                 }
1576         }
1577
1578         if (CHIP_IS_E1(bp))
1579                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1580
1581         DP(NETIF_MSG_IFUP,
1582            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1583            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1584
1585         REG_WR(bp, addr, val);
1586         /*
1587          * Ensure that HC_CONFIG is written before leading/trailing edge config
1588          */
1589         mmiowb();
1590         barrier();
1591
1592         if (!CHIP_IS_E1(bp)) {
1593                 /* init leading/trailing edge */
1594                 if (IS_MF(bp)) {
1595                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1596                         if (bp->port.pmf)
1597                                 /* enable nig and gpio3 attention */
1598                                 val |= 0x1100;
1599                 } else
1600                         val = 0xffff;
1601
1602                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1603                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1604         }
1605
1606         /* Make sure that interrupts are indeed enabled from here on */
1607         mmiowb();
1608 }
1609
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1611 {
1612         u32 val;
1613         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1614         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1615         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1616
1617         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1618
1619         if (msix) {
1620                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1621                          IGU_PF_CONF_SINGLE_ISR_EN);
1622                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1623                         IGU_PF_CONF_ATTN_BIT_EN);
1624
1625                 if (single_msix)
1626                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1627         } else if (msi) {
1628                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1629                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1630                         IGU_PF_CONF_ATTN_BIT_EN |
1631                         IGU_PF_CONF_SINGLE_ISR_EN);
1632         } else {
1633                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1634                 val |= (IGU_PF_CONF_INT_LINE_EN |
1635                         IGU_PF_CONF_ATTN_BIT_EN |
1636                         IGU_PF_CONF_SINGLE_ISR_EN);
1637         }
1638
1639         /* Clean previous status - need to configure igu prior to ack*/
1640         if ((!msix) || single_msix) {
1641                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1642                 bnx2x_ack_int(bp);
1643         }
1644
1645         val |= IGU_PF_CONF_FUNC_EN;
1646
1647         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1648            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1649
1650         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651
1652         if (val & IGU_PF_CONF_INT_LINE_EN)
1653                 pci_intx(bp->pdev, true);
1654
1655         barrier();
1656
1657         /* init leading/trailing edge */
1658         if (IS_MF(bp)) {
1659                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1660                 if (bp->port.pmf)
1661                         /* enable nig and gpio3 attention */
1662                         val |= 0x1100;
1663         } else
1664                 val = 0xffff;
1665
1666         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1667         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1668
1669         /* Make sure that interrupts are indeed enabled from here on */
1670         mmiowb();
1671 }
1672
1673 void bnx2x_int_enable(struct bnx2x *bp)
1674 {
1675         if (bp->common.int_block == INT_BLOCK_HC)
1676                 bnx2x_hc_int_enable(bp);
1677         else
1678                 bnx2x_igu_int_enable(bp);
1679 }
1680
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1682 {
1683         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1684         int i, offset;
1685
1686         if (disable_hw)
1687                 /* prevent the HW from sending interrupts */
1688                 bnx2x_int_disable(bp);
1689
1690         /* make sure all ISRs are done */
1691         if (msix) {
1692                 synchronize_irq(bp->msix_table[0].vector);
1693                 offset = 1;
1694                 if (CNIC_SUPPORT(bp))
1695                         offset++;
1696                 for_each_eth_queue(bp, i)
1697                         synchronize_irq(bp->msix_table[offset++].vector);
1698         } else
1699                 synchronize_irq(bp->pdev->irq);
1700
1701         /* make sure sp_task is not running */
1702         cancel_delayed_work(&bp->sp_task);
1703         cancel_delayed_work(&bp->period_task);
1704         flush_workqueue(bnx2x_wq);
1705 }
1706
1707 /* fast path */
1708
1709 /*
1710  * General service functions
1711  */
1712
1713 /* Return true if succeeded to acquire the lock */
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1715 {
1716         u32 lock_status;
1717         u32 resource_bit = (1 << resource);
1718         int func = BP_FUNC(bp);
1719         u32 hw_lock_control_reg;
1720
1721         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1722            "Trying to take a lock on resource %d\n", resource);
1723
1724         /* Validating that the resource is within range */
1725         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1726                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1728                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1729                 return false;
1730         }
1731
1732         if (func <= 5)
1733                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1734         else
1735                 hw_lock_control_reg =
1736                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1737
1738         /* Try to acquire the lock */
1739         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1740         lock_status = REG_RD(bp, hw_lock_control_reg);
1741         if (lock_status & resource_bit)
1742                 return true;
1743
1744         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1745            "Failed to get a lock on resource %d\n", resource);
1746         return false;
1747 }
1748
1749 /**
1750  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1751  *
1752  * @bp: driver handle
1753  *
1754  * Returns the recovery leader resource id according to the engine this function
1755  * belongs to. Currently only only 2 engines is supported.
1756  */
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1758 {
1759         if (BP_PATH(bp))
1760                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1761         else
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1763 }
1764
1765 /**
1766  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1767  *
1768  * @bp: driver handle
1769  *
1770  * Tries to acquire a leader lock for current engine.
1771  */
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1773 {
1774         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1775 }
1776
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1778
1779 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1781 {
1782         /* Set the interrupt occurred bit for the sp-task to recognize it
1783          * must ack the interrupt and transition according to the IGU
1784          * state machine.
1785          */
1786         atomic_set(&bp->interrupt_occurred, 1);
1787
1788         /* The sp_task must execute only after this bit
1789          * is set, otherwise we will get out of sync and miss all
1790          * further interrupts. Hence, the barrier.
1791          */
1792         smp_wmb();
1793
1794         /* schedule sp_task to workqueue */
1795         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1796 }
1797
1798 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1799 {
1800         struct bnx2x *bp = fp->bp;
1801         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1803         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1804         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1805
1806         DP(BNX2X_MSG_SP,
1807            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1808            fp->index, cid, command, bp->state,
1809            rr_cqe->ramrod_cqe.ramrod_type);
1810
1811         /* If cid is within VF range, replace the slowpath object with the
1812          * one corresponding to this VF
1813          */
1814         if (cid >= BNX2X_FIRST_VF_CID  &&
1815             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1816                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1817
1818         switch (command) {
1819         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1820                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1821                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1822                 break;
1823
1824         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1825                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1826                 drv_cmd = BNX2X_Q_CMD_SETUP;
1827                 break;
1828
1829         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1830                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1831                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1832                 break;
1833
1834         case (RAMROD_CMD_ID_ETH_HALT):
1835                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1836                 drv_cmd = BNX2X_Q_CMD_HALT;
1837                 break;
1838
1839         case (RAMROD_CMD_ID_ETH_TERMINATE):
1840                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1841                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1842                 break;
1843
1844         case (RAMROD_CMD_ID_ETH_EMPTY):
1845                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1846                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1847                 break;
1848
1849         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1850                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1851                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1852                 break;
1853
1854         default:
1855                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1856                           command, fp->index);
1857                 return;
1858         }
1859
1860         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1861             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1862                 /* q_obj->complete_cmd() failure means that this was
1863                  * an unexpected completion.
1864                  *
1865                  * In this case we don't want to increase the bp->spq_left
1866                  * because apparently we haven't sent this command the first
1867                  * place.
1868                  */
1869 #ifdef BNX2X_STOP_ON_ERROR
1870                 bnx2x_panic();
1871 #else
1872                 return;
1873 #endif
1874
1875         smp_mb__before_atomic();
1876         atomic_inc(&bp->cq_spq_left);
1877         /* push the change in bp->spq_left and towards the memory */
1878         smp_mb__after_atomic();
1879
1880         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1881
1882         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1883             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1884                 /* if Q update ramrod is completed for last Q in AFEX vif set
1885                  * flow, then ACK MCP at the end
1886                  *
1887                  * mark pending ACK to MCP bit.
1888                  * prevent case that both bits are cleared.
1889                  * At the end of load/unload driver checks that
1890                  * sp_state is cleared, and this order prevents
1891                  * races
1892                  */
1893                 smp_mb__before_atomic();
1894                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1895                 wmb();
1896                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1897                 smp_mb__after_atomic();
1898
1899                 /* schedule the sp task as mcp ack is required */
1900                 bnx2x_schedule_sp_task(bp);
1901         }
1902
1903         return;
1904 }
1905
1906 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1907 {
1908         struct bnx2x *bp = netdev_priv(dev_instance);
1909         u16 status = bnx2x_ack_int(bp);
1910         u16 mask;
1911         int i;
1912         u8 cos;
1913
1914         /* Return here if interrupt is shared and it's not for us */
1915         if (unlikely(status == 0)) {
1916                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1917                 return IRQ_NONE;
1918         }
1919         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1920
1921 #ifdef BNX2X_STOP_ON_ERROR
1922         if (unlikely(bp->panic))
1923                 return IRQ_HANDLED;
1924 #endif
1925
1926         for_each_eth_queue(bp, i) {
1927                 struct bnx2x_fastpath *fp = &bp->fp[i];
1928
1929                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1930                 if (status & mask) {
1931                         /* Handle Rx or Tx according to SB id */
1932                         for_each_cos_in_tx_queue(fp, cos)
1933                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1934                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1935                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1936                         status &= ~mask;
1937                 }
1938         }
1939
1940         if (CNIC_SUPPORT(bp)) {
1941                 mask = 0x2;
1942                 if (status & (mask | 0x1)) {
1943                         struct cnic_ops *c_ops = NULL;
1944
1945                         rcu_read_lock();
1946                         c_ops = rcu_dereference(bp->cnic_ops);
1947                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1948                                       CNIC_DRV_STATE_HANDLES_IRQ))
1949                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1950                         rcu_read_unlock();
1951
1952                         status &= ~mask;
1953                 }
1954         }
1955
1956         if (unlikely(status & 0x1)) {
1957
1958                 /* schedule sp task to perform default status block work, ack
1959                  * attentions and enable interrupts.
1960                  */
1961                 bnx2x_schedule_sp_task(bp);
1962
1963                 status &= ~0x1;
1964                 if (!status)
1965                         return IRQ_HANDLED;
1966         }
1967
1968         if (unlikely(status))
1969                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1970                    status);
1971
1972         return IRQ_HANDLED;
1973 }
1974
1975 /* Link */
1976
1977 /*
1978  * General service functions
1979  */
1980
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1982 {
1983         u32 lock_status;
1984         u32 resource_bit = (1 << resource);
1985         int func = BP_FUNC(bp);
1986         u32 hw_lock_control_reg;
1987         int cnt;
1988
1989         /* Validating that the resource is within range */
1990         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1991                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1992                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1993                 return -EINVAL;
1994         }
1995
1996         if (func <= 5) {
1997                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1998         } else {
1999                 hw_lock_control_reg =
2000                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2001         }
2002
2003         /* Validating that the resource is not already taken */
2004         lock_status = REG_RD(bp, hw_lock_control_reg);
2005         if (lock_status & resource_bit) {
2006                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2007                    lock_status, resource_bit);
2008                 return -EEXIST;
2009         }
2010
2011         /* Try for 5 second every 5ms */
2012         for (cnt = 0; cnt < 1000; cnt++) {
2013                 /* Try to acquire the lock */
2014                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2015                 lock_status = REG_RD(bp, hw_lock_control_reg);
2016                 if (lock_status & resource_bit)
2017                         return 0;
2018
2019                 usleep_range(5000, 10000);
2020         }
2021         BNX2X_ERR("Timeout\n");
2022         return -EAGAIN;
2023 }
2024
2025 int bnx2x_release_leader_lock(struct bnx2x *bp)
2026 {
2027         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2028 }
2029
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2031 {
2032         u32 lock_status;
2033         u32 resource_bit = (1 << resource);
2034         int func = BP_FUNC(bp);
2035         u32 hw_lock_control_reg;
2036
2037         /* Validating that the resource is within range */
2038         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2039                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2040                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2041                 return -EINVAL;
2042         }
2043
2044         if (func <= 5) {
2045                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2046         } else {
2047                 hw_lock_control_reg =
2048                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2049         }
2050
2051         /* Validating that the resource is currently taken */
2052         lock_status = REG_RD(bp, hw_lock_control_reg);
2053         if (!(lock_status & resource_bit)) {
2054                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2055                           lock_status, resource_bit);
2056                 return -EFAULT;
2057         }
2058
2059         REG_WR(bp, hw_lock_control_reg, resource_bit);
2060         return 0;
2061 }
2062
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2064 {
2065         /* The GPIO should be swapped if swap register is set and active */
2066         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2067                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2068         int gpio_shift = gpio_num +
2069                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2070         u32 gpio_mask = (1 << gpio_shift);
2071         u32 gpio_reg;
2072         int value;
2073
2074         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2075                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2076                 return -EINVAL;
2077         }
2078
2079         /* read GPIO value */
2080         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2081
2082         /* get the requested pin value */
2083         if ((gpio_reg & gpio_mask) == gpio_mask)
2084                 value = 1;
2085         else
2086                 value = 0;
2087
2088         return value;
2089 }
2090
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2092 {
2093         /* The GPIO should be swapped if swap register is set and active */
2094         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2095                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2096         int gpio_shift = gpio_num +
2097                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2098         u32 gpio_mask = (1 << gpio_shift);
2099         u32 gpio_reg;
2100
2101         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2102                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2103                 return -EINVAL;
2104         }
2105
2106         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107         /* read GPIO and mask except the float bits */
2108         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2109
2110         switch (mode) {
2111         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2112                 DP(NETIF_MSG_LINK,
2113                    "Set GPIO %d (shift %d) -> output low\n",
2114                    gpio_num, gpio_shift);
2115                 /* clear FLOAT and set CLR */
2116                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2117                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2118                 break;
2119
2120         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output high\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set SET */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> input\n",
2132                    gpio_num, gpio_shift);
2133                 /* set FLOAT */
2134                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 break;
2136
2137         default:
2138                 break;
2139         }
2140
2141         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2142         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143
2144         return 0;
2145 }
2146
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2148 {
2149         u32 gpio_reg = 0;
2150         int rc = 0;
2151
2152         /* Any port swapping should be handled by caller. */
2153
2154         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2155         /* read GPIO and mask except the float bits */
2156         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2160
2161         switch (mode) {
2162         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2164                 /* set CLR */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2166                 break;
2167
2168         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2169                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2170                 /* set SET */
2171                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2172                 break;
2173
2174         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2175                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2176                 /* set FLOAT */
2177                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2178                 break;
2179
2180         default:
2181                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2182                 rc = -EINVAL;
2183                 break;
2184         }
2185
2186         if (rc == 0)
2187                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2188
2189         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2190
2191         return rc;
2192 }
2193
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2195 {
2196         /* The GPIO should be swapped if swap register is set and active */
2197         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2198                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2199         int gpio_shift = gpio_num +
2200                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2201         u32 gpio_mask = (1 << gpio_shift);
2202         u32 gpio_reg;
2203
2204         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2205                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2206                 return -EINVAL;
2207         }
2208
2209         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2210         /* read GPIO int */
2211         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2212
2213         switch (mode) {
2214         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2215                 DP(NETIF_MSG_LINK,
2216                    "Clear GPIO INT %d (shift %d) -> output low\n",
2217                    gpio_num, gpio_shift);
2218                 /* clear SET and set CLR */
2219                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2220                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2221                 break;
2222
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2224                 DP(NETIF_MSG_LINK,
2225                    "Set GPIO INT %d (shift %d) -> output high\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear CLR and set SET */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2230                 break;
2231
2232         default:
2233                 break;
2234         }
2235
2236         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2237         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2238
2239         return 0;
2240 }
2241
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2243 {
2244         u32 spio_reg;
2245
2246         /* Only 2 SPIOs are configurable */
2247         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2248                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2249                 return -EINVAL;
2250         }
2251
2252         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2253         /* read SPIO and mask except the float bits */
2254         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2255
2256         switch (mode) {
2257         case MISC_SPIO_OUTPUT_LOW:
2258                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2259                 /* clear FLOAT and set CLR */
2260                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2261                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2262                 break;
2263
2264         case MISC_SPIO_OUTPUT_HIGH:
2265                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2266                 /* clear FLOAT and set SET */
2267                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2269                 break;
2270
2271         case MISC_SPIO_INPUT_HI_Z:
2272                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2273                 /* set FLOAT */
2274                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2275                 break;
2276
2277         default:
2278                 break;
2279         }
2280
2281         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2282         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2283
2284         return 0;
2285 }
2286
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2288 {
2289         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2290         switch (bp->link_vars.ieee_fc &
2291                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2292         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2293                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2294                                                    ADVERTISED_Pause);
2295                 break;
2296
2297         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2298                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2299                                                   ADVERTISED_Pause);
2300                 break;
2301
2302         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2303                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2304                 break;
2305
2306         default:
2307                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2308                                                    ADVERTISED_Pause);
2309                 break;
2310         }
2311 }
2312
2313 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2314 {
2315         /* Initialize link parameters structure variables
2316          * It is recommended to turn off RX FC for jumbo frames
2317          *  for better performance
2318          */
2319         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2320                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2321         else
2322                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2323 }
2324
2325 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2326 {
2327         u32 pause_enabled = 0;
2328
2329         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2330                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2331                         pause_enabled = 1;
2332
2333                 REG_WR(bp, BAR_USTRORM_INTMEM +
2334                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2335                        pause_enabled);
2336         }
2337
2338         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2339            pause_enabled ? "enabled" : "disabled");
2340 }
2341
2342 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2343 {
2344         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2345         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2346
2347         if (!BP_NOMCP(bp)) {
2348                 bnx2x_set_requested_fc(bp);
2349                 bnx2x_acquire_phy_lock(bp);
2350
2351                 if (load_mode == LOAD_DIAG) {
2352                         struct link_params *lp = &bp->link_params;
2353                         lp->loopback_mode = LOOPBACK_XGXS;
2354                         /* do PHY loopback at 10G speed, if possible */
2355                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2356                                 if (lp->speed_cap_mask[cfx_idx] &
2357                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2358                                         lp->req_line_speed[cfx_idx] =
2359                                         SPEED_10000;
2360                                 else
2361                                         lp->req_line_speed[cfx_idx] =
2362                                         SPEED_1000;
2363                         }
2364                 }
2365
2366                 if (load_mode == LOAD_LOOPBACK_EXT) {
2367                         struct link_params *lp = &bp->link_params;
2368                         lp->loopback_mode = LOOPBACK_EXT;
2369                 }
2370
2371                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2372
2373                 bnx2x_release_phy_lock(bp);
2374
2375                 bnx2x_init_dropless_fc(bp);
2376
2377                 bnx2x_calc_fc_adv(bp);
2378
2379                 if (bp->link_vars.link_up) {
2380                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2381                         bnx2x_link_report(bp);
2382                 }
2383                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2384                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2385                 return rc;
2386         }
2387         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2388         return -EINVAL;
2389 }
2390
2391 void bnx2x_link_set(struct bnx2x *bp)
2392 {
2393         if (!BP_NOMCP(bp)) {
2394                 bnx2x_acquire_phy_lock(bp);
2395                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2396                 bnx2x_release_phy_lock(bp);
2397
2398                 bnx2x_init_dropless_fc(bp);
2399
2400                 bnx2x_calc_fc_adv(bp);
2401         } else
2402                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2403 }
2404
2405 static void bnx2x__link_reset(struct bnx2x *bp)
2406 {
2407         if (!BP_NOMCP(bp)) {
2408                 bnx2x_acquire_phy_lock(bp);
2409                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2410                 bnx2x_release_phy_lock(bp);
2411         } else
2412                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2413 }
2414
2415 void bnx2x_force_link_reset(struct bnx2x *bp)
2416 {
2417         bnx2x_acquire_phy_lock(bp);
2418         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2419         bnx2x_release_phy_lock(bp);
2420 }
2421
2422 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2423 {
2424         u8 rc = 0;
2425
2426         if (!BP_NOMCP(bp)) {
2427                 bnx2x_acquire_phy_lock(bp);
2428                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2429                                      is_serdes);
2430                 bnx2x_release_phy_lock(bp);
2431         } else
2432                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2433
2434         return rc;
2435 }
2436
2437 /* Calculates the sum of vn_min_rates.
2438    It's needed for further normalizing of the min_rates.
2439    Returns:
2440      sum of vn_min_rates.
2441        or
2442      0 - if all the min_rates are 0.
2443      In the later case fairness algorithm should be deactivated.
2444      If not all min_rates are zero then those that are zeroes will be set to 1.
2445  */
2446 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2447                                       struct cmng_init_input *input)
2448 {
2449         int all_zero = 1;
2450         int vn;
2451
2452         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2453                 u32 vn_cfg = bp->mf_config[vn];
2454                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2455                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2456
2457                 /* Skip hidden vns */
2458                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2459                         vn_min_rate = 0;
2460                 /* If min rate is zero - set it to 1 */
2461                 else if (!vn_min_rate)
2462                         vn_min_rate = DEF_MIN_RATE;
2463                 else
2464                         all_zero = 0;
2465
2466                 input->vnic_min_rate[vn] = vn_min_rate;
2467         }
2468
2469         /* if ETS or all min rates are zeros - disable fairness */
2470         if (BNX2X_IS_ETS_ENABLED(bp)) {
2471                 input->flags.cmng_enables &=
2472                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2473                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2474         } else if (all_zero) {
2475                 input->flags.cmng_enables &=
2476                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2477                 DP(NETIF_MSG_IFUP,
2478                    "All MIN values are zeroes fairness will be disabled\n");
2479         } else
2480                 input->flags.cmng_enables |=
2481                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 }
2483
2484 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2485                                     struct cmng_init_input *input)
2486 {
2487         u16 vn_max_rate;
2488         u32 vn_cfg = bp->mf_config[vn];
2489
2490         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2491                 vn_max_rate = 0;
2492         else {
2493                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2494
2495                 if (IS_MF_SI(bp)) {
2496                         /* maxCfg in percents of linkspeed */
2497                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2498                 } else /* SD modes */
2499                         /* maxCfg is absolute in 100Mb units */
2500                         vn_max_rate = maxCfg * 100;
2501         }
2502
2503         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2504
2505         input->vnic_max_rate[vn] = vn_max_rate;
2506 }
2507
2508 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2509 {
2510         if (CHIP_REV_IS_SLOW(bp))
2511                 return CMNG_FNS_NONE;
2512         if (IS_MF(bp))
2513                 return CMNG_FNS_MINMAX;
2514
2515         return CMNG_FNS_NONE;
2516 }
2517
2518 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2519 {
2520         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2521
2522         if (BP_NOMCP(bp))
2523                 return; /* what should be the default value in this case */
2524
2525         /* For 2 port configuration the absolute function number formula
2526          * is:
2527          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2528          *
2529          *      and there are 4 functions per port
2530          *
2531          * For 4 port configuration it is
2532          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2533          *
2534          *      and there are 2 functions per port
2535          */
2536         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2537                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2538
2539                 if (func >= E1H_FUNC_MAX)
2540                         break;
2541
2542                 bp->mf_config[vn] =
2543                         MF_CFG_RD(bp, func_mf_config[func].config);
2544         }
2545         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2546                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2547                 bp->flags |= MF_FUNC_DIS;
2548         } else {
2549                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2550                 bp->flags &= ~MF_FUNC_DIS;
2551         }
2552 }
2553
2554 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2555 {
2556         struct cmng_init_input input;
2557         memset(&input, 0, sizeof(struct cmng_init_input));
2558
2559         input.port_rate = bp->link_vars.line_speed;
2560
2561         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2562                 int vn;
2563
2564                 /* read mf conf from shmem */
2565                 if (read_cfg)
2566                         bnx2x_read_mf_cfg(bp);
2567
2568                 /* vn_weight_sum and enable fairness if not 0 */
2569                 bnx2x_calc_vn_min(bp, &input);
2570
2571                 /* calculate and set min-max rate for each vn */
2572                 if (bp->port.pmf)
2573                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2574                                 bnx2x_calc_vn_max(bp, vn, &input);
2575
2576                 /* always enable rate shaping and fairness */
2577                 input.flags.cmng_enables |=
2578                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2579
2580                 bnx2x_init_cmng(&input, &bp->cmng);
2581                 return;
2582         }
2583
2584         /* rate shaping and fairness are disabled */
2585         DP(NETIF_MSG_IFUP,
2586            "rate shaping and fairness are disabled\n");
2587 }
2588
2589 static void storm_memset_cmng(struct bnx2x *bp,
2590                               struct cmng_init *cmng,
2591                               u8 port)
2592 {
2593         int vn;
2594         size_t size = sizeof(struct cmng_struct_per_port);
2595
2596         u32 addr = BAR_XSTRORM_INTMEM +
2597                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2598
2599         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2600
2601         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2602                 int func = func_by_vn(bp, vn);
2603
2604                 addr = BAR_XSTRORM_INTMEM +
2605                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2606                 size = sizeof(struct rate_shaping_vars_per_vn);
2607                 __storm_memset_struct(bp, addr, size,
2608                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2609
2610                 addr = BAR_XSTRORM_INTMEM +
2611                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2612                 size = sizeof(struct fairness_vars_per_vn);
2613                 __storm_memset_struct(bp, addr, size,
2614                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2615         }
2616 }
2617
2618 /* init cmng mode in HW according to local configuration */
2619 void bnx2x_set_local_cmng(struct bnx2x *bp)
2620 {
2621         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2622
2623         if (cmng_fns != CMNG_FNS_NONE) {
2624                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2625                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2626         } else {
2627                 /* rate shaping and fairness are disabled */
2628                 DP(NETIF_MSG_IFUP,
2629                    "single function mode without fairness\n");
2630         }
2631 }
2632
2633 /* This function is called upon link interrupt */
2634 static void bnx2x_link_attn(struct bnx2x *bp)
2635 {
2636         /* Make sure that we are synced with the current statistics */
2637         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2638
2639         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2640
2641         bnx2x_init_dropless_fc(bp);
2642
2643         if (bp->link_vars.link_up) {
2644
2645                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2646                         struct host_port_stats *pstats;
2647
2648                         pstats = bnx2x_sp(bp, port_stats);
2649                         /* reset old mac stats */
2650                         memset(&(pstats->mac_stx[0]), 0,
2651                                sizeof(struct mac_stx));
2652                 }
2653                 if (bp->state == BNX2X_STATE_OPEN)
2654                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2655         }
2656
2657         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2658                 bnx2x_set_local_cmng(bp);
2659
2660         __bnx2x_link_report(bp);
2661
2662         if (IS_MF(bp))
2663                 bnx2x_link_sync_notify(bp);
2664 }
2665
2666 void bnx2x__link_status_update(struct bnx2x *bp)
2667 {
2668         if (bp->state != BNX2X_STATE_OPEN)
2669                 return;
2670
2671         /* read updated dcb configuration */
2672         if (IS_PF(bp)) {
2673                 bnx2x_dcbx_pmf_update(bp);
2674                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2675                 if (bp->link_vars.link_up)
2676                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2677                 else
2678                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2679                         /* indicate link status */
2680                 bnx2x_link_report(bp);
2681
2682         } else { /* VF */
2683                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2684                                           SUPPORTED_10baseT_Full |
2685                                           SUPPORTED_100baseT_Half |
2686                                           SUPPORTED_100baseT_Full |
2687                                           SUPPORTED_1000baseT_Full |
2688                                           SUPPORTED_2500baseX_Full |
2689                                           SUPPORTED_10000baseT_Full |
2690                                           SUPPORTED_TP |
2691                                           SUPPORTED_FIBRE |
2692                                           SUPPORTED_Autoneg |
2693                                           SUPPORTED_Pause |
2694                                           SUPPORTED_Asym_Pause);
2695                 bp->port.advertising[0] = bp->port.supported[0];
2696
2697                 bp->link_params.bp = bp;
2698                 bp->link_params.port = BP_PORT(bp);
2699                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2700                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2701                 bp->link_params.req_line_speed[0] = SPEED_10000;
2702                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2703                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2704                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2705                 bp->link_vars.line_speed = SPEED_10000;
2706                 bp->link_vars.link_status =
2707                         (LINK_STATUS_LINK_UP |
2708                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2709                 bp->link_vars.link_up = 1;
2710                 bp->link_vars.duplex = DUPLEX_FULL;
2711                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2712                 __bnx2x_link_report(bp);
2713
2714                 bnx2x_sample_bulletin(bp);
2715
2716                 /* if bulletin board did not have an update for link status
2717                  * __bnx2x_link_report will report current status
2718                  * but it will NOT duplicate report in case of already reported
2719                  * during sampling bulletin board.
2720                  */
2721                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2722         }
2723 }
2724
2725 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2726                                   u16 vlan_val, u8 allowed_prio)
2727 {
2728         struct bnx2x_func_state_params func_params = {NULL};
2729         struct bnx2x_func_afex_update_params *f_update_params =
2730                 &func_params.params.afex_update;
2731
2732         func_params.f_obj = &bp->func_obj;
2733         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2734
2735         /* no need to wait for RAMROD completion, so don't
2736          * set RAMROD_COMP_WAIT flag
2737          */
2738
2739         f_update_params->vif_id = vifid;
2740         f_update_params->afex_default_vlan = vlan_val;
2741         f_update_params->allowed_priorities = allowed_prio;
2742
2743         /* if ramrod can not be sent, response to MCP immediately */
2744         if (bnx2x_func_state_change(bp, &func_params) < 0)
2745                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2746
2747         return 0;
2748 }
2749
2750 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2751                                           u16 vif_index, u8 func_bit_map)
2752 {
2753         struct bnx2x_func_state_params func_params = {NULL};
2754         struct bnx2x_func_afex_viflists_params *update_params =
2755                 &func_params.params.afex_viflists;
2756         int rc;
2757         u32 drv_msg_code;
2758
2759         /* validate only LIST_SET and LIST_GET are received from switch */
2760         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2761                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2762                           cmd_type);
2763
2764         func_params.f_obj = &bp->func_obj;
2765         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2766
2767         /* set parameters according to cmd_type */
2768         update_params->afex_vif_list_command = cmd_type;
2769         update_params->vif_list_index = vif_index;
2770         update_params->func_bit_map =
2771                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2772         update_params->func_to_clear = 0;
2773         drv_msg_code =
2774                 (cmd_type == VIF_LIST_RULE_GET) ?
2775                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2776                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2777
2778         /* if ramrod can not be sent, respond to MCP immediately for
2779          * SET and GET requests (other are not triggered from MCP)
2780          */
2781         rc = bnx2x_func_state_change(bp, &func_params);
2782         if (rc < 0)
2783                 bnx2x_fw_command(bp, drv_msg_code, 0);
2784
2785         return 0;
2786 }
2787
2788 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2789 {
2790         struct afex_stats afex_stats;
2791         u32 func = BP_ABS_FUNC(bp);
2792         u32 mf_config;
2793         u16 vlan_val;
2794         u32 vlan_prio;
2795         u16 vif_id;
2796         u8 allowed_prio;
2797         u8 vlan_mode;
2798         u32 addr_to_write, vifid, addrs, stats_type, i;
2799
2800         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2801                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2802                 DP(BNX2X_MSG_MCP,
2803                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2804                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2805         }
2806
2807         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2808                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2809                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2810                 DP(BNX2X_MSG_MCP,
2811                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2812                    vifid, addrs);
2813                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2814                                                addrs);
2815         }
2816
2817         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2818                 addr_to_write = SHMEM2_RD(bp,
2819                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2820                 stats_type = SHMEM2_RD(bp,
2821                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2822
2823                 DP(BNX2X_MSG_MCP,
2824                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2825                    addr_to_write);
2826
2827                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2828
2829                 /* write response to scratchpad, for MCP */
2830                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2831                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2832                                *(((u32 *)(&afex_stats))+i));
2833
2834                 /* send ack message to MCP */
2835                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2836         }
2837
2838         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2839                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2840                 bp->mf_config[BP_VN(bp)] = mf_config;
2841                 DP(BNX2X_MSG_MCP,
2842                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2843                    mf_config);
2844
2845                 /* if VIF_SET is "enabled" */
2846                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2847                         /* set rate limit directly to internal RAM */
2848                         struct cmng_init_input cmng_input;
2849                         struct rate_shaping_vars_per_vn m_rs_vn;
2850                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2851                         u32 addr = BAR_XSTRORM_INTMEM +
2852                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2853
2854                         bp->mf_config[BP_VN(bp)] = mf_config;
2855
2856                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2857                         m_rs_vn.vn_counter.rate =
2858                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2859                         m_rs_vn.vn_counter.quota =
2860                                 (m_rs_vn.vn_counter.rate *
2861                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2862
2863                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2864
2865                         /* read relevant values from mf_cfg struct in shmem */
2866                         vif_id =
2867                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2869                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2870                         vlan_val =
2871                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2872                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2873                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2874                         vlan_prio = (mf_config &
2875                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2876                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2877                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2878                         vlan_mode =
2879                                 (MF_CFG_RD(bp,
2880                                            func_mf_config[func].afex_config) &
2881                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2882                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2883                         allowed_prio =
2884                                 (MF_CFG_RD(bp,
2885                                            func_mf_config[func].afex_config) &
2886                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2887                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2888
2889                         /* send ramrod to FW, return in case of failure */
2890                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2891                                                    allowed_prio))
2892                                 return;
2893
2894                         bp->afex_def_vlan_tag = vlan_val;
2895                         bp->afex_vlan_mode = vlan_mode;
2896                 } else {
2897                         /* notify link down because BP->flags is disabled */
2898                         bnx2x_link_report(bp);
2899
2900                         /* send INVALID VIF ramrod to FW */
2901                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2902
2903                         /* Reset the default afex VLAN */
2904                         bp->afex_def_vlan_tag = -1;
2905                 }
2906         }
2907 }
2908
2909 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2910 {
2911         struct bnx2x_func_switch_update_params *switch_update_params;
2912         struct bnx2x_func_state_params func_params;
2913
2914         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2915         switch_update_params = &func_params.params.switch_update;
2916         func_params.f_obj = &bp->func_obj;
2917         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2918
2919         if (IS_MF_UFP(bp)) {
2920                 int func = BP_ABS_FUNC(bp);
2921                 u32 val;
2922
2923                 /* Re-learn the S-tag from shmem */
2924                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2925                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2926                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2927                         bp->mf_ov = val;
2928                 } else {
2929                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2930                         goto fail;
2931                 }
2932
2933                 /* Configure new S-tag in LLH */
2934                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2935                        bp->mf_ov);
2936
2937                 /* Send Ramrod to update FW of change */
2938                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2939                           &switch_update_params->changes);
2940                 switch_update_params->vlan = bp->mf_ov;
2941
2942                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2943                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2944                                   bp->mf_ov);
2945                         goto fail;
2946                 }
2947
2948                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2949
2950                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2951
2952                 return;
2953         }
2954
2955         /* not supported by SW yet */
2956 fail:
2957         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2958 }
2959
2960 static void bnx2x_pmf_update(struct bnx2x *bp)
2961 {
2962         int port = BP_PORT(bp);
2963         u32 val;
2964
2965         bp->port.pmf = 1;
2966         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2967
2968         /*
2969          * We need the mb() to ensure the ordering between the writing to
2970          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2971          */
2972         smp_mb();
2973
2974         /* queue a periodic task */
2975         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2976
2977         bnx2x_dcbx_pmf_update(bp);
2978
2979         /* enable nig attention */
2980         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2981         if (bp->common.int_block == INT_BLOCK_HC) {
2982                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2983                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2984         } else if (!CHIP_IS_E1x(bp)) {
2985                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2986                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2987         }
2988
2989         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2990 }
2991
2992 /* end of Link */
2993
2994 /* slow path */
2995
2996 /*
2997  * General service functions
2998  */
2999
3000 /* send the MCP a request, block until there is a reply */
3001 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3002 {
3003         int mb_idx = BP_FW_MB_IDX(bp);
3004         u32 seq;
3005         u32 rc = 0;
3006         u32 cnt = 1;
3007         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3008
3009         mutex_lock(&bp->fw_mb_mutex);
3010         seq = ++bp->fw_seq;
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3012         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3013
3014         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3015                         (command | seq), param);
3016
3017         do {
3018                 /* let the FW do it's magic ... */
3019                 msleep(delay);
3020
3021                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3022
3023                 /* Give the FW up to 5 second (500*10ms) */
3024         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3025
3026         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3027            cnt*delay, rc, seq);
3028
3029         /* is this a reply to our command? */
3030         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3031                 rc &= FW_MSG_CODE_MASK;
3032         else {
3033                 /* FW BUG! */
3034                 BNX2X_ERR("FW failed to respond!\n");
3035                 bnx2x_fw_dump(bp);
3036                 rc = 0;
3037         }
3038         mutex_unlock(&bp->fw_mb_mutex);
3039
3040         return rc;
3041 }
3042
3043 static void storm_memset_func_cfg(struct bnx2x *bp,
3044                                  struct tstorm_eth_function_common_config *tcfg,
3045                                  u16 abs_fid)
3046 {
3047         size_t size = sizeof(struct tstorm_eth_function_common_config);
3048
3049         u32 addr = BAR_TSTRORM_INTMEM +
3050                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3051
3052         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3053 }
3054
3055 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3056 {
3057         if (CHIP_IS_E1x(bp)) {
3058                 struct tstorm_eth_function_common_config tcfg = {0};
3059
3060                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3061         }
3062
3063         /* Enable the function in the FW */
3064         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3065         storm_memset_func_en(bp, p->func_id, 1);
3066
3067         /* spq */
3068         if (p->func_flgs & FUNC_FLG_SPQ) {
3069                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3070                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3071                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3072         }
3073 }
3074
3075 /**
3076  * bnx2x_get_common_flags - Return common flags
3077  *
3078  * @bp          device handle
3079  * @fp          queue handle
3080  * @zero_stats  TRUE if statistics zeroing is needed
3081  *
3082  * Return the flags that are common for the Tx-only and not normal connections.
3083  */
3084 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3085                                             struct bnx2x_fastpath *fp,
3086                                             bool zero_stats)
3087 {
3088         unsigned long flags = 0;
3089
3090         /* PF driver will always initialize the Queue to an ACTIVE state */
3091         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3092
3093         /* tx only connections collect statistics (on the same index as the
3094          * parent connection). The statistics are zeroed when the parent
3095          * connection is initialized.
3096          */
3097
3098         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3099         if (zero_stats)
3100                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3101
3102         if (bp->flags & TX_SWITCHING)
3103                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3104
3105         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3106         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3107
3108 #ifdef BNX2X_STOP_ON_ERROR
3109         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3110 #endif
3111
3112         return flags;
3113 }
3114
3115 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3116                                        struct bnx2x_fastpath *fp,
3117                                        bool leading)
3118 {
3119         unsigned long flags = 0;
3120
3121         /* calculate other queue flags */
3122         if (IS_MF_SD(bp))
3123                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3124
3125         if (IS_FCOE_FP(fp)) {
3126                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3127                 /* For FCoE - force usage of default priority (for afex) */
3128                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3129         }
3130
3131         if (!fp->disable_tpa) {
3132                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3133                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3134                 if (fp->mode == TPA_MODE_GRO)
3135                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3136         }
3137
3138         if (leading) {
3139                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3140                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3141         }
3142
3143         /* Always set HW VLAN stripping */
3144         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3145
3146         /* configure silent vlan removal */
3147         if (IS_MF_AFEX(bp))
3148                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3149
3150         return flags | bnx2x_get_common_flags(bp, fp, true);
3151 }
3152
3153 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3154         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3155         u8 cos)
3156 {
3157         gen_init->stat_id = bnx2x_stats_id(fp);
3158         gen_init->spcl_id = fp->cl_id;
3159
3160         /* Always use mini-jumbo MTU for FCoE L2 ring */
3161         if (IS_FCOE_FP(fp))
3162                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3163         else
3164                 gen_init->mtu = bp->dev->mtu;
3165
3166         gen_init->cos = cos;
3167
3168         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3169 }
3170
3171 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3172         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3173         struct bnx2x_rxq_setup_params *rxq_init)
3174 {
3175         u8 max_sge = 0;
3176         u16 sge_sz = 0;
3177         u16 tpa_agg_size = 0;
3178
3179         if (!fp->disable_tpa) {
3180                 pause->sge_th_lo = SGE_TH_LO(bp);
3181                 pause->sge_th_hi = SGE_TH_HI(bp);
3182
3183                 /* validate SGE ring has enough to cross high threshold */
3184                 WARN_ON(bp->dropless_fc &&
3185                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3186                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3187
3188                 tpa_agg_size = TPA_AGG_SIZE;
3189                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3190                         SGE_PAGE_SHIFT;
3191                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3192                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3193                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3194         }
3195
3196         /* pause - not for e1 */
3197         if (!CHIP_IS_E1(bp)) {
3198                 pause->bd_th_lo = BD_TH_LO(bp);
3199                 pause->bd_th_hi = BD_TH_HI(bp);
3200
3201                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3202                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3203                 /*
3204                  * validate that rings have enough entries to cross
3205                  * high thresholds
3206                  */
3207                 WARN_ON(bp->dropless_fc &&
3208                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3209                                 bp->rx_ring_size);
3210                 WARN_ON(bp->dropless_fc &&
3211                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3212                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3213
3214                 pause->pri_map = 1;
3215         }
3216
3217         /* rxq setup */
3218         rxq_init->dscr_map = fp->rx_desc_mapping;
3219         rxq_init->sge_map = fp->rx_sge_mapping;
3220         rxq_init->rcq_map = fp->rx_comp_mapping;
3221         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3222
3223         /* This should be a maximum number of data bytes that may be
3224          * placed on the BD (not including paddings).
3225          */
3226         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3227                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3228
3229         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3230         rxq_init->tpa_agg_sz = tpa_agg_size;
3231         rxq_init->sge_buf_sz = sge_sz;
3232         rxq_init->max_sges_pkt = max_sge;
3233         rxq_init->rss_engine_id = BP_FUNC(bp);
3234         rxq_init->mcast_engine_id = BP_FUNC(bp);
3235
3236         /* Maximum number or simultaneous TPA aggregation for this Queue.
3237          *
3238          * For PF Clients it should be the maximum available number.
3239          * VF driver(s) may want to define it to a smaller value.
3240          */
3241         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3242
3243         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3244         rxq_init->fw_sb_id = fp->fw_sb_id;
3245
3246         if (IS_FCOE_FP(fp))
3247                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3248         else
3249                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3250         /* configure silent vlan removal
3251          * if multi function mode is afex, then mask default vlan
3252          */
3253         if (IS_MF_AFEX(bp)) {
3254                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3255                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3256         }
3257 }
3258
3259 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3260         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3261         u8 cos)
3262 {
3263         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3264         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3265         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3266         txq_init->fw_sb_id = fp->fw_sb_id;
3267
3268         /*
3269          * set the tss leading client id for TX classification ==
3270          * leading RSS client id
3271          */
3272         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3273
3274         if (IS_FCOE_FP(fp)) {
3275                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3276                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3277         }
3278 }
3279
3280 static void bnx2x_pf_init(struct bnx2x *bp)
3281 {
3282         struct bnx2x_func_init_params func_init = {0};
3283         struct event_ring_data eq_data = { {0} };
3284         u16 flags;
3285
3286         if (!CHIP_IS_E1x(bp)) {
3287                 /* reset IGU PF statistics: MSIX + ATTN */
3288                 /* PF */
3289                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3290                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3291                            (CHIP_MODE_IS_4_PORT(bp) ?
3292                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3293                 /* ATTN */
3294                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3295                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3296                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3297                            (CHIP_MODE_IS_4_PORT(bp) ?
3298                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3299         }
3300
3301         /* function setup flags */
3302         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3303
3304         /* This flag is relevant for E1x only.
3305          * E2 doesn't have a TPA configuration in a function level.
3306          */
3307         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3308
3309         func_init.func_flgs = flags;
3310         func_init.pf_id = BP_FUNC(bp);
3311         func_init.func_id = BP_FUNC(bp);
3312         func_init.spq_map = bp->spq_mapping;
3313         func_init.spq_prod = bp->spq_prod_idx;
3314
3315         bnx2x_func_init(bp, &func_init);
3316
3317         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318
3319         /*
3320          * Congestion management values depend on the link rate
3321          * There is no active link so initial link rate is set to 10 Gbps.
3322          * When the link comes up The congestion management values are
3323          * re-calculated according to the actual link rate.
3324          */
3325         bp->link_vars.line_speed = SPEED_10000;
3326         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327
3328         /* Only the PMF sets the HW */
3329         if (bp->port.pmf)
3330                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331
3332         /* init Event Queue - PCI bus guarantees correct endianity*/
3333         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335         eq_data.producer = bp->eq_prod;
3336         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337         eq_data.sb_id = DEF_SB_ID;
3338         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339 }
3340
3341 static void bnx2x_e1h_disable(struct bnx2x *bp)
3342 {
3343         int port = BP_PORT(bp);
3344
3345         bnx2x_tx_disable(bp);
3346
3347         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3348 }
3349
3350 static void bnx2x_e1h_enable(struct bnx2x *bp)
3351 {
3352         int port = BP_PORT(bp);
3353
3354         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3356
3357         /* Tx queue should be only re-enabled */
3358         netif_tx_wake_all_queues(bp->dev);
3359
3360         /*
3361          * Should not call netif_carrier_on since it will be called if the link
3362          * is up when checking for link state
3363          */
3364 }
3365
3366 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369 {
3370         struct eth_stats_info *ether_stat =
3371                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3372         struct bnx2x_vlan_mac_obj *mac_obj =
3373                 &bp->sp_objs->mac_obj;
3374         int i;
3375
3376         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377                 ETH_STAT_INFO_VERSION_LEN);
3378
3379         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380          * mac_local field in ether_stat struct. The base address is offset by 2
3381          * bytes to account for the field being 8 bytes but a mac address is
3382          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384          * allocated by the ether_stat struct, so the macs will land in their
3385          * proper positions.
3386          */
3387         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388                 memset(ether_stat->mac_local + i, 0,
3389                        sizeof(ether_stat->mac_local[0]));
3390         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393                                 ETH_ALEN);
3394         ether_stat->mtu_size = bp->dev->mtu;
3395         if (bp->dev->features & NETIF_F_RXCSUM)
3396                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397         if (bp->dev->features & NETIF_F_TSO)
3398                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399         ether_stat->feature_flags |= bp->common.boot_mode;
3400
3401         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402
3403         ether_stat->txq_size = bp->tx_ring_size;
3404         ether_stat->rxq_size = bp->rx_ring_size;
3405
3406 #ifdef CONFIG_BNX2X_SRIOV
3407         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3408 #endif
3409 }
3410
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412 {
3413         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414         struct fcoe_stats_info *fcoe_stat =
3415                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416
3417         if (!CNIC_LOADED(bp))
3418                 return;
3419
3420         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3421
3422         fcoe_stat->qos_priority =
3423                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424
3425         /* insert FCoE stats from ramrod response */
3426         if (!NO_FCOE(bp)) {
3427                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         tstorm_queue_statistics;
3430
3431                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3432                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3433                         xstorm_queue_statistics;
3434
3435                 struct fcoe_statistics_params *fw_fcoe_stat =
3436                         &bp->fw_stats_data->fcoe;
3437
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3441
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3446
3447                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449                           fcoe_stat->rx_bytes_lo,
3450                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3451
3452                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454                           fcoe_stat->rx_bytes_lo,
3455                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3456
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3460
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3464
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3468
3469                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470                           fcoe_stat->rx_frames_lo,
3471                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3472
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3476
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3481
3482                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484                           fcoe_stat->tx_bytes_lo,
3485                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3486
3487                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489                           fcoe_stat->tx_bytes_lo,
3490                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3491
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3495
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3499
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3503
3504                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505                           fcoe_stat->tx_frames_lo,
3506                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3507         }
3508
3509         /* ask L5 driver to add data to the struct */
3510         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3511 }
3512
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514 {
3515         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516         struct iscsi_stats_info *iscsi_stat =
3517                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518
3519         if (!CNIC_LOADED(bp))
3520                 return;
3521
3522         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523                ETH_ALEN);
3524
3525         iscsi_stat->qos_priority =
3526                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527
3528         /* ask L5 driver to add data to the struct */
3529         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3530 }
3531
3532 /* called due to MCP event (on pmf):
3533  *      reread new bandwidth configuration
3534  *      configure FW
3535  *      notify others function about the change
3536  */
3537 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3538 {
3539         if (bp->link_vars.link_up) {
3540                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3541                 bnx2x_link_sync_notify(bp);
3542         }
3543         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3544 }
3545
3546 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3547 {
3548         bnx2x_config_mf_bw(bp);
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550 }
3551
3552 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3553 {
3554         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3555         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556 }
3557
3558 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3559 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3560
3561 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3562 {
3563         enum drv_info_opcode op_code;
3564         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3565         bool release = false;
3566         int wait;
3567
3568         /* if drv_info version supported by MFW doesn't match - send NACK */
3569         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3570                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3571                 return;
3572         }
3573
3574         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3575                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3576
3577         /* Must prevent other flows from accessing drv_info_to_mcp */
3578         mutex_lock(&bp->drv_info_mutex);
3579
3580         memset(&bp->slowpath->drv_info_to_mcp, 0,
3581                sizeof(union drv_info_to_mcp));
3582
3583         switch (op_code) {
3584         case ETH_STATS_OPCODE:
3585                 bnx2x_drv_info_ether_stat(bp);
3586                 break;
3587         case FCOE_STATS_OPCODE:
3588                 bnx2x_drv_info_fcoe_stat(bp);
3589                 break;
3590         case ISCSI_STATS_OPCODE:
3591                 bnx2x_drv_info_iscsi_stat(bp);
3592                 break;
3593         default:
3594                 /* if op code isn't supported - send NACK */
3595                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596                 goto out;
3597         }
3598
3599         /* if we got drv_info attn from MFW then these fields are defined in
3600          * shmem2 for sure
3601          */
3602         SHMEM2_WR(bp, drv_info_host_addr_lo,
3603                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604         SHMEM2_WR(bp, drv_info_host_addr_hi,
3605                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606
3607         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3608
3609         /* Since possible management wants both this and get_driver_version
3610          * need to wait until management notifies us it finished utilizing
3611          * the buffer.
3612          */
3613         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3614                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3615         } else if (!bp->drv_info_mng_owner) {
3616                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3617
3618                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3619                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3620
3621                         /* Management is done; need to clear indication */
3622                         if (indication & bit) {
3623                                 SHMEM2_WR(bp, mfw_drv_indication,
3624                                           indication & ~bit);
3625                                 release = true;
3626                                 break;
3627                         }
3628
3629                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3630                 }
3631         }
3632         if (!release) {
3633                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3634                 bp->drv_info_mng_owner = true;
3635         }
3636
3637 out:
3638         mutex_unlock(&bp->drv_info_mutex);
3639 }
3640
3641 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3642 {
3643         u8 vals[4];
3644         int i = 0;
3645
3646         if (bnx2x_format) {
3647                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3648                            &vals[0], &vals[1], &vals[2], &vals[3]);
3649                 if (i > 0)
3650                         vals[0] -= '0';
3651         } else {
3652                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3653                            &vals[0], &vals[1], &vals[2], &vals[3]);
3654         }
3655
3656         while (i < 4)
3657                 vals[i++] = 0;
3658
3659         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3660 }
3661
3662 void bnx2x_update_mng_version(struct bnx2x *bp)
3663 {
3664         u32 iscsiver = DRV_VER_NOT_LOADED;
3665         u32 fcoever = DRV_VER_NOT_LOADED;
3666         u32 ethver = DRV_VER_NOT_LOADED;
3667         int idx = BP_FW_MB_IDX(bp);
3668         u8 *version;
3669
3670         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3671                 return;
3672
3673         mutex_lock(&bp->drv_info_mutex);
3674         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675         if (bp->drv_info_mng_owner)
3676                 goto out;
3677
3678         if (bp->state != BNX2X_STATE_OPEN)
3679                 goto out;
3680
3681         /* Parse ethernet driver version */
3682         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3683         if (!CNIC_LOADED(bp))
3684                 goto out;
3685
3686         /* Try getting storage driver version via cnic */
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_iscsi_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3691         iscsiver = bnx2x_update_mng_version_utility(version, false);
3692
3693         memset(&bp->slowpath->drv_info_to_mcp, 0,
3694                sizeof(union drv_info_to_mcp));
3695         bnx2x_drv_info_fcoe_stat(bp);
3696         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3697         fcoever = bnx2x_update_mng_version_utility(version, false);
3698
3699 out:
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3703
3704         mutex_unlock(&bp->drv_info_mutex);
3705
3706         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707            ethver, iscsiver, fcoever);
3708 }
3709
3710 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3711 {
3712         u32 cmd_ok, cmd_fail;
3713
3714         /* sanity */
3715         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3716             event & DRV_STATUS_OEM_EVENT_MASK) {
3717                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3718                 return;
3719         }
3720
3721         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3722                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3723                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3724         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3725                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3726                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3727         }
3728
3729         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3730
3731         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3732                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3733                 /* This is the only place besides the function initialization
3734                  * where the bp->flags can change so it is done without any
3735                  * locks
3736                  */
3737                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3738                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3739                         bp->flags |= MF_FUNC_DIS;
3740
3741                         bnx2x_e1h_disable(bp);
3742                 } else {
3743                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3744                         bp->flags &= ~MF_FUNC_DIS;
3745
3746                         bnx2x_e1h_enable(bp);
3747                 }
3748                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3749                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3750         }
3751
3752         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3753                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3754                 bnx2x_config_mf_bw(bp);
3755                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3756                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3757         }
3758
3759         /* Report results to MCP */
3760         if (event)
3761                 bnx2x_fw_command(bp, cmd_fail, 0);
3762         else
3763                 bnx2x_fw_command(bp, cmd_ok, 0);
3764 }
3765
3766 /* must be called under the spq lock */
3767 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3768 {
3769         struct eth_spe *next_spe = bp->spq_prod_bd;
3770
3771         if (bp->spq_prod_bd == bp->spq_last_bd) {
3772                 bp->spq_prod_bd = bp->spq;
3773                 bp->spq_prod_idx = 0;
3774                 DP(BNX2X_MSG_SP, "end of spq\n");
3775         } else {
3776                 bp->spq_prod_bd++;
3777                 bp->spq_prod_idx++;
3778         }
3779         return next_spe;
3780 }
3781
3782 /* must be called under the spq lock */
3783 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3784 {
3785         int func = BP_FUNC(bp);
3786
3787         /*
3788          * Make sure that BD data is updated before writing the producer:
3789          * BD data is written to the memory, the producer is read from the
3790          * memory, thus we need a full memory barrier to ensure the ordering.
3791          */
3792         mb();
3793
3794         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3795                  bp->spq_prod_idx);
3796         mmiowb();
3797 }
3798
3799 /**
3800  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3801  *
3802  * @cmd:        command to check
3803  * @cmd_type:   command type
3804  */
3805 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3806 {
3807         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3808             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3809             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3810             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3811             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3812             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3813             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3814                 return true;
3815         else
3816                 return false;
3817 }
3818
3819 /**
3820  * bnx2x_sp_post - place a single command on an SP ring
3821  *
3822  * @bp:         driver handle
3823  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3824  * @cid:        SW CID the command is related to
3825  * @data_hi:    command private data address (high 32 bits)
3826  * @data_lo:    command private data address (low 32 bits)
3827  * @cmd_type:   command type (e.g. NONE, ETH)
3828  *
3829  * SP data is handled as if it's always an address pair, thus data fields are
3830  * not swapped to little endian in upper functions. Instead this function swaps
3831  * data as if it's two u32 fields.
3832  */
3833 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3834                   u32 data_hi, u32 data_lo, int cmd_type)
3835 {
3836         struct eth_spe *spe;
3837         u16 type;
3838         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3839
3840 #ifdef BNX2X_STOP_ON_ERROR
3841         if (unlikely(bp->panic)) {
3842                 BNX2X_ERR("Can't post SP when there is panic\n");
3843                 return -EIO;
3844         }
3845 #endif
3846
3847         spin_lock_bh(&bp->spq_lock);
3848
3849         if (common) {
3850                 if (!atomic_read(&bp->eq_spq_left)) {
3851                         BNX2X_ERR("BUG! EQ ring full!\n");
3852                         spin_unlock_bh(&bp->spq_lock);
3853                         bnx2x_panic();
3854                         return -EBUSY;
3855                 }
3856         } else if (!atomic_read(&bp->cq_spq_left)) {
3857                         BNX2X_ERR("BUG! SPQ ring full!\n");
3858                         spin_unlock_bh(&bp->spq_lock);
3859                         bnx2x_panic();
3860                         return -EBUSY;
3861         }
3862
3863         spe = bnx2x_sp_get_next(bp);
3864
3865         /* CID needs port number to be encoded int it */
3866         spe->hdr.conn_and_cmd_data =
3867                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3868                                     HW_CID(bp, cid));
3869
3870         /* In some cases, type may already contain the func-id
3871          * mainly in SRIOV related use cases, so we add it here only
3872          * if it's not already set.
3873          */
3874         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3875                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3876                         SPE_HDR_CONN_TYPE;
3877                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3878                          SPE_HDR_FUNCTION_ID);
3879         } else {
3880                 type = cmd_type;
3881         }
3882
3883         spe->hdr.type = cpu_to_le16(type);
3884
3885         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3886         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3887
3888         /*
3889          * It's ok if the actual decrement is issued towards the memory
3890          * somewhere between the spin_lock and spin_unlock. Thus no
3891          * more explicit memory barrier is needed.
3892          */
3893         if (common)
3894                 atomic_dec(&bp->eq_spq_left);
3895         else
3896                 atomic_dec(&bp->cq_spq_left);
3897
3898         DP(BNX2X_MSG_SP,
3899            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3900            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3901            (u32)(U64_LO(bp->spq_mapping) +
3902            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3903            HW_CID(bp, cid), data_hi, data_lo, type,
3904            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3905
3906         bnx2x_sp_prod_update(bp);
3907         spin_unlock_bh(&bp->spq_lock);
3908         return 0;
3909 }
3910
3911 /* acquire split MCP access lock register */
3912 static int bnx2x_acquire_alr(struct bnx2x *bp)
3913 {
3914         u32 j, val;
3915         int rc = 0;
3916
3917         might_sleep();
3918         for (j = 0; j < 1000; j++) {
3919                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3920                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3921                 if (val & MCPR_ACCESS_LOCK_LOCK)
3922                         break;
3923
3924                 usleep_range(5000, 10000);
3925         }
3926         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3927                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3928                 rc = -EBUSY;
3929         }
3930
3931         return rc;
3932 }
3933
3934 /* release split MCP access lock register */
3935 static void bnx2x_release_alr(struct bnx2x *bp)
3936 {
3937         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3938 }
3939
3940 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3941 #define BNX2X_DEF_SB_IDX        0x0002
3942
3943 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3944 {
3945         struct host_sp_status_block *def_sb = bp->def_status_blk;
3946         u16 rc = 0;
3947
3948         barrier(); /* status block is written to by the chip */
3949         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3950                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3951                 rc |= BNX2X_DEF_SB_ATT_IDX;
3952         }
3953
3954         if (bp->def_idx != def_sb->sp_sb.running_index) {
3955                 bp->def_idx = def_sb->sp_sb.running_index;
3956                 rc |= BNX2X_DEF_SB_IDX;
3957         }
3958
3959         /* Do not reorder: indices reading should complete before handling */
3960         barrier();
3961         return rc;
3962 }
3963
3964 /*
3965  * slow path service functions
3966  */
3967
3968 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3969 {
3970         int port = BP_PORT(bp);
3971         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3972                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3973         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3974                                        NIG_REG_MASK_INTERRUPT_PORT0;
3975         u32 aeu_mask;
3976         u32 nig_mask = 0;
3977         u32 reg_addr;
3978
3979         if (bp->attn_state & asserted)
3980                 BNX2X_ERR("IGU ERROR\n");
3981
3982         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3983         aeu_mask = REG_RD(bp, aeu_addr);
3984
3985         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3986            aeu_mask, asserted);
3987         aeu_mask &= ~(asserted & 0x3ff);
3988         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3989
3990         REG_WR(bp, aeu_addr, aeu_mask);
3991         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3992
3993         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3994         bp->attn_state |= asserted;
3995         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3996
3997         if (asserted & ATTN_HARD_WIRED_MASK) {
3998                 if (asserted & ATTN_NIG_FOR_FUNC) {
3999
4000                         bnx2x_acquire_phy_lock(bp);
4001
4002                         /* save nig interrupt mask */
4003                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4004
4005                         /* If nig_mask is not set, no need to call the update
4006                          * function.
4007                          */
4008                         if (nig_mask) {
4009                                 REG_WR(bp, nig_int_mask_addr, 0);
4010
4011                                 bnx2x_link_attn(bp);
4012                         }
4013
4014                         /* handle unicore attn? */
4015                 }
4016                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4017                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4018
4019                 if (asserted & GPIO_2_FUNC)
4020                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4021
4022                 if (asserted & GPIO_3_FUNC)
4023                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4024
4025                 if (asserted & GPIO_4_FUNC)
4026                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4027
4028                 if (port == 0) {
4029                         if (asserted & ATTN_GENERAL_ATTN_1) {
4030                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4031                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4032                         }
4033                         if (asserted & ATTN_GENERAL_ATTN_2) {
4034                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4035                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4036                         }
4037                         if (asserted & ATTN_GENERAL_ATTN_3) {
4038                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4039                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4040                         }
4041                 } else {
4042                         if (asserted & ATTN_GENERAL_ATTN_4) {
4043                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4044                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4045                         }
4046                         if (asserted & ATTN_GENERAL_ATTN_5) {
4047                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4048                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4049                         }
4050                         if (asserted & ATTN_GENERAL_ATTN_6) {
4051                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4052                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4053                         }
4054                 }
4055
4056         } /* if hardwired */
4057
4058         if (bp->common.int_block == INT_BLOCK_HC)
4059                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4060                             COMMAND_REG_ATTN_BITS_SET);
4061         else
4062                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4063
4064         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4065            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4066         REG_WR(bp, reg_addr, asserted);
4067
4068         /* now set back the mask */
4069         if (asserted & ATTN_NIG_FOR_FUNC) {
4070                 /* Verify that IGU ack through BAR was written before restoring
4071                  * NIG mask. This loop should exit after 2-3 iterations max.
4072                  */
4073                 if (bp->common.int_block != INT_BLOCK_HC) {
4074                         u32 cnt = 0, igu_acked;
4075                         do {
4076                                 igu_acked = REG_RD(bp,
4077                                                    IGU_REG_ATTENTION_ACK_BITS);
4078                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4079                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4080                         if (!igu_acked)
4081                                 DP(NETIF_MSG_HW,
4082                                    "Failed to verify IGU ack on time\n");
4083                         barrier();
4084                 }
4085                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4086                 bnx2x_release_phy_lock(bp);
4087         }
4088 }
4089
4090 static void bnx2x_fan_failure(struct bnx2x *bp)
4091 {
4092         int port = BP_PORT(bp);
4093         u32 ext_phy_config;
4094         /* mark the failure */
4095         ext_phy_config =
4096                 SHMEM_RD(bp,
4097                          dev_info.port_hw_config[port].external_phy_config);
4098
4099         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4100         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4101         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4102                  ext_phy_config);
4103
4104         /* log the failure */
4105         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4106                             "Please contact OEM Support for assistance\n");
4107
4108         /* Schedule device reset (unload)
4109          * This is due to some boards consuming sufficient power when driver is
4110          * up to overheat if fan fails.
4111          */
4112         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4113 }
4114
4115 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4116 {
4117         int port = BP_PORT(bp);
4118         int reg_offset;
4119         u32 val;
4120
4121         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4122                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4123
4124         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4125
4126                 val = REG_RD(bp, reg_offset);
4127                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4128                 REG_WR(bp, reg_offset, val);
4129
4130                 BNX2X_ERR("SPIO5 hw attention\n");
4131
4132                 /* Fan failure attention */
4133                 bnx2x_hw_reset_phy(&bp->link_params);
4134                 bnx2x_fan_failure(bp);
4135         }
4136
4137         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4138                 bnx2x_acquire_phy_lock(bp);
4139                 bnx2x_handle_module_detect_int(&bp->link_params);
4140                 bnx2x_release_phy_lock(bp);
4141         }
4142
4143         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4144
4145                 val = REG_RD(bp, reg_offset);
4146                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4147                 REG_WR(bp, reg_offset, val);
4148
4149                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4150                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4151                 bnx2x_panic();
4152         }
4153 }
4154
4155 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4156 {
4157         u32 val;
4158
4159         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4160
4161                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4162                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4163                 /* DORQ discard attention */
4164                 if (val & 0x2)
4165                         BNX2X_ERR("FATAL error from DORQ\n");
4166         }
4167
4168         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4169
4170                 int port = BP_PORT(bp);
4171                 int reg_offset;
4172
4173                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4174                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4175
4176                 val = REG_RD(bp, reg_offset);
4177                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4178                 REG_WR(bp, reg_offset, val);
4179
4180                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4181                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4182                 bnx2x_panic();
4183         }
4184 }
4185
4186 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4187 {
4188         u32 val;
4189
4190         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4191
4192                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4193                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4194                 /* CFC error attention */
4195                 if (val & 0x2)
4196                         BNX2X_ERR("FATAL error from CFC\n");
4197         }
4198
4199         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4200                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4201                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4202                 /* RQ_USDMDP_FIFO_OVERFLOW */
4203                 if (val & 0x18000)
4204                         BNX2X_ERR("FATAL error from PXP\n");
4205
4206                 if (!CHIP_IS_E1x(bp)) {
4207                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4208                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4209                 }
4210         }
4211
4212         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4213
4214                 int port = BP_PORT(bp);
4215                 int reg_offset;
4216
4217                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4218                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4219
4220                 val = REG_RD(bp, reg_offset);
4221                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4222                 REG_WR(bp, reg_offset, val);
4223
4224                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4225                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4226                 bnx2x_panic();
4227         }
4228 }
4229
4230 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4231 {
4232         u32 val;
4233
4234         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4235
4236                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4237                         int func = BP_FUNC(bp);
4238
4239                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4240                         bnx2x_read_mf_cfg(bp);
4241                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4242                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4243                         val = SHMEM_RD(bp,
4244                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4245
4246                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4247                                    DRV_STATUS_OEM_EVENT_MASK))
4248                                 bnx2x_oem_event(bp,
4249                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4250                                                 DRV_STATUS_OEM_EVENT_MASK)));
4251
4252                         if (val & DRV_STATUS_SET_MF_BW)
4253                                 bnx2x_set_mf_bw(bp);
4254
4255                         if (val & DRV_STATUS_DRV_INFO_REQ)
4256                                 bnx2x_handle_drv_info_req(bp);
4257
4258                         if (val & DRV_STATUS_VF_DISABLED)
4259                                 bnx2x_schedule_iov_task(bp,
4260                                                         BNX2X_IOV_HANDLE_FLR);
4261
4262                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4263                                 bnx2x_pmf_update(bp);
4264
4265                         if (bp->port.pmf &&
4266                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4267                                 bp->dcbx_enabled > 0)
4268                                 /* start dcbx state machine */
4269                                 bnx2x_dcbx_set_params(bp,
4270                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4271                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4272                                 bnx2x_handle_afex_cmd(bp,
4273                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4274                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4275                                 bnx2x_handle_eee_event(bp);
4276
4277                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4278                                 bnx2x_handle_update_svid_cmd(bp);
4279
4280                         if (bp->link_vars.periodic_flags &
4281                             PERIODIC_FLAGS_LINK_EVENT) {
4282                                 /*  sync with link */
4283                                 bnx2x_acquire_phy_lock(bp);
4284                                 bp->link_vars.periodic_flags &=
4285                                         ~PERIODIC_FLAGS_LINK_EVENT;
4286                                 bnx2x_release_phy_lock(bp);
4287                                 if (IS_MF(bp))
4288                                         bnx2x_link_sync_notify(bp);
4289                                 bnx2x_link_report(bp);
4290                         }
4291                         /* Always call it here: bnx2x_link_report() will
4292                          * prevent the link indication duplication.
4293                          */
4294                         bnx2x__link_status_update(bp);
4295                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4296
4297                         BNX2X_ERR("MC assert!\n");
4298                         bnx2x_mc_assert(bp);
4299                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4300                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4301                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4302                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4303                         bnx2x_panic();
4304
4305                 } else if (attn & BNX2X_MCP_ASSERT) {
4306
4307                         BNX2X_ERR("MCP assert!\n");
4308                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4309                         bnx2x_fw_dump(bp);
4310
4311                 } else
4312                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4313         }
4314
4315         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4316                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4317                 if (attn & BNX2X_GRC_TIMEOUT) {
4318                         val = CHIP_IS_E1(bp) ? 0 :
4319                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4320                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4321                 }
4322                 if (attn & BNX2X_GRC_RSV) {
4323                         val = CHIP_IS_E1(bp) ? 0 :
4324                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4325                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4326                 }
4327                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4328         }
4329 }
4330
4331 /*
4332  * Bits map:
4333  * 0-7   - Engine0 load counter.
4334  * 8-15  - Engine1 load counter.
4335  * 16    - Engine0 RESET_IN_PROGRESS bit.
4336  * 17    - Engine1 RESET_IN_PROGRESS bit.
4337  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4338  *         on the engine
4339  * 19    - Engine1 ONE_IS_LOADED.
4340  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4341  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4342  *         just the one belonging to its engine).
4343  *
4344  */
4345 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4346
4347 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4348 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4349 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4350 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4351 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4352 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4353 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4354
4355 /*
4356  * Set the GLOBAL_RESET bit.
4357  *
4358  * Should be run under rtnl lock
4359  */
4360 void bnx2x_set_reset_global(struct bnx2x *bp)
4361 {
4362         u32 val;
4363         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4364         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4365         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4366         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4367 }
4368
4369 /*
4370  * Clear the GLOBAL_RESET bit.
4371  *
4372  * Should be run under rtnl lock
4373  */
4374 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4375 {
4376         u32 val;
4377         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4378         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4379         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4380         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4381 }
4382
4383 /*
4384  * Checks the GLOBAL_RESET bit.
4385  *
4386  * should be run under rtnl lock
4387  */
4388 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4389 {
4390         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4391
4392         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4393         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4394 }
4395
4396 /*
4397  * Clear RESET_IN_PROGRESS bit for the current engine.
4398  *
4399  * Should be run under rtnl lock
4400  */
4401 static void bnx2x_set_reset_done(struct bnx2x *bp)
4402 {
4403         u32 val;
4404         u32 bit = BP_PATH(bp) ?
4405                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4406         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4407         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4408
4409         /* Clear the bit */
4410         val &= ~bit;
4411         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4412
4413         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4414 }
4415
4416 /*
4417  * Set RESET_IN_PROGRESS for the current engine.
4418  *
4419  * should be run under rtnl lock
4420  */
4421 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4422 {
4423         u32 val;
4424         u32 bit = BP_PATH(bp) ?
4425                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4426         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4427         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4428
4429         /* Set the bit */
4430         val |= bit;
4431         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4432         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4433 }
4434
4435 /*
4436  * Checks the RESET_IN_PROGRESS bit for the given engine.
4437  * should be run under rtnl lock
4438  */
4439 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4440 {
4441         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4442         u32 bit = engine ?
4443                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4444
4445         /* return false if bit is set */
4446         return (val & bit) ? false : true;
4447 }
4448
4449 /*
4450  * set pf load for the current pf.
4451  *
4452  * should be run under rtnl lock
4453  */
4454 void bnx2x_set_pf_load(struct bnx2x *bp)
4455 {
4456         u32 val1, val;
4457         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4458                              BNX2X_PATH0_LOAD_CNT_MASK;
4459         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4460                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4461
4462         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4463         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4464
4465         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4466
4467         /* get the current counter value */
4468         val1 = (val & mask) >> shift;
4469
4470         /* set bit of that PF */
4471         val1 |= (1 << bp->pf_num);
4472
4473         /* clear the old value */
4474         val &= ~mask;
4475
4476         /* set the new one */
4477         val |= ((val1 << shift) & mask);
4478
4479         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4480         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4481 }
4482
4483 /**
4484  * bnx2x_clear_pf_load - clear pf load mark
4485  *
4486  * @bp:         driver handle
4487  *
4488  * Should be run under rtnl lock.
4489  * Decrements the load counter for the current engine. Returns
4490  * whether other functions are still loaded
4491  */
4492 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4493 {
4494         u32 val1, val;
4495         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4496                              BNX2X_PATH0_LOAD_CNT_MASK;
4497         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4498                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4499
4500         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4501         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4502         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4503
4504         /* get the current counter value */
4505         val1 = (val & mask) >> shift;
4506
4507         /* clear bit of that PF */
4508         val1 &= ~(1 << bp->pf_num);
4509
4510         /* clear the old value */
4511         val &= ~mask;
4512
4513         /* set the new one */
4514         val |= ((val1 << shift) & mask);
4515
4516         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4517         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4518         return val1 != 0;
4519 }
4520
4521 /*
4522  * Read the load status for the current engine.
4523  *
4524  * should be run under rtnl lock
4525  */
4526 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4527 {
4528         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4529                              BNX2X_PATH0_LOAD_CNT_MASK);
4530         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4531                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4532         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4533
4534         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4535
4536         val = (val & mask) >> shift;
4537
4538         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4539            engine, val);
4540
4541         return val != 0;
4542 }
4543
4544 static void _print_parity(struct bnx2x *bp, u32 reg)
4545 {
4546         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4547 }
4548
4549 static void _print_next_block(int idx, const char *blk)
4550 {
4551         pr_cont("%s%s", idx ? ", " : "", blk);
4552 }
4553
4554 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4555                                             int *par_num, bool print)
4556 {
4557         u32 cur_bit;
4558         bool res;
4559         int i;
4560
4561         res = false;
4562
4563         for (i = 0; sig; i++) {
4564                 cur_bit = (0x1UL << i);
4565                 if (sig & cur_bit) {
4566                         res |= true; /* Each bit is real error! */
4567
4568                         if (print) {
4569                                 switch (cur_bit) {
4570                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4571                                         _print_next_block((*par_num)++, "BRB");
4572                                         _print_parity(bp,
4573                                                       BRB1_REG_BRB1_PRTY_STS);
4574                                         break;
4575                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4576                                         _print_next_block((*par_num)++,
4577                                                           "PARSER");
4578                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4579                                         break;
4580                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4581                                         _print_next_block((*par_num)++, "TSDM");
4582                                         _print_parity(bp,
4583                                                       TSDM_REG_TSDM_PRTY_STS);
4584                                         break;
4585                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4586                                         _print_next_block((*par_num)++,
4587                                                           "SEARCHER");
4588                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4589                                         break;
4590                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4591                                         _print_next_block((*par_num)++, "TCM");
4592                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4593                                         break;
4594                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4595                                         _print_next_block((*par_num)++,
4596                                                           "TSEMI");
4597                                         _print_parity(bp,
4598                                                       TSEM_REG_TSEM_PRTY_STS_0);
4599                                         _print_parity(bp,
4600                                                       TSEM_REG_TSEM_PRTY_STS_1);
4601                                         break;
4602                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4603                                         _print_next_block((*par_num)++, "XPB");
4604                                         _print_parity(bp, GRCBASE_XPB +
4605                                                           PB_REG_PB_PRTY_STS);
4606                                         break;
4607                                 }
4608                         }
4609
4610                         /* Clear the bit */
4611                         sig &= ~cur_bit;
4612                 }
4613         }
4614
4615         return res;
4616 }
4617
4618 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4619                                             int *par_num, bool *global,
4620                                             bool print)
4621 {
4622         u32 cur_bit;
4623         bool res;
4624         int i;
4625
4626         res = false;
4627
4628         for (i = 0; sig; i++) {
4629                 cur_bit = (0x1UL << i);
4630                 if (sig & cur_bit) {
4631                         res |= true; /* Each bit is real error! */
4632                         switch (cur_bit) {
4633                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4634                                 if (print) {
4635                                         _print_next_block((*par_num)++, "PBF");
4636                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4637                                 }
4638                                 break;
4639                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4640                                 if (print) {
4641                                         _print_next_block((*par_num)++, "QM");
4642                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4643                                 }
4644                                 break;
4645                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4646                                 if (print) {
4647                                         _print_next_block((*par_num)++, "TM");
4648                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4649                                 }
4650                                 break;
4651                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4652                                 if (print) {
4653                                         _print_next_block((*par_num)++, "XSDM");
4654                                         _print_parity(bp,
4655                                                       XSDM_REG_XSDM_PRTY_STS);
4656                                 }
4657                                 break;
4658                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4659                                 if (print) {
4660                                         _print_next_block((*par_num)++, "XCM");
4661                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4662                                 }
4663                                 break;
4664                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4665                                 if (print) {
4666                                         _print_next_block((*par_num)++,
4667                                                           "XSEMI");
4668                                         _print_parity(bp,
4669                                                       XSEM_REG_XSEM_PRTY_STS_0);
4670                                         _print_parity(bp,
4671                                                       XSEM_REG_XSEM_PRTY_STS_1);
4672                                 }
4673                                 break;
4674                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4675                                 if (print) {
4676                                         _print_next_block((*par_num)++,
4677                                                           "DOORBELLQ");
4678                                         _print_parity(bp,
4679                                                       DORQ_REG_DORQ_PRTY_STS);
4680                                 }
4681                                 break;
4682                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4683                                 if (print) {
4684                                         _print_next_block((*par_num)++, "NIG");
4685                                         if (CHIP_IS_E1x(bp)) {
4686                                                 _print_parity(bp,
4687                                                         NIG_REG_NIG_PRTY_STS);
4688                                         } else {
4689                                                 _print_parity(bp,
4690                                                         NIG_REG_NIG_PRTY_STS_0);
4691                                                 _print_parity(bp,
4692                                                         NIG_REG_NIG_PRTY_STS_1);
4693                                         }
4694                                 }
4695                                 break;
4696                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4697                                 if (print)
4698                                         _print_next_block((*par_num)++,
4699                                                           "VAUX PCI CORE");
4700                                 *global = true;
4701                                 break;
4702                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4703                                 if (print) {
4704                                         _print_next_block((*par_num)++,
4705                                                           "DEBUG");
4706                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4707                                 }
4708                                 break;
4709                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4710                                 if (print) {
4711                                         _print_next_block((*par_num)++, "USDM");
4712                                         _print_parity(bp,
4713                                                       USDM_REG_USDM_PRTY_STS);
4714                                 }
4715                                 break;
4716                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4717                                 if (print) {
4718                                         _print_next_block((*par_num)++, "UCM");
4719                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4720                                 }
4721                                 break;
4722                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4723                                 if (print) {
4724                                         _print_next_block((*par_num)++,
4725                                                           "USEMI");
4726                                         _print_parity(bp,
4727                                                       USEM_REG_USEM_PRTY_STS_0);
4728                                         _print_parity(bp,
4729                                                       USEM_REG_USEM_PRTY_STS_1);
4730                                 }
4731                                 break;
4732                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4733                                 if (print) {
4734                                         _print_next_block((*par_num)++, "UPB");
4735                                         _print_parity(bp, GRCBASE_UPB +
4736                                                           PB_REG_PB_PRTY_STS);
4737                                 }
4738                                 break;
4739                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4740                                 if (print) {
4741                                         _print_next_block((*par_num)++, "CSDM");
4742                                         _print_parity(bp,
4743                                                       CSDM_REG_CSDM_PRTY_STS);
4744                                 }
4745                                 break;
4746                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4747                                 if (print) {
4748                                         _print_next_block((*par_num)++, "CCM");
4749                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4750                                 }
4751                                 break;
4752                         }
4753
4754                         /* Clear the bit */
4755                         sig &= ~cur_bit;
4756                 }
4757         }
4758
4759         return res;
4760 }
4761
4762 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4763                                             int *par_num, bool print)
4764 {
4765         u32 cur_bit;
4766         bool res;
4767         int i;
4768
4769         res = false;
4770
4771         for (i = 0; sig; i++) {
4772                 cur_bit = (0x1UL << i);
4773                 if (sig & cur_bit) {
4774                         res = true; /* Each bit is real error! */
4775                         if (print) {
4776                                 switch (cur_bit) {
4777                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4778                                         _print_next_block((*par_num)++,
4779                                                           "CSEMI");
4780                                         _print_parity(bp,
4781                                                       CSEM_REG_CSEM_PRTY_STS_0);
4782                                         _print_parity(bp,
4783                                                       CSEM_REG_CSEM_PRTY_STS_1);
4784                                         break;
4785                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4786                                         _print_next_block((*par_num)++, "PXP");
4787                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4788                                         _print_parity(bp,
4789                                                       PXP2_REG_PXP2_PRTY_STS_0);
4790                                         _print_parity(bp,
4791                                                       PXP2_REG_PXP2_PRTY_STS_1);
4792                                         break;
4793                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4794                                         _print_next_block((*par_num)++,
4795                                                           "PXPPCICLOCKCLIENT");
4796                                         break;
4797                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4798                                         _print_next_block((*par_num)++, "CFC");
4799                                         _print_parity(bp,
4800                                                       CFC_REG_CFC_PRTY_STS);
4801                                         break;
4802                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4803                                         _print_next_block((*par_num)++, "CDU");
4804                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4805                                         break;
4806                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4807                                         _print_next_block((*par_num)++, "DMAE");
4808                                         _print_parity(bp,
4809                                                       DMAE_REG_DMAE_PRTY_STS);
4810                                         break;
4811                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4812                                         _print_next_block((*par_num)++, "IGU");
4813                                         if (CHIP_IS_E1x(bp))
4814                                                 _print_parity(bp,
4815                                                         HC_REG_HC_PRTY_STS);
4816                                         else
4817                                                 _print_parity(bp,
4818                                                         IGU_REG_IGU_PRTY_STS);
4819                                         break;
4820                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4821                                         _print_next_block((*par_num)++, "MISC");
4822                                         _print_parity(bp,
4823                                                       MISC_REG_MISC_PRTY_STS);
4824                                         break;
4825                                 }
4826                         }
4827
4828                         /* Clear the bit */
4829                         sig &= ~cur_bit;
4830                 }
4831         }
4832
4833         return res;
4834 }
4835
4836 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4837                                             int *par_num, bool *global,
4838                                             bool print)
4839 {
4840         bool res = false;
4841         u32 cur_bit;
4842         int i;
4843
4844         for (i = 0; sig; i++) {
4845                 cur_bit = (0x1UL << i);
4846                 if (sig & cur_bit) {
4847                         switch (cur_bit) {
4848                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4849                                 if (print)
4850                                         _print_next_block((*par_num)++,
4851                                                           "MCP ROM");
4852                                 *global = true;
4853                                 res = true;
4854                                 break;
4855                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4856                                 if (print)
4857                                         _print_next_block((*par_num)++,
4858                                                           "MCP UMP RX");
4859                                 *global = true;
4860                                 res = true;
4861                                 break;
4862                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4863                                 if (print)
4864                                         _print_next_block((*par_num)++,
4865                                                           "MCP UMP TX");
4866                                 *global = true;
4867                                 res = true;
4868                                 break;
4869                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4870                                 if (print)
4871                                         _print_next_block((*par_num)++,
4872                                                           "MCP SCPAD");
4873                                 /* clear latched SCPAD PATIRY from MCP */
4874                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4875                                        1UL << 10);
4876                                 break;
4877                         }
4878
4879                         /* Clear the bit */
4880                         sig &= ~cur_bit;
4881                 }
4882         }
4883
4884         return res;
4885 }
4886
4887 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4888                                             int *par_num, bool print)
4889 {
4890         u32 cur_bit;
4891         bool res;
4892         int i;
4893
4894         res = false;
4895
4896         for (i = 0; sig; i++) {
4897                 cur_bit = (0x1UL << i);
4898                 if (sig & cur_bit) {
4899                         res = true; /* Each bit is real error! */
4900                         if (print) {
4901                                 switch (cur_bit) {
4902                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4903                                         _print_next_block((*par_num)++,
4904                                                           "PGLUE_B");
4905                                         _print_parity(bp,
4906                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4907                                         break;
4908                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4909                                         _print_next_block((*par_num)++, "ATC");
4910                                         _print_parity(bp,
4911                                                       ATC_REG_ATC_PRTY_STS);
4912                                         break;
4913                                 }
4914                         }
4915                         /* Clear the bit */
4916                         sig &= ~cur_bit;
4917                 }
4918         }
4919
4920         return res;
4921 }
4922
4923 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4924                               u32 *sig)
4925 {
4926         bool res = false;
4927
4928         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4929             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4930             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4931             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4932             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4933                 int par_num = 0;
4934                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4935                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4936                           sig[0] & HW_PRTY_ASSERT_SET_0,
4937                           sig[1] & HW_PRTY_ASSERT_SET_1,
4938                           sig[2] & HW_PRTY_ASSERT_SET_2,
4939                           sig[3] & HW_PRTY_ASSERT_SET_3,
4940                           sig[4] & HW_PRTY_ASSERT_SET_4);
4941                 if (print)
4942                         netdev_err(bp->dev,
4943                                    "Parity errors detected in blocks: ");
4944                 res |= bnx2x_check_blocks_with_parity0(bp,
4945                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4946                 res |= bnx2x_check_blocks_with_parity1(bp,
4947                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4948                 res |= bnx2x_check_blocks_with_parity2(bp,
4949                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4950                 res |= bnx2x_check_blocks_with_parity3(bp,
4951                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4952                 res |= bnx2x_check_blocks_with_parity4(bp,
4953                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4954
4955                 if (print)
4956                         pr_cont("\n");
4957         }
4958
4959         return res;
4960 }
4961
4962 /**
4963  * bnx2x_chk_parity_attn - checks for parity attentions.
4964  *
4965  * @bp:         driver handle
4966  * @global:     true if there was a global attention
4967  * @print:      show parity attention in syslog
4968  */
4969 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4970 {
4971         struct attn_route attn = { {0} };
4972         int port = BP_PORT(bp);
4973
4974         attn.sig[0] = REG_RD(bp,
4975                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4976                              port*4);
4977         attn.sig[1] = REG_RD(bp,
4978                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4979                              port*4);
4980         attn.sig[2] = REG_RD(bp,
4981                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4982                              port*4);
4983         attn.sig[3] = REG_RD(bp,
4984                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4985                              port*4);
4986         /* Since MCP attentions can't be disabled inside the block, we need to
4987          * read AEU registers to see whether they're currently disabled
4988          */
4989         attn.sig[3] &= ((REG_RD(bp,
4990                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4991                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4992                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4993                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4994
4995         if (!CHIP_IS_E1x(bp))
4996                 attn.sig[4] = REG_RD(bp,
4997                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4998                                      port*4);
4999
5000         return bnx2x_parity_attn(bp, global, print, attn.sig);
5001 }
5002
5003 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5004 {
5005         u32 val;
5006         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5007
5008                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5009                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5010                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5011                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5012                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5013                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5014                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5015                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5016                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5017                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5018                 if (val &
5019                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5020                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5021                 if (val &
5022                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5023                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5024                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5025                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5026                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5027                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5028                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5029                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5030         }
5031         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5032                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5033                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5034                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5035                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5036                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5037                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5038                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5039                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5040                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5041                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5042                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5043                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5044                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5045                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5046         }
5047
5048         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5049                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5050                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5051                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5052                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5053         }
5054 }
5055
5056 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5057 {
5058         struct attn_route attn, *group_mask;
5059         int port = BP_PORT(bp);
5060         int index;
5061         u32 reg_addr;
5062         u32 val;
5063         u32 aeu_mask;
5064         bool global = false;
5065
5066         /* need to take HW lock because MCP or other port might also
5067            try to handle this event */
5068         bnx2x_acquire_alr(bp);
5069
5070         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5071 #ifndef BNX2X_STOP_ON_ERROR
5072                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5073                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5074                 /* Disable HW interrupts */
5075                 bnx2x_int_disable(bp);
5076                 /* In case of parity errors don't handle attentions so that
5077                  * other function would "see" parity errors.
5078                  */
5079 #else
5080                 bnx2x_panic();
5081 #endif
5082                 bnx2x_release_alr(bp);
5083                 return;
5084         }
5085
5086         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5087         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5088         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5089         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5090         if (!CHIP_IS_E1x(bp))
5091                 attn.sig[4] =
5092                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5093         else
5094                 attn.sig[4] = 0;
5095
5096         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5097            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5098
5099         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5100                 if (deasserted & (1 << index)) {
5101                         group_mask = &bp->attn_group[index];
5102
5103                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5104                            index,
5105                            group_mask->sig[0], group_mask->sig[1],
5106                            group_mask->sig[2], group_mask->sig[3],
5107                            group_mask->sig[4]);
5108
5109                         bnx2x_attn_int_deasserted4(bp,
5110                                         attn.sig[4] & group_mask->sig[4]);
5111                         bnx2x_attn_int_deasserted3(bp,
5112                                         attn.sig[3] & group_mask->sig[3]);
5113                         bnx2x_attn_int_deasserted1(bp,
5114                                         attn.sig[1] & group_mask->sig[1]);
5115                         bnx2x_attn_int_deasserted2(bp,
5116                                         attn.sig[2] & group_mask->sig[2]);
5117                         bnx2x_attn_int_deasserted0(bp,
5118                                         attn.sig[0] & group_mask->sig[0]);
5119                 }
5120         }
5121
5122         bnx2x_release_alr(bp);
5123
5124         if (bp->common.int_block == INT_BLOCK_HC)
5125                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5126                             COMMAND_REG_ATTN_BITS_CLR);
5127         else
5128                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5129
5130         val = ~deasserted;
5131         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5132            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5133         REG_WR(bp, reg_addr, val);
5134
5135         if (~bp->attn_state & deasserted)
5136                 BNX2X_ERR("IGU ERROR\n");
5137
5138         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5139                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5140
5141         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5142         aeu_mask = REG_RD(bp, reg_addr);
5143
5144         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5145            aeu_mask, deasserted);
5146         aeu_mask |= (deasserted & 0x3ff);
5147         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5148
5149         REG_WR(bp, reg_addr, aeu_mask);
5150         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5151
5152         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5153         bp->attn_state &= ~deasserted;
5154         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5155 }
5156
5157 static void bnx2x_attn_int(struct bnx2x *bp)
5158 {
5159         /* read local copy of bits */
5160         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5161                                                                 attn_bits);
5162         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5163                                                                 attn_bits_ack);
5164         u32 attn_state = bp->attn_state;
5165
5166         /* look for changed bits */
5167         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5168         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5169
5170         DP(NETIF_MSG_HW,
5171            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5172            attn_bits, attn_ack, asserted, deasserted);
5173
5174         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5175                 BNX2X_ERR("BAD attention state\n");
5176
5177         /* handle bits that were raised */
5178         if (asserted)
5179                 bnx2x_attn_int_asserted(bp, asserted);
5180
5181         if (deasserted)
5182                 bnx2x_attn_int_deasserted(bp, deasserted);
5183 }
5184
5185 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5186                       u16 index, u8 op, u8 update)
5187 {
5188         u32 igu_addr = bp->igu_base_addr;
5189         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5190         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5191                              igu_addr);
5192 }
5193
5194 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5195 {
5196         /* No memory barriers */
5197         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5198         mmiowb(); /* keep prod updates ordered */
5199 }
5200
5201 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5202                                       union event_ring_elem *elem)
5203 {
5204         u8 err = elem->message.error;
5205
5206         if (!bp->cnic_eth_dev.starting_cid  ||
5207             (cid < bp->cnic_eth_dev.starting_cid &&
5208             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5209                 return 1;
5210
5211         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5212
5213         if (unlikely(err)) {
5214
5215                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5216                           cid);
5217                 bnx2x_panic_dump(bp, false);
5218         }
5219         bnx2x_cnic_cfc_comp(bp, cid, err);
5220         return 0;
5221 }
5222
5223 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5224 {
5225         struct bnx2x_mcast_ramrod_params rparam;
5226         int rc;
5227
5228         memset(&rparam, 0, sizeof(rparam));
5229
5230         rparam.mcast_obj = &bp->mcast_obj;
5231
5232         netif_addr_lock_bh(bp->dev);
5233
5234         /* Clear pending state for the last command */
5235         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5236
5237         /* If there are pending mcast commands - send them */
5238         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5239                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5240                 if (rc < 0)
5241                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5242                                   rc);
5243         }
5244
5245         netif_addr_unlock_bh(bp->dev);
5246 }
5247
5248 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5249                                             union event_ring_elem *elem)
5250 {
5251         unsigned long ramrod_flags = 0;
5252         int rc = 0;
5253         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5254         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5255
5256         /* Always push next commands out, don't wait here */
5257         __set_bit(RAMROD_CONT, &ramrod_flags);
5258
5259         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5260                             >> BNX2X_SWCID_SHIFT) {
5261         case BNX2X_FILTER_MAC_PENDING:
5262                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5263                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5264                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5265                 else
5266                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5267
5268                 break;
5269         case BNX2X_FILTER_MCAST_PENDING:
5270                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5271                 /* This is only relevant for 57710 where multicast MACs are
5272                  * configured as unicast MACs using the same ramrod.
5273                  */
5274                 bnx2x_handle_mcast_eqe(bp);
5275                 return;
5276         default:
5277                 BNX2X_ERR("Unsupported classification command: %d\n",
5278                           elem->message.data.eth_event.echo);
5279                 return;
5280         }
5281
5282         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5283
5284         if (rc < 0)
5285                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5286         else if (rc > 0)
5287                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5288 }
5289
5290 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5291
5292 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5293 {
5294         netif_addr_lock_bh(bp->dev);
5295
5296         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5297
5298         /* Send rx_mode command again if was requested */
5299         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5300                 bnx2x_set_storm_rx_mode(bp);
5301         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5302                                     &bp->sp_state))
5303                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5304         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5305                                     &bp->sp_state))
5306                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5307
5308         netif_addr_unlock_bh(bp->dev);
5309 }
5310
5311 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5312                                               union event_ring_elem *elem)
5313 {
5314         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5315                 DP(BNX2X_MSG_SP,
5316                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5317                    elem->message.data.vif_list_event.func_bit_map);
5318                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5319                         elem->message.data.vif_list_event.func_bit_map);
5320         } else if (elem->message.data.vif_list_event.echo ==
5321                    VIF_LIST_RULE_SET) {
5322                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5323                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5324         }
5325 }
5326
5327 /* called with rtnl_lock */
5328 static void bnx2x_after_function_update(struct bnx2x *bp)
5329 {
5330         int q, rc;
5331         struct bnx2x_fastpath *fp;
5332         struct bnx2x_queue_state_params queue_params = {NULL};
5333         struct bnx2x_queue_update_params *q_update_params =
5334                 &queue_params.params.update;
5335
5336         /* Send Q update command with afex vlan removal values for all Qs */
5337         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5338
5339         /* set silent vlan removal values according to vlan mode */
5340         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5341                   &q_update_params->update_flags);
5342         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5343                   &q_update_params->update_flags);
5344         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5345
5346         /* in access mode mark mask and value are 0 to strip all vlans */
5347         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5348                 q_update_params->silent_removal_value = 0;
5349                 q_update_params->silent_removal_mask = 0;
5350         } else {
5351                 q_update_params->silent_removal_value =
5352                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5353                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5354         }
5355
5356         for_each_eth_queue(bp, q) {
5357                 /* Set the appropriate Queue object */
5358                 fp = &bp->fp[q];
5359                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5360
5361                 /* send the ramrod */
5362                 rc = bnx2x_queue_state_change(bp, &queue_params);
5363                 if (rc < 0)
5364                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5365                                   q);
5366         }
5367
5368         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5369                 fp = &bp->fp[FCOE_IDX(bp)];
5370                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5371
5372                 /* clear pending completion bit */
5373                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5374
5375                 /* mark latest Q bit */
5376                 smp_mb__before_atomic();
5377                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5378                 smp_mb__after_atomic();
5379
5380                 /* send Q update ramrod for FCoE Q */
5381                 rc = bnx2x_queue_state_change(bp, &queue_params);
5382                 if (rc < 0)
5383                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5384                                   q);
5385         } else {
5386                 /* If no FCoE ring - ACK MCP now */
5387                 bnx2x_link_report(bp);
5388                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5389         }
5390 }
5391
5392 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5393         struct bnx2x *bp, u32 cid)
5394 {
5395         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5396
5397         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5398                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5399         else
5400                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5401 }
5402
5403 static void bnx2x_eq_int(struct bnx2x *bp)
5404 {
5405         u16 hw_cons, sw_cons, sw_prod;
5406         union event_ring_elem *elem;
5407         u8 echo;
5408         u32 cid;
5409         u8 opcode;
5410         int rc, spqe_cnt = 0;
5411         struct bnx2x_queue_sp_obj *q_obj;
5412         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5413         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5414
5415         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5416
5417         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5418          * when we get the next-page we need to adjust so the loop
5419          * condition below will be met. The next element is the size of a
5420          * regular element and hence incrementing by 1
5421          */
5422         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5423                 hw_cons++;
5424
5425         /* This function may never run in parallel with itself for a
5426          * specific bp, thus there is no need in "paired" read memory
5427          * barrier here.
5428          */
5429         sw_cons = bp->eq_cons;
5430         sw_prod = bp->eq_prod;
5431
5432         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5433                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5434
5435         for (; sw_cons != hw_cons;
5436               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5437
5438                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5439
5440                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5441                 if (!rc) {
5442                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5443                            rc);
5444                         goto next_spqe;
5445                 }
5446
5447                 /* elem CID originates from FW; actually LE */
5448                 cid = SW_CID((__force __le32)
5449                              elem->message.data.cfc_del_event.cid);
5450                 opcode = elem->message.opcode;
5451
5452                 /* handle eq element */
5453                 switch (opcode) {
5454                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5455                         bnx2x_vf_mbx_schedule(bp,
5456                                               &elem->message.data.vf_pf_event);
5457                         continue;
5458
5459                 case EVENT_RING_OPCODE_STAT_QUERY:
5460                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5461                                "got statistics comp event %d\n",
5462                                bp->stats_comp++);
5463                         /* nothing to do with stats comp */
5464                         goto next_spqe;
5465
5466                 case EVENT_RING_OPCODE_CFC_DEL:
5467                         /* handle according to cid range */
5468                         /*
5469                          * we may want to verify here that the bp state is
5470                          * HALTING
5471                          */
5472                         DP(BNX2X_MSG_SP,
5473                            "got delete ramrod for MULTI[%d]\n", cid);
5474
5475                         if (CNIC_LOADED(bp) &&
5476                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5477                                 goto next_spqe;
5478
5479                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5480
5481                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5482                                 break;
5483
5484                         goto next_spqe;
5485
5486                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5487                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5488                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5489                         if (f_obj->complete_cmd(bp, f_obj,
5490                                                 BNX2X_F_CMD_TX_STOP))
5491                                 break;
5492                         goto next_spqe;
5493
5494                 case EVENT_RING_OPCODE_START_TRAFFIC:
5495                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5496                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5497                         if (f_obj->complete_cmd(bp, f_obj,
5498                                                 BNX2X_F_CMD_TX_START))
5499                                 break;
5500                         goto next_spqe;
5501
5502                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5503                         echo = elem->message.data.function_update_event.echo;
5504                         if (echo == SWITCH_UPDATE) {
5505                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5506                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5507                                 if (f_obj->complete_cmd(
5508                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5509                                         break;
5510
5511                         } else {
5512                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5513
5514                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5515                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5516                                 f_obj->complete_cmd(bp, f_obj,
5517                                                     BNX2X_F_CMD_AFEX_UPDATE);
5518
5519                                 /* We will perform the Queues update from
5520                                  * sp_rtnl task as all Queue SP operations
5521                                  * should run under rtnl_lock.
5522                                  */
5523                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5524                         }
5525
5526                         goto next_spqe;
5527
5528                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5529                         f_obj->complete_cmd(bp, f_obj,
5530                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5531                         bnx2x_after_afex_vif_lists(bp, elem);
5532                         goto next_spqe;
5533                 case EVENT_RING_OPCODE_FUNCTION_START:
5534                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5535                            "got FUNC_START ramrod\n");
5536                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5537                                 break;
5538
5539                         goto next_spqe;
5540
5541                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5542                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5543                            "got FUNC_STOP ramrod\n");
5544                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5545                                 break;
5546
5547                         goto next_spqe;
5548
5549                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5550                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5551                            "got set_timesync ramrod completion\n");
5552                         if (f_obj->complete_cmd(bp, f_obj,
5553                                                 BNX2X_F_CMD_SET_TIMESYNC))
5554                                 break;
5555                         goto next_spqe;
5556                 }
5557
5558                 switch (opcode | bp->state) {
5559                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5560                       BNX2X_STATE_OPEN):
5561                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5562                       BNX2X_STATE_OPENING_WAIT4_PORT):
5563                         cid = elem->message.data.eth_event.echo &
5564                                 BNX2X_SWCID_MASK;
5565                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5566                            cid);
5567                         rss_raw->clear_pending(rss_raw);
5568                         break;
5569
5570                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5571                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5572                 case (EVENT_RING_OPCODE_SET_MAC |
5573                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5574                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5575                       BNX2X_STATE_OPEN):
5576                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5577                       BNX2X_STATE_DIAG):
5578                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5579                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5580                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5581                         bnx2x_handle_classification_eqe(bp, elem);
5582                         break;
5583
5584                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5585                       BNX2X_STATE_OPEN):
5586                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5587                       BNX2X_STATE_DIAG):
5588                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5589                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5590                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5591                         bnx2x_handle_mcast_eqe(bp);
5592                         break;
5593
5594                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5595                       BNX2X_STATE_OPEN):
5596                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5597                       BNX2X_STATE_DIAG):
5598                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5599                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5600                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5601                         bnx2x_handle_rx_mode_eqe(bp);
5602                         break;
5603                 default:
5604                         /* unknown event log error and continue */
5605                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5606                                   elem->message.opcode, bp->state);
5607                 }
5608 next_spqe:
5609                 spqe_cnt++;
5610         } /* for */
5611
5612         smp_mb__before_atomic();
5613         atomic_add(spqe_cnt, &bp->eq_spq_left);
5614
5615         bp->eq_cons = sw_cons;
5616         bp->eq_prod = sw_prod;
5617         /* Make sure that above mem writes were issued towards the memory */
5618         smp_wmb();
5619
5620         /* update producer */
5621         bnx2x_update_eq_prod(bp, bp->eq_prod);
5622 }
5623
5624 static void bnx2x_sp_task(struct work_struct *work)
5625 {
5626         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5627
5628         DP(BNX2X_MSG_SP, "sp task invoked\n");
5629
5630         /* make sure the atomic interrupt_occurred has been written */
5631         smp_rmb();
5632         if (atomic_read(&bp->interrupt_occurred)) {
5633
5634                 /* what work needs to be performed? */
5635                 u16 status = bnx2x_update_dsb_idx(bp);
5636
5637                 DP(BNX2X_MSG_SP, "status %x\n", status);
5638                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5639                 atomic_set(&bp->interrupt_occurred, 0);
5640
5641                 /* HW attentions */
5642                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5643                         bnx2x_attn_int(bp);
5644                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5645                 }
5646
5647                 /* SP events: STAT_QUERY and others */
5648                 if (status & BNX2X_DEF_SB_IDX) {
5649                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5650
5651                 if (FCOE_INIT(bp) &&
5652                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5653                                 /* Prevent local bottom-halves from running as
5654                                  * we are going to change the local NAPI list.
5655                                  */
5656                                 local_bh_disable();
5657                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5658                                 local_bh_enable();
5659                         }
5660
5661                         /* Handle EQ completions */
5662                         bnx2x_eq_int(bp);
5663                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5664                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5665
5666                         status &= ~BNX2X_DEF_SB_IDX;
5667                 }
5668
5669                 /* if status is non zero then perhaps something went wrong */
5670                 if (unlikely(status))
5671                         DP(BNX2X_MSG_SP,
5672                            "got an unknown interrupt! (status 0x%x)\n", status);
5673
5674                 /* ack status block only if something was actually handled */
5675                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5676                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5677         }
5678
5679         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5680         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5681                                &bp->sp_state)) {
5682                 bnx2x_link_report(bp);
5683                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5684         }
5685 }
5686
5687 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5688 {
5689         struct net_device *dev = dev_instance;
5690         struct bnx2x *bp = netdev_priv(dev);
5691
5692         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5693                      IGU_INT_DISABLE, 0);
5694
5695 #ifdef BNX2X_STOP_ON_ERROR
5696         if (unlikely(bp->panic))
5697                 return IRQ_HANDLED;
5698 #endif
5699
5700         if (CNIC_LOADED(bp)) {
5701                 struct cnic_ops *c_ops;
5702
5703                 rcu_read_lock();
5704                 c_ops = rcu_dereference(bp->cnic_ops);
5705                 if (c_ops)
5706                         c_ops->cnic_handler(bp->cnic_data, NULL);
5707                 rcu_read_unlock();
5708         }
5709
5710         /* schedule sp task to perform default status block work, ack
5711          * attentions and enable interrupts.
5712          */
5713         bnx2x_schedule_sp_task(bp);
5714
5715         return IRQ_HANDLED;
5716 }
5717
5718 /* end of slow path */
5719
5720 void bnx2x_drv_pulse(struct bnx2x *bp)
5721 {
5722         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5723                  bp->fw_drv_pulse_wr_seq);
5724 }
5725
5726 static void bnx2x_timer(unsigned long data)
5727 {
5728         struct bnx2x *bp = (struct bnx2x *) data;
5729
5730         if (!netif_running(bp->dev))
5731                 return;
5732
5733         if (IS_PF(bp) &&
5734             !BP_NOMCP(bp)) {
5735                 int mb_idx = BP_FW_MB_IDX(bp);
5736                 u16 drv_pulse;
5737                 u16 mcp_pulse;
5738
5739                 ++bp->fw_drv_pulse_wr_seq;
5740                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5741                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5742                 bnx2x_drv_pulse(bp);
5743
5744                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5745                              MCP_PULSE_SEQ_MASK);
5746                 /* The delta between driver pulse and mcp response
5747                  * should not get too big. If the MFW is more than 5 pulses
5748                  * behind, we should worry about it enough to generate an error
5749                  * log.
5750                  */
5751                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5752                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5753                                   drv_pulse, mcp_pulse);
5754         }
5755
5756         if (bp->state == BNX2X_STATE_OPEN)
5757                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5758
5759         /* sample pf vf bulletin board for new posts from pf */
5760         if (IS_VF(bp))
5761                 bnx2x_timer_sriov(bp);
5762
5763         mod_timer(&bp->timer, jiffies + bp->current_interval);
5764 }
5765
5766 /* end of Statistics */
5767
5768 /* nic init */
5769
5770 /*
5771  * nic init service functions
5772  */
5773
5774 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5775 {
5776         u32 i;
5777         if (!(len%4) && !(addr%4))
5778                 for (i = 0; i < len; i += 4)
5779                         REG_WR(bp, addr + i, fill);
5780         else
5781                 for (i = 0; i < len; i++)
5782                         REG_WR8(bp, addr + i, fill);
5783 }
5784
5785 /* helper: writes FP SP data to FW - data_size in dwords */
5786 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5787                                 int fw_sb_id,
5788                                 u32 *sb_data_p,
5789                                 u32 data_size)
5790 {
5791         int index;
5792         for (index = 0; index < data_size; index++)
5793                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5794                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5795                         sizeof(u32)*index,
5796                         *(sb_data_p + index));
5797 }
5798
5799 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5800 {
5801         u32 *sb_data_p;
5802         u32 data_size = 0;
5803         struct hc_status_block_data_e2 sb_data_e2;
5804         struct hc_status_block_data_e1x sb_data_e1x;
5805
5806         /* disable the function first */
5807         if (!CHIP_IS_E1x(bp)) {
5808                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5809                 sb_data_e2.common.state = SB_DISABLED;
5810                 sb_data_e2.common.p_func.vf_valid = false;
5811                 sb_data_p = (u32 *)&sb_data_e2;
5812                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5813         } else {
5814                 memset(&sb_data_e1x, 0,
5815                        sizeof(struct hc_status_block_data_e1x));
5816                 sb_data_e1x.common.state = SB_DISABLED;
5817                 sb_data_e1x.common.p_func.vf_valid = false;
5818                 sb_data_p = (u32 *)&sb_data_e1x;
5819                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5820         }
5821         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5822
5823         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5824                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5825                         CSTORM_STATUS_BLOCK_SIZE);
5826         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5827                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5828                         CSTORM_SYNC_BLOCK_SIZE);
5829 }
5830
5831 /* helper:  writes SP SB data to FW */
5832 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5833                 struct hc_sp_status_block_data *sp_sb_data)
5834 {
5835         int func = BP_FUNC(bp);
5836         int i;
5837         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5838                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5839                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5840                         i*sizeof(u32),
5841                         *((u32 *)sp_sb_data + i));
5842 }
5843
5844 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5845 {
5846         int func = BP_FUNC(bp);
5847         struct hc_sp_status_block_data sp_sb_data;
5848         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5849
5850         sp_sb_data.state = SB_DISABLED;
5851         sp_sb_data.p_func.vf_valid = false;
5852
5853         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5854
5855         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5856                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5857                         CSTORM_SP_STATUS_BLOCK_SIZE);
5858         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5859                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5860                         CSTORM_SP_SYNC_BLOCK_SIZE);
5861 }
5862
5863 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5864                                            int igu_sb_id, int igu_seg_id)
5865 {
5866         hc_sm->igu_sb_id = igu_sb_id;
5867         hc_sm->igu_seg_id = igu_seg_id;
5868         hc_sm->timer_value = 0xFF;
5869         hc_sm->time_to_expire = 0xFFFFFFFF;
5870 }
5871
5872 /* allocates state machine ids. */
5873 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5874 {
5875         /* zero out state machine indices */
5876         /* rx indices */
5877         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5878
5879         /* tx indices */
5880         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5881         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5882         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5883         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5884
5885         /* map indices */
5886         /* rx indices */
5887         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5888                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5889
5890         /* tx indices */
5891         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5892                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5893         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5894                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5895         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5896                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5897         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5898                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5899 }
5900
5901 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5902                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5903 {
5904         int igu_seg_id;
5905
5906         struct hc_status_block_data_e2 sb_data_e2;
5907         struct hc_status_block_data_e1x sb_data_e1x;
5908         struct hc_status_block_sm  *hc_sm_p;
5909         int data_size;
5910         u32 *sb_data_p;
5911
5912         if (CHIP_INT_MODE_IS_BC(bp))
5913                 igu_seg_id = HC_SEG_ACCESS_NORM;
5914         else
5915                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5916
5917         bnx2x_zero_fp_sb(bp, fw_sb_id);
5918
5919         if (!CHIP_IS_E1x(bp)) {
5920                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5921                 sb_data_e2.common.state = SB_ENABLED;
5922                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5923                 sb_data_e2.common.p_func.vf_id = vfid;
5924                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5925                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5926                 sb_data_e2.common.same_igu_sb_1b = true;
5927                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5928                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5929                 hc_sm_p = sb_data_e2.common.state_machine;
5930                 sb_data_p = (u32 *)&sb_data_e2;
5931                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5932                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5933         } else {
5934                 memset(&sb_data_e1x, 0,
5935                        sizeof(struct hc_status_block_data_e1x));
5936                 sb_data_e1x.common.state = SB_ENABLED;
5937                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5938                 sb_data_e1x.common.p_func.vf_id = 0xff;
5939                 sb_data_e1x.common.p_func.vf_valid = false;
5940                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5941                 sb_data_e1x.common.same_igu_sb_1b = true;
5942                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5943                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5944                 hc_sm_p = sb_data_e1x.common.state_machine;
5945                 sb_data_p = (u32 *)&sb_data_e1x;
5946                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5947                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5948         }
5949
5950         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5951                                        igu_sb_id, igu_seg_id);
5952         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5953                                        igu_sb_id, igu_seg_id);
5954
5955         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5956
5957         /* write indices to HW - PCI guarantees endianity of regpairs */
5958         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5959 }
5960
5961 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5962                                      u16 tx_usec, u16 rx_usec)
5963 {
5964         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5965                                     false, rx_usec);
5966         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5967                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5968                                        tx_usec);
5969         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5970                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5971                                        tx_usec);
5972         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5973                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5974                                        tx_usec);
5975 }
5976
5977 static void bnx2x_init_def_sb(struct bnx2x *bp)
5978 {
5979         struct host_sp_status_block *def_sb = bp->def_status_blk;
5980         dma_addr_t mapping = bp->def_status_blk_mapping;
5981         int igu_sp_sb_index;
5982         int igu_seg_id;
5983         int port = BP_PORT(bp);
5984         int func = BP_FUNC(bp);
5985         int reg_offset, reg_offset_en5;
5986         u64 section;
5987         int index;
5988         struct hc_sp_status_block_data sp_sb_data;
5989         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5990
5991         if (CHIP_INT_MODE_IS_BC(bp)) {
5992                 igu_sp_sb_index = DEF_SB_IGU_ID;
5993                 igu_seg_id = HC_SEG_ACCESS_DEF;
5994         } else {
5995                 igu_sp_sb_index = bp->igu_dsb_id;
5996                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5997         }
5998
5999         /* ATTN */
6000         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6001                                             atten_status_block);
6002         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6003
6004         bp->attn_state = 0;
6005
6006         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6007                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6008         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6009                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6010         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6011                 int sindex;
6012                 /* take care of sig[0]..sig[4] */
6013                 for (sindex = 0; sindex < 4; sindex++)
6014                         bp->attn_group[index].sig[sindex] =
6015                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6016
6017                 if (!CHIP_IS_E1x(bp))
6018                         /*
6019                          * enable5 is separate from the rest of the registers,
6020                          * and therefore the address skip is 4
6021                          * and not 16 between the different groups
6022                          */
6023                         bp->attn_group[index].sig[4] = REG_RD(bp,
6024                                         reg_offset_en5 + 0x4*index);
6025                 else
6026                         bp->attn_group[index].sig[4] = 0;
6027         }
6028
6029         if (bp->common.int_block == INT_BLOCK_HC) {
6030                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6031                                      HC_REG_ATTN_MSG0_ADDR_L);
6032
6033                 REG_WR(bp, reg_offset, U64_LO(section));
6034                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6035         } else if (!CHIP_IS_E1x(bp)) {
6036                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6037                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6038         }
6039
6040         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6041                                             sp_sb);
6042
6043         bnx2x_zero_sp_sb(bp);
6044
6045         /* PCI guarantees endianity of regpairs */
6046         sp_sb_data.state                = SB_ENABLED;
6047         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6048         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6049         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6050         sp_sb_data.igu_seg_id           = igu_seg_id;
6051         sp_sb_data.p_func.pf_id         = func;
6052         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6053         sp_sb_data.p_func.vf_id         = 0xff;
6054
6055         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6056
6057         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6058 }
6059
6060 void bnx2x_update_coalesce(struct bnx2x *bp)
6061 {
6062         int i;
6063
6064         for_each_eth_queue(bp, i)
6065                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6066                                          bp->tx_ticks, bp->rx_ticks);
6067 }
6068
6069 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6070 {
6071         spin_lock_init(&bp->spq_lock);
6072         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6073
6074         bp->spq_prod_idx = 0;
6075         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6076         bp->spq_prod_bd = bp->spq;
6077         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6078 }
6079
6080 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6081 {
6082         int i;
6083         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6084                 union event_ring_elem *elem =
6085                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6086
6087                 elem->next_page.addr.hi =
6088                         cpu_to_le32(U64_HI(bp->eq_mapping +
6089                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6090                 elem->next_page.addr.lo =
6091                         cpu_to_le32(U64_LO(bp->eq_mapping +
6092                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6093         }
6094         bp->eq_cons = 0;
6095         bp->eq_prod = NUM_EQ_DESC;
6096         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6097         /* we want a warning message before it gets wrought... */
6098         atomic_set(&bp->eq_spq_left,
6099                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6100 }
6101
6102 /* called with netif_addr_lock_bh() */
6103 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6104                                unsigned long rx_mode_flags,
6105                                unsigned long rx_accept_flags,
6106                                unsigned long tx_accept_flags,
6107                                unsigned long ramrod_flags)
6108 {
6109         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6110         int rc;
6111
6112         memset(&ramrod_param, 0, sizeof(ramrod_param));
6113
6114         /* Prepare ramrod parameters */
6115         ramrod_param.cid = 0;
6116         ramrod_param.cl_id = cl_id;
6117         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6118         ramrod_param.func_id = BP_FUNC(bp);
6119
6120         ramrod_param.pstate = &bp->sp_state;
6121         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6122
6123         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6124         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6125
6126         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6127
6128         ramrod_param.ramrod_flags = ramrod_flags;
6129         ramrod_param.rx_mode_flags = rx_mode_flags;
6130
6131         ramrod_param.rx_accept_flags = rx_accept_flags;
6132         ramrod_param.tx_accept_flags = tx_accept_flags;
6133
6134         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6135         if (rc < 0) {
6136                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6137                 return rc;
6138         }
6139
6140         return 0;
6141 }
6142
6143 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6144                                    unsigned long *rx_accept_flags,
6145                                    unsigned long *tx_accept_flags)
6146 {
6147         /* Clear the flags first */
6148         *rx_accept_flags = 0;
6149         *tx_accept_flags = 0;
6150
6151         switch (rx_mode) {
6152         case BNX2X_RX_MODE_NONE:
6153                 /*
6154                  * 'drop all' supersedes any accept flags that may have been
6155                  * passed to the function.
6156                  */
6157                 break;
6158         case BNX2X_RX_MODE_NORMAL:
6159                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6160                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6161                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6162
6163                 /* internal switching mode */
6164                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6165                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6166                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6167
6168                 break;
6169         case BNX2X_RX_MODE_ALLMULTI:
6170                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6171                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6172                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6173
6174                 /* internal switching mode */
6175                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6176                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6177                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6178
6179                 break;
6180         case BNX2X_RX_MODE_PROMISC:
6181                 /* According to definition of SI mode, iface in promisc mode
6182                  * should receive matched and unmatched (in resolution of port)
6183                  * unicast packets.
6184                  */
6185                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6186                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6187                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6188                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6189
6190                 /* internal switching mode */
6191                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6192                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6193
6194                 if (IS_MF_SI(bp))
6195                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6196                 else
6197                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6198
6199                 break;
6200         default:
6201                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6202                 return -EINVAL;
6203         }
6204
6205         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6206         if (rx_mode != BNX2X_RX_MODE_NONE) {
6207                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6208                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6209         }
6210
6211         return 0;
6212 }
6213
6214 /* called with netif_addr_lock_bh() */
6215 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6216 {
6217         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6218         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6219         int rc;
6220
6221         if (!NO_FCOE(bp))
6222                 /* Configure rx_mode of FCoE Queue */
6223                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6224
6225         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6226                                      &tx_accept_flags);
6227         if (rc)
6228                 return rc;
6229
6230         __set_bit(RAMROD_RX, &ramrod_flags);
6231         __set_bit(RAMROD_TX, &ramrod_flags);
6232
6233         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6234                                    rx_accept_flags, tx_accept_flags,
6235                                    ramrod_flags);
6236 }
6237
6238 static void bnx2x_init_internal_common(struct bnx2x *bp)
6239 {
6240         int i;
6241
6242         /* Zero this manually as its initialization is
6243            currently missing in the initTool */
6244         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6245                 REG_WR(bp, BAR_USTRORM_INTMEM +
6246                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6247         if (!CHIP_IS_E1x(bp)) {
6248                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6249                         CHIP_INT_MODE_IS_BC(bp) ?
6250                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6251         }
6252 }
6253
6254 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6255 {
6256         switch (load_code) {
6257         case FW_MSG_CODE_DRV_LOAD_COMMON:
6258         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6259                 bnx2x_init_internal_common(bp);
6260                 /* no break */
6261
6262         case FW_MSG_CODE_DRV_LOAD_PORT:
6263                 /* nothing to do */
6264                 /* no break */
6265
6266         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6267                 /* internal memory per function is
6268                    initialized inside bnx2x_pf_init */
6269                 break;
6270
6271         default:
6272                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6273                 break;
6274         }
6275 }
6276
6277 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6278 {
6279         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6280 }
6281
6282 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6283 {
6284         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6285 }
6286
6287 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6288 {
6289         if (CHIP_IS_E1x(fp->bp))
6290                 return BP_L_ID(fp->bp) + fp->index;
6291         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6292                 return bnx2x_fp_igu_sb_id(fp);
6293 }
6294
6295 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6296 {
6297         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6298         u8 cos;
6299         unsigned long q_type = 0;
6300         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6301         fp->rx_queue = fp_idx;
6302         fp->cid = fp_idx;
6303         fp->cl_id = bnx2x_fp_cl_id(fp);
6304         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6305         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6306         /* qZone id equals to FW (per path) client id */
6307         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6308
6309         /* init shortcut */
6310         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6311
6312         /* Setup SB indices */
6313         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6314
6315         /* Configure Queue State object */
6316         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6317         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6318
6319         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6320
6321         /* init tx data */
6322         for_each_cos_in_tx_queue(fp, cos) {
6323                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6324                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6325                                   FP_COS_TO_TXQ(fp, cos, bp),
6326                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6327                 cids[cos] = fp->txdata_ptr[cos]->cid;
6328         }
6329
6330         /* nothing more for vf to do here */
6331         if (IS_VF(bp))
6332                 return;
6333
6334         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6335                       fp->fw_sb_id, fp->igu_sb_id);
6336         bnx2x_update_fpsb_idx(fp);
6337         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6338                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6339                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6340
6341         /**
6342          * Configure classification DBs: Always enable Tx switching
6343          */
6344         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6345
6346         DP(NETIF_MSG_IFUP,
6347            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6348            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6349            fp->igu_sb_id);
6350 }
6351
6352 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6353 {
6354         int i;
6355
6356         for (i = 1; i <= NUM_TX_RINGS; i++) {
6357                 struct eth_tx_next_bd *tx_next_bd =
6358                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6359
6360                 tx_next_bd->addr_hi =
6361                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6362                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6363                 tx_next_bd->addr_lo =
6364                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6365                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6366         }
6367
6368         *txdata->tx_cons_sb = cpu_to_le16(0);
6369
6370         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6371         txdata->tx_db.data.zero_fill1 = 0;
6372         txdata->tx_db.data.prod = 0;
6373
6374         txdata->tx_pkt_prod = 0;
6375         txdata->tx_pkt_cons = 0;
6376         txdata->tx_bd_prod = 0;
6377         txdata->tx_bd_cons = 0;
6378         txdata->tx_pkt = 0;
6379 }
6380
6381 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6382 {
6383         int i;
6384
6385         for_each_tx_queue_cnic(bp, i)
6386                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6387 }
6388
6389 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6390 {
6391         int i;
6392         u8 cos;
6393
6394         for_each_eth_queue(bp, i)
6395                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6396                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6397 }
6398
6399 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6400 {
6401         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6402         unsigned long q_type = 0;
6403
6404         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6405         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6406                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6407         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6408         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6409         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6410         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6411         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6412                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6413                           fp);
6414
6415         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6416
6417         /* qZone id equals to FW (per path) client id */
6418         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6419         /* init shortcut */
6420         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6421                 bnx2x_rx_ustorm_prods_offset(fp);
6422
6423         /* Configure Queue State object */
6424         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6425         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6426
6427         /* No multi-CoS for FCoE L2 client */
6428         BUG_ON(fp->max_cos != 1);
6429
6430         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6431                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6432                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6433
6434         DP(NETIF_MSG_IFUP,
6435            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6436            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6437            fp->igu_sb_id);
6438 }
6439
6440 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6441 {
6442         if (!NO_FCOE(bp))
6443                 bnx2x_init_fcoe_fp(bp);
6444
6445         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6446                       BNX2X_VF_ID_INVALID, false,
6447                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6448
6449         /* ensure status block indices were read */
6450         rmb();
6451         bnx2x_init_rx_rings_cnic(bp);
6452         bnx2x_init_tx_rings_cnic(bp);
6453
6454         /* flush all */
6455         mb();
6456         mmiowb();
6457 }
6458
6459 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6460 {
6461         int i;
6462
6463         /* Setup NIC internals and enable interrupts */
6464         for_each_eth_queue(bp, i)
6465                 bnx2x_init_eth_fp(bp, i);
6466
6467         /* ensure status block indices were read */
6468         rmb();
6469         bnx2x_init_rx_rings(bp);
6470         bnx2x_init_tx_rings(bp);
6471
6472         if (IS_PF(bp)) {
6473                 /* Initialize MOD_ABS interrupts */
6474                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6475                                        bp->common.shmem_base,
6476                                        bp->common.shmem2_base, BP_PORT(bp));
6477
6478                 /* initialize the default status block and sp ring */
6479                 bnx2x_init_def_sb(bp);
6480                 bnx2x_update_dsb_idx(bp);
6481                 bnx2x_init_sp_ring(bp);
6482         } else {
6483                 bnx2x_memset_stats(bp);
6484         }
6485 }
6486
6487 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6488 {
6489         bnx2x_init_eq_ring(bp);
6490         bnx2x_init_internal(bp, load_code);
6491         bnx2x_pf_init(bp);
6492         bnx2x_stats_init(bp);
6493
6494         /* flush all before enabling interrupts */
6495         mb();
6496         mmiowb();
6497
6498         bnx2x_int_enable(bp);
6499
6500         /* Check for SPIO5 */
6501         bnx2x_attn_int_deasserted0(bp,
6502                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6503                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6504 }
6505
6506 /* gzip service functions */
6507 static int bnx2x_gunzip_init(struct bnx2x *bp)
6508 {
6509         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6510                                             &bp->gunzip_mapping, GFP_KERNEL);
6511         if (bp->gunzip_buf  == NULL)
6512                 goto gunzip_nomem1;
6513
6514         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6515         if (bp->strm  == NULL)
6516                 goto gunzip_nomem2;
6517
6518         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6519         if (bp->strm->workspace == NULL)
6520                 goto gunzip_nomem3;
6521
6522         return 0;
6523
6524 gunzip_nomem3:
6525         kfree(bp->strm);
6526         bp->strm = NULL;
6527
6528 gunzip_nomem2:
6529         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6530                           bp->gunzip_mapping);
6531         bp->gunzip_buf = NULL;
6532
6533 gunzip_nomem1:
6534         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6535         return -ENOMEM;
6536 }
6537
6538 static void bnx2x_gunzip_end(struct bnx2x *bp)
6539 {
6540         if (bp->strm) {
6541                 vfree(bp->strm->workspace);
6542                 kfree(bp->strm);
6543                 bp->strm = NULL;
6544         }
6545
6546         if (bp->gunzip_buf) {
6547                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6548                                   bp->gunzip_mapping);
6549                 bp->gunzip_buf = NULL;
6550         }
6551 }
6552
6553 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6554 {
6555         int n, rc;
6556
6557         /* check gzip header */
6558         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6559                 BNX2X_ERR("Bad gzip header\n");
6560                 return -EINVAL;
6561         }
6562
6563         n = 10;
6564
6565 #define FNAME                           0x8
6566
6567         if (zbuf[3] & FNAME)
6568                 while ((zbuf[n++] != 0) && (n < len));
6569
6570         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6571         bp->strm->avail_in = len - n;
6572         bp->strm->next_out = bp->gunzip_buf;
6573         bp->strm->avail_out = FW_BUF_SIZE;
6574
6575         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6576         if (rc != Z_OK)
6577                 return rc;
6578
6579         rc = zlib_inflate(bp->strm, Z_FINISH);
6580         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6581                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6582                            bp->strm->msg);
6583
6584         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6585         if (bp->gunzip_outlen & 0x3)
6586                 netdev_err(bp->dev,
6587                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6588                                 bp->gunzip_outlen);
6589         bp->gunzip_outlen >>= 2;
6590
6591         zlib_inflateEnd(bp->strm);
6592
6593         if (rc == Z_STREAM_END)
6594                 return 0;
6595
6596         return rc;
6597 }
6598
6599 /* nic load/unload */
6600
6601 /*
6602  * General service functions
6603  */
6604
6605 /* send a NIG loopback debug packet */
6606 static void bnx2x_lb_pckt(struct bnx2x *bp)
6607 {
6608         u32 wb_write[3];
6609
6610         /* Ethernet source and destination addresses */
6611         wb_write[0] = 0x55555555;
6612         wb_write[1] = 0x55555555;
6613         wb_write[2] = 0x20;             /* SOP */
6614         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6615
6616         /* NON-IP protocol */
6617         wb_write[0] = 0x09000000;
6618         wb_write[1] = 0x55555555;
6619         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6620         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6621 }
6622
6623 /* some of the internal memories
6624  * are not directly readable from the driver
6625  * to test them we send debug packets
6626  */
6627 static int bnx2x_int_mem_test(struct bnx2x *bp)
6628 {
6629         int factor;
6630         int count, i;
6631         u32 val = 0;
6632
6633         if (CHIP_REV_IS_FPGA(bp))
6634                 factor = 120;
6635         else if (CHIP_REV_IS_EMUL(bp))
6636                 factor = 200;
6637         else
6638                 factor = 1;
6639
6640         /* Disable inputs of parser neighbor blocks */
6641         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6642         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6643         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6644         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6645
6646         /*  Write 0 to parser credits for CFC search request */
6647         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6648
6649         /* send Ethernet packet */
6650         bnx2x_lb_pckt(bp);
6651
6652         /* TODO do i reset NIG statistic? */
6653         /* Wait until NIG register shows 1 packet of size 0x10 */
6654         count = 1000 * factor;
6655         while (count) {
6656
6657                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6658                 val = *bnx2x_sp(bp, wb_data[0]);
6659                 if (val == 0x10)
6660                         break;
6661
6662                 usleep_range(10000, 20000);
6663                 count--;
6664         }
6665         if (val != 0x10) {
6666                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6667                 return -1;
6668         }
6669
6670         /* Wait until PRS register shows 1 packet */
6671         count = 1000 * factor;
6672         while (count) {
6673                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6674                 if (val == 1)
6675                         break;
6676
6677                 usleep_range(10000, 20000);
6678                 count--;
6679         }
6680         if (val != 0x1) {
6681                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6682                 return -2;
6683         }
6684
6685         /* Reset and init BRB, PRS */
6686         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6687         msleep(50);
6688         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6689         msleep(50);
6690         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6691         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6692
6693         DP(NETIF_MSG_HW, "part2\n");
6694
6695         /* Disable inputs of parser neighbor blocks */
6696         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6697         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6698         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6699         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6700
6701         /* Write 0 to parser credits for CFC search request */
6702         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6703
6704         /* send 10 Ethernet packets */
6705         for (i = 0; i < 10; i++)
6706                 bnx2x_lb_pckt(bp);
6707
6708         /* Wait until NIG register shows 10 + 1
6709            packets of size 11*0x10 = 0xb0 */
6710         count = 1000 * factor;
6711         while (count) {
6712
6713                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6714                 val = *bnx2x_sp(bp, wb_data[0]);
6715                 if (val == 0xb0)
6716                         break;
6717
6718                 usleep_range(10000, 20000);
6719                 count--;
6720         }
6721         if (val != 0xb0) {
6722                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6723                 return -3;
6724         }
6725
6726         /* Wait until PRS register shows 2 packets */
6727         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6728         if (val != 2)
6729                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6730
6731         /* Write 1 to parser credits for CFC search request */
6732         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6733
6734         /* Wait until PRS register shows 3 packets */
6735         msleep(10 * factor);
6736         /* Wait until NIG register shows 1 packet of size 0x10 */
6737         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6738         if (val != 3)
6739                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6740
6741         /* clear NIG EOP FIFO */
6742         for (i = 0; i < 11; i++)
6743                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6744         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6745         if (val != 1) {
6746                 BNX2X_ERR("clear of NIG failed\n");
6747                 return -4;
6748         }
6749
6750         /* Reset and init BRB, PRS, NIG */
6751         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6752         msleep(50);
6753         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6754         msleep(50);
6755         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6756         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6757         if (!CNIC_SUPPORT(bp))
6758                 /* set NIC mode */
6759                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6760
6761         /* Enable inputs of parser neighbor blocks */
6762         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6763         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6764         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6765         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6766
6767         DP(NETIF_MSG_HW, "done\n");
6768
6769         return 0; /* OK */
6770 }
6771
6772 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6773 {
6774         u32 val;
6775
6776         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6777         if (!CHIP_IS_E1x(bp))
6778                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6779         else
6780                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6781         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6782         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6783         /*
6784          * mask read length error interrupts in brb for parser
6785          * (parsing unit and 'checksum and crc' unit)
6786          * these errors are legal (PU reads fixed length and CAC can cause
6787          * read length error on truncated packets)
6788          */
6789         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6790         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6791         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6792         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6793         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6794         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6795 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6796 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6797         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6798         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6799         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6800 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6801 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6802         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6803         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6804         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6805         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6806 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6807 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6808
6809         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6810                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6811                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6812         if (!CHIP_IS_E1x(bp))
6813                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6814                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6815         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6816
6817         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6818         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6819         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6820 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6821
6822         if (!CHIP_IS_E1x(bp))
6823                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6824                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6825
6826         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6827         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6828 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6829         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6830 }
6831
6832 static void bnx2x_reset_common(struct bnx2x *bp)
6833 {
6834         u32 val = 0x1400;
6835
6836         /* reset_common */
6837         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6838                0xd3ffff7f);
6839
6840         if (CHIP_IS_E3(bp)) {
6841                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6842                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6843         }
6844
6845         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6846 }
6847
6848 static void bnx2x_setup_dmae(struct bnx2x *bp)
6849 {
6850         bp->dmae_ready = 0;
6851         spin_lock_init(&bp->dmae_lock);
6852 }
6853
6854 static void bnx2x_init_pxp(struct bnx2x *bp)
6855 {
6856         u16 devctl;
6857         int r_order, w_order;
6858
6859         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6860         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6861         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6862         if (bp->mrrs == -1)
6863                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6864         else {
6865                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6866                 r_order = bp->mrrs;
6867         }
6868
6869         bnx2x_init_pxp_arb(bp, r_order, w_order);
6870 }
6871
6872 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6873 {
6874         int is_required;
6875         u32 val;
6876         int port;
6877
6878         if (BP_NOMCP(bp))
6879                 return;
6880
6881         is_required = 0;
6882         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6883               SHARED_HW_CFG_FAN_FAILURE_MASK;
6884
6885         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6886                 is_required = 1;
6887
6888         /*
6889          * The fan failure mechanism is usually related to the PHY type since
6890          * the power consumption of the board is affected by the PHY. Currently,
6891          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6892          */
6893         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6894                 for (port = PORT_0; port < PORT_MAX; port++) {
6895                         is_required |=
6896                                 bnx2x_fan_failure_det_req(
6897                                         bp,
6898                                         bp->common.shmem_base,
6899                                         bp->common.shmem2_base,
6900                                         port);
6901                 }
6902
6903         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6904
6905         if (is_required == 0)
6906                 return;
6907
6908         /* Fan failure is indicated by SPIO 5 */
6909         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6910
6911         /* set to active low mode */
6912         val = REG_RD(bp, MISC_REG_SPIO_INT);
6913         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6914         REG_WR(bp, MISC_REG_SPIO_INT, val);
6915
6916         /* enable interrupt to signal the IGU */
6917         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6918         val |= MISC_SPIO_SPIO5;
6919         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6920 }
6921
6922 void bnx2x_pf_disable(struct bnx2x *bp)
6923 {
6924         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6925         val &= ~IGU_PF_CONF_FUNC_EN;
6926
6927         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6928         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6929         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6930 }
6931
6932 static void bnx2x__common_init_phy(struct bnx2x *bp)
6933 {
6934         u32 shmem_base[2], shmem2_base[2];
6935         /* Avoid common init in case MFW supports LFA */
6936         if (SHMEM2_RD(bp, size) >
6937             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6938                 return;
6939         shmem_base[0] =  bp->common.shmem_base;
6940         shmem2_base[0] = bp->common.shmem2_base;
6941         if (!CHIP_IS_E1x(bp)) {
6942                 shmem_base[1] =
6943                         SHMEM2_RD(bp, other_shmem_base_addr);
6944                 shmem2_base[1] =
6945                         SHMEM2_RD(bp, other_shmem2_base_addr);
6946         }
6947         bnx2x_acquire_phy_lock(bp);
6948         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6949                               bp->common.chip_id);
6950         bnx2x_release_phy_lock(bp);
6951 }
6952
6953 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6954 {
6955         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6956         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6957         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6958         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6959         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6960
6961         /* make sure this value is 0 */
6962         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6963
6964         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6965         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6966         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6967         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6968 }
6969
6970 static void bnx2x_set_endianity(struct bnx2x *bp)
6971 {
6972 #ifdef __BIG_ENDIAN
6973         bnx2x_config_endianity(bp, 1);
6974 #else
6975         bnx2x_config_endianity(bp, 0);
6976 #endif
6977 }
6978
6979 static void bnx2x_reset_endianity(struct bnx2x *bp)
6980 {
6981         bnx2x_config_endianity(bp, 0);
6982 }
6983
6984 /**
6985  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6986  *
6987  * @bp:         driver handle
6988  */
6989 static int bnx2x_init_hw_common(struct bnx2x *bp)
6990 {
6991         u32 val;
6992
6993         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6994
6995         /*
6996          * take the RESET lock to protect undi_unload flow from accessing
6997          * registers while we're resetting the chip
6998          */
6999         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7000
7001         bnx2x_reset_common(bp);
7002         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7003
7004         val = 0xfffc;
7005         if (CHIP_IS_E3(bp)) {
7006                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7007                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7008         }
7009         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7010
7011         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7012
7013         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7014
7015         if (!CHIP_IS_E1x(bp)) {
7016                 u8 abs_func_id;
7017
7018                 /**
7019                  * 4-port mode or 2-port mode we need to turn of master-enable
7020                  * for everyone, after that, turn it back on for self.
7021                  * so, we disregard multi-function or not, and always disable
7022                  * for all functions on the given path, this means 0,2,4,6 for
7023                  * path 0 and 1,3,5,7 for path 1
7024                  */
7025                 for (abs_func_id = BP_PATH(bp);
7026                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7027                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7028                                 REG_WR(bp,
7029                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7030                                     1);
7031                                 continue;
7032                         }
7033
7034                         bnx2x_pretend_func(bp, abs_func_id);
7035                         /* clear pf enable */
7036                         bnx2x_pf_disable(bp);
7037                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7038                 }
7039         }
7040
7041         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7042         if (CHIP_IS_E1(bp)) {
7043                 /* enable HW interrupt from PXP on USDM overflow
7044                    bit 16 on INT_MASK_0 */
7045                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7046         }
7047
7048         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7049         bnx2x_init_pxp(bp);
7050         bnx2x_set_endianity(bp);
7051         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7052
7053         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7054                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7055
7056         /* let the HW do it's magic ... */
7057         msleep(100);
7058         /* finish PXP init */
7059         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7060         if (val != 1) {
7061                 BNX2X_ERR("PXP2 CFG failed\n");
7062                 return -EBUSY;
7063         }
7064         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7065         if (val != 1) {
7066                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7067                 return -EBUSY;
7068         }
7069
7070         /* Timers bug workaround E2 only. We need to set the entire ILT to
7071          * have entries with value "0" and valid bit on.
7072          * This needs to be done by the first PF that is loaded in a path
7073          * (i.e. common phase)
7074          */
7075         if (!CHIP_IS_E1x(bp)) {
7076 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7077  * (i.e. vnic3) to start even if it is marked as "scan-off".
7078  * This occurs when a different function (func2,3) is being marked
7079  * as "scan-off". Real-life scenario for example: if a driver is being
7080  * load-unloaded while func6,7 are down. This will cause the timer to access
7081  * the ilt, translate to a logical address and send a request to read/write.
7082  * Since the ilt for the function that is down is not valid, this will cause
7083  * a translation error which is unrecoverable.
7084  * The Workaround is intended to make sure that when this happens nothing fatal
7085  * will occur. The workaround:
7086  *      1.  First PF driver which loads on a path will:
7087  *              a.  After taking the chip out of reset, by using pretend,
7088  *                  it will write "0" to the following registers of
7089  *                  the other vnics.
7090  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7091  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7092  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7093  *                  And for itself it will write '1' to
7094  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7095  *                  dmae-operations (writing to pram for example.)
7096  *                  note: can be done for only function 6,7 but cleaner this
7097  *                        way.
7098  *              b.  Write zero+valid to the entire ILT.
7099  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7100  *                  VNIC3 (of that port). The range allocated will be the
7101  *                  entire ILT. This is needed to prevent  ILT range error.
7102  *      2.  Any PF driver load flow:
7103  *              a.  ILT update with the physical addresses of the allocated
7104  *                  logical pages.
7105  *              b.  Wait 20msec. - note that this timeout is needed to make
7106  *                  sure there are no requests in one of the PXP internal
7107  *                  queues with "old" ILT addresses.
7108  *              c.  PF enable in the PGLC.
7109  *              d.  Clear the was_error of the PF in the PGLC. (could have
7110  *                  occurred while driver was down)
7111  *              e.  PF enable in the CFC (WEAK + STRONG)
7112  *              f.  Timers scan enable
7113  *      3.  PF driver unload flow:
7114  *              a.  Clear the Timers scan_en.
7115  *              b.  Polling for scan_on=0 for that PF.
7116  *              c.  Clear the PF enable bit in the PXP.
7117  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7118  *              e.  Write zero+valid to all ILT entries (The valid bit must
7119  *                  stay set)
7120  *              f.  If this is VNIC 3 of a port then also init
7121  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7122  *                  to the last entry in the ILT.
7123  *
7124  *      Notes:
7125  *      Currently the PF error in the PGLC is non recoverable.
7126  *      In the future the there will be a recovery routine for this error.
7127  *      Currently attention is masked.
7128  *      Having an MCP lock on the load/unload process does not guarantee that
7129  *      there is no Timer disable during Func6/7 enable. This is because the
7130  *      Timers scan is currently being cleared by the MCP on FLR.
7131  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7132  *      there is error before clearing it. But the flow above is simpler and
7133  *      more general.
7134  *      All ILT entries are written by zero+valid and not just PF6/7
7135  *      ILT entries since in the future the ILT entries allocation for
7136  *      PF-s might be dynamic.
7137  */
7138                 struct ilt_client_info ilt_cli;
7139                 struct bnx2x_ilt ilt;
7140                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7141                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7142
7143                 /* initialize dummy TM client */
7144                 ilt_cli.start = 0;
7145                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7146                 ilt_cli.client_num = ILT_CLIENT_TM;
7147
7148                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7149                  * Step 2: set the timers first/last ilt entry to point
7150                  * to the entire range to prevent ILT range error for 3rd/4th
7151                  * vnic (this code assumes existence of the vnic)
7152                  *
7153                  * both steps performed by call to bnx2x_ilt_client_init_op()
7154                  * with dummy TM client
7155                  *
7156                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7157                  * and his brother are split registers
7158                  */
7159                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7160                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7161                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7162
7163                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7164                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7165                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7166         }
7167
7168         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7169         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7170
7171         if (!CHIP_IS_E1x(bp)) {
7172                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7173                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7174                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7175
7176                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7177
7178                 /* let the HW do it's magic ... */
7179                 do {
7180                         msleep(200);
7181                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7182                 } while (factor-- && (val != 1));
7183
7184                 if (val != 1) {
7185                         BNX2X_ERR("ATC_INIT failed\n");
7186                         return -EBUSY;
7187                 }
7188         }
7189
7190         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7191
7192         bnx2x_iov_init_dmae(bp);
7193
7194         /* clean the DMAE memory */
7195         bp->dmae_ready = 1;
7196         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7197
7198         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7199
7200         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7201
7202         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7203
7204         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7205
7206         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7207         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7208         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7209         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7210
7211         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7212
7213         /* QM queues pointers table */
7214         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7215
7216         /* soft reset pulse */
7217         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7218         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7219
7220         if (CNIC_SUPPORT(bp))
7221                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7222
7223         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7224
7225         if (!CHIP_REV_IS_SLOW(bp))
7226                 /* enable hw interrupt from doorbell Q */
7227                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7228
7229         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7230
7231         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7232         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7233
7234         if (!CHIP_IS_E1(bp))
7235                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7236
7237         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7238                 if (IS_MF_AFEX(bp)) {
7239                         /* configure that VNTag and VLAN headers must be
7240                          * received in afex mode
7241                          */
7242                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7243                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7244                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7245                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7246                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7247                 } else {
7248                         /* Bit-map indicating which L2 hdrs may appear
7249                          * after the basic Ethernet header
7250                          */
7251                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7252                                bp->path_has_ovlan ? 7 : 6);
7253                 }
7254         }
7255
7256         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7257         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7258         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7259         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7260
7261         if (!CHIP_IS_E1x(bp)) {
7262                 /* reset VFC memories */
7263                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7264                            VFC_MEMORIES_RST_REG_CAM_RST |
7265                            VFC_MEMORIES_RST_REG_RAM_RST);
7266                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7267                            VFC_MEMORIES_RST_REG_CAM_RST |
7268                            VFC_MEMORIES_RST_REG_RAM_RST);
7269
7270                 msleep(20);
7271         }
7272
7273         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7274         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7275         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7276         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7277
7278         /* sync semi rtc */
7279         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7280                0x80000000);
7281         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7282                0x80000000);
7283
7284         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7285         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7286         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7287
7288         if (!CHIP_IS_E1x(bp)) {
7289                 if (IS_MF_AFEX(bp)) {
7290                         /* configure that VNTag and VLAN headers must be
7291                          * sent in afex mode
7292                          */
7293                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7294                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7295                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7296                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7297                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7298                 } else {
7299                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7300                                bp->path_has_ovlan ? 7 : 6);
7301                 }
7302         }
7303
7304         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7305
7306         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7307
7308         if (CNIC_SUPPORT(bp)) {
7309                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7310                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7311                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7312                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7313                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7314                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7315                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7316                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7317                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7318                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7319         }
7320         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7321
7322         if (sizeof(union cdu_context) != 1024)
7323                 /* we currently assume that a context is 1024 bytes */
7324                 dev_alert(&bp->pdev->dev,
7325                           "please adjust the size of cdu_context(%ld)\n",
7326                           (long)sizeof(union cdu_context));
7327
7328         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7329         val = (4 << 24) + (0 << 12) + 1024;
7330         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7331
7332         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7333         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7334         /* enable context validation interrupt from CFC */
7335         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7336
7337         /* set the thresholds to prevent CFC/CDU race */
7338         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7339
7340         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7341
7342         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7343                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7344
7345         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7346         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7347
7348         /* Reset PCIE errors for debug */
7349         REG_WR(bp, 0x2814, 0xffffffff);
7350         REG_WR(bp, 0x3820, 0xffffffff);
7351
7352         if (!CHIP_IS_E1x(bp)) {
7353                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7354                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7355                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7356                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7357                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7358                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7359                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7360                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7361                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7362                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7363                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7364         }
7365
7366         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7367         if (!CHIP_IS_E1(bp)) {
7368                 /* in E3 this done in per-port section */
7369                 if (!CHIP_IS_E3(bp))
7370                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7371         }
7372         if (CHIP_IS_E1H(bp))
7373                 /* not applicable for E2 (and above ...) */
7374                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7375
7376         if (CHIP_REV_IS_SLOW(bp))
7377                 msleep(200);
7378
7379         /* finish CFC init */
7380         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7381         if (val != 1) {
7382                 BNX2X_ERR("CFC LL_INIT failed\n");
7383                 return -EBUSY;
7384         }
7385         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7386         if (val != 1) {
7387                 BNX2X_ERR("CFC AC_INIT failed\n");
7388                 return -EBUSY;
7389         }
7390         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7391         if (val != 1) {
7392                 BNX2X_ERR("CFC CAM_INIT failed\n");
7393                 return -EBUSY;
7394         }
7395         REG_WR(bp, CFC_REG_DEBUG0, 0);
7396
7397         if (CHIP_IS_E1(bp)) {
7398                 /* read NIG statistic
7399                    to see if this is our first up since powerup */
7400                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7401                 val = *bnx2x_sp(bp, wb_data[0]);
7402
7403                 /* do internal memory self test */
7404                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7405                         BNX2X_ERR("internal mem self test failed\n");
7406                         return -EBUSY;
7407                 }
7408         }
7409
7410         bnx2x_setup_fan_failure_detection(bp);
7411
7412         /* clear PXP2 attentions */
7413         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7414
7415         bnx2x_enable_blocks_attention(bp);
7416         bnx2x_enable_blocks_parity(bp);
7417
7418         if (!BP_NOMCP(bp)) {
7419                 if (CHIP_IS_E1x(bp))
7420                         bnx2x__common_init_phy(bp);
7421         } else
7422                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7423
7424         return 0;
7425 }
7426
7427 /**
7428  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7429  *
7430  * @bp:         driver handle
7431  */
7432 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7433 {
7434         int rc = bnx2x_init_hw_common(bp);
7435
7436         if (rc)
7437                 return rc;
7438
7439         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7440         if (!BP_NOMCP(bp))
7441                 bnx2x__common_init_phy(bp);
7442
7443         return 0;
7444 }
7445
7446 static int bnx2x_init_hw_port(struct bnx2x *bp)
7447 {
7448         int port = BP_PORT(bp);
7449         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7450         u32 low, high;
7451         u32 val, reg;
7452
7453         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7454
7455         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7456
7457         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7458         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7459         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7460
7461         /* Timers bug workaround: disables the pf_master bit in pglue at
7462          * common phase, we need to enable it here before any dmae access are
7463          * attempted. Therefore we manually added the enable-master to the
7464          * port phase (it also happens in the function phase)
7465          */
7466         if (!CHIP_IS_E1x(bp))
7467                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7468
7469         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7470         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7471         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7472         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7473
7474         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7475         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7476         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7477         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7478
7479         /* QM cid (connection) count */
7480         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7481
7482         if (CNIC_SUPPORT(bp)) {
7483                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7484                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7485                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7486         }
7487
7488         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7489
7490         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7491
7492         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7493
7494                 if (IS_MF(bp))
7495                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7496                 else if (bp->dev->mtu > 4096) {
7497                         if (bp->flags & ONE_PORT_FLAG)
7498                                 low = 160;
7499                         else {
7500                                 val = bp->dev->mtu;
7501                                 /* (24*1024 + val*4)/256 */
7502                                 low = 96 + (val/64) +
7503                                                 ((val % 64) ? 1 : 0);
7504                         }
7505                 } else
7506                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7507                 high = low + 56;        /* 14*1024/256 */
7508                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7509                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7510         }
7511
7512         if (CHIP_MODE_IS_4_PORT(bp))
7513                 REG_WR(bp, (BP_PORT(bp) ?
7514                             BRB1_REG_MAC_GUARANTIED_1 :
7515                             BRB1_REG_MAC_GUARANTIED_0), 40);
7516
7517         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7518         if (CHIP_IS_E3B0(bp)) {
7519                 if (IS_MF_AFEX(bp)) {
7520                         /* configure headers for AFEX mode */
7521                         REG_WR(bp, BP_PORT(bp) ?
7522                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7523                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7524                         REG_WR(bp, BP_PORT(bp) ?
7525                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7526                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7527                         REG_WR(bp, BP_PORT(bp) ?
7528                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7529                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7530                 } else {
7531                         /* Ovlan exists only if we are in multi-function +
7532                          * switch-dependent mode, in switch-independent there
7533                          * is no ovlan headers
7534                          */
7535                         REG_WR(bp, BP_PORT(bp) ?
7536                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7537                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7538                                (bp->path_has_ovlan ? 7 : 6));
7539                 }
7540         }
7541
7542         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7543         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7544         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7545         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7546
7547         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7548         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7549         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7550         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7551
7552         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7553         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7554
7555         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7556
7557         if (CHIP_IS_E1x(bp)) {
7558                 /* configure PBF to work without PAUSE mtu 9000 */
7559                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7560
7561                 /* update threshold */
7562                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7563                 /* update init credit */
7564                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7565
7566                 /* probe changes */
7567                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7568                 udelay(50);
7569                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7570         }
7571
7572         if (CNIC_SUPPORT(bp))
7573                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7574
7575         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7576         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7577
7578         if (CHIP_IS_E1(bp)) {
7579                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7580                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7581         }
7582         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7583
7584         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7585
7586         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7587         /* init aeu_mask_attn_func_0/1:
7588          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7589          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7590          *             bits 4-7 are used for "per vn group attention" */
7591         val = IS_MF(bp) ? 0xF7 : 0x7;
7592         /* Enable DCBX attention for all but E1 */
7593         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7594         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7595
7596         /* SCPAD_PARITY should NOT trigger close the gates */
7597         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7598         REG_WR(bp, reg,
7599                REG_RD(bp, reg) &
7600                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7601
7602         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7603         REG_WR(bp, reg,
7604                REG_RD(bp, reg) &
7605                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7606
7607         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7608
7609         if (!CHIP_IS_E1x(bp)) {
7610                 /* Bit-map indicating which L2 hdrs may appear after the
7611                  * basic Ethernet header
7612                  */
7613                 if (IS_MF_AFEX(bp))
7614                         REG_WR(bp, BP_PORT(bp) ?
7615                                NIG_REG_P1_HDRS_AFTER_BASIC :
7616                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7617                 else
7618                         REG_WR(bp, BP_PORT(bp) ?
7619                                NIG_REG_P1_HDRS_AFTER_BASIC :
7620                                NIG_REG_P0_HDRS_AFTER_BASIC,
7621                                IS_MF_SD(bp) ? 7 : 6);
7622
7623                 if (CHIP_IS_E3(bp))
7624                         REG_WR(bp, BP_PORT(bp) ?
7625                                    NIG_REG_LLH1_MF_MODE :
7626                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7627         }
7628         if (!CHIP_IS_E3(bp))
7629                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7630
7631         if (!CHIP_IS_E1(bp)) {
7632                 /* 0x2 disable mf_ov, 0x1 enable */
7633                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7634                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7635
7636                 if (!CHIP_IS_E1x(bp)) {
7637                         val = 0;
7638                         switch (bp->mf_mode) {
7639                         case MULTI_FUNCTION_SD:
7640                                 val = 1;
7641                                 break;
7642                         case MULTI_FUNCTION_SI:
7643                         case MULTI_FUNCTION_AFEX:
7644                                 val = 2;
7645                                 break;
7646                         }
7647
7648                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7649                                                   NIG_REG_LLH0_CLS_TYPE), val);
7650                 }
7651                 {
7652                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7653                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7654                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7655                 }
7656         }
7657
7658         /* If SPIO5 is set to generate interrupts, enable it for this port */
7659         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7660         if (val & MISC_SPIO_SPIO5) {
7661                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7662                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7663                 val = REG_RD(bp, reg_addr);
7664                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7665                 REG_WR(bp, reg_addr, val);
7666         }
7667
7668         return 0;
7669 }
7670
7671 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7672 {
7673         int reg;
7674         u32 wb_write[2];
7675
7676         if (CHIP_IS_E1(bp))
7677                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7678         else
7679                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7680
7681         wb_write[0] = ONCHIP_ADDR1(addr);
7682         wb_write[1] = ONCHIP_ADDR2(addr);
7683         REG_WR_DMAE(bp, reg, wb_write, 2);
7684 }
7685
7686 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7687 {
7688         u32 data, ctl, cnt = 100;
7689         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7690         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7691         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7692         u32 sb_bit =  1 << (idu_sb_id%32);
7693         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7694         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7695
7696         /* Not supported in BC mode */
7697         if (CHIP_INT_MODE_IS_BC(bp))
7698                 return;
7699
7700         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7701                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7702                 IGU_REGULAR_CLEANUP_SET                         |
7703                 IGU_REGULAR_BCLEANUP;
7704
7705         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7706               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7707               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7708
7709         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7710                          data, igu_addr_data);
7711         REG_WR(bp, igu_addr_data, data);
7712         mmiowb();
7713         barrier();
7714         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7715                           ctl, igu_addr_ctl);
7716         REG_WR(bp, igu_addr_ctl, ctl);
7717         mmiowb();
7718         barrier();
7719
7720         /* wait for clean up to finish */
7721         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7722                 msleep(20);
7723
7724         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7725                 DP(NETIF_MSG_HW,
7726                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7727                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7728         }
7729 }
7730
7731 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7732 {
7733         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7734 }
7735
7736 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7737 {
7738         u32 i, base = FUNC_ILT_BASE(func);
7739         for (i = base; i < base + ILT_PER_FUNC; i++)
7740                 bnx2x_ilt_wr(bp, i, 0);
7741 }
7742
7743 static void bnx2x_init_searcher(struct bnx2x *bp)
7744 {
7745         int port = BP_PORT(bp);
7746         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7747         /* T1 hash bits value determines the T1 number of entries */
7748         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7749 }
7750
7751 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7752 {
7753         int rc;
7754         struct bnx2x_func_state_params func_params = {NULL};
7755         struct bnx2x_func_switch_update_params *switch_update_params =
7756                 &func_params.params.switch_update;
7757
7758         /* Prepare parameters for function state transitions */
7759         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7760         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7761
7762         func_params.f_obj = &bp->func_obj;
7763         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7764
7765         /* Function parameters */
7766         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7767                   &switch_update_params->changes);
7768         if (suspend)
7769                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7770                           &switch_update_params->changes);
7771
7772         rc = bnx2x_func_state_change(bp, &func_params);
7773
7774         return rc;
7775 }
7776
7777 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7778 {
7779         int rc, i, port = BP_PORT(bp);
7780         int vlan_en = 0, mac_en[NUM_MACS];
7781
7782         /* Close input from network */
7783         if (bp->mf_mode == SINGLE_FUNCTION) {
7784                 bnx2x_set_rx_filter(&bp->link_params, 0);
7785         } else {
7786                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7787                                    NIG_REG_LLH0_FUNC_EN);
7788                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7789                           NIG_REG_LLH0_FUNC_EN, 0);
7790                 for (i = 0; i < NUM_MACS; i++) {
7791                         mac_en[i] = REG_RD(bp, port ?
7792                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7793                                               4 * i) :
7794                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7795                                               4 * i));
7796                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7797                                               4 * i) :
7798                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7799                 }
7800         }
7801
7802         /* Close BMC to host */
7803         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7804                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7805
7806         /* Suspend Tx switching to the PF. Completion of this ramrod
7807          * further guarantees that all the packets of that PF / child
7808          * VFs in BRB were processed by the Parser, so it is safe to
7809          * change the NIC_MODE register.
7810          */
7811         rc = bnx2x_func_switch_update(bp, 1);
7812         if (rc) {
7813                 BNX2X_ERR("Can't suspend tx-switching!\n");
7814                 return rc;
7815         }
7816
7817         /* Change NIC_MODE register */
7818         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7819
7820         /* Open input from network */
7821         if (bp->mf_mode == SINGLE_FUNCTION) {
7822                 bnx2x_set_rx_filter(&bp->link_params, 1);
7823         } else {
7824                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7825                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7826                 for (i = 0; i < NUM_MACS; i++) {
7827                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7828                                               4 * i) :
7829                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7830                                   mac_en[i]);
7831                 }
7832         }
7833
7834         /* Enable BMC to host */
7835         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7836                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7837
7838         /* Resume Tx switching to the PF */
7839         rc = bnx2x_func_switch_update(bp, 0);
7840         if (rc) {
7841                 BNX2X_ERR("Can't resume tx-switching!\n");
7842                 return rc;
7843         }
7844
7845         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7846         return 0;
7847 }
7848
7849 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7850 {
7851         int rc;
7852
7853         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7854
7855         if (CONFIGURE_NIC_MODE(bp)) {
7856                 /* Configure searcher as part of function hw init */
7857                 bnx2x_init_searcher(bp);
7858
7859                 /* Reset NIC mode */
7860                 rc = bnx2x_reset_nic_mode(bp);
7861                 if (rc)
7862                         BNX2X_ERR("Can't change NIC mode!\n");
7863                 return rc;
7864         }
7865
7866         return 0;
7867 }
7868
7869 static int bnx2x_init_hw_func(struct bnx2x *bp)
7870 {
7871         int port = BP_PORT(bp);
7872         int func = BP_FUNC(bp);
7873         int init_phase = PHASE_PF0 + func;
7874         struct bnx2x_ilt *ilt = BP_ILT(bp);
7875         u16 cdu_ilt_start;
7876         u32 addr, val;
7877         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7878         int i, main_mem_width, rc;
7879
7880         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7881
7882         /* FLR cleanup - hmmm */
7883         if (!CHIP_IS_E1x(bp)) {
7884                 rc = bnx2x_pf_flr_clnup(bp);
7885                 if (rc) {
7886                         bnx2x_fw_dump(bp);
7887                         return rc;
7888                 }
7889         }
7890
7891         /* set MSI reconfigure capability */
7892         if (bp->common.int_block == INT_BLOCK_HC) {
7893                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7894                 val = REG_RD(bp, addr);
7895                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7896                 REG_WR(bp, addr, val);
7897         }
7898
7899         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7900         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7901
7902         ilt = BP_ILT(bp);
7903         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7904
7905         if (IS_SRIOV(bp))
7906                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7907         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7908
7909         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7910          * those of the VFs, so start line should be reset
7911          */
7912         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7913         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7914                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7915                 ilt->lines[cdu_ilt_start + i].page_mapping =
7916                         bp->context[i].cxt_mapping;
7917                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7918         }
7919
7920         bnx2x_ilt_init_op(bp, INITOP_SET);
7921
7922         if (!CONFIGURE_NIC_MODE(bp)) {
7923                 bnx2x_init_searcher(bp);
7924                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7925                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7926         } else {
7927                 /* Set NIC mode */
7928                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7929                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7930         }
7931
7932         if (!CHIP_IS_E1x(bp)) {
7933                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7934
7935                 /* Turn on a single ISR mode in IGU if driver is going to use
7936                  * INT#x or MSI
7937                  */
7938                 if (!(bp->flags & USING_MSIX_FLAG))
7939                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7940                 /*
7941                  * Timers workaround bug: function init part.
7942                  * Need to wait 20msec after initializing ILT,
7943                  * needed to make sure there are no requests in
7944                  * one of the PXP internal queues with "old" ILT addresses
7945                  */
7946                 msleep(20);
7947                 /*
7948                  * Master enable - Due to WB DMAE writes performed before this
7949                  * register is re-initialized as part of the regular function
7950                  * init
7951                  */
7952                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7953                 /* Enable the function in IGU */
7954                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7955         }
7956
7957         bp->dmae_ready = 1;
7958
7959         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7960
7961         if (!CHIP_IS_E1x(bp))
7962                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7963
7964         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7965         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7966         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7967         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7968         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7969         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7970         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7971         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7972         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7973         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7974         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7975         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7976         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7977
7978         if (!CHIP_IS_E1x(bp))
7979                 REG_WR(bp, QM_REG_PF_EN, 1);
7980
7981         if (!CHIP_IS_E1x(bp)) {
7982                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7983                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7984                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7985                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7986         }
7987         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7988
7989         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7990         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7991         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7992
7993         bnx2x_iov_init_dq(bp);
7994
7995         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7996         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7997         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7998         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7999         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8000         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8001         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8002         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8003         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8004         if (!CHIP_IS_E1x(bp))
8005                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8006
8007         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8008
8009         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8010
8011         if (!CHIP_IS_E1x(bp))
8012                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8013
8014         if (IS_MF(bp)) {
8015                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8016                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8017                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8018                                bp->mf_ov);
8019                 }
8020         }
8021
8022         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8023
8024         /* HC init per function */
8025         if (bp->common.int_block == INT_BLOCK_HC) {
8026                 if (CHIP_IS_E1H(bp)) {
8027                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8028
8029                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8030                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8031                 }
8032                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8033
8034         } else {
8035                 int num_segs, sb_idx, prod_offset;
8036
8037                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8038
8039                 if (!CHIP_IS_E1x(bp)) {
8040                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8041                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8042                 }
8043
8044                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8045
8046                 if (!CHIP_IS_E1x(bp)) {
8047                         int dsb_idx = 0;
8048                         /**
8049                          * Producer memory:
8050                          * E2 mode: address 0-135 match to the mapping memory;
8051                          * 136 - PF0 default prod; 137 - PF1 default prod;
8052                          * 138 - PF2 default prod; 139 - PF3 default prod;
8053                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8054                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8055                          * 144-147 reserved.
8056                          *
8057                          * E1.5 mode - In backward compatible mode;
8058                          * for non default SB; each even line in the memory
8059                          * holds the U producer and each odd line hold
8060                          * the C producer. The first 128 producers are for
8061                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8062                          * producers are for the DSB for each PF.
8063                          * Each PF has five segments: (the order inside each
8064                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8065                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8066                          * 144-147 attn prods;
8067                          */
8068                         /* non-default-status-blocks */
8069                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8070                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8071                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8072                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8073                                         num_segs;
8074
8075                                 for (i = 0; i < num_segs; i++) {
8076                                         addr = IGU_REG_PROD_CONS_MEMORY +
8077                                                         (prod_offset + i) * 4;
8078                                         REG_WR(bp, addr, 0);
8079                                 }
8080                                 /* send consumer update with value 0 */
8081                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8082                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8083                                 bnx2x_igu_clear_sb(bp,
8084                                                    bp->igu_base_sb + sb_idx);
8085                         }
8086
8087                         /* default-status-blocks */
8088                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8089                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8090
8091                         if (CHIP_MODE_IS_4_PORT(bp))
8092                                 dsb_idx = BP_FUNC(bp);
8093                         else
8094                                 dsb_idx = BP_VN(bp);
8095
8096                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8097                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8098                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8099
8100                         /*
8101                          * igu prods come in chunks of E1HVN_MAX (4) -
8102                          * does not matters what is the current chip mode
8103                          */
8104                         for (i = 0; i < (num_segs * E1HVN_MAX);
8105                              i += E1HVN_MAX) {
8106                                 addr = IGU_REG_PROD_CONS_MEMORY +
8107                                                         (prod_offset + i)*4;
8108                                 REG_WR(bp, addr, 0);
8109                         }
8110                         /* send consumer update with 0 */
8111                         if (CHIP_INT_MODE_IS_BC(bp)) {
8112                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8113                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8114                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8115                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8116                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8117                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8118                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8119                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8120                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8121                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8122                         } else {
8123                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8124                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8125                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8126                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8127                         }
8128                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8129
8130                         /* !!! These should become driver const once
8131                            rf-tool supports split-68 const */
8132                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8133                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8134                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8135                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8136                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8137                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8138                 }
8139         }
8140
8141         /* Reset PCIE errors for debug */
8142         REG_WR(bp, 0x2114, 0xffffffff);
8143         REG_WR(bp, 0x2120, 0xffffffff);
8144
8145         if (CHIP_IS_E1x(bp)) {
8146                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8147                 main_mem_base = HC_REG_MAIN_MEMORY +
8148                                 BP_PORT(bp) * (main_mem_size * 4);
8149                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8150                 main_mem_width = 8;
8151
8152                 val = REG_RD(bp, main_mem_prty_clr);
8153                 if (val)
8154                         DP(NETIF_MSG_HW,
8155                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8156                            val);
8157
8158                 /* Clear "false" parity errors in MSI-X table */
8159                 for (i = main_mem_base;
8160                      i < main_mem_base + main_mem_size * 4;
8161                      i += main_mem_width) {
8162                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8163                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8164                                          i, main_mem_width / 4);
8165                 }
8166                 /* Clear HC parity attention */
8167                 REG_RD(bp, main_mem_prty_clr);
8168         }
8169
8170 #ifdef BNX2X_STOP_ON_ERROR
8171         /* Enable STORMs SP logging */
8172         REG_WR8(bp, BAR_USTRORM_INTMEM +
8173                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8174         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8175                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8176         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8177                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8178         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8179                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8180 #endif
8181
8182         bnx2x_phy_probe(&bp->link_params);
8183
8184         return 0;
8185 }
8186
8187 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8188 {
8189         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8190
8191         if (!CHIP_IS_E1x(bp))
8192                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8193                                sizeof(struct host_hc_status_block_e2));
8194         else
8195                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8196                                sizeof(struct host_hc_status_block_e1x));
8197
8198         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8199 }
8200
8201 void bnx2x_free_mem(struct bnx2x *bp)
8202 {
8203         int i;
8204
8205         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8206                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8207
8208         if (IS_VF(bp))
8209                 return;
8210
8211         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8212                        sizeof(struct host_sp_status_block));
8213
8214         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8215                        sizeof(struct bnx2x_slowpath));
8216
8217         for (i = 0; i < L2_ILT_LINES(bp); i++)
8218                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8219                                bp->context[i].size);
8220         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8221
8222         BNX2X_FREE(bp->ilt->lines);
8223
8224         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8225
8226         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8227                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8228
8229         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8230
8231         bnx2x_iov_free_mem(bp);
8232 }
8233
8234 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8235 {
8236         if (!CHIP_IS_E1x(bp)) {
8237                 /* size = the status block + ramrod buffers */
8238                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8239                                                     sizeof(struct host_hc_status_block_e2));
8240                 if (!bp->cnic_sb.e2_sb)
8241                         goto alloc_mem_err;
8242         } else {
8243                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8244                                                      sizeof(struct host_hc_status_block_e1x));
8245                 if (!bp->cnic_sb.e1x_sb)
8246                         goto alloc_mem_err;
8247         }
8248
8249         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8250                 /* allocate searcher T2 table, as it wasn't allocated before */
8251                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8252                 if (!bp->t2)
8253                         goto alloc_mem_err;
8254         }
8255
8256         /* write address to which L5 should insert its values */
8257         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8258                 &bp->slowpath->drv_info_to_mcp;
8259
8260         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8261                 goto alloc_mem_err;
8262
8263         return 0;
8264
8265 alloc_mem_err:
8266         bnx2x_free_mem_cnic(bp);
8267         BNX2X_ERR("Can't allocate memory\n");
8268         return -ENOMEM;
8269 }
8270
8271 int bnx2x_alloc_mem(struct bnx2x *bp)
8272 {
8273         int i, allocated, context_size;
8274
8275         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8276                 /* allocate searcher T2 table */
8277                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8278                 if (!bp->t2)
8279                         goto alloc_mem_err;
8280         }
8281
8282         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8283                                              sizeof(struct host_sp_status_block));
8284         if (!bp->def_status_blk)
8285                 goto alloc_mem_err;
8286
8287         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8288                                        sizeof(struct bnx2x_slowpath));
8289         if (!bp->slowpath)
8290                 goto alloc_mem_err;
8291
8292         /* Allocate memory for CDU context:
8293          * This memory is allocated separately and not in the generic ILT
8294          * functions because CDU differs in few aspects:
8295          * 1. There are multiple entities allocating memory for context -
8296          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8297          * its own ILT lines.
8298          * 2. Since CDU page-size is not a single 4KB page (which is the case
8299          * for the other ILT clients), to be efficient we want to support
8300          * allocation of sub-page-size in the last entry.
8301          * 3. Context pointers are used by the driver to pass to FW / update
8302          * the context (for the other ILT clients the pointers are used just to
8303          * free the memory during unload).
8304          */
8305         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8306
8307         for (i = 0, allocated = 0; allocated < context_size; i++) {
8308                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8309                                           (context_size - allocated));
8310                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8311                                                       bp->context[i].size);
8312                 if (!bp->context[i].vcxt)
8313                         goto alloc_mem_err;
8314                 allocated += bp->context[i].size;
8315         }
8316         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8317                                  GFP_KERNEL);
8318         if (!bp->ilt->lines)
8319                 goto alloc_mem_err;
8320
8321         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8322                 goto alloc_mem_err;
8323
8324         if (bnx2x_iov_alloc_mem(bp))
8325                 goto alloc_mem_err;
8326
8327         /* Slow path ring */
8328         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8329         if (!bp->spq)
8330                 goto alloc_mem_err;
8331
8332         /* EQ */
8333         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8334                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8335         if (!bp->eq_ring)
8336                 goto alloc_mem_err;
8337
8338         return 0;
8339
8340 alloc_mem_err:
8341         bnx2x_free_mem(bp);
8342         BNX2X_ERR("Can't allocate memory\n");
8343         return -ENOMEM;
8344 }
8345
8346 /*
8347  * Init service functions
8348  */
8349
8350 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8351                       struct bnx2x_vlan_mac_obj *obj, bool set,
8352                       int mac_type, unsigned long *ramrod_flags)
8353 {
8354         int rc;
8355         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8356
8357         memset(&ramrod_param, 0, sizeof(ramrod_param));
8358
8359         /* Fill general parameters */
8360         ramrod_param.vlan_mac_obj = obj;
8361         ramrod_param.ramrod_flags = *ramrod_flags;
8362
8363         /* Fill a user request section if needed */
8364         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8365                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8366
8367                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8368
8369                 /* Set the command: ADD or DEL */
8370                 if (set)
8371                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8372                 else
8373                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8374         }
8375
8376         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8377
8378         if (rc == -EEXIST) {
8379                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8380                 /* do not treat adding same MAC as error */
8381                 rc = 0;
8382         } else if (rc < 0)
8383                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8384
8385         return rc;
8386 }
8387
8388 int bnx2x_del_all_macs(struct bnx2x *bp,
8389                        struct bnx2x_vlan_mac_obj *mac_obj,
8390                        int mac_type, bool wait_for_comp)
8391 {
8392         int rc;
8393         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8394
8395         /* Wait for completion of requested */
8396         if (wait_for_comp)
8397                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8398
8399         /* Set the mac type of addresses we want to clear */
8400         __set_bit(mac_type, &vlan_mac_flags);
8401
8402         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8403         if (rc < 0)
8404                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8405
8406         return rc;
8407 }
8408
8409 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8410 {
8411         if (IS_PF(bp)) {
8412                 unsigned long ramrod_flags = 0;
8413
8414                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8415                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8416                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8417                                          &bp->sp_objs->mac_obj, set,
8418                                          BNX2X_ETH_MAC, &ramrod_flags);
8419         } else { /* vf */
8420                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8421                                              bp->fp->index, true);
8422         }
8423 }
8424
8425 int bnx2x_setup_leading(struct bnx2x *bp)
8426 {
8427         if (IS_PF(bp))
8428                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8429         else /* VF */
8430                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8431 }
8432
8433 /**
8434  * bnx2x_set_int_mode - configure interrupt mode
8435  *
8436  * @bp:         driver handle
8437  *
8438  * In case of MSI-X it will also try to enable MSI-X.
8439  */
8440 int bnx2x_set_int_mode(struct bnx2x *bp)
8441 {
8442         int rc = 0;
8443
8444         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8445                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8446                 return -EINVAL;
8447         }
8448
8449         switch (int_mode) {
8450         case BNX2X_INT_MODE_MSIX:
8451                 /* attempt to enable msix */
8452                 rc = bnx2x_enable_msix(bp);
8453
8454                 /* msix attained */
8455                 if (!rc)
8456                         return 0;
8457
8458                 /* vfs use only msix */
8459                 if (rc && IS_VF(bp))
8460                         return rc;
8461
8462                 /* failed to enable multiple MSI-X */
8463                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8464                                bp->num_queues,
8465                                1 + bp->num_cnic_queues);
8466
8467                 /* falling through... */
8468         case BNX2X_INT_MODE_MSI:
8469                 bnx2x_enable_msi(bp);
8470
8471                 /* falling through... */
8472         case BNX2X_INT_MODE_INTX:
8473                 bp->num_ethernet_queues = 1;
8474                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8475                 BNX2X_DEV_INFO("set number of queues to 1\n");
8476                 break;
8477         default:
8478                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8479                 return -EINVAL;
8480         }
8481         return 0;
8482 }
8483
8484 /* must be called prior to any HW initializations */
8485 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8486 {
8487         if (IS_SRIOV(bp))
8488                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8489         return L2_ILT_LINES(bp);
8490 }
8491
8492 void bnx2x_ilt_set_info(struct bnx2x *bp)
8493 {
8494         struct ilt_client_info *ilt_client;
8495         struct bnx2x_ilt *ilt = BP_ILT(bp);
8496         u16 line = 0;
8497
8498         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8499         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8500
8501         /* CDU */
8502         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8503         ilt_client->client_num = ILT_CLIENT_CDU;
8504         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8505         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8506         ilt_client->start = line;
8507         line += bnx2x_cid_ilt_lines(bp);
8508
8509         if (CNIC_SUPPORT(bp))
8510                 line += CNIC_ILT_LINES;
8511         ilt_client->end = line - 1;
8512
8513         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8514            ilt_client->start,
8515            ilt_client->end,
8516            ilt_client->page_size,
8517            ilt_client->flags,
8518            ilog2(ilt_client->page_size >> 12));
8519
8520         /* QM */
8521         if (QM_INIT(bp->qm_cid_count)) {
8522                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8523                 ilt_client->client_num = ILT_CLIENT_QM;
8524                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8525                 ilt_client->flags = 0;
8526                 ilt_client->start = line;
8527
8528                 /* 4 bytes for each cid */
8529                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8530                                                          QM_ILT_PAGE_SZ);
8531
8532                 ilt_client->end = line - 1;
8533
8534                 DP(NETIF_MSG_IFUP,
8535                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8536                    ilt_client->start,
8537                    ilt_client->end,
8538                    ilt_client->page_size,
8539                    ilt_client->flags,
8540                    ilog2(ilt_client->page_size >> 12));
8541         }
8542
8543         if (CNIC_SUPPORT(bp)) {
8544                 /* SRC */
8545                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8546                 ilt_client->client_num = ILT_CLIENT_SRC;
8547                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8548                 ilt_client->flags = 0;
8549                 ilt_client->start = line;
8550                 line += SRC_ILT_LINES;
8551                 ilt_client->end = line - 1;
8552
8553                 DP(NETIF_MSG_IFUP,
8554                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8555                    ilt_client->start,
8556                    ilt_client->end,
8557                    ilt_client->page_size,
8558                    ilt_client->flags,
8559                    ilog2(ilt_client->page_size >> 12));
8560
8561                 /* TM */
8562                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8563                 ilt_client->client_num = ILT_CLIENT_TM;
8564                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8565                 ilt_client->flags = 0;
8566                 ilt_client->start = line;
8567                 line += TM_ILT_LINES;
8568                 ilt_client->end = line - 1;
8569
8570                 DP(NETIF_MSG_IFUP,
8571                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8572                    ilt_client->start,
8573                    ilt_client->end,
8574                    ilt_client->page_size,
8575                    ilt_client->flags,
8576                    ilog2(ilt_client->page_size >> 12));
8577         }
8578
8579         BUG_ON(line > ILT_MAX_LINES);
8580 }
8581
8582 /**
8583  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8584  *
8585  * @bp:                 driver handle
8586  * @fp:                 pointer to fastpath
8587  * @init_params:        pointer to parameters structure
8588  *
8589  * parameters configured:
8590  *      - HC configuration
8591  *      - Queue's CDU context
8592  */
8593 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8594         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8595 {
8596         u8 cos;
8597         int cxt_index, cxt_offset;
8598
8599         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8600         if (!IS_FCOE_FP(fp)) {
8601                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8602                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8603
8604                 /* If HC is supported, enable host coalescing in the transition
8605                  * to INIT state.
8606                  */
8607                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8608                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8609
8610                 /* HC rate */
8611                 init_params->rx.hc_rate = bp->rx_ticks ?
8612                         (1000000 / bp->rx_ticks) : 0;
8613                 init_params->tx.hc_rate = bp->tx_ticks ?
8614                         (1000000 / bp->tx_ticks) : 0;
8615
8616                 /* FW SB ID */
8617                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8618                         fp->fw_sb_id;
8619
8620                 /*
8621                  * CQ index among the SB indices: FCoE clients uses the default
8622                  * SB, therefore it's different.
8623                  */
8624                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8625                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8626         }
8627
8628         /* set maximum number of COSs supported by this queue */
8629         init_params->max_cos = fp->max_cos;
8630
8631         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8632             fp->index, init_params->max_cos);
8633
8634         /* set the context pointers queue object */
8635         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8636                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8637                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8638                                 ILT_PAGE_CIDS);
8639                 init_params->cxts[cos] =
8640                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8641         }
8642 }
8643
8644 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8645                         struct bnx2x_queue_state_params *q_params,
8646                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8647                         int tx_index, bool leading)
8648 {
8649         memset(tx_only_params, 0, sizeof(*tx_only_params));
8650
8651         /* Set the command */
8652         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8653
8654         /* Set tx-only QUEUE flags: don't zero statistics */
8655         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8656
8657         /* choose the index of the cid to send the slow path on */
8658         tx_only_params->cid_index = tx_index;
8659
8660         /* Set general TX_ONLY_SETUP parameters */
8661         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8662
8663         /* Set Tx TX_ONLY_SETUP parameters */
8664         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8665
8666         DP(NETIF_MSG_IFUP,
8667            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8668            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8669            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8670            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8671
8672         /* send the ramrod */
8673         return bnx2x_queue_state_change(bp, q_params);
8674 }
8675
8676 /**
8677  * bnx2x_setup_queue - setup queue
8678  *
8679  * @bp:         driver handle
8680  * @fp:         pointer to fastpath
8681  * @leading:    is leading
8682  *
8683  * This function performs 2 steps in a Queue state machine
8684  *      actually: 1) RESET->INIT 2) INIT->SETUP
8685  */
8686
8687 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8688                        bool leading)
8689 {
8690         struct bnx2x_queue_state_params q_params = {NULL};
8691         struct bnx2x_queue_setup_params *setup_params =
8692                                                 &q_params.params.setup;
8693         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8694                                                 &q_params.params.tx_only;
8695         int rc;
8696         u8 tx_index;
8697
8698         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8699
8700         /* reset IGU state skip FCoE L2 queue */
8701         if (!IS_FCOE_FP(fp))
8702                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8703                              IGU_INT_ENABLE, 0);
8704
8705         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8706         /* We want to wait for completion in this context */
8707         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8708
8709         /* Prepare the INIT parameters */
8710         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8711
8712         /* Set the command */
8713         q_params.cmd = BNX2X_Q_CMD_INIT;
8714
8715         /* Change the state to INIT */
8716         rc = bnx2x_queue_state_change(bp, &q_params);
8717         if (rc) {
8718                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8719                 return rc;
8720         }
8721
8722         DP(NETIF_MSG_IFUP, "init complete\n");
8723
8724         /* Now move the Queue to the SETUP state... */
8725         memset(setup_params, 0, sizeof(*setup_params));
8726
8727         /* Set QUEUE flags */
8728         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8729
8730         /* Set general SETUP parameters */
8731         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8732                                 FIRST_TX_COS_INDEX);
8733
8734         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8735                             &setup_params->rxq_params);
8736
8737         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8738                            FIRST_TX_COS_INDEX);
8739
8740         /* Set the command */
8741         q_params.cmd = BNX2X_Q_CMD_SETUP;
8742
8743         if (IS_FCOE_FP(fp))
8744                 bp->fcoe_init = true;
8745
8746         /* Change the state to SETUP */
8747         rc = bnx2x_queue_state_change(bp, &q_params);
8748         if (rc) {
8749                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8750                 return rc;
8751         }
8752
8753         /* loop through the relevant tx-only indices */
8754         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8755               tx_index < fp->max_cos;
8756               tx_index++) {
8757
8758                 /* prepare and send tx-only ramrod*/
8759                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8760                                           tx_only_params, tx_index, leading);
8761                 if (rc) {
8762                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8763                                   fp->index, tx_index);
8764                         return rc;
8765                 }
8766         }
8767
8768         return rc;
8769 }
8770
8771 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8772 {
8773         struct bnx2x_fastpath *fp = &bp->fp[index];
8774         struct bnx2x_fp_txdata *txdata;
8775         struct bnx2x_queue_state_params q_params = {NULL};
8776         int rc, tx_index;
8777
8778         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8779
8780         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8781         /* We want to wait for completion in this context */
8782         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8783
8784         /* close tx-only connections */
8785         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8786              tx_index < fp->max_cos;
8787              tx_index++){
8788
8789                 /* ascertain this is a normal queue*/
8790                 txdata = fp->txdata_ptr[tx_index];
8791
8792                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8793                                                         txdata->txq_index);
8794
8795                 /* send halt terminate on tx-only connection */
8796                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8797                 memset(&q_params.params.terminate, 0,
8798                        sizeof(q_params.params.terminate));
8799                 q_params.params.terminate.cid_index = tx_index;
8800
8801                 rc = bnx2x_queue_state_change(bp, &q_params);
8802                 if (rc)
8803                         return rc;
8804
8805                 /* send halt terminate on tx-only connection */
8806                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8807                 memset(&q_params.params.cfc_del, 0,
8808                        sizeof(q_params.params.cfc_del));
8809                 q_params.params.cfc_del.cid_index = tx_index;
8810                 rc = bnx2x_queue_state_change(bp, &q_params);
8811                 if (rc)
8812                         return rc;
8813         }
8814         /* Stop the primary connection: */
8815         /* ...halt the connection */
8816         q_params.cmd = BNX2X_Q_CMD_HALT;
8817         rc = bnx2x_queue_state_change(bp, &q_params);
8818         if (rc)
8819                 return rc;
8820
8821         /* ...terminate the connection */
8822         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8823         memset(&q_params.params.terminate, 0,
8824                sizeof(q_params.params.terminate));
8825         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8826         rc = bnx2x_queue_state_change(bp, &q_params);
8827         if (rc)
8828                 return rc;
8829         /* ...delete cfc entry */
8830         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8831         memset(&q_params.params.cfc_del, 0,
8832                sizeof(q_params.params.cfc_del));
8833         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8834         return bnx2x_queue_state_change(bp, &q_params);
8835 }
8836
8837 static void bnx2x_reset_func(struct bnx2x *bp)
8838 {
8839         int port = BP_PORT(bp);
8840         int func = BP_FUNC(bp);
8841         int i;
8842
8843         /* Disable the function in the FW */
8844         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8845         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8846         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8847         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8848
8849         /* FP SBs */
8850         for_each_eth_queue(bp, i) {
8851                 struct bnx2x_fastpath *fp = &bp->fp[i];
8852                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8853                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8854                            SB_DISABLED);
8855         }
8856
8857         if (CNIC_LOADED(bp))
8858                 /* CNIC SB */
8859                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8860                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8861                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8862
8863         /* SP SB */
8864         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8865                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8866                 SB_DISABLED);
8867
8868         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8869                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8870                        0);
8871
8872         /* Configure IGU */
8873         if (bp->common.int_block == INT_BLOCK_HC) {
8874                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8875                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8876         } else {
8877                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8878                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8879         }
8880
8881         if (CNIC_LOADED(bp)) {
8882                 /* Disable Timer scan */
8883                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8884                 /*
8885                  * Wait for at least 10ms and up to 2 second for the timers
8886                  * scan to complete
8887                  */
8888                 for (i = 0; i < 200; i++) {
8889                         usleep_range(10000, 20000);
8890                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8891                                 break;
8892                 }
8893         }
8894         /* Clear ILT */
8895         bnx2x_clear_func_ilt(bp, func);
8896
8897         /* Timers workaround bug for E2: if this is vnic-3,
8898          * we need to set the entire ilt range for this timers.
8899          */
8900         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8901                 struct ilt_client_info ilt_cli;
8902                 /* use dummy TM client */
8903                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8904                 ilt_cli.start = 0;
8905                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8906                 ilt_cli.client_num = ILT_CLIENT_TM;
8907
8908                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8909         }
8910
8911         /* this assumes that reset_port() called before reset_func()*/
8912         if (!CHIP_IS_E1x(bp))
8913                 bnx2x_pf_disable(bp);
8914
8915         bp->dmae_ready = 0;
8916 }
8917
8918 static void bnx2x_reset_port(struct bnx2x *bp)
8919 {
8920         int port = BP_PORT(bp);
8921         u32 val;
8922
8923         /* Reset physical Link */
8924         bnx2x__link_reset(bp);
8925
8926         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8927
8928         /* Do not rcv packets to BRB */
8929         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8930         /* Do not direct rcv packets that are not for MCP to the BRB */
8931         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8932                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8933
8934         /* Configure AEU */
8935         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8936
8937         msleep(100);
8938         /* Check for BRB port occupancy */
8939         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8940         if (val)
8941                 DP(NETIF_MSG_IFDOWN,
8942                    "BRB1 is not empty  %d blocks are occupied\n", val);
8943
8944         /* TODO: Close Doorbell port? */
8945 }
8946
8947 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8948 {
8949         struct bnx2x_func_state_params func_params = {NULL};
8950
8951         /* Prepare parameters for function state transitions */
8952         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8953
8954         func_params.f_obj = &bp->func_obj;
8955         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8956
8957         func_params.params.hw_init.load_phase = load_code;
8958
8959         return bnx2x_func_state_change(bp, &func_params);
8960 }
8961
8962 static int bnx2x_func_stop(struct bnx2x *bp)
8963 {
8964         struct bnx2x_func_state_params func_params = {NULL};
8965         int rc;
8966
8967         /* Prepare parameters for function state transitions */
8968         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8969         func_params.f_obj = &bp->func_obj;
8970         func_params.cmd = BNX2X_F_CMD_STOP;
8971
8972         /*
8973          * Try to stop the function the 'good way'. If fails (in case
8974          * of a parity error during bnx2x_chip_cleanup()) and we are
8975          * not in a debug mode, perform a state transaction in order to
8976          * enable further HW_RESET transaction.
8977          */
8978         rc = bnx2x_func_state_change(bp, &func_params);
8979         if (rc) {
8980 #ifdef BNX2X_STOP_ON_ERROR
8981                 return rc;
8982 #else
8983                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8984                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8985                 return bnx2x_func_state_change(bp, &func_params);
8986 #endif
8987         }
8988
8989         return 0;
8990 }
8991
8992 /**
8993  * bnx2x_send_unload_req - request unload mode from the MCP.
8994  *
8995  * @bp:                 driver handle
8996  * @unload_mode:        requested function's unload mode
8997  *
8998  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8999  */
9000 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9001 {
9002         u32 reset_code = 0;
9003         int port = BP_PORT(bp);
9004
9005         /* Select the UNLOAD request mode */
9006         if (unload_mode == UNLOAD_NORMAL)
9007                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9008
9009         else if (bp->flags & NO_WOL_FLAG)
9010                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9011
9012         else if (bp->wol) {
9013                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9014                 u8 *mac_addr = bp->dev->dev_addr;
9015                 struct pci_dev *pdev = bp->pdev;
9016                 u32 val;
9017                 u16 pmc;
9018
9019                 /* The mac address is written to entries 1-4 to
9020                  * preserve entry 0 which is used by the PMF
9021                  */
9022                 u8 entry = (BP_VN(bp) + 1)*8;
9023
9024                 val = (mac_addr[0] << 8) | mac_addr[1];
9025                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9026
9027                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9028                       (mac_addr[4] << 8) | mac_addr[5];
9029                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9030
9031                 /* Enable the PME and clear the status */
9032                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9033                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9034                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9035
9036                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9037
9038         } else
9039                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9040
9041         /* Send the request to the MCP */
9042         if (!BP_NOMCP(bp))
9043                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9044         else {
9045                 int path = BP_PATH(bp);
9046
9047                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9048                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9049                    bnx2x_load_count[path][2]);
9050                 bnx2x_load_count[path][0]--;
9051                 bnx2x_load_count[path][1 + port]--;
9052                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9053                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9054                    bnx2x_load_count[path][2]);
9055                 if (bnx2x_load_count[path][0] == 0)
9056                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9057                 else if (bnx2x_load_count[path][1 + port] == 0)
9058                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9059                 else
9060                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9061         }
9062
9063         return reset_code;
9064 }
9065
9066 /**
9067  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9068  *
9069  * @bp:         driver handle
9070  * @keep_link:          true iff link should be kept up
9071  */
9072 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9073 {
9074         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9075
9076         /* Report UNLOAD_DONE to MCP */
9077         if (!BP_NOMCP(bp))
9078                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9079 }
9080
9081 static int bnx2x_func_wait_started(struct bnx2x *bp)
9082 {
9083         int tout = 50;
9084         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9085
9086         if (!bp->port.pmf)
9087                 return 0;
9088
9089         /*
9090          * (assumption: No Attention from MCP at this stage)
9091          * PMF probably in the middle of TX disable/enable transaction
9092          * 1. Sync IRS for default SB
9093          * 2. Sync SP queue - this guarantees us that attention handling started
9094          * 3. Wait, that TX disable/enable transaction completes
9095          *
9096          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9097          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9098          * received completion for the transaction the state is TX_STOPPED.
9099          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9100          * transaction.
9101          */
9102
9103         /* make sure default SB ISR is done */
9104         if (msix)
9105                 synchronize_irq(bp->msix_table[0].vector);
9106         else
9107                 synchronize_irq(bp->pdev->irq);
9108
9109         flush_workqueue(bnx2x_wq);
9110         flush_workqueue(bnx2x_iov_wq);
9111
9112         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9113                                 BNX2X_F_STATE_STARTED && tout--)
9114                 msleep(20);
9115
9116         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9117                                                 BNX2X_F_STATE_STARTED) {
9118 #ifdef BNX2X_STOP_ON_ERROR
9119                 BNX2X_ERR("Wrong function state\n");
9120                 return -EBUSY;
9121 #else
9122                 /*
9123                  * Failed to complete the transaction in a "good way"
9124                  * Force both transactions with CLR bit
9125                  */
9126                 struct bnx2x_func_state_params func_params = {NULL};
9127
9128                 DP(NETIF_MSG_IFDOWN,
9129                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9130
9131                 func_params.f_obj = &bp->func_obj;
9132                 __set_bit(RAMROD_DRV_CLR_ONLY,
9133                                         &func_params.ramrod_flags);
9134
9135                 /* STARTED-->TX_ST0PPED */
9136                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9137                 bnx2x_func_state_change(bp, &func_params);
9138
9139                 /* TX_ST0PPED-->STARTED */
9140                 func_params.cmd = BNX2X_F_CMD_TX_START;
9141                 return bnx2x_func_state_change(bp, &func_params);
9142 #endif
9143         }
9144
9145         return 0;
9146 }
9147
9148 static void bnx2x_disable_ptp(struct bnx2x *bp)
9149 {
9150         int port = BP_PORT(bp);
9151
9152         /* Disable sending PTP packets to host */
9153         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9154                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9155
9156         /* Reset PTP event detection rules */
9157         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9158                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9159         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9160                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9161         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9162                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9163         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9164                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9165
9166         /* Disable the PTP feature */
9167         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9168                NIG_REG_P0_PTP_EN, 0x0);
9169 }
9170
9171 /* Called during unload, to stop PTP-related stuff */
9172 void bnx2x_stop_ptp(struct bnx2x *bp)
9173 {
9174         /* Cancel PTP work queue. Should be done after the Tx queues are
9175          * drained to prevent additional scheduling.
9176          */
9177         cancel_work_sync(&bp->ptp_task);
9178
9179         if (bp->ptp_tx_skb) {
9180                 dev_kfree_skb_any(bp->ptp_tx_skb);
9181                 bp->ptp_tx_skb = NULL;
9182         }
9183
9184         /* Disable PTP in HW */
9185         bnx2x_disable_ptp(bp);
9186
9187         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9188 }
9189
9190 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9191 {
9192         int port = BP_PORT(bp);
9193         int i, rc = 0;
9194         u8 cos;
9195         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9196         u32 reset_code;
9197
9198         /* Wait until tx fastpath tasks complete */
9199         for_each_tx_queue(bp, i) {
9200                 struct bnx2x_fastpath *fp = &bp->fp[i];
9201
9202                 for_each_cos_in_tx_queue(fp, cos)
9203                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9204 #ifdef BNX2X_STOP_ON_ERROR
9205                 if (rc)
9206                         return;
9207 #endif
9208         }
9209
9210         /* Give HW time to discard old tx messages */
9211         usleep_range(1000, 2000);
9212
9213         /* Clean all ETH MACs */
9214         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9215                                 false);
9216         if (rc < 0)
9217                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9218
9219         /* Clean up UC list  */
9220         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9221                                 true);
9222         if (rc < 0)
9223                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9224                           rc);
9225
9226         /* Disable LLH */
9227         if (!CHIP_IS_E1(bp))
9228                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9229
9230         /* Set "drop all" (stop Rx).
9231          * We need to take a netif_addr_lock() here in order to prevent
9232          * a race between the completion code and this code.
9233          */
9234         netif_addr_lock_bh(bp->dev);
9235         /* Schedule the rx_mode command */
9236         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9237                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9238         else
9239                 bnx2x_set_storm_rx_mode(bp);
9240
9241         /* Cleanup multicast configuration */
9242         rparam.mcast_obj = &bp->mcast_obj;
9243         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9244         if (rc < 0)
9245                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9246
9247         netif_addr_unlock_bh(bp->dev);
9248
9249         bnx2x_iov_chip_cleanup(bp);
9250
9251         /*
9252          * Send the UNLOAD_REQUEST to the MCP. This will return if
9253          * this function should perform FUNC, PORT or COMMON HW
9254          * reset.
9255          */
9256         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9257
9258         /*
9259          * (assumption: No Attention from MCP at this stage)
9260          * PMF probably in the middle of TX disable/enable transaction
9261          */
9262         rc = bnx2x_func_wait_started(bp);
9263         if (rc) {
9264                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9265 #ifdef BNX2X_STOP_ON_ERROR
9266                 return;
9267 #endif
9268         }
9269
9270         /* Close multi and leading connections
9271          * Completions for ramrods are collected in a synchronous way
9272          */
9273         for_each_eth_queue(bp, i)
9274                 if (bnx2x_stop_queue(bp, i))
9275 #ifdef BNX2X_STOP_ON_ERROR
9276                         return;
9277 #else
9278                         goto unload_error;
9279 #endif
9280
9281         if (CNIC_LOADED(bp)) {
9282                 for_each_cnic_queue(bp, i)
9283                         if (bnx2x_stop_queue(bp, i))
9284 #ifdef BNX2X_STOP_ON_ERROR
9285                                 return;
9286 #else
9287                                 goto unload_error;
9288 #endif
9289         }
9290
9291         /* If SP settings didn't get completed so far - something
9292          * very wrong has happen.
9293          */
9294         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9295                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9296
9297 #ifndef BNX2X_STOP_ON_ERROR
9298 unload_error:
9299 #endif
9300         rc = bnx2x_func_stop(bp);
9301         if (rc) {
9302                 BNX2X_ERR("Function stop failed!\n");
9303 #ifdef BNX2X_STOP_ON_ERROR
9304                 return;
9305 #endif
9306         }
9307
9308         /* stop_ptp should be after the Tx queues are drained to prevent
9309          * scheduling to the cancelled PTP work queue. It should also be after
9310          * function stop ramrod is sent, since as part of this ramrod FW access
9311          * PTP registers.
9312          */
9313         bnx2x_stop_ptp(bp);
9314
9315         /* Disable HW interrupts, NAPI */
9316         bnx2x_netif_stop(bp, 1);
9317         /* Delete all NAPI objects */
9318         bnx2x_del_all_napi(bp);
9319         if (CNIC_LOADED(bp))
9320                 bnx2x_del_all_napi_cnic(bp);
9321
9322         /* Release IRQs */
9323         bnx2x_free_irq(bp);
9324
9325         /* Reset the chip */
9326         rc = bnx2x_reset_hw(bp, reset_code);
9327         if (rc)
9328                 BNX2X_ERR("HW_RESET failed\n");
9329
9330         /* Report UNLOAD_DONE to MCP */
9331         bnx2x_send_unload_done(bp, keep_link);
9332 }
9333
9334 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9335 {
9336         u32 val;
9337
9338         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9339
9340         if (CHIP_IS_E1(bp)) {
9341                 int port = BP_PORT(bp);
9342                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9343                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9344
9345                 val = REG_RD(bp, addr);
9346                 val &= ~(0x300);
9347                 REG_WR(bp, addr, val);
9348         } else {
9349                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9350                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9351                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9352                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9353         }
9354 }
9355
9356 /* Close gates #2, #3 and #4: */
9357 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9358 {
9359         u32 val;
9360
9361         /* Gates #2 and #4a are closed/opened for "not E1" only */
9362         if (!CHIP_IS_E1(bp)) {
9363                 /* #4 */
9364                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9365                 /* #2 */
9366                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9367         }
9368
9369         /* #3 */
9370         if (CHIP_IS_E1x(bp)) {
9371                 /* Prevent interrupts from HC on both ports */
9372                 val = REG_RD(bp, HC_REG_CONFIG_1);
9373                 REG_WR(bp, HC_REG_CONFIG_1,
9374                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9375                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9376
9377                 val = REG_RD(bp, HC_REG_CONFIG_0);
9378                 REG_WR(bp, HC_REG_CONFIG_0,
9379                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9380                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9381         } else {
9382                 /* Prevent incoming interrupts in IGU */
9383                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9384
9385                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9386                        (!close) ?
9387                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9388                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9389         }
9390
9391         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9392                 close ? "closing" : "opening");
9393         mmiowb();
9394 }
9395
9396 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9397
9398 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9399 {
9400         /* Do some magic... */
9401         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9402         *magic_val = val & SHARED_MF_CLP_MAGIC;
9403         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9404 }
9405
9406 /**
9407  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9408  *
9409  * @bp:         driver handle
9410  * @magic_val:  old value of the `magic' bit.
9411  */
9412 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9413 {
9414         /* Restore the `magic' bit value... */
9415         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9416         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9417                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9418 }
9419
9420 /**
9421  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9422  *
9423  * @bp:         driver handle
9424  * @magic_val:  old value of 'magic' bit.
9425  *
9426  * Takes care of CLP configurations.
9427  */
9428 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9429 {
9430         u32 shmem;
9431         u32 validity_offset;
9432
9433         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9434
9435         /* Set `magic' bit in order to save MF config */
9436         if (!CHIP_IS_E1(bp))
9437                 bnx2x_clp_reset_prep(bp, magic_val);
9438
9439         /* Get shmem offset */
9440         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9441         validity_offset =
9442                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9443
9444         /* Clear validity map flags */
9445         if (shmem > 0)
9446                 REG_WR(bp, shmem + validity_offset, 0);
9447 }
9448
9449 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9450 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9451
9452 /**
9453  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9454  *
9455  * @bp: driver handle
9456  */
9457 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9458 {
9459         /* special handling for emulation and FPGA,
9460            wait 10 times longer */
9461         if (CHIP_REV_IS_SLOW(bp))
9462                 msleep(MCP_ONE_TIMEOUT*10);
9463         else
9464                 msleep(MCP_ONE_TIMEOUT);
9465 }
9466
9467 /*
9468  * initializes bp->common.shmem_base and waits for validity signature to appear
9469  */
9470 static int bnx2x_init_shmem(struct bnx2x *bp)
9471 {
9472         int cnt = 0;
9473         u32 val = 0;
9474
9475         do {
9476                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9477                 if (bp->common.shmem_base) {
9478                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9479                         if (val & SHR_MEM_VALIDITY_MB)
9480                                 return 0;
9481                 }
9482
9483                 bnx2x_mcp_wait_one(bp);
9484
9485         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9486
9487         BNX2X_ERR("BAD MCP validity signature\n");
9488
9489         return -ENODEV;
9490 }
9491
9492 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9493 {
9494         int rc = bnx2x_init_shmem(bp);
9495
9496         /* Restore the `magic' bit value */
9497         if (!CHIP_IS_E1(bp))
9498                 bnx2x_clp_reset_done(bp, magic_val);
9499
9500         return rc;
9501 }
9502
9503 static void bnx2x_pxp_prep(struct bnx2x *bp)
9504 {
9505         if (!CHIP_IS_E1(bp)) {
9506                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9507                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9508                 mmiowb();
9509         }
9510 }
9511
9512 /*
9513  * Reset the whole chip except for:
9514  *      - PCIE core
9515  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9516  *              one reset bit)
9517  *      - IGU
9518  *      - MISC (including AEU)
9519  *      - GRC
9520  *      - RBCN, RBCP
9521  */
9522 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9523 {
9524         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9525         u32 global_bits2, stay_reset2;
9526
9527         /*
9528          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9529          * (per chip) blocks.
9530          */
9531         global_bits2 =
9532                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9533                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9534
9535         /* Don't reset the following blocks.
9536          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9537          *            reset, as in 4 port device they might still be owned
9538          *            by the MCP (there is only one leader per path).
9539          */
9540         not_reset_mask1 =
9541                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9542                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9543                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9544
9545         not_reset_mask2 =
9546                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9547                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9548                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9549                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9550                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9551                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9552                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9553                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9554                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9555                 MISC_REGISTERS_RESET_REG_2_PGLC |
9556                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9557                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9558                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9559                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9560                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9561                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9562
9563         /*
9564          * Keep the following blocks in reset:
9565          *  - all xxMACs are handled by the bnx2x_link code.
9566          */
9567         stay_reset2 =
9568                 MISC_REGISTERS_RESET_REG_2_XMAC |
9569                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9570
9571         /* Full reset masks according to the chip */
9572         reset_mask1 = 0xffffffff;
9573
9574         if (CHIP_IS_E1(bp))
9575                 reset_mask2 = 0xffff;
9576         else if (CHIP_IS_E1H(bp))
9577                 reset_mask2 = 0x1ffff;
9578         else if (CHIP_IS_E2(bp))
9579                 reset_mask2 = 0xfffff;
9580         else /* CHIP_IS_E3 */
9581                 reset_mask2 = 0x3ffffff;
9582
9583         /* Don't reset global blocks unless we need to */
9584         if (!global)
9585                 reset_mask2 &= ~global_bits2;
9586
9587         /*
9588          * In case of attention in the QM, we need to reset PXP
9589          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9590          * because otherwise QM reset would release 'close the gates' shortly
9591          * before resetting the PXP, then the PSWRQ would send a write
9592          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9593          * read the payload data from PSWWR, but PSWWR would not
9594          * respond. The write queue in PGLUE would stuck, dmae commands
9595          * would not return. Therefore it's important to reset the second
9596          * reset register (containing the
9597          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9598          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9599          * bit).
9600          */
9601         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9602                reset_mask2 & (~not_reset_mask2));
9603
9604         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9605                reset_mask1 & (~not_reset_mask1));
9606
9607         barrier();
9608         mmiowb();
9609
9610         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9611                reset_mask2 & (~stay_reset2));
9612
9613         barrier();
9614         mmiowb();
9615
9616         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9617         mmiowb();
9618 }
9619
9620 /**
9621  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9622  * It should get cleared in no more than 1s.
9623  *
9624  * @bp: driver handle
9625  *
9626  * It should get cleared in no more than 1s. Returns 0 if
9627  * pending writes bit gets cleared.
9628  */
9629 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9630 {
9631         u32 cnt = 1000;
9632         u32 pend_bits = 0;
9633
9634         do {
9635                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9636
9637                 if (pend_bits == 0)
9638                         break;
9639
9640                 usleep_range(1000, 2000);
9641         } while (cnt-- > 0);
9642
9643         if (cnt <= 0) {
9644                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9645                           pend_bits);
9646                 return -EBUSY;
9647         }
9648
9649         return 0;
9650 }
9651
9652 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9653 {
9654         int cnt = 1000;
9655         u32 val = 0;
9656         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9657         u32 tags_63_32 = 0;
9658
9659         /* Empty the Tetris buffer, wait for 1s */
9660         do {
9661                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9662                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9663                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9664                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9665                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9666                 if (CHIP_IS_E3(bp))
9667                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9668
9669                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9670                     ((port_is_idle_0 & 0x1) == 0x1) &&
9671                     ((port_is_idle_1 & 0x1) == 0x1) &&
9672                     (pgl_exp_rom2 == 0xffffffff) &&
9673                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9674                         break;
9675                 usleep_range(1000, 2000);
9676         } while (cnt-- > 0);
9677
9678         if (cnt <= 0) {
9679                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9680                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9681                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9682                           pgl_exp_rom2);
9683                 return -EAGAIN;
9684         }
9685
9686         barrier();
9687
9688         /* Close gates #2, #3 and #4 */
9689         bnx2x_set_234_gates(bp, true);
9690
9691         /* Poll for IGU VQs for 57712 and newer chips */
9692         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9693                 return -EAGAIN;
9694
9695         /* TBD: Indicate that "process kill" is in progress to MCP */
9696
9697         /* Clear "unprepared" bit */
9698         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9699         barrier();
9700
9701         /* Make sure all is written to the chip before the reset */
9702         mmiowb();
9703
9704         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9705          * PSWHST, GRC and PSWRD Tetris buffer.
9706          */
9707         usleep_range(1000, 2000);
9708
9709         /* Prepare to chip reset: */
9710         /* MCP */
9711         if (global)
9712                 bnx2x_reset_mcp_prep(bp, &val);
9713
9714         /* PXP */
9715         bnx2x_pxp_prep(bp);
9716         barrier();
9717
9718         /* reset the chip */
9719         bnx2x_process_kill_chip_reset(bp, global);
9720         barrier();
9721
9722         /* clear errors in PGB */
9723         if (!CHIP_IS_E1x(bp))
9724                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9725
9726         /* Recover after reset: */
9727         /* MCP */
9728         if (global && bnx2x_reset_mcp_comp(bp, val))
9729                 return -EAGAIN;
9730
9731         /* TBD: Add resetting the NO_MCP mode DB here */
9732
9733         /* Open the gates #2, #3 and #4 */
9734         bnx2x_set_234_gates(bp, false);
9735
9736         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9737          * reset state, re-enable attentions. */
9738
9739         return 0;
9740 }
9741
9742 static int bnx2x_leader_reset(struct bnx2x *bp)
9743 {
9744         int rc = 0;
9745         bool global = bnx2x_reset_is_global(bp);
9746         u32 load_code;
9747
9748         /* if not going to reset MCP - load "fake" driver to reset HW while
9749          * driver is owner of the HW
9750          */
9751         if (!global && !BP_NOMCP(bp)) {
9752                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9753                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9754                 if (!load_code) {
9755                         BNX2X_ERR("MCP response failure, aborting\n");
9756                         rc = -EAGAIN;
9757                         goto exit_leader_reset;
9758                 }
9759                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9760                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9761                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9762                         rc = -EAGAIN;
9763                         goto exit_leader_reset2;
9764                 }
9765                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9766                 if (!load_code) {
9767                         BNX2X_ERR("MCP response failure, aborting\n");
9768                         rc = -EAGAIN;
9769                         goto exit_leader_reset2;
9770                 }
9771         }
9772
9773         /* Try to recover after the failure */
9774         if (bnx2x_process_kill(bp, global)) {
9775                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9776                           BP_PATH(bp));
9777                 rc = -EAGAIN;
9778                 goto exit_leader_reset2;
9779         }
9780
9781         /*
9782          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9783          * state.
9784          */
9785         bnx2x_set_reset_done(bp);
9786         if (global)
9787                 bnx2x_clear_reset_global(bp);
9788
9789 exit_leader_reset2:
9790         /* unload "fake driver" if it was loaded */
9791         if (!global && !BP_NOMCP(bp)) {
9792                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9793                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9794         }
9795 exit_leader_reset:
9796         bp->is_leader = 0;
9797         bnx2x_release_leader_lock(bp);
9798         smp_mb();
9799         return rc;
9800 }
9801
9802 static void bnx2x_recovery_failed(struct bnx2x *bp)
9803 {
9804         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9805
9806         /* Disconnect this device */
9807         netif_device_detach(bp->dev);
9808
9809         /*
9810          * Block ifup for all function on this engine until "process kill"
9811          * or power cycle.
9812          */
9813         bnx2x_set_reset_in_progress(bp);
9814
9815         /* Shut down the power */
9816         bnx2x_set_power_state(bp, PCI_D3hot);
9817
9818         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9819
9820         smp_mb();
9821 }
9822
9823 /*
9824  * Assumption: runs under rtnl lock. This together with the fact
9825  * that it's called only from bnx2x_sp_rtnl() ensure that it
9826  * will never be called when netif_running(bp->dev) is false.
9827  */
9828 static void bnx2x_parity_recover(struct bnx2x *bp)
9829 {
9830         bool global = false;
9831         u32 error_recovered, error_unrecovered;
9832         bool is_parity;
9833
9834         DP(NETIF_MSG_HW, "Handling parity\n");
9835         while (1) {
9836                 switch (bp->recovery_state) {
9837                 case BNX2X_RECOVERY_INIT:
9838                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9839                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9840                         WARN_ON(!is_parity);
9841
9842                         /* Try to get a LEADER_LOCK HW lock */
9843                         if (bnx2x_trylock_leader_lock(bp)) {
9844                                 bnx2x_set_reset_in_progress(bp);
9845                                 /*
9846                                  * Check if there is a global attention and if
9847                                  * there was a global attention, set the global
9848                                  * reset bit.
9849                                  */
9850
9851                                 if (global)
9852                                         bnx2x_set_reset_global(bp);
9853
9854                                 bp->is_leader = 1;
9855                         }
9856
9857                         /* Stop the driver */
9858                         /* If interface has been removed - break */
9859                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9860                                 return;
9861
9862                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9863
9864                         /* Ensure "is_leader", MCP command sequence and
9865                          * "recovery_state" update values are seen on other
9866                          * CPUs.
9867                          */
9868                         smp_mb();
9869                         break;
9870
9871                 case BNX2X_RECOVERY_WAIT:
9872                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9873                         if (bp->is_leader) {
9874                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9875                                 bool other_load_status =
9876                                         bnx2x_get_load_status(bp, other_engine);
9877                                 bool load_status =
9878                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9879                                 global = bnx2x_reset_is_global(bp);
9880
9881                                 /*
9882                                  * In case of a parity in a global block, let
9883                                  * the first leader that performs a
9884                                  * leader_reset() reset the global blocks in
9885                                  * order to clear global attentions. Otherwise
9886                                  * the gates will remain closed for that
9887                                  * engine.
9888                                  */
9889                                 if (load_status ||
9890                                     (global && other_load_status)) {
9891                                         /* Wait until all other functions get
9892                                          * down.
9893                                          */
9894                                         schedule_delayed_work(&bp->sp_rtnl_task,
9895                                                                 HZ/10);
9896                                         return;
9897                                 } else {
9898                                         /* If all other functions got down -
9899                                          * try to bring the chip back to
9900                                          * normal. In any case it's an exit
9901                                          * point for a leader.
9902                                          */
9903                                         if (bnx2x_leader_reset(bp)) {
9904                                                 bnx2x_recovery_failed(bp);
9905                                                 return;
9906                                         }
9907
9908                                         /* If we are here, means that the
9909                                          * leader has succeeded and doesn't
9910                                          * want to be a leader any more. Try
9911                                          * to continue as a none-leader.
9912                                          */
9913                                         break;
9914                                 }
9915                         } else { /* non-leader */
9916                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9917                                         /* Try to get a LEADER_LOCK HW lock as
9918                                          * long as a former leader may have
9919                                          * been unloaded by the user or
9920                                          * released a leadership by another
9921                                          * reason.
9922                                          */
9923                                         if (bnx2x_trylock_leader_lock(bp)) {
9924                                                 /* I'm a leader now! Restart a
9925                                                  * switch case.
9926                                                  */
9927                                                 bp->is_leader = 1;
9928                                                 break;
9929                                         }
9930
9931                                         schedule_delayed_work(&bp->sp_rtnl_task,
9932                                                                 HZ/10);
9933                                         return;
9934
9935                                 } else {
9936                                         /*
9937                                          * If there was a global attention, wait
9938                                          * for it to be cleared.
9939                                          */
9940                                         if (bnx2x_reset_is_global(bp)) {
9941                                                 schedule_delayed_work(
9942                                                         &bp->sp_rtnl_task,
9943                                                         HZ/10);
9944                                                 return;
9945                                         }
9946
9947                                         error_recovered =
9948                                           bp->eth_stats.recoverable_error;
9949                                         error_unrecovered =
9950                                           bp->eth_stats.unrecoverable_error;
9951                                         bp->recovery_state =
9952                                                 BNX2X_RECOVERY_NIC_LOADING;
9953                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9954                                                 error_unrecovered++;
9955                                                 netdev_err(bp->dev,
9956                                                            "Recovery failed. Power cycle needed\n");
9957                                                 /* Disconnect this device */
9958                                                 netif_device_detach(bp->dev);
9959                                                 /* Shut down the power */
9960                                                 bnx2x_set_power_state(
9961                                                         bp, PCI_D3hot);
9962                                                 smp_mb();
9963                                         } else {
9964                                                 bp->recovery_state =
9965                                                         BNX2X_RECOVERY_DONE;
9966                                                 error_recovered++;
9967                                                 smp_mb();
9968                                         }
9969                                         bp->eth_stats.recoverable_error =
9970                                                 error_recovered;
9971                                         bp->eth_stats.unrecoverable_error =
9972                                                 error_unrecovered;
9973
9974                                         return;
9975                                 }
9976                         }
9977                 default:
9978                         return;
9979                 }
9980         }
9981 }
9982
9983 static int bnx2x_close(struct net_device *dev);
9984
9985 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9986  * scheduled on a general queue in order to prevent a dead lock.
9987  */
9988 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9989 {
9990         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9991
9992         rtnl_lock();
9993
9994         if (!netif_running(bp->dev)) {
9995                 rtnl_unlock();
9996                 return;
9997         }
9998
9999         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10000 #ifdef BNX2X_STOP_ON_ERROR
10001                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10002                           "you will need to reboot when done\n");
10003                 goto sp_rtnl_not_reset;
10004 #endif
10005                 /*
10006                  * Clear all pending SP commands as we are going to reset the
10007                  * function anyway.
10008                  */
10009                 bp->sp_rtnl_state = 0;
10010                 smp_mb();
10011
10012                 bnx2x_parity_recover(bp);
10013
10014                 rtnl_unlock();
10015                 return;
10016         }
10017
10018         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10019 #ifdef BNX2X_STOP_ON_ERROR
10020                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10021                           "you will need to reboot when done\n");
10022                 goto sp_rtnl_not_reset;
10023 #endif
10024
10025                 /*
10026                  * Clear all pending SP commands as we are going to reset the
10027                  * function anyway.
10028                  */
10029                 bp->sp_rtnl_state = 0;
10030                 smp_mb();
10031
10032                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10033                 bnx2x_nic_load(bp, LOAD_NORMAL);
10034
10035                 rtnl_unlock();
10036                 return;
10037         }
10038 #ifdef BNX2X_STOP_ON_ERROR
10039 sp_rtnl_not_reset:
10040 #endif
10041         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10042                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10043         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10044                 bnx2x_after_function_update(bp);
10045         /*
10046          * in case of fan failure we need to reset id if the "stop on error"
10047          * debug flag is set, since we trying to prevent permanent overheating
10048          * damage
10049          */
10050         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10051                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10052                 netif_device_detach(bp->dev);
10053                 bnx2x_close(bp->dev);
10054                 rtnl_unlock();
10055                 return;
10056         }
10057
10058         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10059                 DP(BNX2X_MSG_SP,
10060                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10061                 bnx2x_vfpf_set_mcast(bp->dev);
10062         }
10063         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10064                                &bp->sp_rtnl_state)){
10065                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10066                         bnx2x_tx_disable(bp);
10067                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10068                 }
10069         }
10070
10071         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10072                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10073                 bnx2x_set_rx_mode_inner(bp);
10074         }
10075
10076         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10077                                &bp->sp_rtnl_state))
10078                 bnx2x_pf_set_vfs_vlan(bp);
10079
10080         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10081                 bnx2x_dcbx_stop_hw_tx(bp);
10082                 bnx2x_dcbx_resume_hw_tx(bp);
10083         }
10084
10085         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10086                                &bp->sp_rtnl_state))
10087                 bnx2x_update_mng_version(bp);
10088
10089         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10090          * can be called from other contexts as well)
10091          */
10092         rtnl_unlock();
10093
10094         /* enable SR-IOV if applicable */
10095         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10096                                                &bp->sp_rtnl_state)) {
10097                 bnx2x_disable_sriov(bp);
10098                 bnx2x_enable_sriov(bp);
10099         }
10100 }
10101
10102 static void bnx2x_period_task(struct work_struct *work)
10103 {
10104         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10105
10106         if (!netif_running(bp->dev))
10107                 goto period_task_exit;
10108
10109         if (CHIP_REV_IS_SLOW(bp)) {
10110                 BNX2X_ERR("period task called on emulation, ignoring\n");
10111                 goto period_task_exit;
10112         }
10113
10114         bnx2x_acquire_phy_lock(bp);
10115         /*
10116          * The barrier is needed to ensure the ordering between the writing to
10117          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10118          * the reading here.
10119          */
10120         smp_mb();
10121         if (bp->port.pmf) {
10122                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10123
10124                 /* Re-queue task in 1 sec */
10125                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10126         }
10127
10128         bnx2x_release_phy_lock(bp);
10129 period_task_exit:
10130         return;
10131 }
10132
10133 /*
10134  * Init service functions
10135  */
10136
10137 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10138 {
10139         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10140         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10141         return base + (BP_ABS_FUNC(bp)) * stride;
10142 }
10143
10144 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10145                                         struct bnx2x_mac_vals *vals)
10146 {
10147         u32 val, base_addr, offset, mask, reset_reg;
10148         bool mac_stopped = false;
10149         u8 port = BP_PORT(bp);
10150
10151         /* reset addresses as they also mark which values were changed */
10152         vals->bmac_addr = 0;
10153         vals->umac_addr = 0;
10154         vals->xmac_addr = 0;
10155         vals->emac_addr = 0;
10156
10157         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10158
10159         if (!CHIP_IS_E3(bp)) {
10160                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10161                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10162                 if ((mask & reset_reg) && val) {
10163                         u32 wb_data[2];
10164                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10165                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10166                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10167                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10168                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10169
10170                         /*
10171                          * use rd/wr since we cannot use dmae. This is safe
10172                          * since MCP won't access the bus due to the request
10173                          * to unload, and no function on the path can be
10174                          * loaded at this time.
10175                          */
10176                         wb_data[0] = REG_RD(bp, base_addr + offset);
10177                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10178                         vals->bmac_addr = base_addr + offset;
10179                         vals->bmac_val[0] = wb_data[0];
10180                         vals->bmac_val[1] = wb_data[1];
10181                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10182                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10183                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10184                 }
10185                 BNX2X_DEV_INFO("Disable emac Rx\n");
10186                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10187                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10188                 REG_WR(bp, vals->emac_addr, 0);
10189                 mac_stopped = true;
10190         } else {
10191                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10192                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10193                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10194                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10195                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10196                                val & ~(1 << 1));
10197                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10198                                val | (1 << 1));
10199                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10200                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10201                         REG_WR(bp, vals->xmac_addr, 0);
10202                         mac_stopped = true;
10203                 }
10204                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10205                 if (mask & reset_reg) {
10206                         BNX2X_DEV_INFO("Disable umac Rx\n");
10207                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10208                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10209                         vals->umac_val = REG_RD(bp, vals->umac_addr);
10210                         REG_WR(bp, vals->umac_addr, 0);
10211                         mac_stopped = true;
10212                 }
10213         }
10214
10215         if (mac_stopped)
10216                 msleep(20);
10217 }
10218
10219 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10220 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10221                                         0x1848 + ((f) << 4))
10222 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10223 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10224 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10225
10226 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10227 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10228 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10229
10230 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10231 {
10232         /* UNDI marks its presence in DORQ -
10233          * it initializes CID offset for normal bell to 0x7
10234          */
10235         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10236             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10237                 return false;
10238
10239         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10240                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10241                 return true;
10242         }
10243
10244         return false;
10245 }
10246
10247 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10248 {
10249         u16 rcq, bd;
10250         u32 addr, tmp_reg;
10251
10252         if (BP_FUNC(bp) < 2)
10253                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10254         else
10255                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10256
10257         tmp_reg = REG_RD(bp, addr);
10258         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10259         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10260
10261         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10262         REG_WR(bp, addr, tmp_reg);
10263
10264         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10265                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10266 }
10267
10268 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10269 {
10270         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10271                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10272         if (!rc) {
10273                 BNX2X_ERR("MCP response failure, aborting\n");
10274                 return -EBUSY;
10275         }
10276
10277         return 0;
10278 }
10279
10280 static struct bnx2x_prev_path_list *
10281                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10282 {
10283         struct bnx2x_prev_path_list *tmp_list;
10284
10285         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10286                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10287                     bp->pdev->bus->number == tmp_list->bus &&
10288                     BP_PATH(bp) == tmp_list->path)
10289                         return tmp_list;
10290
10291         return NULL;
10292 }
10293
10294 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10295 {
10296         struct bnx2x_prev_path_list *tmp_list;
10297         int rc;
10298
10299         rc = down_interruptible(&bnx2x_prev_sem);
10300         if (rc) {
10301                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10302                 return rc;
10303         }
10304
10305         tmp_list = bnx2x_prev_path_get_entry(bp);
10306         if (tmp_list) {
10307                 tmp_list->aer = 1;
10308                 rc = 0;
10309         } else {
10310                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10311                           BP_PATH(bp));
10312         }
10313
10314         up(&bnx2x_prev_sem);
10315
10316         return rc;
10317 }
10318
10319 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10320 {
10321         struct bnx2x_prev_path_list *tmp_list;
10322         bool rc = false;
10323
10324         if (down_trylock(&bnx2x_prev_sem))
10325                 return false;
10326
10327         tmp_list = bnx2x_prev_path_get_entry(bp);
10328         if (tmp_list) {
10329                 if (tmp_list->aer) {
10330                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10331                            BP_PATH(bp));
10332                 } else {
10333                         rc = true;
10334                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10335                                        BP_PATH(bp));
10336                 }
10337         }
10338
10339         up(&bnx2x_prev_sem);
10340
10341         return rc;
10342 }
10343
10344 bool bnx2x_port_after_undi(struct bnx2x *bp)
10345 {
10346         struct bnx2x_prev_path_list *entry;
10347         bool val;
10348
10349         down(&bnx2x_prev_sem);
10350
10351         entry = bnx2x_prev_path_get_entry(bp);
10352         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10353
10354         up(&bnx2x_prev_sem);
10355
10356         return val;
10357 }
10358
10359 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10360 {
10361         struct bnx2x_prev_path_list *tmp_list;
10362         int rc;
10363
10364         rc = down_interruptible(&bnx2x_prev_sem);
10365         if (rc) {
10366                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10367                 return rc;
10368         }
10369
10370         /* Check whether the entry for this path already exists */
10371         tmp_list = bnx2x_prev_path_get_entry(bp);
10372         if (tmp_list) {
10373                 if (!tmp_list->aer) {
10374                         BNX2X_ERR("Re-Marking the path.\n");
10375                 } else {
10376                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10377                            BP_PATH(bp));
10378                         tmp_list->aer = 0;
10379                 }
10380                 up(&bnx2x_prev_sem);
10381                 return 0;
10382         }
10383         up(&bnx2x_prev_sem);
10384
10385         /* Create an entry for this path and add it */
10386         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10387         if (!tmp_list) {
10388                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10389                 return -ENOMEM;
10390         }
10391
10392         tmp_list->bus = bp->pdev->bus->number;
10393         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10394         tmp_list->path = BP_PATH(bp);
10395         tmp_list->aer = 0;
10396         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10397
10398         rc = down_interruptible(&bnx2x_prev_sem);
10399         if (rc) {
10400                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10401                 kfree(tmp_list);
10402         } else {
10403                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10404                    BP_PATH(bp));
10405                 list_add(&tmp_list->list, &bnx2x_prev_list);
10406                 up(&bnx2x_prev_sem);
10407         }
10408
10409         return rc;
10410 }
10411
10412 static int bnx2x_do_flr(struct bnx2x *bp)
10413 {
10414         struct pci_dev *dev = bp->pdev;
10415
10416         if (CHIP_IS_E1x(bp)) {
10417                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10418                 return -EINVAL;
10419         }
10420
10421         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10422         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10423                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10424                           bp->common.bc_ver);
10425                 return -EINVAL;
10426         }
10427
10428         if (!pci_wait_for_pending_transaction(dev))
10429                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10430
10431         BNX2X_DEV_INFO("Initiating FLR\n");
10432         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10433
10434         return 0;
10435 }
10436
10437 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10438 {
10439         int rc;
10440
10441         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10442
10443         /* Test if previous unload process was already finished for this path */
10444         if (bnx2x_prev_is_path_marked(bp))
10445                 return bnx2x_prev_mcp_done(bp);
10446
10447         BNX2X_DEV_INFO("Path is unmarked\n");
10448
10449         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10450         if (bnx2x_prev_is_after_undi(bp))
10451                 goto out;
10452
10453         /* If function has FLR capabilities, and existing FW version matches
10454          * the one required, then FLR will be sufficient to clean any residue
10455          * left by previous driver
10456          */
10457         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10458
10459         if (!rc) {
10460                 /* fw version is good */
10461                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10462                 rc = bnx2x_do_flr(bp);
10463         }
10464
10465         if (!rc) {
10466                 /* FLR was performed */
10467                 BNX2X_DEV_INFO("FLR successful\n");
10468                 return 0;
10469         }
10470
10471         BNX2X_DEV_INFO("Could not FLR\n");
10472
10473 out:
10474         /* Close the MCP request, return failure*/
10475         rc = bnx2x_prev_mcp_done(bp);
10476         if (!rc)
10477                 rc = BNX2X_PREV_WAIT_NEEDED;
10478
10479         return rc;
10480 }
10481
10482 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10483 {
10484         u32 reset_reg, tmp_reg = 0, rc;
10485         bool prev_undi = false;
10486         struct bnx2x_mac_vals mac_vals;
10487
10488         /* It is possible a previous function received 'common' answer,
10489          * but hasn't loaded yet, therefore creating a scenario of
10490          * multiple functions receiving 'common' on the same path.
10491          */
10492         BNX2X_DEV_INFO("Common unload Flow\n");
10493
10494         memset(&mac_vals, 0, sizeof(mac_vals));
10495
10496         if (bnx2x_prev_is_path_marked(bp))
10497                 return bnx2x_prev_mcp_done(bp);
10498
10499         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10500
10501         /* Reset should be performed after BRB is emptied */
10502         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10503                 u32 timer_count = 1000;
10504
10505                 /* Close the MAC Rx to prevent BRB from filling up */
10506                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10507
10508                 /* close LLH filters towards the BRB */
10509                 bnx2x_set_rx_filter(&bp->link_params, 0);
10510
10511                 /* Check if the UNDI driver was previously loaded */
10512                 if (bnx2x_prev_is_after_undi(bp)) {
10513                         prev_undi = true;
10514                         /* clear the UNDI indication */
10515                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10516                         /* clear possible idle check errors */
10517                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10518                 }
10519                 if (!CHIP_IS_E1x(bp))
10520                         /* block FW from writing to host */
10521                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10522
10523                 /* wait until BRB is empty */
10524                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10525                 while (timer_count) {
10526                         u32 prev_brb = tmp_reg;
10527
10528                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10529                         if (!tmp_reg)
10530                                 break;
10531
10532                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10533
10534                         /* reset timer as long as BRB actually gets emptied */
10535                         if (prev_brb > tmp_reg)
10536                                 timer_count = 1000;
10537                         else
10538                                 timer_count--;
10539
10540                         /* If UNDI resides in memory, manually increment it */
10541                         if (prev_undi)
10542                                 bnx2x_prev_unload_undi_inc(bp, 1);
10543
10544                         udelay(10);
10545                 }
10546
10547                 if (!timer_count)
10548                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10549         }
10550
10551         /* No packets are in the pipeline, path is ready for reset */
10552         bnx2x_reset_common(bp);
10553
10554         if (mac_vals.xmac_addr)
10555                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10556         if (mac_vals.umac_addr)
10557                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10558         if (mac_vals.emac_addr)
10559                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10560         if (mac_vals.bmac_addr) {
10561                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10562                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10563         }
10564
10565         rc = bnx2x_prev_mark_path(bp, prev_undi);
10566         if (rc) {
10567                 bnx2x_prev_mcp_done(bp);
10568                 return rc;
10569         }
10570
10571         return bnx2x_prev_mcp_done(bp);
10572 }
10573
10574 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10575  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10576  * the addresses of the transaction, resulting in was-error bit set in the pci
10577  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10578  * to clear the interrupt which detected this from the pglueb and the was done
10579  * bit
10580  */
10581 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10582 {
10583         if (!CHIP_IS_E1x(bp)) {
10584                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10585                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10586                         DP(BNX2X_MSG_SP,
10587                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10588                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10589                                1 << BP_FUNC(bp));
10590                 }
10591         }
10592 }
10593
10594 static int bnx2x_prev_unload(struct bnx2x *bp)
10595 {
10596         int time_counter = 10;
10597         u32 rc, fw, hw_lock_reg, hw_lock_val;
10598         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10599
10600         /* clear hw from errors which may have resulted from an interrupted
10601          * dmae transaction.
10602          */
10603         bnx2x_prev_interrupted_dmae(bp);
10604
10605         /* Release previously held locks */
10606         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10607                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10608                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10609
10610         hw_lock_val = REG_RD(bp, hw_lock_reg);
10611         if (hw_lock_val) {
10612                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10613                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10614                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10615                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10616                 }
10617
10618                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10619                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10620         } else
10621                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10622
10623         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10624                 BNX2X_DEV_INFO("Release previously held alr\n");
10625                 bnx2x_release_alr(bp);
10626         }
10627
10628         do {
10629                 int aer = 0;
10630                 /* Lock MCP using an unload request */
10631                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10632                 if (!fw) {
10633                         BNX2X_ERR("MCP response failure, aborting\n");
10634                         rc = -EBUSY;
10635                         break;
10636                 }
10637
10638                 rc = down_interruptible(&bnx2x_prev_sem);
10639                 if (rc) {
10640                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10641                                   rc);
10642                 } else {
10643                         /* If Path is marked by EEH, ignore unload status */
10644                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10645                                  bnx2x_prev_path_get_entry(bp)->aer);
10646                         up(&bnx2x_prev_sem);
10647                 }
10648
10649                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10650                         rc = bnx2x_prev_unload_common(bp);
10651                         break;
10652                 }
10653
10654                 /* non-common reply from MCP might require looping */
10655                 rc = bnx2x_prev_unload_uncommon(bp);
10656                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10657                         break;
10658
10659                 msleep(20);
10660         } while (--time_counter);
10661
10662         if (!time_counter || rc) {
10663                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10664                 rc = -EPROBE_DEFER;
10665         }
10666
10667         /* Mark function if its port was used to boot from SAN */
10668         if (bnx2x_port_after_undi(bp))
10669                 bp->link_params.feature_config_flags |=
10670                         FEATURE_CONFIG_BOOT_FROM_SAN;
10671
10672         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10673
10674         return rc;
10675 }
10676
10677 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10678 {
10679         u32 val, val2, val3, val4, id, boot_mode;
10680         u16 pmc;
10681
10682         /* Get the chip revision id and number. */
10683         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10684         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10685         id = ((val & 0xffff) << 16);
10686         val = REG_RD(bp, MISC_REG_CHIP_REV);
10687         id |= ((val & 0xf) << 12);
10688
10689         /* Metal is read from PCI regs, but we can't access >=0x400 from
10690          * the configuration space (so we need to reg_rd)
10691          */
10692         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10693         id |= (((val >> 24) & 0xf) << 4);
10694         val = REG_RD(bp, MISC_REG_BOND_ID);
10695         id |= (val & 0xf);
10696         bp->common.chip_id = id;
10697
10698         /* force 57811 according to MISC register */
10699         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10700                 if (CHIP_IS_57810(bp))
10701                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10702                                 (bp->common.chip_id & 0x0000FFFF);
10703                 else if (CHIP_IS_57810_MF(bp))
10704                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10705                                 (bp->common.chip_id & 0x0000FFFF);
10706                 bp->common.chip_id |= 0x1;
10707         }
10708
10709         /* Set doorbell size */
10710         bp->db_size = (1 << BNX2X_DB_SHIFT);
10711
10712         if (!CHIP_IS_E1x(bp)) {
10713                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10714                 if ((val & 1) == 0)
10715                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10716                 else
10717                         val = (val >> 1) & 1;
10718                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10719                                                        "2_PORT_MODE");
10720                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10721                                                  CHIP_2_PORT_MODE;
10722
10723                 if (CHIP_MODE_IS_4_PORT(bp))
10724                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10725                 else
10726                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10727         } else {
10728                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10729                 bp->pfid = bp->pf_num;                  /* 0..7 */
10730         }
10731
10732         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10733
10734         bp->link_params.chip_id = bp->common.chip_id;
10735         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10736
10737         val = (REG_RD(bp, 0x2874) & 0x55);
10738         if ((bp->common.chip_id & 0x1) ||
10739             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10740                 bp->flags |= ONE_PORT_FLAG;
10741                 BNX2X_DEV_INFO("single port device\n");
10742         }
10743
10744         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10745         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10746                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10747         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10748                        bp->common.flash_size, bp->common.flash_size);
10749
10750         bnx2x_init_shmem(bp);
10751
10752         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10753                                         MISC_REG_GENERIC_CR_1 :
10754                                         MISC_REG_GENERIC_CR_0));
10755
10756         bp->link_params.shmem_base = bp->common.shmem_base;
10757         bp->link_params.shmem2_base = bp->common.shmem2_base;
10758         if (SHMEM2_RD(bp, size) >
10759             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10760                 bp->link_params.lfa_base =
10761                 REG_RD(bp, bp->common.shmem2_base +
10762                        (u32)offsetof(struct shmem2_region,
10763                                      lfa_host_addr[BP_PORT(bp)]));
10764         else
10765                 bp->link_params.lfa_base = 0;
10766         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10767                        bp->common.shmem_base, bp->common.shmem2_base);
10768
10769         if (!bp->common.shmem_base) {
10770                 BNX2X_DEV_INFO("MCP not active\n");
10771                 bp->flags |= NO_MCP_FLAG;
10772                 return;
10773         }
10774
10775         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10776         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10777
10778         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10779                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10780                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10781
10782         bp->link_params.feature_config_flags = 0;
10783         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10784         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10785                 bp->link_params.feature_config_flags |=
10786                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10787         else
10788                 bp->link_params.feature_config_flags &=
10789                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10790
10791         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10792         bp->common.bc_ver = val;
10793         BNX2X_DEV_INFO("bc_ver %X\n", val);
10794         if (val < BNX2X_BC_VER) {
10795                 /* for now only warn
10796                  * later we might need to enforce this */
10797                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10798                           BNX2X_BC_VER, val);
10799         }
10800         bp->link_params.feature_config_flags |=
10801                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10802                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10803
10804         bp->link_params.feature_config_flags |=
10805                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10806                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10807         bp->link_params.feature_config_flags |=
10808                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10809                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10810         bp->link_params.feature_config_flags |=
10811                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10812                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10813
10814         bp->link_params.feature_config_flags |=
10815                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10816                 FEATURE_CONFIG_MT_SUPPORT : 0;
10817
10818         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10819                         BC_SUPPORTS_PFC_STATS : 0;
10820
10821         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10822                         BC_SUPPORTS_FCOE_FEATURES : 0;
10823
10824         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10825                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10826
10827         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10828                         BC_SUPPORTS_RMMOD_CMD : 0;
10829
10830         boot_mode = SHMEM_RD(bp,
10831                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10832                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10833         switch (boot_mode) {
10834         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10835                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10836                 break;
10837         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10838                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10839                 break;
10840         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10841                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10842                 break;
10843         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10844                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10845                 break;
10846         }
10847
10848         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10849         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10850
10851         BNX2X_DEV_INFO("%sWoL capable\n",
10852                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10853
10854         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10855         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10856         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10857         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10858
10859         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10860                  val, val2, val3, val4);
10861 }
10862
10863 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10864 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10865
10866 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10867 {
10868         int pfid = BP_FUNC(bp);
10869         int igu_sb_id;
10870         u32 val;
10871         u8 fid, igu_sb_cnt = 0;
10872
10873         bp->igu_base_sb = 0xff;
10874         if (CHIP_INT_MODE_IS_BC(bp)) {
10875                 int vn = BP_VN(bp);
10876                 igu_sb_cnt = bp->igu_sb_cnt;
10877                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10878                         FP_SB_MAX_E1x;
10879
10880                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10881                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10882
10883                 return 0;
10884         }
10885
10886         /* IGU in normal mode - read CAM */
10887         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10888              igu_sb_id++) {
10889                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10890                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10891                         continue;
10892                 fid = IGU_FID(val);
10893                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10894                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10895                                 continue;
10896                         if (IGU_VEC(val) == 0)
10897                                 /* default status block */
10898                                 bp->igu_dsb_id = igu_sb_id;
10899                         else {
10900                                 if (bp->igu_base_sb == 0xff)
10901                                         bp->igu_base_sb = igu_sb_id;
10902                                 igu_sb_cnt++;
10903                         }
10904                 }
10905         }
10906
10907 #ifdef CONFIG_PCI_MSI
10908         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10909          * optional that number of CAM entries will not be equal to the value
10910          * advertised in PCI.
10911          * Driver should use the minimal value of both as the actual status
10912          * block count
10913          */
10914         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10915 #endif
10916
10917         if (igu_sb_cnt == 0) {
10918                 BNX2X_ERR("CAM configuration error\n");
10919                 return -EINVAL;
10920         }
10921
10922         return 0;
10923 }
10924
10925 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10926 {
10927         int cfg_size = 0, idx, port = BP_PORT(bp);
10928
10929         /* Aggregation of supported attributes of all external phys */
10930         bp->port.supported[0] = 0;
10931         bp->port.supported[1] = 0;
10932         switch (bp->link_params.num_phys) {
10933         case 1:
10934                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10935                 cfg_size = 1;
10936                 break;
10937         case 2:
10938                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10939                 cfg_size = 1;
10940                 break;
10941         case 3:
10942                 if (bp->link_params.multi_phy_config &
10943                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10944                         bp->port.supported[1] =
10945                                 bp->link_params.phy[EXT_PHY1].supported;
10946                         bp->port.supported[0] =
10947                                 bp->link_params.phy[EXT_PHY2].supported;
10948                 } else {
10949                         bp->port.supported[0] =
10950                                 bp->link_params.phy[EXT_PHY1].supported;
10951                         bp->port.supported[1] =
10952                                 bp->link_params.phy[EXT_PHY2].supported;
10953                 }
10954                 cfg_size = 2;
10955                 break;
10956         }
10957
10958         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10959                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10960                            SHMEM_RD(bp,
10961                            dev_info.port_hw_config[port].external_phy_config),
10962                            SHMEM_RD(bp,
10963                            dev_info.port_hw_config[port].external_phy_config2));
10964                         return;
10965         }
10966
10967         if (CHIP_IS_E3(bp))
10968                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10969         else {
10970                 switch (switch_cfg) {
10971                 case SWITCH_CFG_1G:
10972                         bp->port.phy_addr = REG_RD(
10973                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10974                         break;
10975                 case SWITCH_CFG_10G:
10976                         bp->port.phy_addr = REG_RD(
10977                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10978                         break;
10979                 default:
10980                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10981                                   bp->port.link_config[0]);
10982                         return;
10983                 }
10984         }
10985         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10986         /* mask what we support according to speed_cap_mask per configuration */
10987         for (idx = 0; idx < cfg_size; idx++) {
10988                 if (!(bp->link_params.speed_cap_mask[idx] &
10989                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10990                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10991
10992                 if (!(bp->link_params.speed_cap_mask[idx] &
10993                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10994                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10995
10996                 if (!(bp->link_params.speed_cap_mask[idx] &
10997                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10998                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10999
11000                 if (!(bp->link_params.speed_cap_mask[idx] &
11001                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11002                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11003
11004                 if (!(bp->link_params.speed_cap_mask[idx] &
11005                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11006                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11007                                                      SUPPORTED_1000baseT_Full);
11008
11009                 if (!(bp->link_params.speed_cap_mask[idx] &
11010                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11011                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11012
11013                 if (!(bp->link_params.speed_cap_mask[idx] &
11014                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11015                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11016
11017                 if (!(bp->link_params.speed_cap_mask[idx] &
11018                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11019                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11020         }
11021
11022         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11023                        bp->port.supported[1]);
11024 }
11025
11026 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11027 {
11028         u32 link_config, idx, cfg_size = 0;
11029         bp->port.advertising[0] = 0;
11030         bp->port.advertising[1] = 0;
11031         switch (bp->link_params.num_phys) {
11032         case 1:
11033         case 2:
11034                 cfg_size = 1;
11035                 break;
11036         case 3:
11037                 cfg_size = 2;
11038                 break;
11039         }
11040         for (idx = 0; idx < cfg_size; idx++) {
11041                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11042                 link_config = bp->port.link_config[idx];
11043                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11044                 case PORT_FEATURE_LINK_SPEED_AUTO:
11045                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11046                                 bp->link_params.req_line_speed[idx] =
11047                                         SPEED_AUTO_NEG;
11048                                 bp->port.advertising[idx] |=
11049                                         bp->port.supported[idx];
11050                                 if (bp->link_params.phy[EXT_PHY1].type ==
11051                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11052                                         bp->port.advertising[idx] |=
11053                                         (SUPPORTED_100baseT_Half |
11054                                          SUPPORTED_100baseT_Full);
11055                         } else {
11056                                 /* force 10G, no AN */
11057                                 bp->link_params.req_line_speed[idx] =
11058                                         SPEED_10000;
11059                                 bp->port.advertising[idx] |=
11060                                         (ADVERTISED_10000baseT_Full |
11061                                          ADVERTISED_FIBRE);
11062                                 continue;
11063                         }
11064                         break;
11065
11066                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11067                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11068                                 bp->link_params.req_line_speed[idx] =
11069                                         SPEED_10;
11070                                 bp->port.advertising[idx] |=
11071                                         (ADVERTISED_10baseT_Full |
11072                                          ADVERTISED_TP);
11073                         } else {
11074                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11075                                             link_config,
11076                                     bp->link_params.speed_cap_mask[idx]);
11077                                 return;
11078                         }
11079                         break;
11080
11081                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11082                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11083                                 bp->link_params.req_line_speed[idx] =
11084                                         SPEED_10;
11085                                 bp->link_params.req_duplex[idx] =
11086                                         DUPLEX_HALF;
11087                                 bp->port.advertising[idx] |=
11088                                         (ADVERTISED_10baseT_Half |
11089                                          ADVERTISED_TP);
11090                         } else {
11091                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11092                                             link_config,
11093                                           bp->link_params.speed_cap_mask[idx]);
11094                                 return;
11095                         }
11096                         break;
11097
11098                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11099                         if (bp->port.supported[idx] &
11100                             SUPPORTED_100baseT_Full) {
11101                                 bp->link_params.req_line_speed[idx] =
11102                                         SPEED_100;
11103                                 bp->port.advertising[idx] |=
11104                                         (ADVERTISED_100baseT_Full |
11105                                          ADVERTISED_TP);
11106                         } else {
11107                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11108                                             link_config,
11109                                           bp->link_params.speed_cap_mask[idx]);
11110                                 return;
11111                         }
11112                         break;
11113
11114                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11115                         if (bp->port.supported[idx] &
11116                             SUPPORTED_100baseT_Half) {
11117                                 bp->link_params.req_line_speed[idx] =
11118                                                                 SPEED_100;
11119                                 bp->link_params.req_duplex[idx] =
11120                                                                 DUPLEX_HALF;
11121                                 bp->port.advertising[idx] |=
11122                                         (ADVERTISED_100baseT_Half |
11123                                          ADVERTISED_TP);
11124                         } else {
11125                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11126                                     link_config,
11127                                     bp->link_params.speed_cap_mask[idx]);
11128                                 return;
11129                         }
11130                         break;
11131
11132                 case PORT_FEATURE_LINK_SPEED_1G:
11133                         if (bp->port.supported[idx] &
11134                             SUPPORTED_1000baseT_Full) {
11135                                 bp->link_params.req_line_speed[idx] =
11136                                         SPEED_1000;
11137                                 bp->port.advertising[idx] |=
11138                                         (ADVERTISED_1000baseT_Full |
11139                                          ADVERTISED_TP);
11140                         } else {
11141                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11142                                     link_config,
11143                                     bp->link_params.speed_cap_mask[idx]);
11144                                 return;
11145                         }
11146                         break;
11147
11148                 case PORT_FEATURE_LINK_SPEED_2_5G:
11149                         if (bp->port.supported[idx] &
11150                             SUPPORTED_2500baseX_Full) {
11151                                 bp->link_params.req_line_speed[idx] =
11152                                         SPEED_2500;
11153                                 bp->port.advertising[idx] |=
11154                                         (ADVERTISED_2500baseX_Full |
11155                                                 ADVERTISED_TP);
11156                         } else {
11157                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11158                                     link_config,
11159                                     bp->link_params.speed_cap_mask[idx]);
11160                                 return;
11161                         }
11162                         break;
11163
11164                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11165                         if (bp->port.supported[idx] &
11166                             SUPPORTED_10000baseT_Full) {
11167                                 bp->link_params.req_line_speed[idx] =
11168                                         SPEED_10000;
11169                                 bp->port.advertising[idx] |=
11170                                         (ADVERTISED_10000baseT_Full |
11171                                                 ADVERTISED_FIBRE);
11172                         } else {
11173                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11174                                     link_config,
11175                                     bp->link_params.speed_cap_mask[idx]);
11176                                 return;
11177                         }
11178                         break;
11179                 case PORT_FEATURE_LINK_SPEED_20G:
11180                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11181
11182                         break;
11183                 default:
11184                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11185                                   link_config);
11186                                 bp->link_params.req_line_speed[idx] =
11187                                                         SPEED_AUTO_NEG;
11188                                 bp->port.advertising[idx] =
11189                                                 bp->port.supported[idx];
11190                         break;
11191                 }
11192
11193                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11194                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11195                 if (bp->link_params.req_flow_ctrl[idx] ==
11196                     BNX2X_FLOW_CTRL_AUTO) {
11197                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11198                                 bp->link_params.req_flow_ctrl[idx] =
11199                                                         BNX2X_FLOW_CTRL_NONE;
11200                         else
11201                                 bnx2x_set_requested_fc(bp);
11202                 }
11203
11204                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11205                                bp->link_params.req_line_speed[idx],
11206                                bp->link_params.req_duplex[idx],
11207                                bp->link_params.req_flow_ctrl[idx],
11208                                bp->port.advertising[idx]);
11209         }
11210 }
11211
11212 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11213 {
11214         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11215         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11216         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11217         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11218 }
11219
11220 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11221 {
11222         int port = BP_PORT(bp);
11223         u32 config;
11224         u32 ext_phy_type, ext_phy_config, eee_mode;
11225
11226         bp->link_params.bp = bp;
11227         bp->link_params.port = port;
11228
11229         bp->link_params.lane_config =
11230                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11231
11232         bp->link_params.speed_cap_mask[0] =
11233                 SHMEM_RD(bp,
11234                          dev_info.port_hw_config[port].speed_capability_mask) &
11235                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11236         bp->link_params.speed_cap_mask[1] =
11237                 SHMEM_RD(bp,
11238                          dev_info.port_hw_config[port].speed_capability_mask2) &
11239                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11240         bp->port.link_config[0] =
11241                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11242
11243         bp->port.link_config[1] =
11244                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11245
11246         bp->link_params.multi_phy_config =
11247                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11248         /* If the device is capable of WoL, set the default state according
11249          * to the HW
11250          */
11251         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11252         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11253                    (config & PORT_FEATURE_WOL_ENABLED));
11254
11255         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11256             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11257                 bp->flags |= NO_ISCSI_FLAG;
11258         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11259             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11260                 bp->flags |= NO_FCOE_FLAG;
11261
11262         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11263                        bp->link_params.lane_config,
11264                        bp->link_params.speed_cap_mask[0],
11265                        bp->port.link_config[0]);
11266
11267         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11268                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11269         bnx2x_phy_probe(&bp->link_params);
11270         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11271
11272         bnx2x_link_settings_requested(bp);
11273
11274         /*
11275          * If connected directly, work with the internal PHY, otherwise, work
11276          * with the external PHY
11277          */
11278         ext_phy_config =
11279                 SHMEM_RD(bp,
11280                          dev_info.port_hw_config[port].external_phy_config);
11281         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11282         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11283                 bp->mdio.prtad = bp->port.phy_addr;
11284
11285         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11286                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11287                 bp->mdio.prtad =
11288                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11289
11290         /* Configure link feature according to nvram value */
11291         eee_mode = (((SHMEM_RD(bp, dev_info.
11292                       port_feature_config[port].eee_power_mode)) &
11293                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11294                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11295         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11296                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11297                                            EEE_MODE_ENABLE_LPI |
11298                                            EEE_MODE_OUTPUT_TIME;
11299         } else {
11300                 bp->link_params.eee_mode = 0;
11301         }
11302 }
11303
11304 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11305 {
11306         u32 no_flags = NO_ISCSI_FLAG;
11307         int port = BP_PORT(bp);
11308         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11309                                 drv_lic_key[port].max_iscsi_conn);
11310
11311         if (!CNIC_SUPPORT(bp)) {
11312                 bp->flags |= no_flags;
11313                 return;
11314         }
11315
11316         /* Get the number of maximum allowed iSCSI connections */
11317         bp->cnic_eth_dev.max_iscsi_conn =
11318                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11319                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11320
11321         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11322                        bp->cnic_eth_dev.max_iscsi_conn);
11323
11324         /*
11325          * If maximum allowed number of connections is zero -
11326          * disable the feature.
11327          */
11328         if (!bp->cnic_eth_dev.max_iscsi_conn)
11329                 bp->flags |= no_flags;
11330 }
11331
11332 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11333 {
11334         /* Port info */
11335         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11336                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11337         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11338                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11339
11340         /* Node info */
11341         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11342                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11343         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11344                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11345 }
11346
11347 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11348 {
11349         u8 count = 0;
11350
11351         if (IS_MF(bp)) {
11352                 u8 fid;
11353
11354                 /* iterate over absolute function ids for this path: */
11355                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11356                         if (IS_MF_SD(bp)) {
11357                                 u32 cfg = MF_CFG_RD(bp,
11358                                                     func_mf_config[fid].config);
11359
11360                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11361                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11362                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11363                                         count++;
11364                         } else {
11365                                 u32 cfg = MF_CFG_RD(bp,
11366                                                     func_ext_config[fid].
11367                                                                       func_cfg);
11368
11369                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11370                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11371                                         count++;
11372                         }
11373                 }
11374         } else { /* SF */
11375                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11376
11377                 for (port = 0; port < port_cnt; port++) {
11378                         u32 lic = SHMEM_RD(bp,
11379                                            drv_lic_key[port].max_fcoe_conn) ^
11380                                   FW_ENCODE_32BIT_PATTERN;
11381                         if (lic)
11382                                 count++;
11383                 }
11384         }
11385
11386         return count;
11387 }
11388
11389 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11390 {
11391         int port = BP_PORT(bp);
11392         int func = BP_ABS_FUNC(bp);
11393         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11394                                 drv_lic_key[port].max_fcoe_conn);
11395         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11396
11397         if (!CNIC_SUPPORT(bp)) {
11398                 bp->flags |= NO_FCOE_FLAG;
11399                 return;
11400         }
11401
11402         /* Get the number of maximum allowed FCoE connections */
11403         bp->cnic_eth_dev.max_fcoe_conn =
11404                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11405                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11406
11407         /* Calculate the number of maximum allowed FCoE tasks */
11408         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11409
11410         /* check if FCoE resources must be shared between different functions */
11411         if (num_fcoe_func)
11412                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11413
11414         /* Read the WWN: */
11415         if (!IS_MF(bp)) {
11416                 /* Port info */
11417                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11418                         SHMEM_RD(bp,
11419                                  dev_info.port_hw_config[port].
11420                                  fcoe_wwn_port_name_upper);
11421                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11422                         SHMEM_RD(bp,
11423                                  dev_info.port_hw_config[port].
11424                                  fcoe_wwn_port_name_lower);
11425
11426                 /* Node info */
11427                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11428                         SHMEM_RD(bp,
11429                                  dev_info.port_hw_config[port].
11430                                  fcoe_wwn_node_name_upper);
11431                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11432                         SHMEM_RD(bp,
11433                                  dev_info.port_hw_config[port].
11434                                  fcoe_wwn_node_name_lower);
11435         } else if (!IS_MF_SD(bp)) {
11436                 /* Read the WWN info only if the FCoE feature is enabled for
11437                  * this function.
11438                  */
11439                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11440                         bnx2x_get_ext_wwn_info(bp, func);
11441         } else {
11442                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11443                         bnx2x_get_ext_wwn_info(bp, func);
11444         }
11445
11446         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11447
11448         /*
11449          * If maximum allowed number of connections is zero -
11450          * disable the feature.
11451          */
11452         if (!bp->cnic_eth_dev.max_fcoe_conn)
11453                 bp->flags |= NO_FCOE_FLAG;
11454 }
11455
11456 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11457 {
11458         /*
11459          * iSCSI may be dynamically disabled but reading
11460          * info here we will decrease memory usage by driver
11461          * if the feature is disabled for good
11462          */
11463         bnx2x_get_iscsi_info(bp);
11464         bnx2x_get_fcoe_info(bp);
11465 }
11466
11467 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11468 {
11469         u32 val, val2;
11470         int func = BP_ABS_FUNC(bp);
11471         int port = BP_PORT(bp);
11472         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11473         u8 *fip_mac = bp->fip_mac;
11474
11475         if (IS_MF(bp)) {
11476                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11477                  * FCoE MAC then the appropriate feature should be disabled.
11478                  * In non SD mode features configuration comes from struct
11479                  * func_ext_config.
11480                  */
11481                 if (!IS_MF_SD(bp)) {
11482                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11483                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11484                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11485                                                  iscsi_mac_addr_upper);
11486                                 val = MF_CFG_RD(bp, func_ext_config[func].
11487                                                 iscsi_mac_addr_lower);
11488                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11489                                 BNX2X_DEV_INFO
11490                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11491                         } else {
11492                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11493                         }
11494
11495                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11496                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11497                                                  fcoe_mac_addr_upper);
11498                                 val = MF_CFG_RD(bp, func_ext_config[func].
11499                                                 fcoe_mac_addr_lower);
11500                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11501                                 BNX2X_DEV_INFO
11502                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11503                         } else {
11504                                 bp->flags |= NO_FCOE_FLAG;
11505                         }
11506
11507                         bp->mf_ext_config = cfg;
11508
11509                 } else { /* SD MODE */
11510                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11511                                 /* use primary mac as iscsi mac */
11512                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11513
11514                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11515                                 BNX2X_DEV_INFO
11516                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11517                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11518                                 /* use primary mac as fip mac */
11519                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11520                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11521                                 BNX2X_DEV_INFO
11522                                         ("Read FIP MAC: %pM\n", fip_mac);
11523                         }
11524                 }
11525
11526                 /* If this is a storage-only interface, use SAN mac as
11527                  * primary MAC. Notice that for SD this is already the case,
11528                  * as the SAN mac was copied from the primary MAC.
11529                  */
11530                 if (IS_MF_FCOE_AFEX(bp))
11531                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11532         } else {
11533                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11534                                 iscsi_mac_upper);
11535                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11536                                iscsi_mac_lower);
11537                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11538
11539                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11540                                 fcoe_fip_mac_upper);
11541                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11542                                fcoe_fip_mac_lower);
11543                 bnx2x_set_mac_buf(fip_mac, val, val2);
11544         }
11545
11546         /* Disable iSCSI OOO if MAC configuration is invalid. */
11547         if (!is_valid_ether_addr(iscsi_mac)) {
11548                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11549                 memset(iscsi_mac, 0, ETH_ALEN);
11550         }
11551
11552         /* Disable FCoE if MAC configuration is invalid. */
11553         if (!is_valid_ether_addr(fip_mac)) {
11554                 bp->flags |= NO_FCOE_FLAG;
11555                 memset(bp->fip_mac, 0, ETH_ALEN);
11556         }
11557 }
11558
11559 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11560 {
11561         u32 val, val2;
11562         int func = BP_ABS_FUNC(bp);
11563         int port = BP_PORT(bp);
11564
11565         /* Zero primary MAC configuration */
11566         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11567
11568         if (BP_NOMCP(bp)) {
11569                 BNX2X_ERROR("warning: random MAC workaround active\n");
11570                 eth_hw_addr_random(bp->dev);
11571         } else if (IS_MF(bp)) {
11572                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11573                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11574                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11575                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11576                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11577
11578                 if (CNIC_SUPPORT(bp))
11579                         bnx2x_get_cnic_mac_hwinfo(bp);
11580         } else {
11581                 /* in SF read MACs from port configuration */
11582                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11583                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11584                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11585
11586                 if (CNIC_SUPPORT(bp))
11587                         bnx2x_get_cnic_mac_hwinfo(bp);
11588         }
11589
11590         if (!BP_NOMCP(bp)) {
11591                 /* Read physical port identifier from shmem */
11592                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11593                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11594                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11595                 bp->flags |= HAS_PHYS_PORT_ID;
11596         }
11597
11598         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11599
11600         if (!is_valid_ether_addr(bp->dev->dev_addr))
11601                 dev_err(&bp->pdev->dev,
11602                         "bad Ethernet MAC address configuration: %pM\n"
11603                         "change it manually before bringing up the appropriate network interface\n",
11604                         bp->dev->dev_addr);
11605 }
11606
11607 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11608 {
11609         int tmp;
11610         u32 cfg;
11611
11612         if (IS_VF(bp))
11613                 return 0;
11614
11615         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11616                 /* Take function: tmp = func */
11617                 tmp = BP_ABS_FUNC(bp);
11618                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11619                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11620         } else {
11621                 /* Take port: tmp = port */
11622                 tmp = BP_PORT(bp);
11623                 cfg = SHMEM_RD(bp,
11624                                dev_info.port_hw_config[tmp].generic_features);
11625                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11626         }
11627         return cfg;
11628 }
11629
11630 static void validate_set_si_mode(struct bnx2x *bp)
11631 {
11632         u8 func = BP_ABS_FUNC(bp);
11633         u32 val;
11634
11635         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11636
11637         /* check for legal mac (upper bytes) */
11638         if (val != 0xffff) {
11639                 bp->mf_mode = MULTI_FUNCTION_SI;
11640                 bp->mf_config[BP_VN(bp)] =
11641                         MF_CFG_RD(bp, func_mf_config[func].config);
11642         } else
11643                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11644 }
11645
11646 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11647 {
11648         int /*abs*/func = BP_ABS_FUNC(bp);
11649         int vn;
11650         u32 val = 0, val2 = 0;
11651         int rc = 0;
11652
11653         bnx2x_get_common_hwinfo(bp);
11654
11655         /*
11656          * initialize IGU parameters
11657          */
11658         if (CHIP_IS_E1x(bp)) {
11659                 bp->common.int_block = INT_BLOCK_HC;
11660
11661                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11662                 bp->igu_base_sb = 0;
11663         } else {
11664                 bp->common.int_block = INT_BLOCK_IGU;
11665
11666                 /* do not allow device reset during IGU info processing */
11667                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11668
11669                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11670
11671                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11672                         int tout = 5000;
11673
11674                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11675
11676                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11677                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11678                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11679
11680                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11681                                 tout--;
11682                                 usleep_range(1000, 2000);
11683                         }
11684
11685                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11686                                 dev_err(&bp->pdev->dev,
11687                                         "FORCING Normal Mode failed!!!\n");
11688                                 bnx2x_release_hw_lock(bp,
11689                                                       HW_LOCK_RESOURCE_RESET);
11690                                 return -EPERM;
11691                         }
11692                 }
11693
11694                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11695                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11696                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11697                 } else
11698                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11699
11700                 rc = bnx2x_get_igu_cam_info(bp);
11701                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11702                 if (rc)
11703                         return rc;
11704         }
11705
11706         /*
11707          * set base FW non-default (fast path) status block id, this value is
11708          * used to initialize the fw_sb_id saved on the fp/queue structure to
11709          * determine the id used by the FW.
11710          */
11711         if (CHIP_IS_E1x(bp))
11712                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11713         else /*
11714               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11715               * the same queue are indicated on the same IGU SB). So we prefer
11716               * FW and IGU SBs to be the same value.
11717               */
11718                 bp->base_fw_ndsb = bp->igu_base_sb;
11719
11720         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11721                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11722                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11723
11724         /*
11725          * Initialize MF configuration
11726          */
11727
11728         bp->mf_ov = 0;
11729         bp->mf_mode = 0;
11730         bp->mf_sub_mode = 0;
11731         vn = BP_VN(bp);
11732
11733         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11734                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11735                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11736                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11737
11738                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11739                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11740                 else
11741                         bp->common.mf_cfg_base = bp->common.shmem_base +
11742                                 offsetof(struct shmem_region, func_mb) +
11743                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11744                 /*
11745                  * get mf configuration:
11746                  * 1. Existence of MF configuration
11747                  * 2. MAC address must be legal (check only upper bytes)
11748                  *    for  Switch-Independent mode;
11749                  *    OVLAN must be legal for Switch-Dependent mode
11750                  * 3. SF_MODE configures specific MF mode
11751                  */
11752                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11753                         /* get mf configuration */
11754                         val = SHMEM_RD(bp,
11755                                        dev_info.shared_feature_config.config);
11756                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11757
11758                         switch (val) {
11759                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11760                                 validate_set_si_mode(bp);
11761                                 break;
11762                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11763                                 if ((!CHIP_IS_E1x(bp)) &&
11764                                     (MF_CFG_RD(bp, func_mf_config[func].
11765                                                mac_upper) != 0xffff) &&
11766                                     (SHMEM2_HAS(bp,
11767                                                 afex_driver_support))) {
11768                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11769                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11770                                                 func_mf_config[func].config);
11771                                 } else {
11772                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11773                                 }
11774                                 break;
11775                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11776                                 /* get OV configuration */
11777                                 val = MF_CFG_RD(bp,
11778                                         func_mf_config[FUNC_0].e1hov_tag);
11779                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11780
11781                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11782                                         bp->mf_mode = MULTI_FUNCTION_SD;
11783                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11784                                                 func_mf_config[func].config);
11785                                 } else
11786                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11787                                 break;
11788                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11789                                 bp->mf_mode = MULTI_FUNCTION_SD;
11790                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11791                                 bp->mf_config[vn] =
11792                                         MF_CFG_RD(bp,
11793                                                   func_mf_config[func].config);
11794                                 break;
11795                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11796                                 bp->mf_config[vn] = 0;
11797                                 break;
11798                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11799                                 val2 = SHMEM_RD(bp,
11800                                         dev_info.shared_hw_config.config_3);
11801                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11802                                 switch (val2) {
11803                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11804                                         validate_set_si_mode(bp);
11805                                         bp->mf_sub_mode =
11806                                                         SUB_MF_MODE_NPAR1_DOT_5;
11807                                         break;
11808                                 default:
11809                                         /* Unknown configuration */
11810                                         bp->mf_config[vn] = 0;
11811                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11812                                                        val);
11813                                 }
11814                                 break;
11815                         default:
11816                                 /* Unknown configuration: reset mf_config */
11817                                 bp->mf_config[vn] = 0;
11818                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11819                         }
11820                 }
11821
11822                 BNX2X_DEV_INFO("%s function mode\n",
11823                                IS_MF(bp) ? "multi" : "single");
11824
11825                 switch (bp->mf_mode) {
11826                 case MULTI_FUNCTION_SD:
11827                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11828                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11829                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11830                                 bp->mf_ov = val;
11831                                 bp->path_has_ovlan = true;
11832
11833                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11834                                                func, bp->mf_ov, bp->mf_ov);
11835                         } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11836                                 dev_err(&bp->pdev->dev,
11837                                         "Unexpected - no valid MF OV for func %d in UFP mode\n",
11838                                         func);
11839                                 bp->path_has_ovlan = true;
11840                         } else {
11841                                 dev_err(&bp->pdev->dev,
11842                                         "No valid MF OV for func %d, aborting\n",
11843                                         func);
11844                                 return -EPERM;
11845                         }
11846                         break;
11847                 case MULTI_FUNCTION_AFEX:
11848                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11849                         break;
11850                 case MULTI_FUNCTION_SI:
11851                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11852                                        func);
11853                         break;
11854                 default:
11855                         if (vn) {
11856                                 dev_err(&bp->pdev->dev,
11857                                         "VN %d is in a single function mode, aborting\n",
11858                                         vn);
11859                                 return -EPERM;
11860                         }
11861                         break;
11862                 }
11863
11864                 /* check if other port on the path needs ovlan:
11865                  * Since MF configuration is shared between ports
11866                  * Possible mixed modes are only
11867                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11868                  */
11869                 if (CHIP_MODE_IS_4_PORT(bp) &&
11870                     !bp->path_has_ovlan &&
11871                     !IS_MF(bp) &&
11872                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11873                         u8 other_port = !BP_PORT(bp);
11874                         u8 other_func = BP_PATH(bp) + 2*other_port;
11875                         val = MF_CFG_RD(bp,
11876                                         func_mf_config[other_func].e1hov_tag);
11877                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11878                                 bp->path_has_ovlan = true;
11879                 }
11880         }
11881
11882         /* adjust igu_sb_cnt to MF for E1H */
11883         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11884                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11885
11886         /* port info */
11887         bnx2x_get_port_hwinfo(bp);
11888
11889         /* Get MAC addresses */
11890         bnx2x_get_mac_hwinfo(bp);
11891
11892         bnx2x_get_cnic_info(bp);
11893
11894         return rc;
11895 }
11896
11897 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11898 {
11899         int cnt, i, block_end, rodi;
11900         char vpd_start[BNX2X_VPD_LEN+1];
11901         char str_id_reg[VENDOR_ID_LEN+1];
11902         char str_id_cap[VENDOR_ID_LEN+1];
11903         char *vpd_data;
11904         char *vpd_extended_data = NULL;
11905         u8 len;
11906
11907         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11908         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11909
11910         if (cnt < BNX2X_VPD_LEN)
11911                 goto out_not_found;
11912
11913         /* VPD RO tag should be first tag after identifier string, hence
11914          * we should be able to find it in first BNX2X_VPD_LEN chars
11915          */
11916         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11917                              PCI_VPD_LRDT_RO_DATA);
11918         if (i < 0)
11919                 goto out_not_found;
11920
11921         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11922                     pci_vpd_lrdt_size(&vpd_start[i]);
11923
11924         i += PCI_VPD_LRDT_TAG_SIZE;
11925
11926         if (block_end > BNX2X_VPD_LEN) {
11927                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11928                 if (vpd_extended_data  == NULL)
11929                         goto out_not_found;
11930
11931                 /* read rest of vpd image into vpd_extended_data */
11932                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11933                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11934                                    block_end - BNX2X_VPD_LEN,
11935                                    vpd_extended_data + BNX2X_VPD_LEN);
11936                 if (cnt < (block_end - BNX2X_VPD_LEN))
11937                         goto out_not_found;
11938                 vpd_data = vpd_extended_data;
11939         } else
11940                 vpd_data = vpd_start;
11941
11942         /* now vpd_data holds full vpd content in both cases */
11943
11944         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11945                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11946         if (rodi < 0)
11947                 goto out_not_found;
11948
11949         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11950
11951         if (len != VENDOR_ID_LEN)
11952                 goto out_not_found;
11953
11954         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11955
11956         /* vendor specific info */
11957         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11958         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11959         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11960             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11961
11962                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11963                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11964                 if (rodi >= 0) {
11965                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11966
11967                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11968
11969                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11970                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11971                                 bp->fw_ver[len] = ' ';
11972                         }
11973                 }
11974                 kfree(vpd_extended_data);
11975                 return;
11976         }
11977 out_not_found:
11978         kfree(vpd_extended_data);
11979         return;
11980 }
11981
11982 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11983 {
11984         u32 flags = 0;
11985
11986         if (CHIP_REV_IS_FPGA(bp))
11987                 SET_FLAGS(flags, MODE_FPGA);
11988         else if (CHIP_REV_IS_EMUL(bp))
11989                 SET_FLAGS(flags, MODE_EMUL);
11990         else
11991                 SET_FLAGS(flags, MODE_ASIC);
11992
11993         if (CHIP_MODE_IS_4_PORT(bp))
11994                 SET_FLAGS(flags, MODE_PORT4);
11995         else
11996                 SET_FLAGS(flags, MODE_PORT2);
11997
11998         if (CHIP_IS_E2(bp))
11999                 SET_FLAGS(flags, MODE_E2);
12000         else if (CHIP_IS_E3(bp)) {
12001                 SET_FLAGS(flags, MODE_E3);
12002                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12003                         SET_FLAGS(flags, MODE_E3_A0);
12004                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12005                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12006         }
12007
12008         if (IS_MF(bp)) {
12009                 SET_FLAGS(flags, MODE_MF);
12010                 switch (bp->mf_mode) {
12011                 case MULTI_FUNCTION_SD:
12012                         SET_FLAGS(flags, MODE_MF_SD);
12013                         break;
12014                 case MULTI_FUNCTION_SI:
12015                         SET_FLAGS(flags, MODE_MF_SI);
12016                         break;
12017                 case MULTI_FUNCTION_AFEX:
12018                         SET_FLAGS(flags, MODE_MF_AFEX);
12019                         break;
12020                 }
12021         } else
12022                 SET_FLAGS(flags, MODE_SF);
12023
12024 #if defined(__LITTLE_ENDIAN)
12025         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12026 #else /*(__BIG_ENDIAN)*/
12027         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12028 #endif
12029         INIT_MODE_FLAGS(bp) = flags;
12030 }
12031
12032 static int bnx2x_init_bp(struct bnx2x *bp)
12033 {
12034         int func;
12035         int rc;
12036
12037         mutex_init(&bp->port.phy_mutex);
12038         mutex_init(&bp->fw_mb_mutex);
12039         mutex_init(&bp->drv_info_mutex);
12040         bp->drv_info_mng_owner = false;
12041         spin_lock_init(&bp->stats_lock);
12042         sema_init(&bp->stats_sema, 1);
12043
12044         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12045         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12046         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12047         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12048         if (IS_PF(bp)) {
12049                 rc = bnx2x_get_hwinfo(bp);
12050                 if (rc)
12051                         return rc;
12052         } else {
12053                 eth_zero_addr(bp->dev->dev_addr);
12054         }
12055
12056         bnx2x_set_modes_bitmap(bp);
12057
12058         rc = bnx2x_alloc_mem_bp(bp);
12059         if (rc)
12060                 return rc;
12061
12062         bnx2x_read_fwinfo(bp);
12063
12064         func = BP_FUNC(bp);
12065
12066         /* need to reset chip if undi was active */
12067         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12068                 /* init fw_seq */
12069                 bp->fw_seq =
12070                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12071                                                         DRV_MSG_SEQ_NUMBER_MASK;
12072                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12073
12074                 rc = bnx2x_prev_unload(bp);
12075                 if (rc) {
12076                         bnx2x_free_mem_bp(bp);
12077                         return rc;
12078                 }
12079         }
12080
12081         if (CHIP_REV_IS_FPGA(bp))
12082                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12083
12084         if (BP_NOMCP(bp) && (func == 0))
12085                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12086
12087         bp->disable_tpa = disable_tpa;
12088         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12089         /* Reduce memory usage in kdump environment by disabling TPA */
12090         bp->disable_tpa |= is_kdump_kernel();
12091
12092         /* Set TPA flags */
12093         if (bp->disable_tpa) {
12094                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12095                 bp->dev->features &= ~NETIF_F_LRO;
12096         } else {
12097                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12098                 bp->dev->features |= NETIF_F_LRO;
12099         }
12100
12101         if (CHIP_IS_E1(bp))
12102                 bp->dropless_fc = 0;
12103         else
12104                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12105
12106         bp->mrrs = mrrs;
12107
12108         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12109         if (IS_VF(bp))
12110                 bp->rx_ring_size = MAX_RX_AVAIL;
12111
12112         /* make sure that the numbers are in the right granularity */
12113         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12114         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12115
12116         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12117
12118         init_timer(&bp->timer);
12119         bp->timer.expires = jiffies + bp->current_interval;
12120         bp->timer.data = (unsigned long) bp;
12121         bp->timer.function = bnx2x_timer;
12122
12123         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12124             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12125             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12126             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12127                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12128                 bnx2x_dcbx_init_params(bp);
12129         } else {
12130                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12131         }
12132
12133         if (CHIP_IS_E1x(bp))
12134                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12135         else
12136                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12137
12138         /* multiple tx priority */
12139         if (IS_VF(bp))
12140                 bp->max_cos = 1;
12141         else if (CHIP_IS_E1x(bp))
12142                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12143         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12144                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12145         else if (CHIP_IS_E3B0(bp))
12146                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12147         else
12148                 BNX2X_ERR("unknown chip %x revision %x\n",
12149                           CHIP_NUM(bp), CHIP_REV(bp));
12150         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12151
12152         /* We need at least one default status block for slow-path events,
12153          * second status block for the L2 queue, and a third status block for
12154          * CNIC if supported.
12155          */
12156         if (IS_VF(bp))
12157                 bp->min_msix_vec_cnt = 1;
12158         else if (CNIC_SUPPORT(bp))
12159                 bp->min_msix_vec_cnt = 3;
12160         else /* PF w/o cnic */
12161                 bp->min_msix_vec_cnt = 2;
12162         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12163
12164         bp->dump_preset_idx = 1;
12165
12166         if (CHIP_IS_E3B0(bp))
12167                 bp->flags |= PTP_SUPPORTED;
12168
12169         return rc;
12170 }
12171
12172 /****************************************************************************
12173 * General service functions
12174 ****************************************************************************/
12175
12176 /*
12177  * net_device service functions
12178  */
12179
12180 /* called with rtnl_lock */
12181 static int bnx2x_open(struct net_device *dev)
12182 {
12183         struct bnx2x *bp = netdev_priv(dev);
12184         int rc;
12185
12186         bp->stats_init = true;
12187
12188         netif_carrier_off(dev);
12189
12190         bnx2x_set_power_state(bp, PCI_D0);
12191
12192         /* If parity had happen during the unload, then attentions
12193          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12194          * want the first function loaded on the current engine to
12195          * complete the recovery.
12196          * Parity recovery is only relevant for PF driver.
12197          */
12198         if (IS_PF(bp)) {
12199                 int other_engine = BP_PATH(bp) ? 0 : 1;
12200                 bool other_load_status, load_status;
12201                 bool global = false;
12202
12203                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12204                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12205                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12206                     bnx2x_chk_parity_attn(bp, &global, true)) {
12207                         do {
12208                                 /* If there are attentions and they are in a
12209                                  * global blocks, set the GLOBAL_RESET bit
12210                                  * regardless whether it will be this function
12211                                  * that will complete the recovery or not.
12212                                  */
12213                                 if (global)
12214                                         bnx2x_set_reset_global(bp);
12215
12216                                 /* Only the first function on the current
12217                                  * engine should try to recover in open. In case
12218                                  * of attentions in global blocks only the first
12219                                  * in the chip should try to recover.
12220                                  */
12221                                 if ((!load_status &&
12222                                      (!global || !other_load_status)) &&
12223                                       bnx2x_trylock_leader_lock(bp) &&
12224                                       !bnx2x_leader_reset(bp)) {
12225                                         netdev_info(bp->dev,
12226                                                     "Recovered in open\n");
12227                                         break;
12228                                 }
12229
12230                                 /* recovery has failed... */
12231                                 bnx2x_set_power_state(bp, PCI_D3hot);
12232                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12233
12234                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12235                                           "If you still see this message after a few retries then power cycle is required.\n");
12236
12237                                 return -EAGAIN;
12238                         } while (0);
12239                 }
12240         }
12241
12242         bp->recovery_state = BNX2X_RECOVERY_DONE;
12243         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12244         if (rc)
12245                 return rc;
12246         return 0;
12247 }
12248
12249 /* called with rtnl_lock */
12250 static int bnx2x_close(struct net_device *dev)
12251 {
12252         struct bnx2x *bp = netdev_priv(dev);
12253
12254         /* Unload the driver, release IRQs */
12255         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12256
12257         return 0;
12258 }
12259
12260 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12261                                       struct bnx2x_mcast_ramrod_params *p)
12262 {
12263         int mc_count = netdev_mc_count(bp->dev);
12264         struct bnx2x_mcast_list_elem *mc_mac =
12265                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12266         struct netdev_hw_addr *ha;
12267
12268         if (!mc_mac)
12269                 return -ENOMEM;
12270
12271         INIT_LIST_HEAD(&p->mcast_list);
12272
12273         netdev_for_each_mc_addr(ha, bp->dev) {
12274                 mc_mac->mac = bnx2x_mc_addr(ha);
12275                 list_add_tail(&mc_mac->link, &p->mcast_list);
12276                 mc_mac++;
12277         }
12278
12279         p->mcast_list_len = mc_count;
12280
12281         return 0;
12282 }
12283
12284 static void bnx2x_free_mcast_macs_list(
12285         struct bnx2x_mcast_ramrod_params *p)
12286 {
12287         struct bnx2x_mcast_list_elem *mc_mac =
12288                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12289                                  link);
12290
12291         WARN_ON(!mc_mac);
12292         kfree(mc_mac);
12293 }
12294
12295 /**
12296  * bnx2x_set_uc_list - configure a new unicast MACs list.
12297  *
12298  * @bp: driver handle
12299  *
12300  * We will use zero (0) as a MAC type for these MACs.
12301  */
12302 static int bnx2x_set_uc_list(struct bnx2x *bp)
12303 {
12304         int rc;
12305         struct net_device *dev = bp->dev;
12306         struct netdev_hw_addr *ha;
12307         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12308         unsigned long ramrod_flags = 0;
12309
12310         /* First schedule a cleanup up of old configuration */
12311         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12312         if (rc < 0) {
12313                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12314                 return rc;
12315         }
12316
12317         netdev_for_each_uc_addr(ha, dev) {
12318                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12319                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12320                 if (rc == -EEXIST) {
12321                         DP(BNX2X_MSG_SP,
12322                            "Failed to schedule ADD operations: %d\n", rc);
12323                         /* do not treat adding same MAC as error */
12324                         rc = 0;
12325
12326                 } else if (rc < 0) {
12327
12328                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12329                                   rc);
12330                         return rc;
12331                 }
12332         }
12333
12334         /* Execute the pending commands */
12335         __set_bit(RAMROD_CONT, &ramrod_flags);
12336         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12337                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12338 }
12339
12340 static int bnx2x_set_mc_list(struct bnx2x *bp)
12341 {
12342         struct net_device *dev = bp->dev;
12343         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12344         int rc = 0;
12345
12346         rparam.mcast_obj = &bp->mcast_obj;
12347
12348         /* first, clear all configured multicast MACs */
12349         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12350         if (rc < 0) {
12351                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12352                 return rc;
12353         }
12354
12355         /* then, configure a new MACs list */
12356         if (netdev_mc_count(dev)) {
12357                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12358                 if (rc) {
12359                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12360                                   rc);
12361                         return rc;
12362                 }
12363
12364                 /* Now add the new MACs */
12365                 rc = bnx2x_config_mcast(bp, &rparam,
12366                                         BNX2X_MCAST_CMD_ADD);
12367                 if (rc < 0)
12368                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12369                                   rc);
12370
12371                 bnx2x_free_mcast_macs_list(&rparam);
12372         }
12373
12374         return rc;
12375 }
12376
12377 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12378 static void bnx2x_set_rx_mode(struct net_device *dev)
12379 {
12380         struct bnx2x *bp = netdev_priv(dev);
12381
12382         if (bp->state != BNX2X_STATE_OPEN) {
12383                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12384                 return;
12385         } else {
12386                 /* Schedule an SP task to handle rest of change */
12387                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12388                                        NETIF_MSG_IFUP);
12389         }
12390 }
12391
12392 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12393 {
12394         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12395
12396         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12397
12398         netif_addr_lock_bh(bp->dev);
12399
12400         if (bp->dev->flags & IFF_PROMISC) {
12401                 rx_mode = BNX2X_RX_MODE_PROMISC;
12402         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12403                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12404                     CHIP_IS_E1(bp))) {
12405                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12406         } else {
12407                 if (IS_PF(bp)) {
12408                         /* some multicasts */
12409                         if (bnx2x_set_mc_list(bp) < 0)
12410                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12411
12412                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12413                         netif_addr_unlock_bh(bp->dev);
12414                         if (bnx2x_set_uc_list(bp) < 0)
12415                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12416                         netif_addr_lock_bh(bp->dev);
12417                 } else {
12418                         /* configuring mcast to a vf involves sleeping (when we
12419                          * wait for the pf's response).
12420                          */
12421                         bnx2x_schedule_sp_rtnl(bp,
12422                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12423                 }
12424         }
12425
12426         bp->rx_mode = rx_mode;
12427         /* handle ISCSI SD mode */
12428         if (IS_MF_ISCSI_ONLY(bp))
12429                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12430
12431         /* Schedule the rx_mode command */
12432         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12433                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12434                 netif_addr_unlock_bh(bp->dev);
12435                 return;
12436         }
12437
12438         if (IS_PF(bp)) {
12439                 bnx2x_set_storm_rx_mode(bp);
12440                 netif_addr_unlock_bh(bp->dev);
12441         } else {
12442                 /* VF will need to request the PF to make this change, and so
12443                  * the VF needs to release the bottom-half lock prior to the
12444                  * request (as it will likely require sleep on the VF side)
12445                  */
12446                 netif_addr_unlock_bh(bp->dev);
12447                 bnx2x_vfpf_storm_rx_mode(bp);
12448         }
12449 }
12450
12451 /* called with rtnl_lock */
12452 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12453                            int devad, u16 addr)
12454 {
12455         struct bnx2x *bp = netdev_priv(netdev);
12456         u16 value;
12457         int rc;
12458
12459         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12460            prtad, devad, addr);
12461
12462         /* The HW expects different devad if CL22 is used */
12463         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12464
12465         bnx2x_acquire_phy_lock(bp);
12466         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12467         bnx2x_release_phy_lock(bp);
12468         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12469
12470         if (!rc)
12471                 rc = value;
12472         return rc;
12473 }
12474
12475 /* called with rtnl_lock */
12476 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12477                             u16 addr, u16 value)
12478 {
12479         struct bnx2x *bp = netdev_priv(netdev);
12480         int rc;
12481
12482         DP(NETIF_MSG_LINK,
12483            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12484            prtad, devad, addr, value);
12485
12486         /* The HW expects different devad if CL22 is used */
12487         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12488
12489         bnx2x_acquire_phy_lock(bp);
12490         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12491         bnx2x_release_phy_lock(bp);
12492         return rc;
12493 }
12494
12495 /* called with rtnl_lock */
12496 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12497 {
12498         struct bnx2x *bp = netdev_priv(dev);
12499         struct mii_ioctl_data *mdio = if_mii(ifr);
12500
12501         if (!netif_running(dev))
12502                 return -EAGAIN;
12503
12504         switch (cmd) {
12505         case SIOCSHWTSTAMP:
12506                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12507         default:
12508                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12509                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12510                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12511         }
12512 }
12513
12514 #ifdef CONFIG_NET_POLL_CONTROLLER
12515 static void poll_bnx2x(struct net_device *dev)
12516 {
12517         struct bnx2x *bp = netdev_priv(dev);
12518         int i;
12519
12520         for_each_eth_queue(bp, i) {
12521                 struct bnx2x_fastpath *fp = &bp->fp[i];
12522                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12523         }
12524 }
12525 #endif
12526
12527 static int bnx2x_validate_addr(struct net_device *dev)
12528 {
12529         struct bnx2x *bp = netdev_priv(dev);
12530
12531         /* query the bulletin board for mac address configured by the PF */
12532         if (IS_VF(bp))
12533                 bnx2x_sample_bulletin(bp);
12534
12535         if (!is_valid_ether_addr(dev->dev_addr)) {
12536                 BNX2X_ERR("Non-valid Ethernet address\n");
12537                 return -EADDRNOTAVAIL;
12538         }
12539         return 0;
12540 }
12541
12542 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12543                                   struct netdev_phys_item_id *ppid)
12544 {
12545         struct bnx2x *bp = netdev_priv(netdev);
12546
12547         if (!(bp->flags & HAS_PHYS_PORT_ID))
12548                 return -EOPNOTSUPP;
12549
12550         ppid->id_len = sizeof(bp->phys_port_id);
12551         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12552
12553         return 0;
12554 }
12555
12556 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12557                                               struct net_device *dev,
12558                                               netdev_features_t features)
12559 {
12560         return vxlan_features_check(skb, features);
12561 }
12562
12563 static const struct net_device_ops bnx2x_netdev_ops = {
12564         .ndo_open               = bnx2x_open,
12565         .ndo_stop               = bnx2x_close,
12566         .ndo_start_xmit         = bnx2x_start_xmit,
12567         .ndo_select_queue       = bnx2x_select_queue,
12568         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12569         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12570         .ndo_validate_addr      = bnx2x_validate_addr,
12571         .ndo_do_ioctl           = bnx2x_ioctl,
12572         .ndo_change_mtu         = bnx2x_change_mtu,
12573         .ndo_fix_features       = bnx2x_fix_features,
12574         .ndo_set_features       = bnx2x_set_features,
12575         .ndo_tx_timeout         = bnx2x_tx_timeout,
12576 #ifdef CONFIG_NET_POLL_CONTROLLER
12577         .ndo_poll_controller    = poll_bnx2x,
12578 #endif
12579         .ndo_setup_tc           = bnx2x_setup_tc,
12580 #ifdef CONFIG_BNX2X_SRIOV
12581         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12582         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12583         .ndo_get_vf_config      = bnx2x_get_vf_config,
12584 #endif
12585 #ifdef NETDEV_FCOE_WWNN
12586         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12587 #endif
12588
12589 #ifdef CONFIG_NET_RX_BUSY_POLL
12590         .ndo_busy_poll          = bnx2x_low_latency_recv,
12591 #endif
12592         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12593         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12594         .ndo_features_check     = bnx2x_features_check,
12595 };
12596
12597 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12598 {
12599         struct device *dev = &bp->pdev->dev;
12600
12601         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12602             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12603                 dev_err(dev, "System does not support DMA, aborting\n");
12604                 return -EIO;
12605         }
12606
12607         return 0;
12608 }
12609
12610 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12611 {
12612         if (bp->flags & AER_ENABLED) {
12613                 pci_disable_pcie_error_reporting(bp->pdev);
12614                 bp->flags &= ~AER_ENABLED;
12615         }
12616 }
12617
12618 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12619                           struct net_device *dev, unsigned long board_type)
12620 {
12621         int rc;
12622         u32 pci_cfg_dword;
12623         bool chip_is_e1x = (board_type == BCM57710 ||
12624                             board_type == BCM57711 ||
12625                             board_type == BCM57711E);
12626
12627         SET_NETDEV_DEV(dev, &pdev->dev);
12628
12629         bp->dev = dev;
12630         bp->pdev = pdev;
12631
12632         rc = pci_enable_device(pdev);
12633         if (rc) {
12634                 dev_err(&bp->pdev->dev,
12635                         "Cannot enable PCI device, aborting\n");
12636                 goto err_out;
12637         }
12638
12639         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12640                 dev_err(&bp->pdev->dev,
12641                         "Cannot find PCI device base address, aborting\n");
12642                 rc = -ENODEV;
12643                 goto err_out_disable;
12644         }
12645
12646         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12647                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12648                 rc = -ENODEV;
12649                 goto err_out_disable;
12650         }
12651
12652         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12653         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12654             PCICFG_REVESION_ID_ERROR_VAL) {
12655                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12656                 rc = -ENODEV;
12657                 goto err_out_disable;
12658         }
12659
12660         if (atomic_read(&pdev->enable_cnt) == 1) {
12661                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12662                 if (rc) {
12663                         dev_err(&bp->pdev->dev,
12664                                 "Cannot obtain PCI resources, aborting\n");
12665                         goto err_out_disable;
12666                 }
12667
12668                 pci_set_master(pdev);
12669                 pci_save_state(pdev);
12670         }
12671
12672         if (IS_PF(bp)) {
12673                 if (!pdev->pm_cap) {
12674                         dev_err(&bp->pdev->dev,
12675                                 "Cannot find power management capability, aborting\n");
12676                         rc = -EIO;
12677                         goto err_out_release;
12678                 }
12679         }
12680
12681         if (!pci_is_pcie(pdev)) {
12682                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12683                 rc = -EIO;
12684                 goto err_out_release;
12685         }
12686
12687         rc = bnx2x_set_coherency_mask(bp);
12688         if (rc)
12689                 goto err_out_release;
12690
12691         dev->mem_start = pci_resource_start(pdev, 0);
12692         dev->base_addr = dev->mem_start;
12693         dev->mem_end = pci_resource_end(pdev, 0);
12694
12695         dev->irq = pdev->irq;
12696
12697         bp->regview = pci_ioremap_bar(pdev, 0);
12698         if (!bp->regview) {
12699                 dev_err(&bp->pdev->dev,
12700                         "Cannot map register space, aborting\n");
12701                 rc = -ENOMEM;
12702                 goto err_out_release;
12703         }
12704
12705         /* In E1/E1H use pci device function given by kernel.
12706          * In E2/E3 read physical function from ME register since these chips
12707          * support Physical Device Assignment where kernel BDF maybe arbitrary
12708          * (depending on hypervisor).
12709          */
12710         if (chip_is_e1x) {
12711                 bp->pf_num = PCI_FUNC(pdev->devfn);
12712         } else {
12713                 /* chip is E2/3*/
12714                 pci_read_config_dword(bp->pdev,
12715                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12716                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12717                                   ME_REG_ABS_PF_NUM_SHIFT);
12718         }
12719         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12720
12721         /* clean indirect addresses */
12722         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12723                                PCICFG_VENDOR_ID_OFFSET);
12724
12725         /* AER (Advanced Error reporting) configuration */
12726         rc = pci_enable_pcie_error_reporting(pdev);
12727         if (!rc)
12728                 bp->flags |= AER_ENABLED;
12729         else
12730                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12731
12732         /*
12733          * Clean the following indirect addresses for all functions since it
12734          * is not used by the driver.
12735          */
12736         if (IS_PF(bp)) {
12737                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12738                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12739                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12740                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12741
12742                 if (chip_is_e1x) {
12743                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12744                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12745                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12746                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12747                 }
12748
12749                 /* Enable internal target-read (in case we are probed after PF
12750                  * FLR). Must be done prior to any BAR read access. Only for
12751                  * 57712 and up
12752                  */
12753                 if (!chip_is_e1x)
12754                         REG_WR(bp,
12755                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12756         }
12757
12758         dev->watchdog_timeo = TX_TIMEOUT;
12759
12760         dev->netdev_ops = &bnx2x_netdev_ops;
12761         bnx2x_set_ethtool_ops(bp, dev);
12762
12763         dev->priv_flags |= IFF_UNICAST_FLT;
12764
12765         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12766                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12767                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12768                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12769         if (!CHIP_IS_E1x(bp)) {
12770                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12771                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12772                 dev->hw_enc_features =
12773                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12774                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12775                         NETIF_F_GSO_IPIP |
12776                         NETIF_F_GSO_SIT |
12777                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12778         }
12779
12780         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12781                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12782
12783         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12784         dev->features |= NETIF_F_HIGHDMA;
12785
12786         /* Add Loopback capability to the device */
12787         dev->hw_features |= NETIF_F_LOOPBACK;
12788
12789 #ifdef BCM_DCBNL
12790         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12791 #endif
12792
12793         /* get_port_hwinfo() will set prtad and mmds properly */
12794         bp->mdio.prtad = MDIO_PRTAD_NONE;
12795         bp->mdio.mmds = 0;
12796         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12797         bp->mdio.dev = dev;
12798         bp->mdio.mdio_read = bnx2x_mdio_read;
12799         bp->mdio.mdio_write = bnx2x_mdio_write;
12800
12801         return 0;
12802
12803 err_out_release:
12804         if (atomic_read(&pdev->enable_cnt) == 1)
12805                 pci_release_regions(pdev);
12806
12807 err_out_disable:
12808         pci_disable_device(pdev);
12809
12810 err_out:
12811         return rc;
12812 }
12813
12814 static int bnx2x_check_firmware(struct bnx2x *bp)
12815 {
12816         const struct firmware *firmware = bp->firmware;
12817         struct bnx2x_fw_file_hdr *fw_hdr;
12818         struct bnx2x_fw_file_section *sections;
12819         u32 offset, len, num_ops;
12820         __be16 *ops_offsets;
12821         int i;
12822         const u8 *fw_ver;
12823
12824         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12825                 BNX2X_ERR("Wrong FW size\n");
12826                 return -EINVAL;
12827         }
12828
12829         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12830         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12831
12832         /* Make sure none of the offsets and sizes make us read beyond
12833          * the end of the firmware data */
12834         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12835                 offset = be32_to_cpu(sections[i].offset);
12836                 len = be32_to_cpu(sections[i].len);
12837                 if (offset + len > firmware->size) {
12838                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12839                         return -EINVAL;
12840                 }
12841         }
12842
12843         /* Likewise for the init_ops offsets */
12844         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12845         ops_offsets = (__force __be16 *)(firmware->data + offset);
12846         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12847
12848         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12849                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12850                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12851                         return -EINVAL;
12852                 }
12853         }
12854
12855         /* Check FW version */
12856         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12857         fw_ver = firmware->data + offset;
12858         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12859             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12860             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12861             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12862                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12863                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12864                        BCM_5710_FW_MAJOR_VERSION,
12865                        BCM_5710_FW_MINOR_VERSION,
12866                        BCM_5710_FW_REVISION_VERSION,
12867                        BCM_5710_FW_ENGINEERING_VERSION);
12868                 return -EINVAL;
12869         }
12870
12871         return 0;
12872 }
12873
12874 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12875 {
12876         const __be32 *source = (const __be32 *)_source;
12877         u32 *target = (u32 *)_target;
12878         u32 i;
12879
12880         for (i = 0; i < n/4; i++)
12881                 target[i] = be32_to_cpu(source[i]);
12882 }
12883
12884 /*
12885    Ops array is stored in the following format:
12886    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12887  */
12888 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12889 {
12890         const __be32 *source = (const __be32 *)_source;
12891         struct raw_op *target = (struct raw_op *)_target;
12892         u32 i, j, tmp;
12893
12894         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12895                 tmp = be32_to_cpu(source[j]);
12896                 target[i].op = (tmp >> 24) & 0xff;
12897                 target[i].offset = tmp & 0xffffff;
12898                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12899         }
12900 }
12901
12902 /* IRO array is stored in the following format:
12903  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12904  */
12905 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12906 {
12907         const __be32 *source = (const __be32 *)_source;
12908         struct iro *target = (struct iro *)_target;
12909         u32 i, j, tmp;
12910
12911         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12912                 target[i].base = be32_to_cpu(source[j]);
12913                 j++;
12914                 tmp = be32_to_cpu(source[j]);
12915                 target[i].m1 = (tmp >> 16) & 0xffff;
12916                 target[i].m2 = tmp & 0xffff;
12917                 j++;
12918                 tmp = be32_to_cpu(source[j]);
12919                 target[i].m3 = (tmp >> 16) & 0xffff;
12920                 target[i].size = tmp & 0xffff;
12921                 j++;
12922         }
12923 }
12924
12925 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12926 {
12927         const __be16 *source = (const __be16 *)_source;
12928         u16 *target = (u16 *)_target;
12929         u32 i;
12930
12931         for (i = 0; i < n/2; i++)
12932                 target[i] = be16_to_cpu(source[i]);
12933 }
12934
12935 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12936 do {                                                                    \
12937         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12938         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12939         if (!bp->arr)                                                   \
12940                 goto lbl;                                               \
12941         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12942              (u8 *)bp->arr, len);                                       \
12943 } while (0)
12944
12945 static int bnx2x_init_firmware(struct bnx2x *bp)
12946 {
12947         const char *fw_file_name;
12948         struct bnx2x_fw_file_hdr *fw_hdr;
12949         int rc;
12950
12951         if (bp->firmware)
12952                 return 0;
12953
12954         if (CHIP_IS_E1(bp))
12955                 fw_file_name = FW_FILE_NAME_E1;
12956         else if (CHIP_IS_E1H(bp))
12957                 fw_file_name = FW_FILE_NAME_E1H;
12958         else if (!CHIP_IS_E1x(bp))
12959                 fw_file_name = FW_FILE_NAME_E2;
12960         else {
12961                 BNX2X_ERR("Unsupported chip revision\n");
12962                 return -EINVAL;
12963         }
12964         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12965
12966         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12967         if (rc) {
12968                 BNX2X_ERR("Can't load firmware file %s\n",
12969                           fw_file_name);
12970                 goto request_firmware_exit;
12971         }
12972
12973         rc = bnx2x_check_firmware(bp);
12974         if (rc) {
12975                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12976                 goto request_firmware_exit;
12977         }
12978
12979         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12980
12981         /* Initialize the pointers to the init arrays */
12982         /* Blob */
12983         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12984
12985         /* Opcodes */
12986         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12987
12988         /* Offsets */
12989         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12990                             be16_to_cpu_n);
12991
12992         /* STORMs firmware */
12993         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12994                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12995         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12996                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12997         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12998                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12999         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13000                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13001         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13002                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13003         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13004                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13005         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13006                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13007         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13008                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13009         /* IRO */
13010         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13011
13012         return 0;
13013
13014 iro_alloc_err:
13015         kfree(bp->init_ops_offsets);
13016 init_offsets_alloc_err:
13017         kfree(bp->init_ops);
13018 init_ops_alloc_err:
13019         kfree(bp->init_data);
13020 request_firmware_exit:
13021         release_firmware(bp->firmware);
13022         bp->firmware = NULL;
13023
13024         return rc;
13025 }
13026
13027 static void bnx2x_release_firmware(struct bnx2x *bp)
13028 {
13029         kfree(bp->init_ops_offsets);
13030         kfree(bp->init_ops);
13031         kfree(bp->init_data);
13032         release_firmware(bp->firmware);
13033         bp->firmware = NULL;
13034 }
13035
13036 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13037         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13038         .init_hw_cmn      = bnx2x_init_hw_common,
13039         .init_hw_port     = bnx2x_init_hw_port,
13040         .init_hw_func     = bnx2x_init_hw_func,
13041
13042         .reset_hw_cmn     = bnx2x_reset_common,
13043         .reset_hw_port    = bnx2x_reset_port,
13044         .reset_hw_func    = bnx2x_reset_func,
13045
13046         .gunzip_init      = bnx2x_gunzip_init,
13047         .gunzip_end       = bnx2x_gunzip_end,
13048
13049         .init_fw          = bnx2x_init_firmware,
13050         .release_fw       = bnx2x_release_firmware,
13051 };
13052
13053 void bnx2x__init_func_obj(struct bnx2x *bp)
13054 {
13055         /* Prepare DMAE related driver resources */
13056         bnx2x_setup_dmae(bp);
13057
13058         bnx2x_init_func_obj(bp, &bp->func_obj,
13059                             bnx2x_sp(bp, func_rdata),
13060                             bnx2x_sp_mapping(bp, func_rdata),
13061                             bnx2x_sp(bp, func_afex_rdata),
13062                             bnx2x_sp_mapping(bp, func_afex_rdata),
13063                             &bnx2x_func_sp_drv);
13064 }
13065
13066 /* must be called after sriov-enable */
13067 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13068 {
13069         int cid_count = BNX2X_L2_MAX_CID(bp);
13070
13071         if (IS_SRIOV(bp))
13072                 cid_count += BNX2X_VF_CIDS;
13073
13074         if (CNIC_SUPPORT(bp))
13075                 cid_count += CNIC_CID_MAX;
13076
13077         return roundup(cid_count, QM_CID_ROUND);
13078 }
13079
13080 /**
13081  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13082  *
13083  * @dev:        pci device
13084  *
13085  */
13086 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13087 {
13088         int index;
13089         u16 control = 0;
13090
13091         /*
13092          * If MSI-X is not supported - return number of SBs needed to support
13093          * one fast path queue: one FP queue + SB for CNIC
13094          */
13095         if (!pdev->msix_cap) {
13096                 dev_info(&pdev->dev, "no msix capability found\n");
13097                 return 1 + cnic_cnt;
13098         }
13099         dev_info(&pdev->dev, "msix capability found\n");
13100
13101         /*
13102          * The value in the PCI configuration space is the index of the last
13103          * entry, namely one less than the actual size of the table, which is
13104          * exactly what we want to return from this function: number of all SBs
13105          * without the default SB.
13106          * For VFs there is no default SB, then we return (index+1).
13107          */
13108         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13109
13110         index = control & PCI_MSIX_FLAGS_QSIZE;
13111
13112         return index;
13113 }
13114
13115 static int set_max_cos_est(int chip_id)
13116 {
13117         switch (chip_id) {
13118         case BCM57710:
13119         case BCM57711:
13120         case BCM57711E:
13121                 return BNX2X_MULTI_TX_COS_E1X;
13122         case BCM57712:
13123         case BCM57712_MF:
13124                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13125         case BCM57800:
13126         case BCM57800_MF:
13127         case BCM57810:
13128         case BCM57810_MF:
13129         case BCM57840_4_10:
13130         case BCM57840_2_20:
13131         case BCM57840_O:
13132         case BCM57840_MFO:
13133         case BCM57840_MF:
13134         case BCM57811:
13135         case BCM57811_MF:
13136                 return BNX2X_MULTI_TX_COS_E3B0;
13137         case BCM57712_VF:
13138         case BCM57800_VF:
13139         case BCM57810_VF:
13140         case BCM57840_VF:
13141         case BCM57811_VF:
13142                 return 1;
13143         default:
13144                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13145                 return -ENODEV;
13146         }
13147 }
13148
13149 static int set_is_vf(int chip_id)
13150 {
13151         switch (chip_id) {
13152         case BCM57712_VF:
13153         case BCM57800_VF:
13154         case BCM57810_VF:
13155         case BCM57840_VF:
13156         case BCM57811_VF:
13157                 return true;
13158         default:
13159                 return false;
13160         }
13161 }
13162
13163 /* nig_tsgen registers relative address */
13164 #define tsgen_ctrl 0x0
13165 #define tsgen_freecount 0x10
13166 #define tsgen_synctime_t0 0x20
13167 #define tsgen_offset_t0 0x28
13168 #define tsgen_drift_t0 0x30
13169 #define tsgen_synctime_t1 0x58
13170 #define tsgen_offset_t1 0x60
13171 #define tsgen_drift_t1 0x68
13172
13173 /* FW workaround for setting drift */
13174 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13175                                           int best_val, int best_period)
13176 {
13177         struct bnx2x_func_state_params func_params = {NULL};
13178         struct bnx2x_func_set_timesync_params *set_timesync_params =
13179                 &func_params.params.set_timesync;
13180
13181         /* Prepare parameters for function state transitions */
13182         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13183         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13184
13185         func_params.f_obj = &bp->func_obj;
13186         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13187
13188         /* Function parameters */
13189         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13190         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13191         set_timesync_params->add_sub_drift_adjust_value =
13192                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13193         set_timesync_params->drift_adjust_value = best_val;
13194         set_timesync_params->drift_adjust_period = best_period;
13195
13196         return bnx2x_func_state_change(bp, &func_params);
13197 }
13198
13199 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13200 {
13201         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13202         int rc;
13203         int drift_dir = 1;
13204         int val, period, period1, period2, dif, dif1, dif2;
13205         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13206
13207         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13208
13209         if (!netif_running(bp->dev)) {
13210                 DP(BNX2X_MSG_PTP,
13211                    "PTP adjfreq called while the interface is down\n");
13212                 return -EFAULT;
13213         }
13214
13215         if (ppb < 0) {
13216                 ppb = -ppb;
13217                 drift_dir = 0;
13218         }
13219
13220         if (ppb == 0) {
13221                 best_val = 1;
13222                 best_period = 0x1FFFFFF;
13223         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13224                 best_val = 31;
13225                 best_period = 1;
13226         } else {
13227                 /* Changed not to allow val = 8, 16, 24 as these values
13228                  * are not supported in workaround.
13229                  */
13230                 for (val = 0; val <= 31; val++) {
13231                         if ((val & 0x7) == 0)
13232                                 continue;
13233                         period1 = val * 1000000 / ppb;
13234                         period2 = period1 + 1;
13235                         if (period1 != 0)
13236                                 dif1 = ppb - (val * 1000000 / period1);
13237                         else
13238                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13239                         if (dif1 < 0)
13240                                 dif1 = -dif1;
13241                         dif2 = ppb - (val * 1000000 / period2);
13242                         if (dif2 < 0)
13243                                 dif2 = -dif2;
13244                         dif = (dif1 < dif2) ? dif1 : dif2;
13245                         period = (dif1 < dif2) ? period1 : period2;
13246                         if (dif < best_dif) {
13247                                 best_dif = dif;
13248                                 best_val = val;
13249                                 best_period = period;
13250                         }
13251                 }
13252         }
13253
13254         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13255                                             best_period);
13256         if (rc) {
13257                 BNX2X_ERR("Failed to set drift\n");
13258                 return -EFAULT;
13259         }
13260
13261         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13262            best_period);
13263
13264         return 0;
13265 }
13266
13267 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13268 {
13269         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13270
13271         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13272
13273         timecounter_adjtime(&bp->timecounter, delta);
13274
13275         return 0;
13276 }
13277
13278 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13279 {
13280         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13281         u64 ns;
13282         u32 remainder;
13283
13284         ns = timecounter_read(&bp->timecounter);
13285
13286         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13287
13288         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13289         ts->tv_nsec = remainder;
13290
13291         return 0;
13292 }
13293
13294 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13295                              const struct timespec *ts)
13296 {
13297         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13298         u64 ns;
13299
13300         ns = ts->tv_sec * 1000000000ULL;
13301         ns += ts->tv_nsec;
13302
13303         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13304
13305         /* Re-init the timecounter */
13306         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13307
13308         return 0;
13309 }
13310
13311 /* Enable (or disable) ancillary features of the phc subsystem */
13312 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13313                             struct ptp_clock_request *rq, int on)
13314 {
13315         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13316
13317         BNX2X_ERR("PHC ancillary features are not supported\n");
13318         return -ENOTSUPP;
13319 }
13320
13321 void bnx2x_register_phc(struct bnx2x *bp)
13322 {
13323         /* Fill the ptp_clock_info struct and register PTP clock*/
13324         bp->ptp_clock_info.owner = THIS_MODULE;
13325         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13326         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13327         bp->ptp_clock_info.n_alarm = 0;
13328         bp->ptp_clock_info.n_ext_ts = 0;
13329         bp->ptp_clock_info.n_per_out = 0;
13330         bp->ptp_clock_info.pps = 0;
13331         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13332         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13333         bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13334         bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13335         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13336
13337         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13338         if (IS_ERR(bp->ptp_clock)) {
13339                 bp->ptp_clock = NULL;
13340                 BNX2X_ERR("PTP clock registeration failed\n");
13341         }
13342 }
13343
13344 static int bnx2x_init_one(struct pci_dev *pdev,
13345                                     const struct pci_device_id *ent)
13346 {
13347         struct net_device *dev = NULL;
13348         struct bnx2x *bp;
13349         enum pcie_link_width pcie_width;
13350         enum pci_bus_speed pcie_speed;
13351         int rc, max_non_def_sbs;
13352         int rx_count, tx_count, rss_count, doorbell_size;
13353         int max_cos_est;
13354         bool is_vf;
13355         int cnic_cnt;
13356
13357         /* An estimated maximum supported CoS number according to the chip
13358          * version.
13359          * We will try to roughly estimate the maximum number of CoSes this chip
13360          * may support in order to minimize the memory allocated for Tx
13361          * netdev_queue's. This number will be accurately calculated during the
13362          * initialization of bp->max_cos based on the chip versions AND chip
13363          * revision in the bnx2x_init_bp().
13364          */
13365         max_cos_est = set_max_cos_est(ent->driver_data);
13366         if (max_cos_est < 0)
13367                 return max_cos_est;
13368         is_vf = set_is_vf(ent->driver_data);
13369         cnic_cnt = is_vf ? 0 : 1;
13370
13371         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13372
13373         /* add another SB for VF as it has no default SB */
13374         max_non_def_sbs += is_vf ? 1 : 0;
13375
13376         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13377         rss_count = max_non_def_sbs - cnic_cnt;
13378
13379         if (rss_count < 1)
13380                 return -EINVAL;
13381
13382         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13383         rx_count = rss_count + cnic_cnt;
13384
13385         /* Maximum number of netdev Tx queues:
13386          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13387          */
13388         tx_count = rss_count * max_cos_est + cnic_cnt;
13389
13390         /* dev zeroed in init_etherdev */
13391         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13392         if (!dev)
13393                 return -ENOMEM;
13394
13395         bp = netdev_priv(dev);
13396
13397         bp->flags = 0;
13398         if (is_vf)
13399                 bp->flags |= IS_VF_FLAG;
13400
13401         bp->igu_sb_cnt = max_non_def_sbs;
13402         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13403         bp->msg_enable = debug;
13404         bp->cnic_support = cnic_cnt;
13405         bp->cnic_probe = bnx2x_cnic_probe;
13406
13407         pci_set_drvdata(pdev, dev);
13408
13409         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13410         if (rc < 0) {
13411                 free_netdev(dev);
13412                 return rc;
13413         }
13414
13415         BNX2X_DEV_INFO("This is a %s function\n",
13416                        IS_PF(bp) ? "physical" : "virtual");
13417         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13418         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13419         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13420                        tx_count, rx_count);
13421
13422         rc = bnx2x_init_bp(bp);
13423         if (rc)
13424                 goto init_one_exit;
13425
13426         /* Map doorbells here as we need the real value of bp->max_cos which
13427          * is initialized in bnx2x_init_bp() to determine the number of
13428          * l2 connections.
13429          */
13430         if (IS_VF(bp)) {
13431                 bp->doorbells = bnx2x_vf_doorbells(bp);
13432                 rc = bnx2x_vf_pci_alloc(bp);
13433                 if (rc)
13434                         goto init_one_exit;
13435         } else {
13436                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13437                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13438                         dev_err(&bp->pdev->dev,
13439                                 "Cannot map doorbells, bar size too small, aborting\n");
13440                         rc = -ENOMEM;
13441                         goto init_one_exit;
13442                 }
13443                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13444                                                 doorbell_size);
13445         }
13446         if (!bp->doorbells) {
13447                 dev_err(&bp->pdev->dev,
13448                         "Cannot map doorbell space, aborting\n");
13449                 rc = -ENOMEM;
13450                 goto init_one_exit;
13451         }
13452
13453         if (IS_VF(bp)) {
13454                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13455                 if (rc)
13456                         goto init_one_exit;
13457         }
13458
13459         /* Enable SRIOV if capability found in configuration space */
13460         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13461         if (rc)
13462                 goto init_one_exit;
13463
13464         /* calc qm_cid_count */
13465         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13466         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13467
13468         /* disable FCOE L2 queue for E1x*/
13469         if (CHIP_IS_E1x(bp))
13470                 bp->flags |= NO_FCOE_FLAG;
13471
13472         /* Set bp->num_queues for MSI-X mode*/
13473         bnx2x_set_num_queues(bp);
13474
13475         /* Configure interrupt mode: try to enable MSI-X/MSI if
13476          * needed.
13477          */
13478         rc = bnx2x_set_int_mode(bp);
13479         if (rc) {
13480                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13481                 goto init_one_exit;
13482         }
13483         BNX2X_DEV_INFO("set interrupts successfully\n");
13484
13485         /* register the net device */
13486         rc = register_netdev(dev);
13487         if (rc) {
13488                 dev_err(&pdev->dev, "Cannot register net device\n");
13489                 goto init_one_exit;
13490         }
13491         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13492
13493         if (!NO_FCOE(bp)) {
13494                 /* Add storage MAC address */
13495                 rtnl_lock();
13496                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13497                 rtnl_unlock();
13498         }
13499         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13500             pcie_speed == PCI_SPEED_UNKNOWN ||
13501             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13502                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13503         else
13504                 BNX2X_DEV_INFO(
13505                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13506                        board_info[ent->driver_data].name,
13507                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13508                        pcie_width,
13509                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13510                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13511                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13512                        "Unknown",
13513                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13514
13515         bnx2x_register_phc(bp);
13516
13517         return 0;
13518
13519 init_one_exit:
13520         bnx2x_disable_pcie_error_reporting(bp);
13521
13522         if (bp->regview)
13523                 iounmap(bp->regview);
13524
13525         if (IS_PF(bp) && bp->doorbells)
13526                 iounmap(bp->doorbells);
13527
13528         free_netdev(dev);
13529
13530         if (atomic_read(&pdev->enable_cnt) == 1)
13531                 pci_release_regions(pdev);
13532
13533         pci_disable_device(pdev);
13534
13535         return rc;
13536 }
13537
13538 static void __bnx2x_remove(struct pci_dev *pdev,
13539                            struct net_device *dev,
13540                            struct bnx2x *bp,
13541                            bool remove_netdev)
13542 {
13543         if (bp->ptp_clock) {
13544                 ptp_clock_unregister(bp->ptp_clock);
13545                 bp->ptp_clock = NULL;
13546         }
13547
13548         /* Delete storage MAC address */
13549         if (!NO_FCOE(bp)) {
13550                 rtnl_lock();
13551                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13552                 rtnl_unlock();
13553         }
13554
13555 #ifdef BCM_DCBNL
13556         /* Delete app tlvs from dcbnl */
13557         bnx2x_dcbnl_update_applist(bp, true);
13558 #endif
13559
13560         if (IS_PF(bp) &&
13561             !BP_NOMCP(bp) &&
13562             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13563                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13564
13565         /* Close the interface - either directly or implicitly */
13566         if (remove_netdev) {
13567                 unregister_netdev(dev);
13568         } else {
13569                 rtnl_lock();
13570                 dev_close(dev);
13571                 rtnl_unlock();
13572         }
13573
13574         bnx2x_iov_remove_one(bp);
13575
13576         /* Power on: we can't let PCI layer write to us while we are in D3 */
13577         if (IS_PF(bp)) {
13578                 bnx2x_set_power_state(bp, PCI_D0);
13579
13580                 /* Set endianity registers to reset values in case next driver
13581                  * boots in different endianty environment.
13582                  */
13583                 bnx2x_reset_endianity(bp);
13584         }
13585
13586         /* Disable MSI/MSI-X */
13587         bnx2x_disable_msi(bp);
13588
13589         /* Power off */
13590         if (IS_PF(bp))
13591                 bnx2x_set_power_state(bp, PCI_D3hot);
13592
13593         /* Make sure RESET task is not scheduled before continuing */
13594         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13595
13596         /* send message via vfpf channel to release the resources of this vf */
13597         if (IS_VF(bp))
13598                 bnx2x_vfpf_release(bp);
13599
13600         /* Assumes no further PCIe PM changes will occur */
13601         if (system_state == SYSTEM_POWER_OFF) {
13602                 pci_wake_from_d3(pdev, bp->wol);
13603                 pci_set_power_state(pdev, PCI_D3hot);
13604         }
13605
13606         bnx2x_disable_pcie_error_reporting(bp);
13607         if (remove_netdev) {
13608                 if (bp->regview)
13609                         iounmap(bp->regview);
13610
13611                 /* For vfs, doorbells are part of the regview and were unmapped
13612                  * along with it. FW is only loaded by PF.
13613                  */
13614                 if (IS_PF(bp)) {
13615                         if (bp->doorbells)
13616                                 iounmap(bp->doorbells);
13617
13618                         bnx2x_release_firmware(bp);
13619                 } else {
13620                         bnx2x_vf_pci_dealloc(bp);
13621                 }
13622                 bnx2x_free_mem_bp(bp);
13623
13624                 free_netdev(dev);
13625
13626                 if (atomic_read(&pdev->enable_cnt) == 1)
13627                         pci_release_regions(pdev);
13628
13629                 pci_disable_device(pdev);
13630         }
13631 }
13632
13633 static void bnx2x_remove_one(struct pci_dev *pdev)
13634 {
13635         struct net_device *dev = pci_get_drvdata(pdev);
13636         struct bnx2x *bp;
13637
13638         if (!dev) {
13639                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13640                 return;
13641         }
13642         bp = netdev_priv(dev);
13643
13644         __bnx2x_remove(pdev, dev, bp, true);
13645 }
13646
13647 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13648 {
13649         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13650
13651         bp->rx_mode = BNX2X_RX_MODE_NONE;
13652
13653         if (CNIC_LOADED(bp))
13654                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13655
13656         /* Stop Tx */
13657         bnx2x_tx_disable(bp);
13658         /* Delete all NAPI objects */
13659         bnx2x_del_all_napi(bp);
13660         if (CNIC_LOADED(bp))
13661                 bnx2x_del_all_napi_cnic(bp);
13662         netdev_reset_tc(bp->dev);
13663
13664         del_timer_sync(&bp->timer);
13665         cancel_delayed_work_sync(&bp->sp_task);
13666         cancel_delayed_work_sync(&bp->period_task);
13667
13668         spin_lock_bh(&bp->stats_lock);
13669         bp->stats_state = STATS_STATE_DISABLED;
13670         spin_unlock_bh(&bp->stats_lock);
13671
13672         bnx2x_save_statistics(bp);
13673
13674         netif_carrier_off(bp->dev);
13675
13676         return 0;
13677 }
13678
13679 /**
13680  * bnx2x_io_error_detected - called when PCI error is detected
13681  * @pdev: Pointer to PCI device
13682  * @state: The current pci connection state
13683  *
13684  * This function is called after a PCI bus error affecting
13685  * this device has been detected.
13686  */
13687 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13688                                                 pci_channel_state_t state)
13689 {
13690         struct net_device *dev = pci_get_drvdata(pdev);
13691         struct bnx2x *bp = netdev_priv(dev);
13692
13693         rtnl_lock();
13694
13695         BNX2X_ERR("IO error detected\n");
13696
13697         netif_device_detach(dev);
13698
13699         if (state == pci_channel_io_perm_failure) {
13700                 rtnl_unlock();
13701                 return PCI_ERS_RESULT_DISCONNECT;
13702         }
13703
13704         if (netif_running(dev))
13705                 bnx2x_eeh_nic_unload(bp);
13706
13707         bnx2x_prev_path_mark_eeh(bp);
13708
13709         pci_disable_device(pdev);
13710
13711         rtnl_unlock();
13712
13713         /* Request a slot reset */
13714         return PCI_ERS_RESULT_NEED_RESET;
13715 }
13716
13717 /**
13718  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13719  * @pdev: Pointer to PCI device
13720  *
13721  * Restart the card from scratch, as if from a cold-boot.
13722  */
13723 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13724 {
13725         struct net_device *dev = pci_get_drvdata(pdev);
13726         struct bnx2x *bp = netdev_priv(dev);
13727         int i;
13728
13729         rtnl_lock();
13730         BNX2X_ERR("IO slot reset initializing...\n");
13731         if (pci_enable_device(pdev)) {
13732                 dev_err(&pdev->dev,
13733                         "Cannot re-enable PCI device after reset\n");
13734                 rtnl_unlock();
13735                 return PCI_ERS_RESULT_DISCONNECT;
13736         }
13737
13738         pci_set_master(pdev);
13739         pci_restore_state(pdev);
13740         pci_save_state(pdev);
13741
13742         if (netif_running(dev))
13743                 bnx2x_set_power_state(bp, PCI_D0);
13744
13745         if (netif_running(dev)) {
13746                 BNX2X_ERR("IO slot reset --> driver unload\n");
13747
13748                 /* MCP should have been reset; Need to wait for validity */
13749                 bnx2x_init_shmem(bp);
13750
13751                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13752                         u32 v;
13753
13754                         v = SHMEM2_RD(bp,
13755                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13756                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13757                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13758                 }
13759                 bnx2x_drain_tx_queues(bp);
13760                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13761                 bnx2x_netif_stop(bp, 1);
13762                 bnx2x_free_irq(bp);
13763
13764                 /* Report UNLOAD_DONE to MCP */
13765                 bnx2x_send_unload_done(bp, true);
13766
13767                 bp->sp_state = 0;
13768                 bp->port.pmf = 0;
13769
13770                 bnx2x_prev_unload(bp);
13771
13772                 /* We should have reseted the engine, so It's fair to
13773                  * assume the FW will no longer write to the bnx2x driver.
13774                  */
13775                 bnx2x_squeeze_objects(bp);
13776                 bnx2x_free_skbs(bp);
13777                 for_each_rx_queue(bp, i)
13778                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13779                 bnx2x_free_fp_mem(bp);
13780                 bnx2x_free_mem(bp);
13781
13782                 bp->state = BNX2X_STATE_CLOSED;
13783         }
13784
13785         rtnl_unlock();
13786
13787         /* If AER, perform cleanup of the PCIe registers */
13788         if (bp->flags & AER_ENABLED) {
13789                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13790                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13791                 else
13792                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13793         }
13794
13795         return PCI_ERS_RESULT_RECOVERED;
13796 }
13797
13798 /**
13799  * bnx2x_io_resume - called when traffic can start flowing again
13800  * @pdev: Pointer to PCI device
13801  *
13802  * This callback is called when the error recovery driver tells us that
13803  * its OK to resume normal operation.
13804  */
13805 static void bnx2x_io_resume(struct pci_dev *pdev)
13806 {
13807         struct net_device *dev = pci_get_drvdata(pdev);
13808         struct bnx2x *bp = netdev_priv(dev);
13809
13810         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13811                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13812                 return;
13813         }
13814
13815         rtnl_lock();
13816
13817         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13818                                                         DRV_MSG_SEQ_NUMBER_MASK;
13819
13820         if (netif_running(dev))
13821                 bnx2x_nic_load(bp, LOAD_NORMAL);
13822
13823         netif_device_attach(dev);
13824
13825         rtnl_unlock();
13826 }
13827
13828 static const struct pci_error_handlers bnx2x_err_handler = {
13829         .error_detected = bnx2x_io_error_detected,
13830         .slot_reset     = bnx2x_io_slot_reset,
13831         .resume         = bnx2x_io_resume,
13832 };
13833
13834 static void bnx2x_shutdown(struct pci_dev *pdev)
13835 {
13836         struct net_device *dev = pci_get_drvdata(pdev);
13837         struct bnx2x *bp;
13838
13839         if (!dev)
13840                 return;
13841
13842         bp = netdev_priv(dev);
13843         if (!bp)
13844                 return;
13845
13846         rtnl_lock();
13847         netif_device_detach(dev);
13848         rtnl_unlock();
13849
13850         /* Don't remove the netdevice, as there are scenarios which will cause
13851          * the kernel to hang, e.g., when trying to remove bnx2i while the
13852          * rootfs is mounted from SAN.
13853          */
13854         __bnx2x_remove(pdev, dev, bp, false);
13855 }
13856
13857 static struct pci_driver bnx2x_pci_driver = {
13858         .name        = DRV_MODULE_NAME,
13859         .id_table    = bnx2x_pci_tbl,
13860         .probe       = bnx2x_init_one,
13861         .remove      = bnx2x_remove_one,
13862         .suspend     = bnx2x_suspend,
13863         .resume      = bnx2x_resume,
13864         .err_handler = &bnx2x_err_handler,
13865 #ifdef CONFIG_BNX2X_SRIOV
13866         .sriov_configure = bnx2x_sriov_configure,
13867 #endif
13868         .shutdown    = bnx2x_shutdown,
13869 };
13870
13871 static int __init bnx2x_init(void)
13872 {
13873         int ret;
13874
13875         pr_info("%s", version);
13876
13877         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13878         if (bnx2x_wq == NULL) {
13879                 pr_err("Cannot create workqueue\n");
13880                 return -ENOMEM;
13881         }
13882         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13883         if (!bnx2x_iov_wq) {
13884                 pr_err("Cannot create iov workqueue\n");
13885                 destroy_workqueue(bnx2x_wq);
13886                 return -ENOMEM;
13887         }
13888
13889         ret = pci_register_driver(&bnx2x_pci_driver);
13890         if (ret) {
13891                 pr_err("Cannot register driver\n");
13892                 destroy_workqueue(bnx2x_wq);
13893                 destroy_workqueue(bnx2x_iov_wq);
13894         }
13895         return ret;
13896 }
13897
13898 static void __exit bnx2x_cleanup(void)
13899 {
13900         struct list_head *pos, *q;
13901
13902         pci_unregister_driver(&bnx2x_pci_driver);
13903
13904         destroy_workqueue(bnx2x_wq);
13905         destroy_workqueue(bnx2x_iov_wq);
13906
13907         /* Free globally allocated resources */
13908         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13909                 struct bnx2x_prev_path_list *tmp =
13910                         list_entry(pos, struct bnx2x_prev_path_list, list);
13911                 list_del(pos);
13912                 kfree(tmp);
13913         }
13914 }
13915
13916 void bnx2x_notify_link_changed(struct bnx2x *bp)
13917 {
13918         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13919 }
13920
13921 module_init(bnx2x_init);
13922 module_exit(bnx2x_cleanup);
13923
13924 /**
13925  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13926  *
13927  * @bp:         driver handle
13928  * @set:        set or clear the CAM entry
13929  *
13930  * This function will wait until the ramrod completion returns.
13931  * Return 0 if success, -ENODEV if ramrod doesn't return.
13932  */
13933 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13934 {
13935         unsigned long ramrod_flags = 0;
13936
13937         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13938         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13939                                  &bp->iscsi_l2_mac_obj, true,
13940                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13941 }
13942
13943 /* count denotes the number of new completions we have seen */
13944 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13945 {
13946         struct eth_spe *spe;
13947         int cxt_index, cxt_offset;
13948
13949 #ifdef BNX2X_STOP_ON_ERROR
13950         if (unlikely(bp->panic))
13951                 return;
13952 #endif
13953
13954         spin_lock_bh(&bp->spq_lock);
13955         BUG_ON(bp->cnic_spq_pending < count);
13956         bp->cnic_spq_pending -= count;
13957
13958         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13959                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13960                                 & SPE_HDR_CONN_TYPE) >>
13961                                 SPE_HDR_CONN_TYPE_SHIFT;
13962                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13963                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13964
13965                 /* Set validation for iSCSI L2 client before sending SETUP
13966                  *  ramrod
13967                  */
13968                 if (type == ETH_CONNECTION_TYPE) {
13969                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13970                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13971                                         ILT_PAGE_CIDS;
13972                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13973                                         (cxt_index * ILT_PAGE_CIDS);
13974                                 bnx2x_set_ctx_validation(bp,
13975                                         &bp->context[cxt_index].
13976                                                          vcxt[cxt_offset].eth,
13977                                         BNX2X_ISCSI_ETH_CID(bp));
13978                         }
13979                 }
13980
13981                 /*
13982                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13983                  * and in the air. We also check that number of outstanding
13984                  * COMMON ramrods is not more than the EQ and SPQ can
13985                  * accommodate.
13986                  */
13987                 if (type == ETH_CONNECTION_TYPE) {
13988                         if (!atomic_read(&bp->cq_spq_left))
13989                                 break;
13990                         else
13991                                 atomic_dec(&bp->cq_spq_left);
13992                 } else if (type == NONE_CONNECTION_TYPE) {
13993                         if (!atomic_read(&bp->eq_spq_left))
13994                                 break;
13995                         else
13996                                 atomic_dec(&bp->eq_spq_left);
13997                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13998                            (type == FCOE_CONNECTION_TYPE)) {
13999                         if (bp->cnic_spq_pending >=
14000                             bp->cnic_eth_dev.max_kwqe_pending)
14001                                 break;
14002                         else
14003                                 bp->cnic_spq_pending++;
14004                 } else {
14005                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14006                         bnx2x_panic();
14007                         break;
14008                 }
14009
14010                 spe = bnx2x_sp_get_next(bp);
14011                 *spe = *bp->cnic_kwq_cons;
14012
14013                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14014                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14015
14016                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14017                         bp->cnic_kwq_cons = bp->cnic_kwq;
14018                 else
14019                         bp->cnic_kwq_cons++;
14020         }
14021         bnx2x_sp_prod_update(bp);
14022         spin_unlock_bh(&bp->spq_lock);
14023 }
14024
14025 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14026                                struct kwqe_16 *kwqes[], u32 count)
14027 {
14028         struct bnx2x *bp = netdev_priv(dev);
14029         int i;
14030
14031 #ifdef BNX2X_STOP_ON_ERROR
14032         if (unlikely(bp->panic)) {
14033                 BNX2X_ERR("Can't post to SP queue while panic\n");
14034                 return -EIO;
14035         }
14036 #endif
14037
14038         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14039             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14040                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14041                 return -EAGAIN;
14042         }
14043
14044         spin_lock_bh(&bp->spq_lock);
14045
14046         for (i = 0; i < count; i++) {
14047                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14048
14049                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14050                         break;
14051
14052                 *bp->cnic_kwq_prod = *spe;
14053
14054                 bp->cnic_kwq_pending++;
14055
14056                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14057                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14058                    spe->data.update_data_addr.hi,
14059                    spe->data.update_data_addr.lo,
14060                    bp->cnic_kwq_pending);
14061
14062                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14063                         bp->cnic_kwq_prod = bp->cnic_kwq;
14064                 else
14065                         bp->cnic_kwq_prod++;
14066         }
14067
14068         spin_unlock_bh(&bp->spq_lock);
14069
14070         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14071                 bnx2x_cnic_sp_post(bp, 0);
14072
14073         return i;
14074 }
14075
14076 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14077 {
14078         struct cnic_ops *c_ops;
14079         int rc = 0;
14080
14081         mutex_lock(&bp->cnic_mutex);
14082         c_ops = rcu_dereference_protected(bp->cnic_ops,
14083                                           lockdep_is_held(&bp->cnic_mutex));
14084         if (c_ops)
14085                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14086         mutex_unlock(&bp->cnic_mutex);
14087
14088         return rc;
14089 }
14090
14091 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14092 {
14093         struct cnic_ops *c_ops;
14094         int rc = 0;
14095
14096         rcu_read_lock();
14097         c_ops = rcu_dereference(bp->cnic_ops);
14098         if (c_ops)
14099                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14100         rcu_read_unlock();
14101
14102         return rc;
14103 }
14104
14105 /*
14106  * for commands that have no data
14107  */
14108 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14109 {
14110         struct cnic_ctl_info ctl = {0};
14111
14112         ctl.cmd = cmd;
14113
14114         return bnx2x_cnic_ctl_send(bp, &ctl);
14115 }
14116
14117 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14118 {
14119         struct cnic_ctl_info ctl = {0};
14120
14121         /* first we tell CNIC and only then we count this as a completion */
14122         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14123         ctl.data.comp.cid = cid;
14124         ctl.data.comp.error = err;
14125
14126         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14127         bnx2x_cnic_sp_post(bp, 0);
14128 }
14129
14130 /* Called with netif_addr_lock_bh() taken.
14131  * Sets an rx_mode config for an iSCSI ETH client.
14132  * Doesn't block.
14133  * Completion should be checked outside.
14134  */
14135 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14136 {
14137         unsigned long accept_flags = 0, ramrod_flags = 0;
14138         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14139         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14140
14141         if (start) {
14142                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14143                  * because it's the only way for UIO Queue to accept
14144                  * multicasts (in non-promiscuous mode only one Queue per
14145                  * function will receive multicast packets (leading in our
14146                  * case).
14147                  */
14148                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14149                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14150                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14151                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14152
14153                 /* Clear STOP_PENDING bit if START is requested */
14154                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14155
14156                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14157         } else
14158                 /* Clear START_PENDING bit if STOP is requested */
14159                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14160
14161         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14162                 set_bit(sched_state, &bp->sp_state);
14163         else {
14164                 __set_bit(RAMROD_RX, &ramrod_flags);
14165                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14166                                     ramrod_flags);
14167         }
14168 }
14169
14170 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14171 {
14172         struct bnx2x *bp = netdev_priv(dev);
14173         int rc = 0;
14174
14175         switch (ctl->cmd) {
14176         case DRV_CTL_CTXTBL_WR_CMD: {
14177                 u32 index = ctl->data.io.offset;
14178                 dma_addr_t addr = ctl->data.io.dma_addr;
14179
14180                 bnx2x_ilt_wr(bp, index, addr);
14181                 break;
14182         }
14183
14184         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14185                 int count = ctl->data.credit.credit_count;
14186
14187                 bnx2x_cnic_sp_post(bp, count);
14188                 break;
14189         }
14190
14191         /* rtnl_lock is held.  */
14192         case DRV_CTL_START_L2_CMD: {
14193                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14194                 unsigned long sp_bits = 0;
14195
14196                 /* Configure the iSCSI classification object */
14197                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14198                                    cp->iscsi_l2_client_id,
14199                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14200                                    bnx2x_sp(bp, mac_rdata),
14201                                    bnx2x_sp_mapping(bp, mac_rdata),
14202                                    BNX2X_FILTER_MAC_PENDING,
14203                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14204                                    &bp->macs_pool);
14205
14206                 /* Set iSCSI MAC address */
14207                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14208                 if (rc)
14209                         break;
14210
14211                 mmiowb();
14212                 barrier();
14213
14214                 /* Start accepting on iSCSI L2 ring */
14215
14216                 netif_addr_lock_bh(dev);
14217                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14218                 netif_addr_unlock_bh(dev);
14219
14220                 /* bits to wait on */
14221                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14222                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14223
14224                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14225                         BNX2X_ERR("rx_mode completion timed out!\n");
14226
14227                 break;
14228         }
14229
14230         /* rtnl_lock is held.  */
14231         case DRV_CTL_STOP_L2_CMD: {
14232                 unsigned long sp_bits = 0;
14233
14234                 /* Stop accepting on iSCSI L2 ring */
14235                 netif_addr_lock_bh(dev);
14236                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14237                 netif_addr_unlock_bh(dev);
14238
14239                 /* bits to wait on */
14240                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14241                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14242
14243                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14244                         BNX2X_ERR("rx_mode completion timed out!\n");
14245
14246                 mmiowb();
14247                 barrier();
14248
14249                 /* Unset iSCSI L2 MAC */
14250                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14251                                         BNX2X_ISCSI_ETH_MAC, true);
14252                 break;
14253         }
14254         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14255                 int count = ctl->data.credit.credit_count;
14256
14257                 smp_mb__before_atomic();
14258                 atomic_add(count, &bp->cq_spq_left);
14259                 smp_mb__after_atomic();
14260                 break;
14261         }
14262         case DRV_CTL_ULP_REGISTER_CMD: {
14263                 int ulp_type = ctl->data.register_data.ulp_type;
14264
14265                 if (CHIP_IS_E3(bp)) {
14266                         int idx = BP_FW_MB_IDX(bp);
14267                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14268                         int path = BP_PATH(bp);
14269                         int port = BP_PORT(bp);
14270                         int i;
14271                         u32 scratch_offset;
14272                         u32 *host_addr;
14273
14274                         /* first write capability to shmem2 */
14275                         if (ulp_type == CNIC_ULP_ISCSI)
14276                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14277                         else if (ulp_type == CNIC_ULP_FCOE)
14278                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14279                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14280
14281                         if ((ulp_type != CNIC_ULP_FCOE) ||
14282                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14283                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14284                                 break;
14285
14286                         /* if reached here - should write fcoe capabilities */
14287                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14288                         if (!scratch_offset)
14289                                 break;
14290                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14291                                                    fcoe_features[path][port]);
14292                         host_addr = (u32 *) &(ctl->data.register_data.
14293                                               fcoe_features);
14294                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14295                              i += 4)
14296                                 REG_WR(bp, scratch_offset + i,
14297                                        *(host_addr + i/4));
14298                 }
14299                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14300                 break;
14301         }
14302
14303         case DRV_CTL_ULP_UNREGISTER_CMD: {
14304                 int ulp_type = ctl->data.ulp_type;
14305
14306                 if (CHIP_IS_E3(bp)) {
14307                         int idx = BP_FW_MB_IDX(bp);
14308                         u32 cap;
14309
14310                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14311                         if (ulp_type == CNIC_ULP_ISCSI)
14312                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14313                         else if (ulp_type == CNIC_ULP_FCOE)
14314                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14315                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14316                 }
14317                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14318                 break;
14319         }
14320
14321         default:
14322                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14323                 rc = -EINVAL;
14324         }
14325
14326         return rc;
14327 }
14328
14329 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14330 {
14331         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14332
14333         if (bp->flags & USING_MSIX_FLAG) {
14334                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14335                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14336                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14337         } else {
14338                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14339                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14340         }
14341         if (!CHIP_IS_E1x(bp))
14342                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14343         else
14344                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14345
14346         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14347         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14348         cp->irq_arr[1].status_blk = bp->def_status_blk;
14349         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14350         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14351
14352         cp->num_irq = 2;
14353 }
14354
14355 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14356 {
14357         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14358
14359         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14360                              bnx2x_cid_ilt_lines(bp);
14361         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14362         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14363         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14364
14365         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14366            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14367            cp->iscsi_l2_cid);
14368
14369         if (NO_ISCSI_OOO(bp))
14370                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14371 }
14372
14373 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14374                                void *data)
14375 {
14376         struct bnx2x *bp = netdev_priv(dev);
14377         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14378         int rc;
14379
14380         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14381
14382         if (ops == NULL) {
14383                 BNX2X_ERR("NULL ops received\n");
14384                 return -EINVAL;
14385         }
14386
14387         if (!CNIC_SUPPORT(bp)) {
14388                 BNX2X_ERR("Can't register CNIC when not supported\n");
14389                 return -EOPNOTSUPP;
14390         }
14391
14392         if (!CNIC_LOADED(bp)) {
14393                 rc = bnx2x_load_cnic(bp);
14394                 if (rc) {
14395                         BNX2X_ERR("CNIC-related load failed\n");
14396                         return rc;
14397                 }
14398         }
14399
14400         bp->cnic_enabled = true;
14401
14402         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14403         if (!bp->cnic_kwq)
14404                 return -ENOMEM;
14405
14406         bp->cnic_kwq_cons = bp->cnic_kwq;
14407         bp->cnic_kwq_prod = bp->cnic_kwq;
14408         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14409
14410         bp->cnic_spq_pending = 0;
14411         bp->cnic_kwq_pending = 0;
14412
14413         bp->cnic_data = data;
14414
14415         cp->num_irq = 0;
14416         cp->drv_state |= CNIC_DRV_STATE_REGD;
14417         cp->iro_arr = bp->iro_arr;
14418
14419         bnx2x_setup_cnic_irq_info(bp);
14420
14421         rcu_assign_pointer(bp->cnic_ops, ops);
14422
14423         /* Schedule driver to read CNIC driver versions */
14424         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14425
14426         return 0;
14427 }
14428
14429 static int bnx2x_unregister_cnic(struct net_device *dev)
14430 {
14431         struct bnx2x *bp = netdev_priv(dev);
14432         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14433
14434         mutex_lock(&bp->cnic_mutex);
14435         cp->drv_state = 0;
14436         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14437         mutex_unlock(&bp->cnic_mutex);
14438         synchronize_rcu();
14439         bp->cnic_enabled = false;
14440         kfree(bp->cnic_kwq);
14441         bp->cnic_kwq = NULL;
14442
14443         return 0;
14444 }
14445
14446 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14447 {
14448         struct bnx2x *bp = netdev_priv(dev);
14449         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14450
14451         /* If both iSCSI and FCoE are disabled - return NULL in
14452          * order to indicate CNIC that it should not try to work
14453          * with this device.
14454          */
14455         if (NO_ISCSI(bp) && NO_FCOE(bp))
14456                 return NULL;
14457
14458         cp->drv_owner = THIS_MODULE;
14459         cp->chip_id = CHIP_ID(bp);
14460         cp->pdev = bp->pdev;
14461         cp->io_base = bp->regview;
14462         cp->io_base2 = bp->doorbells;
14463         cp->max_kwqe_pending = 8;
14464         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14465         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14466                              bnx2x_cid_ilt_lines(bp);
14467         cp->ctx_tbl_len = CNIC_ILT_LINES;
14468         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14469         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14470         cp->drv_ctl = bnx2x_drv_ctl;
14471         cp->drv_register_cnic = bnx2x_register_cnic;
14472         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14473         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14474         cp->iscsi_l2_client_id =
14475                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14476         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14477
14478         if (NO_ISCSI_OOO(bp))
14479                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14480
14481         if (NO_ISCSI(bp))
14482                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14483
14484         if (NO_FCOE(bp))
14485                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14486
14487         BNX2X_DEV_INFO(
14488                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14489            cp->ctx_blk_size,
14490            cp->ctx_tbl_offset,
14491            cp->ctx_tbl_len,
14492            cp->starting_cid);
14493         return cp;
14494 }
14495
14496 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14497 {
14498         struct bnx2x *bp = fp->bp;
14499         u32 offset = BAR_USTRORM_INTMEM;
14500
14501         if (IS_VF(bp))
14502                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14503         else if (!CHIP_IS_E1x(bp))
14504                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14505         else
14506                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14507
14508         return offset;
14509 }
14510
14511 /* called only on E1H or E2.
14512  * When pretending to be PF, the pretend value is the function number 0...7
14513  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14514  * combination
14515  */
14516 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14517 {
14518         u32 pretend_reg;
14519
14520         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14521                 return -1;
14522
14523         /* get my own pretend register */
14524         pretend_reg = bnx2x_get_pretend_reg(bp);
14525         REG_WR(bp, pretend_reg, pretend_func_val);
14526         REG_RD(bp, pretend_reg);
14527         return 0;
14528 }
14529
14530 static void bnx2x_ptp_task(struct work_struct *work)
14531 {
14532         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14533         int port = BP_PORT(bp);
14534         u32 val_seq;
14535         u64 timestamp, ns;
14536         struct skb_shared_hwtstamps shhwtstamps;
14537
14538         /* Read Tx timestamp registers */
14539         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14540                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14541         if (val_seq & 0x10000) {
14542                 /* There is a valid timestamp value */
14543                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14544                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14545                 timestamp <<= 32;
14546                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14547                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14548                 /* Reset timestamp register to allow new timestamp */
14549                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14550                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14551                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14552
14553                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14554                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14555                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14556                 dev_kfree_skb_any(bp->ptp_tx_skb);
14557                 bp->ptp_tx_skb = NULL;
14558
14559                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14560                    timestamp, ns);
14561         } else {
14562                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14563                 /* Reschedule to keep checking for a valid timestamp value */
14564                 schedule_work(&bp->ptp_task);
14565         }
14566 }
14567
14568 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14569 {
14570         int port = BP_PORT(bp);
14571         u64 timestamp, ns;
14572
14573         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14574                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14575         timestamp <<= 32;
14576         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14577                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14578
14579         /* Reset timestamp register to allow new timestamp */
14580         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14581                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14582
14583         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14584
14585         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14586
14587         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14588            timestamp, ns);
14589 }
14590
14591 /* Read the PHC */
14592 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14593 {
14594         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14595         int port = BP_PORT(bp);
14596         u32 wb_data[2];
14597         u64 phc_cycles;
14598
14599         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14600                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14601         phc_cycles = wb_data[1];
14602         phc_cycles = (phc_cycles << 32) + wb_data[0];
14603
14604         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14605
14606         return phc_cycles;
14607 }
14608
14609 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14610 {
14611         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14612         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14613         bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14614         bp->cyclecounter.shift = 1;
14615         bp->cyclecounter.mult = 1;
14616 }
14617
14618 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14619 {
14620         struct bnx2x_func_state_params func_params = {NULL};
14621         struct bnx2x_func_set_timesync_params *set_timesync_params =
14622                 &func_params.params.set_timesync;
14623
14624         /* Prepare parameters for function state transitions */
14625         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14626         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14627
14628         func_params.f_obj = &bp->func_obj;
14629         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14630
14631         /* Function parameters */
14632         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14633         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14634
14635         return bnx2x_func_state_change(bp, &func_params);
14636 }
14637
14638 int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14639 {
14640         struct bnx2x_queue_state_params q_params;
14641         int rc, i;
14642
14643         /* send queue update ramrod to enable PTP packets */
14644         memset(&q_params, 0, sizeof(q_params));
14645         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14646         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14647         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14648                   &q_params.params.update.update_flags);
14649         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14650                   &q_params.params.update.update_flags);
14651
14652         /* send the ramrod on all the queues of the PF */
14653         for_each_eth_queue(bp, i) {
14654                 struct bnx2x_fastpath *fp = &bp->fp[i];
14655
14656                 /* Set the appropriate Queue object */
14657                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14658
14659                 /* Update the Queue state */
14660                 rc = bnx2x_queue_state_change(bp, &q_params);
14661                 if (rc) {
14662                         BNX2X_ERR("Failed to enable PTP packets\n");
14663                         return rc;
14664                 }
14665         }
14666
14667         return 0;
14668 }
14669
14670 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14671 {
14672         int port = BP_PORT(bp);
14673         int rc;
14674
14675         if (!bp->hwtstamp_ioctl_called)
14676                 return 0;
14677
14678         switch (bp->tx_type) {
14679         case HWTSTAMP_TX_ON:
14680                 bp->flags |= TX_TIMESTAMPING_EN;
14681                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14682                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14683                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14684                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14685                 break;
14686         case HWTSTAMP_TX_ONESTEP_SYNC:
14687                 BNX2X_ERR("One-step timestamping is not supported\n");
14688                 return -ERANGE;
14689         }
14690
14691         switch (bp->rx_filter) {
14692         case HWTSTAMP_FILTER_NONE:
14693                 break;
14694         case HWTSTAMP_FILTER_ALL:
14695         case HWTSTAMP_FILTER_SOME:
14696                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14697                 break;
14698         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14699         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14700         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14701                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14702                 /* Initialize PTP detection for UDP/IPv4 events */
14703                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14704                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14705                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14706                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14707                 break;
14708         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14709         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14710         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14711                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14712                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14713                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14714                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14715                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14716                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14717                 break;
14718         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14719         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14720         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14721                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14722                 /* Initialize PTP detection L2 events */
14723                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14724                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14725                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14726                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14727
14728                 break;
14729         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14730         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14731         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14732                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14733                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14734                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14735                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14736                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14737                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14738                 break;
14739         }
14740
14741         /* Indicate to FW that this PF expects recorded PTP packets */
14742         rc = bnx2x_enable_ptp_packets(bp);
14743         if (rc)
14744                 return rc;
14745
14746         /* Enable sending PTP packets to host */
14747         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14748                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14749
14750         return 0;
14751 }
14752
14753 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14754 {
14755         struct hwtstamp_config config;
14756         int rc;
14757
14758         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14759
14760         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14761                 return -EFAULT;
14762
14763         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14764            config.tx_type, config.rx_filter);
14765
14766         if (config.flags) {
14767                 BNX2X_ERR("config.flags is reserved for future use\n");
14768                 return -EINVAL;
14769         }
14770
14771         bp->hwtstamp_ioctl_called = 1;
14772         bp->tx_type = config.tx_type;
14773         bp->rx_filter = config.rx_filter;
14774
14775         rc = bnx2x_configure_ptp_filters(bp);
14776         if (rc)
14777                 return rc;
14778
14779         config.rx_filter = bp->rx_filter;
14780
14781         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14782                 -EFAULT : 0;
14783 }
14784
14785 /* Configures HW for PTP */
14786 static int bnx2x_configure_ptp(struct bnx2x *bp)
14787 {
14788         int rc, port = BP_PORT(bp);
14789         u32 wb_data[2];
14790
14791         /* Reset PTP event detection rules - will be configured in the IOCTL */
14792         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14793                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14794         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14795                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14796         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14797                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14798         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14799                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14800
14801         /* Disable PTP packets to host - will be configured in the IOCTL*/
14802         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14803                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14804
14805         /* Enable the PTP feature */
14806         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14807                NIG_REG_P0_PTP_EN, 0x3F);
14808
14809         /* Enable the free-running counter */
14810         wb_data[0] = 0;
14811         wb_data[1] = 0;
14812         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14813
14814         /* Reset drift register (offset register is not reset) */
14815         rc = bnx2x_send_reset_timesync_ramrod(bp);
14816         if (rc) {
14817                 BNX2X_ERR("Failed to reset PHC drift register\n");
14818                 return -EFAULT;
14819         }
14820
14821         /* Reset possibly old timestamps */
14822         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14823                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14824         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14825                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14826
14827         return 0;
14828 }
14829
14830 /* Called during load, to initialize PTP-related stuff */
14831 void bnx2x_init_ptp(struct bnx2x *bp)
14832 {
14833         int rc;
14834
14835         /* Configure PTP in HW */
14836         rc = bnx2x_configure_ptp(bp);
14837         if (rc) {
14838                 BNX2X_ERR("Stopping PTP initialization\n");
14839                 return;
14840         }
14841
14842         /* Init work queue for Tx timestamping */
14843         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14844
14845         /* Init cyclecounter and timecounter. This is done only in the first
14846          * load. If done in every load, PTP application will fail when doing
14847          * unload / load (e.g. MTU change) while it is running.
14848          */
14849         if (!bp->timecounter_init_done) {
14850                 bnx2x_init_cyclecounter(bp);
14851                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14852                                  ktime_to_ns(ktime_get_real()));
14853                 bp->timecounter_init_done = 1;
14854         }
14855
14856         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14857 }