drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_FR_NSMR_TPTE_WR          = 0x20,
 104         FW_RI_INV_LSTAG_WR             = 0x1a,
 105         FW_ISCSI_TX_DATA_WR            = 0x45,
 106         FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
 107         FW_LASTC2E_WR                  = 0x70
 108 };
 109
 110 struct fw_wr_hdr {
 111         __be32 hi;
 112         __be32 lo;
 113 };
 114
 115 /* work request opcode (hi) */
 116 #define FW_WR_OP_S      24
 117 #define FW_WR_OP_M      0xff
 118 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 119 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 120
 121 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 122 #define FW_WR_ATOMIC_S          23
 123 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 124
 125 /* flush flag (hi) - firmware flushes flushable work request buffered
 126  * in the flow context.
 127  */
 128 #define FW_WR_FLUSH_S     22
 129 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 130
 131 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 132 #define FW_WR_COMPL_S     21
 133 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 134 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 135
 136 /* work request immediate data length (hi) */
 137 #define FW_WR_IMMDLEN_S 0
 138 #define FW_WR_IMMDLEN_M 0xff
 139 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 140
 141 /* egress queue status update to associated ingress queue entry (lo) */
 142 #define FW_WR_EQUIQ_S           31
 143 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 144 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 145
 146 /* egress queue status update to egress queue status entry (lo) */
 147 #define FW_WR_EQUEQ_S           30
 148 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 149 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 150
 151 /* flow context identifier (lo) */
 152 #define FW_WR_FLOWID_S          8
 153 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 154
 155 /* length in units of 16-bytes (lo) */
 156 #define FW_WR_LEN16_S           0
 157 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 158
 159 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 160 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 161
 162 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 163 enum fw_filter_wr_cookie {
 164         FW_FILTER_WR_SUCCESS,
 165         FW_FILTER_WR_FLT_ADDED,
 166         FW_FILTER_WR_FLT_DELETED,
 167         FW_FILTER_WR_SMT_TBL_FULL,
 168         FW_FILTER_WR_EINVAL,
 169 };
 170
 171 struct fw_filter_wr {
 172         __be32 op_pkd;
 173         __be32 len16_pkd;
 174         __be64 r3;
 175         __be32 tid_to_iq;
 176         __be32 del_filter_to_l2tix;
 177         __be16 ethtype;
 178         __be16 ethtypem;
 179         __u8   frag_to_ovlan_vldm;
 180         __u8   smac_sel;
 181         __be16 rx_chan_rx_rpl_iq;
 182         __be32 maci_to_matchtypem;
 183         __u8   ptcl;
 184         __u8   ptclm;
 185         __u8   ttyp;
 186         __u8   ttypm;
 187         __be16 ivlan;
 188         __be16 ivlanm;
 189         __be16 ovlan;
 190         __be16 ovlanm;
 191         __u8   lip[16];
 192         __u8   lipm[16];
 193         __u8   fip[16];
 194         __u8   fipm[16];
 195         __be16 lp;
 196         __be16 lpm;
 197         __be16 fp;
 198         __be16 fpm;
 199         __be16 r7;
 200         __u8   sma[6];
 201 };
 202
 203 #define FW_FILTER_WR_TID_S      12
 204 #define FW_FILTER_WR_TID_M      0xfffff
 205 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 206 #define FW_FILTER_WR_TID_G(x)   \
 207         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 208
 209 #define FW_FILTER_WR_RQTYPE_S           11
 210 #define FW_FILTER_WR_RQTYPE_M           0x1
 211 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 212 #define FW_FILTER_WR_RQTYPE_G(x)        \
 213         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 214 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 215
 216 #define FW_FILTER_WR_NOREPLY_S          10
 217 #define FW_FILTER_WR_NOREPLY_M          0x1
 218 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 219 #define FW_FILTER_WR_NOREPLY_G(x)       \
 220         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 221 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 222
 223 #define FW_FILTER_WR_IQ_S       0
 224 #define FW_FILTER_WR_IQ_M       0x3ff
 225 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 226 #define FW_FILTER_WR_IQ_G(x)    \
 227         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 228
 229 #define FW_FILTER_WR_DEL_FILTER_S       31
 230 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 231 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 232 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 233         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 234 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 235
 236 #define FW_FILTER_WR_RPTTID_S           25
 237 #define FW_FILTER_WR_RPTTID_M           0x1
 238 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 239 #define FW_FILTER_WR_RPTTID_G(x)        \
 240         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 241 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 242
 243 #define FW_FILTER_WR_DROP_S     24
 244 #define FW_FILTER_WR_DROP_M     0x1
 245 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 246 #define FW_FILTER_WR_DROP_G(x)  \
 247         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 248 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 249
 250 #define FW_FILTER_WR_DIRSTEER_S         23
 251 #define FW_FILTER_WR_DIRSTEER_M         0x1
 252 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 253 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 254         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 255 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 256
 257 #define FW_FILTER_WR_MASKHASH_S         22
 258 #define FW_FILTER_WR_MASKHASH_M         0x1
 259 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 260 #define FW_FILTER_WR_MASKHASH_G(x)      \
 261         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 262 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 263
 264 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 265 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 266 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 267 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 268         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 269 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 270
 271 #define FW_FILTER_WR_LPBK_S     20
 272 #define FW_FILTER_WR_LPBK_M     0x1
 273 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 274 #define FW_FILTER_WR_LPBK_G(x)  \
 275         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 276 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 277
 278 #define FW_FILTER_WR_DMAC_S     19
 279 #define FW_FILTER_WR_DMAC_M     0x1
 280 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 281 #define FW_FILTER_WR_DMAC_G(x)  \
 282         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 283 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 284
 285 #define FW_FILTER_WR_SMAC_S     18
 286 #define FW_FILTER_WR_SMAC_M     0x1
 287 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 288 #define FW_FILTER_WR_SMAC_G(x)  \
 289         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 290 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 291
 292 #define FW_FILTER_WR_INSVLAN_S          17
 293 #define FW_FILTER_WR_INSVLAN_M          0x1
 294 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 295 #define FW_FILTER_WR_INSVLAN_G(x)       \
 296         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 297 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 298
 299 #define FW_FILTER_WR_RMVLAN_S           16
 300 #define FW_FILTER_WR_RMVLAN_M           0x1
 301 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 302 #define FW_FILTER_WR_RMVLAN_G(x)        \
 303         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 304 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 305
 306 #define FW_FILTER_WR_HITCNTS_S          15
 307 #define FW_FILTER_WR_HITCNTS_M          0x1
 308 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 309 #define FW_FILTER_WR_HITCNTS_G(x)       \
 310         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 311 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 312
 313 #define FW_FILTER_WR_TXCHAN_S           13
 314 #define FW_FILTER_WR_TXCHAN_M           0x3
 315 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 316 #define FW_FILTER_WR_TXCHAN_G(x)        \
 317         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 318
 319 #define FW_FILTER_WR_PRIO_S     12
 320 #define FW_FILTER_WR_PRIO_M     0x1
 321 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 322 #define FW_FILTER_WR_PRIO_G(x)  \
 323         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 324 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 325
 326 #define FW_FILTER_WR_L2TIX_S    0
 327 #define FW_FILTER_WR_L2TIX_M    0xfff
 328 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 329 #define FW_FILTER_WR_L2TIX_G(x) \
 330         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 331
 332 #define FW_FILTER_WR_FRAG_S     7
 333 #define FW_FILTER_WR_FRAG_M     0x1
 334 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 335 #define FW_FILTER_WR_FRAG_G(x)  \
 336         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 337 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 338
 339 #define FW_FILTER_WR_FRAGM_S    6
 340 #define FW_FILTER_WR_FRAGM_M    0x1
 341 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 342 #define FW_FILTER_WR_FRAGM_G(x) \
 343         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 344 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 345
 346 #define FW_FILTER_WR_IVLAN_VLD_S        5
 347 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 348 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 349 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 350         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 351 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 352
 353 #define FW_FILTER_WR_OVLAN_VLD_S        4
 354 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 355 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 356 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 357         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 358 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 359
 360 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 361 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 362 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 363 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 364         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 365 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 366
 367 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 368 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 369 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 370 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 371         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 372 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 373
 374 #define FW_FILTER_WR_RX_CHAN_S          15
 375 #define FW_FILTER_WR_RX_CHAN_M          0x1
 376 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 377 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 378         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 379 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 380
 381 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 382 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 383 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 384 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 385         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 386
 387 #define FW_FILTER_WR_MACI_S     23
 388 #define FW_FILTER_WR_MACI_M     0x1ff
 389 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 390 #define FW_FILTER_WR_MACI_G(x)  \
 391         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 392
 393 #define FW_FILTER_WR_MACIM_S    14
 394 #define FW_FILTER_WR_MACIM_M    0x1ff
 395 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 396 #define FW_FILTER_WR_MACIM_G(x) \
 397         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 398
 399 #define FW_FILTER_WR_FCOE_S     13
 400 #define FW_FILTER_WR_FCOE_M     0x1
 401 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 402 #define FW_FILTER_WR_FCOE_G(x)  \
 403         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 404 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 405
 406 #define FW_FILTER_WR_FCOEM_S    12
 407 #define FW_FILTER_WR_FCOEM_M    0x1
 408 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 409 #define FW_FILTER_WR_FCOEM_G(x) \
 410         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 411 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 412
 413 #define FW_FILTER_WR_PORT_S     9
 414 #define FW_FILTER_WR_PORT_M     0x7
 415 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 416 #define FW_FILTER_WR_PORT_G(x)  \
 417         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 418
 419 #define FW_FILTER_WR_PORTM_S    6
 420 #define FW_FILTER_WR_PORTM_M    0x7
 421 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 422 #define FW_FILTER_WR_PORTM_G(x) \
 423         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 424
 425 #define FW_FILTER_WR_MATCHTYPE_S        3
 426 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 427 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 428 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 429         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 430
 431 #define FW_FILTER_WR_MATCHTYPEM_S       0
 432 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 433 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 434 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 435         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 436
 437 struct fw_ulptx_wr {
 438         __be32 op_to_compl;
 439         __be32 flowid_len16;
 440         u64 cookie;
 441 };
 442
 443 struct fw_tp_wr {
 444         __be32 op_to_immdlen;
 445         __be32 flowid_len16;
 446         u64 cookie;
 447 };
 448
 449 struct fw_eth_tx_pkt_wr {
 450         __be32 op_immdlen;
 451         __be32 equiq_to_len16;
 452         __be64 r3;
 453 };
 454
 455 struct fw_ofld_connection_wr {
 456         __be32 op_compl;
 457         __be32 len16_pkd;
 458         __u64  cookie;
 459         __be64 r2;
 460         __be64 r3;
 461         struct fw_ofld_connection_le {
 462                 __be32 version_cpl;
 463                 __be32 filter;
 464                 __be32 r1;
 465                 __be16 lport;
 466                 __be16 pport;
 467                 union fw_ofld_connection_leip {
 468                         struct fw_ofld_connection_le_ipv4 {
 469                                 __be32 pip;
 470                                 __be32 lip;
 471                                 __be64 r0;
 472                                 __be64 r1;
 473                                 __be64 r2;
 474                         } ipv4;
 475                         struct fw_ofld_connection_le_ipv6 {
 476                                 __be64 pip_hi;
 477                                 __be64 pip_lo;
 478                                 __be64 lip_hi;
 479                                 __be64 lip_lo;
 480                         } ipv6;
 481                 } u;
 482         } le;
 483         struct fw_ofld_connection_tcb {
 484                 __be32 t_state_to_astid;
 485                 __be16 cplrxdataack_cplpassacceptrpl;
 486                 __be16 rcv_adv;
 487                 __be32 rcv_nxt;
 488                 __be32 tx_max;
 489                 __be64 opt0;
 490                 __be32 opt2;
 491                 __be32 r1;
 492                 __be64 r2;
 493                 __be64 r3;
 494         } tcb;
 495 };
 496
 497 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 498 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 499 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 500         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 501 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 502         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 503         FW_OFLD_CONNECTION_WR_VERSION_M)
 504 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 505         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 506
 507 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 508 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 509 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 510 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 511         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 512 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 513
 514 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 516 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 517         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 518 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 519         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 520         FW_OFLD_CONNECTION_WR_T_STATE_M)
 521
 522 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 524 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 525         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 526 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 527         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 528         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 529
 530 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 531 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 532 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 533         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 534 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 535         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 536
 537 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 539 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 540         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 542         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 543         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 544 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 545         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 546
 547 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 549 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 550         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 552         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 553         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 554 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 555         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 556
 557 enum fw_flowc_mnem {
 558         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 559         FW_FLOWC_MNEM_CH,
 560         FW_FLOWC_MNEM_PORT,
 561         FW_FLOWC_MNEM_IQID,
 562         FW_FLOWC_MNEM_SNDNXT,
 563         FW_FLOWC_MNEM_RCVNXT,
 564         FW_FLOWC_MNEM_SNDBUF,
 565         FW_FLOWC_MNEM_MSS,
 566         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 567         FW_FLOWC_MNEM_TCPSTATE,
 568         FW_FLOWC_MNEM_EOSTATE,
 569         FW_FLOWC_MNEM_SCHEDCLASS,
 570         FW_FLOWC_MNEM_DCBPRIO,
 571         FW_FLOWC_MNEM_SND_SCALE,
 572         FW_FLOWC_MNEM_RCV_SCALE,
 573 };
 574
 575 struct fw_flowc_mnemval {
 576         u8 mnemonic;
 577         u8 r4[3];
 578         __be32 val;
 579 };
 580
 581 struct fw_flowc_wr {
 582         __be32 op_to_nparams;
 583         __be32 flowid_len16;
 584         struct fw_flowc_mnemval mnemval[0];
 585 };
 586
 587 #define FW_FLOWC_WR_NPARAMS_S           0
 588 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 589
 590 struct fw_ofld_tx_data_wr {
 591         __be32 op_to_immdlen;
 592         __be32 flowid_len16;
 593         __be32 plen;
 594         __be32 tunnel_to_proxy;
 595 };
 596
 597 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 598 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 599
 600 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 601 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 602
 603 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 604 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 605 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 606
 607 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 608 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 609
 610 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 611 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 612
 613 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 614 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 615 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 616
 617 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 618 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 619
 620 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 621 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 622         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 623
 624 struct fw_cmd_wr {
 625         __be32 op_dma;
 626         __be32 len16_pkd;
 627         __be64 cookie_daddr;
 628 };
 629
 630 #define FW_CMD_WR_DMA_S         17
 631 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 632
 633 struct fw_eth_tx_pkt_vm_wr {
 634         __be32 op_immdlen;
 635         __be32 equiq_to_len16;
 636         __be32 r3[2];
 637         u8 ethmacdst[6];
 638         u8 ethmacsrc[6];
 639         __be16 ethtype;
 640         __be16 vlantci;
 641 };
 642
 643 #define FW_CMD_MAX_TIMEOUT 10000
 644
 645 /*
 646  * If a host driver does a HELLO and discovers that there's already a MASTER
 647  * selected, we may have to wait for that MASTER to finish issuing RESET,
 648  * configuration and INITIALIZE commands.  Also, there's a possibility that
 649  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 650  * RESET command, so we need to be willing to make a few retries of our HELLO.
 651  */
 652 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 653 #define FW_CMD_HELLO_RETRIES    3
 654
 655
 656 enum fw_cmd_opcodes {
 657         FW_LDST_CMD                    = 0x01,
 658         FW_RESET_CMD                   = 0x03,
 659         FW_HELLO_CMD                   = 0x04,
 660         FW_BYE_CMD                     = 0x05,
 661         FW_INITIALIZE_CMD              = 0x06,
 662         FW_CAPS_CONFIG_CMD             = 0x07,
 663         FW_PARAMS_CMD                  = 0x08,
 664         FW_PFVF_CMD                    = 0x09,
 665         FW_IQ_CMD                      = 0x10,
 666         FW_EQ_MNGT_CMD                 = 0x11,
 667         FW_EQ_ETH_CMD                  = 0x12,
 668         FW_EQ_CTRL_CMD                 = 0x13,
 669         FW_EQ_OFLD_CMD                 = 0x21,
 670         FW_VI_CMD                      = 0x14,
 671         FW_VI_MAC_CMD                  = 0x15,
 672         FW_VI_RXMODE_CMD               = 0x16,
 673         FW_VI_ENABLE_CMD               = 0x17,
 674         FW_ACL_MAC_CMD                 = 0x18,
 675         FW_ACL_VLAN_CMD                = 0x19,
 676         FW_VI_STATS_CMD                = 0x1a,
 677         FW_PORT_CMD                    = 0x1b,
 678         FW_PORT_STATS_CMD              = 0x1c,
 679         FW_PORT_LB_STATS_CMD           = 0x1d,
 680         FW_PORT_TRACE_CMD              = 0x1e,
 681         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 682         FW_RSS_IND_TBL_CMD             = 0x20,
 683         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 684         FW_RSS_VI_CONFIG_CMD           = 0x23,
 685         FW_SCHED_CMD                   = 0x24,
 686         FW_DEVLOG_CMD                  = 0x25,
 687         FW_CLIP_CMD                    = 0x28,
 688         FW_LASTC2E_CMD                 = 0x40,
 689         FW_ERROR_CMD                   = 0x80,
 690         FW_DEBUG_CMD                   = 0x81,
 691 };
 692
 693 enum fw_cmd_cap {
 694         FW_CMD_CAP_PF                  = 0x01,
 695         FW_CMD_CAP_DMAQ                = 0x02,
 696         FW_CMD_CAP_PORT                = 0x04,
 697         FW_CMD_CAP_PORTPROMISC         = 0x08,
 698         FW_CMD_CAP_PORTSTATS           = 0x10,
 699         FW_CMD_CAP_VF                  = 0x80,
 700 };
 701
 702 /*
 703  * Generic command header flit0
 704  */
 705 struct fw_cmd_hdr {
 706         __be32 hi;
 707         __be32 lo;
 708 };
 709
 710 #define FW_CMD_OP_S             24
 711 #define FW_CMD_OP_M             0xff
 712 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 713 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 714
 715 #define FW_CMD_REQUEST_S        23
 716 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 717 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 718
 719 #define FW_CMD_READ_S           22
 720 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 721 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 722
 723 #define FW_CMD_WRITE_S          21
 724 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 725 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 726
 727 #define FW_CMD_EXEC_S           20
 728 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 729 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 730
 731 #define FW_CMD_RAMASK_S         20
 732 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 733
 734 #define FW_CMD_RETVAL_S         8
 735 #define FW_CMD_RETVAL_M         0xff
 736 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 737 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 738
 739 #define FW_CMD_LEN16_S          0
 740 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 741
 742 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 743
 744 enum fw_ldst_addrspc {
 745         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 746         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 747         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 748         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 749         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 750         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 751         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 752         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 753         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 754         FW_LDST_ADDRSPC_MPS       = 0x0020,
 755         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 756         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 757 };
 758
 759 enum fw_ldst_mps_fid {
 760         FW_LDST_MPS_ATRB,
 761         FW_LDST_MPS_RPLC
 762 };
 763
 764 enum fw_ldst_func_access_ctl {
 765         FW_LDST_FUNC_ACC_CTL_VIID,
 766         FW_LDST_FUNC_ACC_CTL_FID
 767 };
 768
 769 enum fw_ldst_func_mod_index {
 770         FW_LDST_FUNC_MPS
 771 };
 772
 773 struct fw_ldst_cmd {
 774         __be32 op_to_addrspace;
 775         __be32 cycles_to_len16;
 776         union fw_ldst {
 777                 struct fw_ldst_addrval {
 778                         __be32 addr;
 779                         __be32 val;
 780                 } addrval;
 781                 struct fw_ldst_idctxt {
 782                         __be32 physid;
 783                         __be32 msg_ctxtflush;
 784                         __be32 ctxt_data7;
 785                         __be32 ctxt_data6;
 786                         __be32 ctxt_data5;
 787                         __be32 ctxt_data4;
 788                         __be32 ctxt_data3;
 789                         __be32 ctxt_data2;
 790                         __be32 ctxt_data1;
 791                         __be32 ctxt_data0;
 792                 } idctxt;
 793                 struct fw_ldst_mdio {
 794                         __be16 paddr_mmd;
 795                         __be16 raddr;
 796                         __be16 vctl;
 797                         __be16 rval;
 798                 } mdio;
 799                 struct fw_ldst_cim_rq {
 800                         u8 req_first64[8];
 801                         u8 req_second64[8];
 802                         u8 resp_first64[8];
 803                         u8 resp_second64[8];
 804                         __be32 r3[2];
 805                 } cim_rq;
 806                 union fw_ldst_mps {
 807                         struct fw_ldst_mps_rplc {
 808                                 __be16 fid_idx;
 809                                 __be16 rplcpf_pkd;
 810                                 __be32 rplc255_224;
 811                                 __be32 rplc223_192;
 812                                 __be32 rplc191_160;
 813                                 __be32 rplc159_128;
 814                                 __be32 rplc127_96;
 815                                 __be32 rplc95_64;
 816                                 __be32 rplc63_32;
 817                                 __be32 rplc31_0;
 818                         } rplc;
 819                         struct fw_ldst_mps_atrb {
 820                                 __be16 fid_mpsid;
 821                                 __be16 r2[3];
 822                                 __be32 r3[2];
 823                                 __be32 r4;
 824                                 __be32 atrb;
 825                                 __be16 vlan[16];
 826                         } atrb;
 827                 } mps;
 828                 struct fw_ldst_func {
 829                         u8 access_ctl;
 830                         u8 mod_index;
 831                         __be16 ctl_id;
 832                         __be32 offset;
 833                         __be64 data0;
 834                         __be64 data1;
 835                 } func;
 836                 struct fw_ldst_pcie {
 837                         u8 ctrl_to_fn;
 838                         u8 bnum;
 839                         u8 r;
 840                         u8 ext_r;
 841                         u8 select_naccess;
 842                         u8 pcie_fn;
 843                         __be16 nset_pkd;
 844                         __be32 data[12];
 845                 } pcie;
 846                 struct fw_ldst_i2c_deprecated {
 847                         u8 pid_pkd;
 848                         u8 base;
 849                         u8 boffset;
 850                         u8 data;
 851                         __be32 r9;
 852                 } i2c_deprecated;
 853                 struct fw_ldst_i2c {
 854                         u8 pid;
 855                         u8 did;
 856                         u8 boffset;
 857                         u8 blen;
 858                         __be32 r9;
 859                         __u8   data[48];
 860                 } i2c;
 861                 struct fw_ldst_le {
 862                         __be32 index;
 863                         __be32 r9;
 864                         u8 val[33];
 865                         u8 r11[7];
 866                 } le;
 867         } u;
 868 };
 869
 870 #define FW_LDST_CMD_ADDRSPACE_S         0
 871 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 872
 873 #define FW_LDST_CMD_MSG_S       31
 874 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 875
 876 #define FW_LDST_CMD_CTXTFLUSH_S         30
 877 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 878 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 879
 880 #define FW_LDST_CMD_PADDR_S     8
 881 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 882
 883 #define FW_LDST_CMD_MMD_S       0
 884 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 885
 886 #define FW_LDST_CMD_FID_S       15
 887 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 888
 889 #define FW_LDST_CMD_IDX_S       0
 890 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
 891
 892 #define FW_LDST_CMD_RPLCPF_S    0
 893 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 894
 895 #define FW_LDST_CMD_LC_S        4
 896 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 897 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 898
 899 #define FW_LDST_CMD_FN_S        0
 900 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 901
 902 #define FW_LDST_CMD_NACCESS_S           0
 903 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 904
 905 struct fw_reset_cmd {
 906         __be32 op_to_write;
 907         __be32 retval_len16;
 908         __be32 val;
 909         __be32 halt_pkd;
 910 };
 911
 912 #define FW_RESET_CMD_HALT_S     31
 913 #define FW_RESET_CMD_HALT_M     0x1
 914 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 915 #define FW_RESET_CMD_HALT_G(x)  \
 916         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 917 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 918
 919 enum fw_hellow_cmd {
 920         fw_hello_cmd_stage_os           = 0x0
 921 };
 922
 923 struct fw_hello_cmd {
 924         __be32 op_to_write;
 925         __be32 retval_len16;
 926         __be32 err_to_clearinit;
 927         __be32 fwrev;
 928 };
 929
 930 #define FW_HELLO_CMD_ERR_S      31
 931 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 932 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 933
 934 #define FW_HELLO_CMD_INIT_S     30
 935 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 936 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 937
 938 #define FW_HELLO_CMD_MASTERDIS_S        29
 939 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 940
 941 #define FW_HELLO_CMD_MASTERFORCE_S      28
 942 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 943
 944 #define FW_HELLO_CMD_MBMASTER_S         24
 945 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 946 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 947 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 948         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 949
 950 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 951 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 952
 953 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 954 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 955
 956 #define FW_HELLO_CMD_STAGE_S            17
 957 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 958
 959 #define FW_HELLO_CMD_CLEARINIT_S        16
 960 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 961 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 962
 963 struct fw_bye_cmd {
 964         __be32 op_to_write;
 965         __be32 retval_len16;
 966         __be64 r3;
 967 };
 968
 969 struct fw_initialize_cmd {
 970         __be32 op_to_write;
 971         __be32 retval_len16;
 972         __be64 r3;
 973 };
 974
 975 enum fw_caps_config_hm {
 976         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 977         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 978         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 979         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 980         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 981         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 982         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 983         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 984         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 985         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 986         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 987         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 988         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 989         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 990         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 991         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 992         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 993         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 994         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 995         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 996         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 997         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 998         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 999         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
1000 };
1001
1002 enum fw_caps_config_nbm {
1003         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1004         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1005 };
1006
1007 enum fw_caps_config_link {
1008         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1009         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1010         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1011 };
1012
1013 enum fw_caps_config_switch {
1014         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1015         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1016 };
1017
1018 enum fw_caps_config_nic {
1019         FW_CAPS_CONFIG_NIC              = 0x00000001,
1020         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1021 };
1022
1023 enum fw_caps_config_ofld {
1024         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1025 };
1026
1027 enum fw_caps_config_rdma {
1028         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1029         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1030 };
1031
1032 enum fw_caps_config_iscsi {
1033         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1034         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1035         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1036         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1037 };
1038
1039 enum fw_caps_config_fcoe {
1040         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1041         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1042         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1043 };
1044
1045 enum fw_memtype_cf {
1046         FW_MEMTYPE_CF_EDC0              = 0x0,
1047         FW_MEMTYPE_CF_EDC1              = 0x1,
1048         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1049         FW_MEMTYPE_CF_FLASH             = 0x4,
1050         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1051         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1052 };
1053
1054 struct fw_caps_config_cmd {
1055         __be32 op_to_write;
1056         __be32 cfvalid_to_len16;
1057         __be32 r2;
1058         __be32 hwmbitmap;
1059         __be16 nbmcaps;
1060         __be16 linkcaps;
1061         __be16 switchcaps;
1062         __be16 r3;
1063         __be16 niccaps;
1064         __be16 ofldcaps;
1065         __be16 rdmacaps;
1066         __be16 cryptocaps;
1067         __be16 iscsicaps;
1068         __be16 fcoecaps;
1069         __be32 cfcsum;
1070         __be32 finiver;
1071         __be32 finicsum;
1072 };
1073
1074 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1075 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1076 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1077
1078 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1079 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1080         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1081
1082 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1083 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1084         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1085
1086 /*
1087  * params command mnemonics
1088  */
1089 enum fw_params_mnem {
1090         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1091         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1092         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1093         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1094         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1095         FW_PARAMS_MNEM_LAST
1096 };
1097
1098 /*
1099  * device parameters
1100  */
1101 enum fw_params_param_dev {
1102         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1103         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1104         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1105                                                  * allocated by the device's
1106                                                  * Lookup Engine
1107                                                  */
1108         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1109         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1110         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1111         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1112         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1113         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1114         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1115         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1116         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1117         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1118         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1119         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1120         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1121         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1122         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1123         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1124         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1125         FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR  = 0x1C,
1126 };
1127
1128 /*
1129  * physical and virtual function parameters
1130  */
1131 enum fw_params_param_pfvf {
1132         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1133         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1134         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1135         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1136         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1137         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1138         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1139         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1140         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1141         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1142         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1143         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1144         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1145         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1146         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1147         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1148         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1149         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1150         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1151         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1152         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1153         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1154         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1155         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1156         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1157         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1158         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1159         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1160         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1161         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1162         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1163         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1164         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1165         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1166         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1167         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1168         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1169         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1170         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1171 };
1172
1173 /*
1174  * dma queue parameters
1175  */
1176 enum fw_params_param_dmaq {
1177         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1178         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1179         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1180         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1181         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1182         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1183         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1184 };
1185
1186 enum fw_params_param_dev_phyfw {
1187         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1188         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1189 };
1190
1191 enum fw_params_param_dev_diag {
1192         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1193         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1194 };
1195
1196 enum fw_params_param_dev_fwcache {
1197         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1198         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1199 };
1200
1201 #define FW_PARAMS_MNEM_S        24
1202 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1203
1204 #define FW_PARAMS_PARAM_X_S     16
1205 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1206
1207 #define FW_PARAMS_PARAM_Y_S     8
1208 #define FW_PARAMS_PARAM_Y_M     0xffU
1209 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1210 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1211                 FW_PARAMS_PARAM_Y_M)
1212
1213 #define FW_PARAMS_PARAM_Z_S     0
1214 #define FW_PARAMS_PARAM_Z_M     0xffu
1215 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1216 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1217                 FW_PARAMS_PARAM_Z_M)
1218
1219 #define FW_PARAMS_PARAM_XYZ_S           0
1220 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1221
1222 #define FW_PARAMS_PARAM_YZ_S            0
1223 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1224
1225 struct fw_params_cmd {
1226         __be32 op_to_vfn;
1227         __be32 retval_len16;
1228         struct fw_params_param {
1229                 __be32 mnem;
1230                 __be32 val;
1231         } param[7];
1232 };
1233
1234 #define FW_PARAMS_CMD_PFN_S     8
1235 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1236
1237 #define FW_PARAMS_CMD_VFN_S     0
1238 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1239
1240 struct fw_pfvf_cmd {
1241         __be32 op_to_vfn;
1242         __be32 retval_len16;
1243         __be32 niqflint_niq;
1244         __be32 type_to_neq;
1245         __be32 tc_to_nexactf;
1246         __be32 r_caps_to_nethctrl;
1247         __be16 nricq;
1248         __be16 nriqp;
1249         __be32 r4;
1250 };
1251
1252 #define FW_PFVF_CMD_PFN_S       8
1253 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1254
1255 #define FW_PFVF_CMD_VFN_S       0
1256 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1257
1258 #define FW_PFVF_CMD_NIQFLINT_S          20
1259 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1260 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1261 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1262         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1263
1264 #define FW_PFVF_CMD_NIQ_S       0
1265 #define FW_PFVF_CMD_NIQ_M       0xfffff
1266 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1267 #define FW_PFVF_CMD_NIQ_G(x)    \
1268         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1269
1270 #define FW_PFVF_CMD_TYPE_S      31
1271 #define FW_PFVF_CMD_TYPE_M      0x1
1272 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1273 #define FW_PFVF_CMD_TYPE_G(x)   \
1274         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1275 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1276
1277 #define FW_PFVF_CMD_CMASK_S     24
1278 #define FW_PFVF_CMD_CMASK_M     0xf
1279 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1280 #define FW_PFVF_CMD_CMASK_G(x)  \
1281         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1282
1283 #define FW_PFVF_CMD_PMASK_S     20
1284 #define FW_PFVF_CMD_PMASK_M     0xf
1285 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1286 #define FW_PFVF_CMD_PMASK_G(x) \
1287         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1288
1289 #define FW_PFVF_CMD_NEQ_S       0
1290 #define FW_PFVF_CMD_NEQ_M       0xfffff
1291 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1292 #define FW_PFVF_CMD_NEQ_G(x)    \
1293         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1294
1295 #define FW_PFVF_CMD_TC_S        24
1296 #define FW_PFVF_CMD_TC_M        0xff
1297 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1298 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1299
1300 #define FW_PFVF_CMD_NVI_S       16
1301 #define FW_PFVF_CMD_NVI_M       0xff
1302 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1303 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1304
1305 #define FW_PFVF_CMD_NEXACTF_S           0
1306 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1307 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1308 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1309         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1310
1311 #define FW_PFVF_CMD_R_CAPS_S    24
1312 #define FW_PFVF_CMD_R_CAPS_M    0xff
1313 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1314 #define FW_PFVF_CMD_R_CAPS_G(x) \
1315         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1316
1317 #define FW_PFVF_CMD_WX_CAPS_S           16
1318 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1319 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1320 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1321         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1322
1323 #define FW_PFVF_CMD_NETHCTRL_S          0
1324 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1325 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1326 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1327         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1328
1329 enum fw_iq_type {
1330         FW_IQ_TYPE_FL_INT_CAP,
1331         FW_IQ_TYPE_NO_FL_INT_CAP
1332 };
1333
1334 struct fw_iq_cmd {
1335         __be32 op_to_vfn;
1336         __be32 alloc_to_len16;
1337         __be16 physiqid;
1338         __be16 iqid;
1339         __be16 fl0id;
1340         __be16 fl1id;
1341         __be32 type_to_iqandstindex;
1342         __be16 iqdroprss_to_iqesize;
1343         __be16 iqsize;
1344         __be64 iqaddr;
1345         __be32 iqns_to_fl0congen;
1346         __be16 fl0dcaen_to_fl0cidxfthresh;
1347         __be16 fl0size;
1348         __be64 fl0addr;
1349         __be32 fl1cngchmap_to_fl1congen;
1350         __be16 fl1dcaen_to_fl1cidxfthresh;
1351         __be16 fl1size;
1352         __be64 fl1addr;
1353 };
1354
1355 #define FW_IQ_CMD_PFN_S         8
1356 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1357
1358 #define FW_IQ_CMD_VFN_S         0
1359 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1360
1361 #define FW_IQ_CMD_ALLOC_S       31
1362 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1363 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1364
1365 #define FW_IQ_CMD_FREE_S        30
1366 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1367 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1368
1369 #define FW_IQ_CMD_MODIFY_S      29
1370 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1371 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1372
1373 #define FW_IQ_CMD_IQSTART_S     28
1374 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1375 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1376
1377 #define FW_IQ_CMD_IQSTOP_S      27
1378 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1379 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1380
1381 #define FW_IQ_CMD_TYPE_S        29
1382 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1383
1384 #define FW_IQ_CMD_IQASYNCH_S    28
1385 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1386
1387 #define FW_IQ_CMD_VIID_S        16
1388 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1389
1390 #define FW_IQ_CMD_IQANDST_S     15
1391 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1392
1393 #define FW_IQ_CMD_IQANUS_S      14
1394 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1395
1396 #define FW_IQ_CMD_IQANUD_S      12
1397 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1398
1399 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1400 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1401
1402 #define FW_IQ_CMD_IQDROPRSS_S           15
1403 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1404 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1405
1406 #define FW_IQ_CMD_IQGTSMODE_S           14
1407 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1408 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1409
1410 #define FW_IQ_CMD_IQPCIECH_S    12
1411 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1412
1413 #define FW_IQ_CMD_IQDCAEN_S     11
1414 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1415
1416 #define FW_IQ_CMD_IQDCACPU_S    6
1417 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1418
1419 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1420 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1421
1422 #define FW_IQ_CMD_IQO_S         3
1423 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1424 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1425
1426 #define FW_IQ_CMD_IQCPRIO_S     2
1427 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1428
1429 #define FW_IQ_CMD_IQESIZE_S     0
1430 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1431
1432 #define FW_IQ_CMD_IQNS_S        31
1433 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1434
1435 #define FW_IQ_CMD_IQRO_S        30
1436 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1437
1438 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1439 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1440
1441 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1442 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1443 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1444
1445 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1446 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1447
1448 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1449 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1450
1451 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1452 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1453
1454 #define FW_IQ_CMD_FL0DBP_S      14
1455 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1456
1457 #define FW_IQ_CMD_FL0DATANS_S           13
1458 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1459
1460 #define FW_IQ_CMD_FL0DATARO_S           12
1461 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1462 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1463
1464 #define FW_IQ_CMD_FL0CONGCIF_S          11
1465 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1466 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1467
1468 #define FW_IQ_CMD_FL0ONCHIP_S           10
1469 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1470
1471 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1472 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1473
1474 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1475 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1476
1477 #define FW_IQ_CMD_FL0FETCHNS_S          7
1478 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1479
1480 #define FW_IQ_CMD_FL0FETCHRO_S          6
1481 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1482 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1483
1484 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1485 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1486
1487 #define FW_IQ_CMD_FL0CPRIO_S    3
1488 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1489
1490 #define FW_IQ_CMD_FL0PADEN_S    2
1491 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1492 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1493
1494 #define FW_IQ_CMD_FL0PACKEN_S           1
1495 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1496 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1497
1498 #define FW_IQ_CMD_FL0CONGEN_S           0
1499 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1500 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1501
1502 #define FW_IQ_CMD_FL0DCAEN_S    15
1503 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1504
1505 #define FW_IQ_CMD_FL0DCACPU_S           10
1506 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1507
1508 #define FW_IQ_CMD_FL0FBMIN_S    7
1509 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1510
1511 #define FW_IQ_CMD_FL0FBMAX_S    4
1512 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1513
1514 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1515 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1516 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1517
1518 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1519 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1520
1521 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1522 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1523
1524 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1525 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1526
1527 #define FW_IQ_CMD_FL1DBP_S      14
1528 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1529
1530 #define FW_IQ_CMD_FL1DATANS_S           13
1531 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1532
1533 #define FW_IQ_CMD_FL1DATARO_S           12
1534 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1535
1536 #define FW_IQ_CMD_FL1CONGCIF_S          11
1537 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1538
1539 #define FW_IQ_CMD_FL1ONCHIP_S           10
1540 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1541
1542 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1543 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1544
1545 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1546 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1547
1548 #define FW_IQ_CMD_FL1FETCHNS_S          7
1549 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1550
1551 #define FW_IQ_CMD_FL1FETCHRO_S          6
1552 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1553
1554 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1555 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1556
1557 #define FW_IQ_CMD_FL1CPRIO_S    3
1558 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1559
1560 #define FW_IQ_CMD_FL1PADEN_S    2
1561 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1562 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1563
1564 #define FW_IQ_CMD_FL1PACKEN_S           1
1565 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1566 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1567
1568 #define FW_IQ_CMD_FL1CONGEN_S           0
1569 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1570 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1571
1572 #define FW_IQ_CMD_FL1DCAEN_S    15
1573 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1574
1575 #define FW_IQ_CMD_FL1DCACPU_S           10
1576 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1577
1578 #define FW_IQ_CMD_FL1FBMIN_S    7
1579 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1580
1581 #define FW_IQ_CMD_FL1FBMAX_S    4
1582 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1583
1584 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1585 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1586 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1587
1588 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1589 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1590
1591 struct fw_eq_eth_cmd {
1592         __be32 op_to_vfn;
1593         __be32 alloc_to_len16;
1594         __be32 eqid_pkd;
1595         __be32 physeqid_pkd;
1596         __be32 fetchszm_to_iqid;
1597         __be32 dcaen_to_eqsize;
1598         __be64 eqaddr;
1599         __be32 viid_pkd;
1600         __be32 r8_lo;
1601         __be64 r9;
1602 };
1603
1604 #define FW_EQ_ETH_CMD_PFN_S     8
1605 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1606
1607 #define FW_EQ_ETH_CMD_VFN_S     0
1608 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1609
1610 #define FW_EQ_ETH_CMD_ALLOC_S           31
1611 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1612 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1613
1614 #define FW_EQ_ETH_CMD_FREE_S    30
1615 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1616 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1617
1618 #define FW_EQ_ETH_CMD_MODIFY_S          29
1619 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1620 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1621
1622 #define FW_EQ_ETH_CMD_EQSTART_S         28
1623 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1624 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1625
1626 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1627 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1628 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1629
1630 #define FW_EQ_ETH_CMD_EQID_S    0
1631 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1632 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1633 #define FW_EQ_ETH_CMD_EQID_G(x) \
1634         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1635
1636 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1637 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1638 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1639 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1640         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1641
1642 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1643 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1644 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1645
1646 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1647 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1648
1649 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1650 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1651
1652 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1653 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1654
1655 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1656 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1657 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1658
1659 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1660 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1661
1662 #define FW_EQ_ETH_CMD_CPRIO_S           19
1663 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1664
1665 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1666 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1667
1668 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1669 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1670
1671 #define FW_EQ_ETH_CMD_IQID_S    0
1672 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1673
1674 #define FW_EQ_ETH_CMD_DCAEN_S           31
1675 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1676
1677 #define FW_EQ_ETH_CMD_DCACPU_S          26
1678 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1679
1680 #define FW_EQ_ETH_CMD_FBMIN_S           23
1681 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1682
1683 #define FW_EQ_ETH_CMD_FBMAX_S           20
1684 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1685
1686 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1687 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1688
1689 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1690 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1691
1692 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1693 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1694
1695 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1696 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1697 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1698
1699 #define FW_EQ_ETH_CMD_VIID_S    16
1700 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1701
1702 struct fw_eq_ctrl_cmd {
1703         __be32 op_to_vfn;
1704         __be32 alloc_to_len16;
1705         __be32 cmpliqid_eqid;
1706         __be32 physeqid_pkd;
1707         __be32 fetchszm_to_iqid;
1708         __be32 dcaen_to_eqsize;
1709         __be64 eqaddr;
1710 };
1711
1712 #define FW_EQ_CTRL_CMD_PFN_S    8
1713 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1714
1715 #define FW_EQ_CTRL_CMD_VFN_S    0
1716 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1717
1718 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1719 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1720 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1721
1722 #define FW_EQ_CTRL_CMD_FREE_S           30
1723 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1724 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1725
1726 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1727 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1728 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1729
1730 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1731 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1732 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1733
1734 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1735 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1736 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1737
1738 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1739 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1740
1741 #define FW_EQ_CTRL_CMD_EQID_S           0
1742 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1743 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1744 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1745         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1746
1747 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1748 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1749 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1750         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1751
1752 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1753 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1754 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1755
1756 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1757 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1758 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1759
1760 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1761 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1762 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1763
1764 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1765 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1766 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1767
1768 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1769 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1770 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1771
1772 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1773 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1774
1775 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1776 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1777
1778 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1779 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1780
1781 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1782 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1783
1784 #define FW_EQ_CTRL_CMD_IQID_S           0
1785 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1786
1787 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1788 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1789
1790 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1791 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1792
1793 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1794 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1795
1796 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1797 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1798
1799 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1800 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1801         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1802
1803 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1804 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1805
1806 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1807 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1808
1809 struct fw_eq_ofld_cmd {
1810         __be32 op_to_vfn;
1811         __be32 alloc_to_len16;
1812         __be32 eqid_pkd;
1813         __be32 physeqid_pkd;
1814         __be32 fetchszm_to_iqid;
1815         __be32 dcaen_to_eqsize;
1816         __be64 eqaddr;
1817 };
1818
1819 #define FW_EQ_OFLD_CMD_PFN_S    8
1820 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1821
1822 #define FW_EQ_OFLD_CMD_VFN_S    0
1823 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1824
1825 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1826 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1827 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1828
1829 #define FW_EQ_OFLD_CMD_FREE_S           30
1830 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1831 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1832
1833 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1834 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1835 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1836
1837 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1838 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1839 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1840
1841 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1842 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1843 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1844
1845 #define FW_EQ_OFLD_CMD_EQID_S           0
1846 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1847 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1848 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1849         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1850
1851 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1852 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1853 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1854         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1855
1856 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1857 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1858
1859 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1860 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1861
1862 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1863 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1864
1865 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1866 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1867
1868 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1869 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1870 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1871
1872 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1873 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1874
1875 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1876 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1877
1878 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1879 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1880
1881 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1882 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1883
1884 #define FW_EQ_OFLD_CMD_IQID_S           0
1885 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1886
1887 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1888 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1889
1890 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1891 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1892
1893 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1894 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1895
1896 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1897 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1898
1899 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1900 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1901         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1902
1903 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1904 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1905
1906 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1907 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1908
1909 /*
1910  * Macros for VIID parsing:
1911  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1912  */
1913
1914 #define FW_VIID_PFN_S           8
1915 #define FW_VIID_PFN_M           0x7
1916 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1917
1918 #define FW_VIID_VIVLD_S         7
1919 #define FW_VIID_VIVLD_M         0x1
1920 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1921
1922 #define FW_VIID_VIN_S           0
1923 #define FW_VIID_VIN_M           0x7F
1924 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1925
1926 struct fw_vi_cmd {
1927         __be32 op_to_vfn;
1928         __be32 alloc_to_len16;
1929         __be16 type_viid;
1930         u8 mac[6];
1931         u8 portid_pkd;
1932         u8 nmac;
1933         u8 nmac0[6];
1934         __be16 rsssize_pkd;
1935         u8 nmac1[6];
1936         __be16 idsiiq_pkd;
1937         u8 nmac2[6];
1938         __be16 idseiq_pkd;
1939         u8 nmac3[6];
1940         __be64 r9;
1941         __be64 r10;
1942 };
1943
1944 #define FW_VI_CMD_PFN_S         8
1945 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1946
1947 #define FW_VI_CMD_VFN_S         0
1948 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1949
1950 #define FW_VI_CMD_ALLOC_S       31
1951 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1952 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1953
1954 #define FW_VI_CMD_FREE_S        30
1955 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1956 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1957
1958 #define FW_VI_CMD_VIID_S        0
1959 #define FW_VI_CMD_VIID_M        0xfff
1960 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1961 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1962
1963 #define FW_VI_CMD_PORTID_S      4
1964 #define FW_VI_CMD_PORTID_M      0xf
1965 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1966 #define FW_VI_CMD_PORTID_G(x)   \
1967         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1968
1969 #define FW_VI_CMD_RSSSIZE_S     0
1970 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1971 #define FW_VI_CMD_RSSSIZE_G(x)  \
1972         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1973
1974 /* Special VI_MAC command index ids */
1975 #define FW_VI_MAC_ADD_MAC               0x3FF
1976 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1977 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1978 #define FW_CLS_TCAM_NUM_ENTRIES         336
1979
1980 enum fw_vi_mac_smac {
1981         FW_VI_MAC_MPS_TCAM_ENTRY,
1982         FW_VI_MAC_MPS_TCAM_ONLY,
1983         FW_VI_MAC_SMT_ONLY,
1984         FW_VI_MAC_SMT_AND_MPSTCAM
1985 };
1986
1987 enum fw_vi_mac_result {
1988         FW_VI_MAC_R_SUCCESS,
1989         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1990         FW_VI_MAC_R_SMAC_FAIL,
1991         FW_VI_MAC_R_F_ACL_CHECK
1992 };
1993
1994 struct fw_vi_mac_cmd {
1995         __be32 op_to_viid;
1996         __be32 freemacs_to_len16;
1997         union fw_vi_mac {
1998                 struct fw_vi_mac_exact {
1999                         __be16 valid_to_idx;
2000                         u8 macaddr[6];
2001                 } exact[7];
2002                 struct fw_vi_mac_hash {
2003                         __be64 hashvec;
2004                 } hash;
2005         } u;
2006 };
2007
2008 #define FW_VI_MAC_CMD_VIID_S    0
2009 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2010
2011 #define FW_VI_MAC_CMD_FREEMACS_S        31
2012 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2013
2014 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2015 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2016 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2017
2018 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2019 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2020
2021 #define FW_VI_MAC_CMD_VALID_S           15
2022 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2023 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2024
2025 #define FW_VI_MAC_CMD_PRIO_S    12
2026 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2027
2028 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2029 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2030 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2031 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2032         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2033
2034 #define FW_VI_MAC_CMD_IDX_S     0
2035 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2036 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2037 #define FW_VI_MAC_CMD_IDX_G(x)  \
2038         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2039
2040 #define FW_RXMODE_MTU_NO_CHG    65535
2041
2042 struct fw_vi_rxmode_cmd {
2043         __be32 op_to_viid;
2044         __be32 retval_len16;
2045         __be32 mtu_to_vlanexen;
2046         __be32 r4_lo;
2047 };
2048
2049 #define FW_VI_RXMODE_CMD_VIID_S         0
2050 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2051
2052 #define FW_VI_RXMODE_CMD_MTU_S          16
2053 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2054 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2055
2056 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2057 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2058 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2059
2060 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2061 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2062 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2063         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2064
2065 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2066 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2067 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2068         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2069
2070 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2071 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2072 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2073
2074 struct fw_vi_enable_cmd {
2075         __be32 op_to_viid;
2076         __be32 ien_to_len16;
2077         __be16 blinkdur;
2078         __be16 r3;
2079         __be32 r4;
2080 };
2081
2082 #define FW_VI_ENABLE_CMD_VIID_S         0
2083 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2084
2085 #define FW_VI_ENABLE_CMD_IEN_S          31
2086 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2087
2088 #define FW_VI_ENABLE_CMD_EEN_S          30
2089 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2090
2091 #define FW_VI_ENABLE_CMD_LED_S          29
2092 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2093 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2094
2095 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2096 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2097
2098 /* VI VF stats offset definitions */
2099 #define VI_VF_NUM_STATS 16
2100 enum fw_vi_stats_vf_index {
2101         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2102         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2103         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2104         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2105         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2106         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2107         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2108         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2109         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2110         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2111         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2112         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2113         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2114         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2115         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2116         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2117 };
2118
2119 /* VI PF stats offset definitions */
2120 #define VI_PF_NUM_STATS 17
2121 enum fw_vi_stats_pf_index {
2122         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2123         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2124         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2125         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2126         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2127         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2128         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2129         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2130         FW_VI_PF_STAT_RX_BYTES_IX,
2131         FW_VI_PF_STAT_RX_FRAMES_IX,
2132         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2133         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2134         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2135         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2136         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2137         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2138         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2139 };
2140
2141 struct fw_vi_stats_cmd {
2142         __be32 op_to_viid;
2143         __be32 retval_len16;
2144         union fw_vi_stats {
2145                 struct fw_vi_stats_ctl {
2146                         __be16 nstats_ix;
2147                         __be16 r6;
2148                         __be32 r7;
2149                         __be64 stat0;
2150                         __be64 stat1;
2151                         __be64 stat2;
2152                         __be64 stat3;
2153                         __be64 stat4;
2154                         __be64 stat5;
2155                 } ctl;
2156                 struct fw_vi_stats_pf {
2157                         __be64 tx_bcast_bytes;
2158                         __be64 tx_bcast_frames;
2159                         __be64 tx_mcast_bytes;
2160                         __be64 tx_mcast_frames;
2161                         __be64 tx_ucast_bytes;
2162                         __be64 tx_ucast_frames;
2163                         __be64 tx_offload_bytes;
2164                         __be64 tx_offload_frames;
2165                         __be64 rx_pf_bytes;
2166                         __be64 rx_pf_frames;
2167                         __be64 rx_bcast_bytes;
2168                         __be64 rx_bcast_frames;
2169                         __be64 rx_mcast_bytes;
2170                         __be64 rx_mcast_frames;
2171                         __be64 rx_ucast_bytes;
2172                         __be64 rx_ucast_frames;
2173                         __be64 rx_err_frames;
2174                 } pf;
2175                 struct fw_vi_stats_vf {
2176                         __be64 tx_bcast_bytes;
2177                         __be64 tx_bcast_frames;
2178                         __be64 tx_mcast_bytes;
2179                         __be64 tx_mcast_frames;
2180                         __be64 tx_ucast_bytes;
2181                         __be64 tx_ucast_frames;
2182                         __be64 tx_drop_frames;
2183                         __be64 tx_offload_bytes;
2184                         __be64 tx_offload_frames;
2185                         __be64 rx_bcast_bytes;
2186                         __be64 rx_bcast_frames;
2187                         __be64 rx_mcast_bytes;
2188                         __be64 rx_mcast_frames;
2189                         __be64 rx_ucast_bytes;
2190                         __be64 rx_ucast_frames;
2191                         __be64 rx_err_frames;
2192                 } vf;
2193         } u;
2194 };
2195
2196 #define FW_VI_STATS_CMD_VIID_S          0
2197 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2198
2199 #define FW_VI_STATS_CMD_NSTATS_S        12
2200 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2201
2202 #define FW_VI_STATS_CMD_IX_S    0
2203 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2204
2205 struct fw_acl_mac_cmd {
2206         __be32 op_to_vfn;
2207         __be32 en_to_len16;
2208         u8 nmac;
2209         u8 r3[7];
2210         __be16 r4;
2211         u8 macaddr0[6];
2212         __be16 r5;
2213         u8 macaddr1[6];
2214         __be16 r6;
2215         u8 macaddr2[6];
2216         __be16 r7;
2217         u8 macaddr3[6];
2218 };
2219
2220 #define FW_ACL_MAC_CMD_PFN_S    8
2221 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2222
2223 #define FW_ACL_MAC_CMD_VFN_S    0
2224 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2225
2226 #define FW_ACL_MAC_CMD_EN_S     31
2227 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2228
2229 struct fw_acl_vlan_cmd {
2230         __be32 op_to_vfn;
2231         __be32 en_to_len16;
2232         u8 nvlan;
2233         u8 dropnovlan_fm;
2234         u8 r3_lo[6];
2235         __be16 vlanid[16];
2236 };
2237
2238 #define FW_ACL_VLAN_CMD_PFN_S           8
2239 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2240
2241 #define FW_ACL_VLAN_CMD_VFN_S           0
2242 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2243
2244 #define FW_ACL_VLAN_CMD_EN_S    31
2245 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2246
2247 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2248 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2249
2250 #define FW_ACL_VLAN_CMD_FM_S    6
2251 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2252
2253 enum fw_port_cap {
2254         FW_PORT_CAP_SPEED_100M          = 0x0001,
2255         FW_PORT_CAP_SPEED_1G            = 0x0002,
2256         FW_PORT_CAP_SPEED_25G           = 0x0004,
2257         FW_PORT_CAP_SPEED_10G           = 0x0008,
2258         FW_PORT_CAP_SPEED_40G           = 0x0010,
2259         FW_PORT_CAP_SPEED_100G          = 0x0020,
2260         FW_PORT_CAP_FC_RX               = 0x0040,
2261         FW_PORT_CAP_FC_TX               = 0x0080,
2262         FW_PORT_CAP_ANEG                = 0x0100,
2263         FW_PORT_CAP_MDIX                = 0x0200,
2264         FW_PORT_CAP_MDIAUTO             = 0x0400,
2265         FW_PORT_CAP_FEC                 = 0x0800,
2266         FW_PORT_CAP_TECHKR              = 0x1000,
2267         FW_PORT_CAP_TECHKX4             = 0x2000,
2268         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2269         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2270 };
2271
2272 #define FW_PORT_CAP_SPEED_S     0
2273 #define FW_PORT_CAP_SPEED_M     0x3f
2274 #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2275 #define FW_PORT_CAP_SPEED_G(x) \
2276         (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2277
2278 enum fw_port_mdi {
2279         FW_PORT_CAP_MDI_UNCHANGED,
2280         FW_PORT_CAP_MDI_AUTO,
2281         FW_PORT_CAP_MDI_F_STRAIGHT,
2282         FW_PORT_CAP_MDI_F_CROSSOVER
2283 };
2284
2285 #define FW_PORT_CAP_MDI_S 9
2286 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2287
2288 enum fw_port_action {
2289         FW_PORT_ACTION_L1_CFG           = 0x0001,
2290         FW_PORT_ACTION_L2_CFG           = 0x0002,
2291         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2292         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2293         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2294         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2295         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2296         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2297         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2298         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2299         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2300         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2301         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2302         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2303         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2304         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2305         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2306         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2307         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2308         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2309         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2310         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2311         FW_PORT_ACTION_AN_RESET         = 0x0045
2312 };
2313
2314 enum fw_port_l2cfg_ctlbf {
2315         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2316         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2317         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2318         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2319         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2320         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2321 };
2322
2323 enum fw_port_dcb_versions {
2324         FW_PORT_DCB_VER_UNKNOWN,
2325         FW_PORT_DCB_VER_CEE1D0,
2326         FW_PORT_DCB_VER_CEE1D01,
2327         FW_PORT_DCB_VER_IEEE,
2328         FW_PORT_DCB_VER_AUTO = 7
2329 };
2330
2331 enum fw_port_dcb_cfg {
2332         FW_PORT_DCB_CFG_PG      = 0x01,
2333         FW_PORT_DCB_CFG_PFC     = 0x02,
2334         FW_PORT_DCB_CFG_APPL    = 0x04
2335 };
2336
2337 enum fw_port_dcb_cfg_rc {
2338         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2339         FW_PORT_DCB_CFG_ERROR   = 0x1
2340 };
2341
2342 enum fw_port_dcb_type {
2343         FW_PORT_DCB_TYPE_PGID           = 0x00,
2344         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2345         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2346         FW_PORT_DCB_TYPE_PFC            = 0x03,
2347         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2348         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2349 };
2350
2351 enum fw_port_dcb_feature_state {
2352         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2353         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2354         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2355         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2356 };
2357
2358 struct fw_port_cmd {
2359         __be32 op_to_portid;
2360         __be32 action_to_len16;
2361         union fw_port {
2362                 struct fw_port_l1cfg {
2363                         __be32 rcap;
2364                         __be32 r;
2365                 } l1cfg;
2366                 struct fw_port_l2cfg {
2367                         __u8   ctlbf;
2368                         __u8   ovlan3_to_ivlan0;
2369                         __be16 ivlantype;
2370                         __be16 txipg_force_pinfo;
2371                         __be16 mtu;
2372                         __be16 ovlan0mask;
2373                         __be16 ovlan0type;
2374                         __be16 ovlan1mask;
2375                         __be16 ovlan1type;
2376                         __be16 ovlan2mask;
2377                         __be16 ovlan2type;
2378                         __be16 ovlan3mask;
2379                         __be16 ovlan3type;
2380                 } l2cfg;
2381                 struct fw_port_info {
2382                         __be32 lstatus_to_modtype;
2383                         __be16 pcap;
2384                         __be16 acap;
2385                         __be16 mtu;
2386                         __u8   cbllen;
2387                         __u8   auxlinfo;
2388                         __u8   dcbxdis_pkd;
2389                         __u8   r8_lo;
2390                         __be16 lpacap;
2391                         __be64 r9;
2392                 } info;
2393                 struct fw_port_diags {
2394                         __u8   diagop;
2395                         __u8   r[3];
2396                         __be32 diagval;
2397                 } diags;
2398                 union fw_port_dcb {
2399                         struct fw_port_dcb_pgid {
2400                                 __u8   type;
2401                                 __u8   apply_pkd;
2402                                 __u8   r10_lo[2];
2403                                 __be32 pgid;
2404                                 __be64 r11;
2405                         } pgid;
2406                         struct fw_port_dcb_pgrate {
2407                                 __u8   type;
2408                                 __u8   apply_pkd;
2409                                 __u8   r10_lo[5];
2410                                 __u8   num_tcs_supported;
2411                                 __u8   pgrate[8];
2412                                 __u8   tsa[8];
2413                         } pgrate;
2414                         struct fw_port_dcb_priorate {
2415                                 __u8   type;
2416                                 __u8   apply_pkd;
2417                                 __u8   r10_lo[6];
2418                                 __u8   strict_priorate[8];
2419                         } priorate;
2420                         struct fw_port_dcb_pfc {
2421                                 __u8   type;
2422                                 __u8   pfcen;
2423                                 __u8   r10[5];
2424                                 __u8   max_pfc_tcs;
2425                                 __be64 r11;
2426                         } pfc;
2427                         struct fw_port_app_priority {
2428                                 __u8   type;
2429                                 __u8   r10[2];
2430                                 __u8   idx;
2431                                 __u8   user_prio_map;
2432                                 __u8   sel_field;
2433                                 __be16 protocolid;
2434                                 __be64 r12;
2435                         } app_priority;
2436                         struct fw_port_dcb_control {
2437                                 __u8   type;
2438                                 __u8   all_syncd_pkd;
2439                                 __be16 dcb_version_to_app_state;
2440                                 __be32 r11;
2441                                 __be64 r12;
2442                         } control;
2443                 } dcb;
2444         } u;
2445 };
2446
2447 #define FW_PORT_CMD_READ_S      22
2448 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2449 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2450
2451 #define FW_PORT_CMD_PORTID_S    0
2452 #define FW_PORT_CMD_PORTID_M    0xf
2453 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2454 #define FW_PORT_CMD_PORTID_G(x) \
2455         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2456
2457 #define FW_PORT_CMD_ACTION_S    16
2458 #define FW_PORT_CMD_ACTION_M    0xffff
2459 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2460 #define FW_PORT_CMD_ACTION_G(x) \
2461         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2462
2463 #define FW_PORT_CMD_OVLAN3_S    7
2464 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2465
2466 #define FW_PORT_CMD_OVLAN2_S    6
2467 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2468
2469 #define FW_PORT_CMD_OVLAN1_S    5
2470 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2471
2472 #define FW_PORT_CMD_OVLAN0_S    4
2473 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2474
2475 #define FW_PORT_CMD_IVLAN0_S    3
2476 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2477
2478 #define FW_PORT_CMD_TXIPG_S     3
2479 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2480
2481 #define FW_PORT_CMD_LSTATUS_S           31
2482 #define FW_PORT_CMD_LSTATUS_M           0x1
2483 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2484 #define FW_PORT_CMD_LSTATUS_G(x)        \
2485         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2486 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2487
2488 #define FW_PORT_CMD_LSPEED_S    24
2489 #define FW_PORT_CMD_LSPEED_M    0x3f
2490 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2491 #define FW_PORT_CMD_LSPEED_G(x) \
2492         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2493
2494 #define FW_PORT_CMD_TXPAUSE_S           23
2495 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2496 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2497
2498 #define FW_PORT_CMD_RXPAUSE_S           22
2499 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2500 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2501
2502 #define FW_PORT_CMD_MDIOCAP_S           21
2503 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2504 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2505
2506 #define FW_PORT_CMD_MDIOADDR_S          16
2507 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2508 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2509         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2510
2511 #define FW_PORT_CMD_LPTXPAUSE_S         15
2512 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2513 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2514
2515 #define FW_PORT_CMD_LPRXPAUSE_S         14
2516 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2517 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2518
2519 #define FW_PORT_CMD_PTYPE_S     8
2520 #define FW_PORT_CMD_PTYPE_M     0x1f
2521 #define FW_PORT_CMD_PTYPE_G(x)  \
2522         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2523
2524 #define FW_PORT_CMD_LINKDNRC_S          5
2525 #define FW_PORT_CMD_LINKDNRC_M          0x7
2526 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2527         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2528
2529 #define FW_PORT_CMD_MODTYPE_S           0
2530 #define FW_PORT_CMD_MODTYPE_M           0x1f
2531 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2532 #define FW_PORT_CMD_MODTYPE_G(x)        \
2533         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2534
2535 #define FW_PORT_CMD_DCBXDIS_S           7
2536 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2537 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2538
2539 #define FW_PORT_CMD_APPLY_S     7
2540 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2541 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2542
2543 #define FW_PORT_CMD_ALL_SYNCD_S         7
2544 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2545 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2546
2547 #define FW_PORT_CMD_DCB_VERSION_S       12
2548 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2549 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2550         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2551
2552 enum fw_port_type {
2553         FW_PORT_TYPE_FIBER_XFI,
2554         FW_PORT_TYPE_FIBER_XAUI,
2555         FW_PORT_TYPE_BT_SGMII,
2556         FW_PORT_TYPE_BT_XFI,
2557         FW_PORT_TYPE_BT_XAUI,
2558         FW_PORT_TYPE_KX4,
2559         FW_PORT_TYPE_CX4,
2560         FW_PORT_TYPE_KX,
2561         FW_PORT_TYPE_KR,
2562         FW_PORT_TYPE_SFP,
2563         FW_PORT_TYPE_BP_AP,
2564         FW_PORT_TYPE_BP4_AP,
2565         FW_PORT_TYPE_QSFP_10G,
2566         FW_PORT_TYPE_QSA,
2567         FW_PORT_TYPE_QSFP,
2568         FW_PORT_TYPE_BP40_BA,
2569         FW_PORT_TYPE_KR4_100G,
2570         FW_PORT_TYPE_CR4_QSFP,
2571         FW_PORT_TYPE_CR_QSFP,
2572         FW_PORT_TYPE_CR2_QSFP,
2573         FW_PORT_TYPE_SFP28,
2574
2575         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2576 };
2577
2578 enum fw_port_module_type {
2579         FW_PORT_MOD_TYPE_NA,
2580         FW_PORT_MOD_TYPE_LR,
2581         FW_PORT_MOD_TYPE_SR,
2582         FW_PORT_MOD_TYPE_ER,
2583         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2584         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2585         FW_PORT_MOD_TYPE_LRM,
2586         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2587         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2588         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2589
2590         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2591 };
2592
2593 enum fw_port_mod_sub_type {
2594         FW_PORT_MOD_SUB_TYPE_NA,
2595         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2596         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2597         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2598         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2599         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2600         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2601
2602         /* The following will never been in the VPD.  They are TWINAX cable
2603          * lengths decoded from SFP+ module i2c PROMs.  These should
2604          * almost certainly go somewhere else ...
2605          */
2606         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2607         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2608         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2609         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2610 };
2611
2612 enum fw_port_stats_tx_index {
2613         FW_STAT_TX_PORT_BYTES_IX = 0,
2614         FW_STAT_TX_PORT_FRAMES_IX,
2615         FW_STAT_TX_PORT_BCAST_IX,
2616         FW_STAT_TX_PORT_MCAST_IX,
2617         FW_STAT_TX_PORT_UCAST_IX,
2618         FW_STAT_TX_PORT_ERROR_IX,
2619         FW_STAT_TX_PORT_64B_IX,
2620         FW_STAT_TX_PORT_65B_127B_IX,
2621         FW_STAT_TX_PORT_128B_255B_IX,
2622         FW_STAT_TX_PORT_256B_511B_IX,
2623         FW_STAT_TX_PORT_512B_1023B_IX,
2624         FW_STAT_TX_PORT_1024B_1518B_IX,
2625         FW_STAT_TX_PORT_1519B_MAX_IX,
2626         FW_STAT_TX_PORT_DROP_IX,
2627         FW_STAT_TX_PORT_PAUSE_IX,
2628         FW_STAT_TX_PORT_PPP0_IX,
2629         FW_STAT_TX_PORT_PPP1_IX,
2630         FW_STAT_TX_PORT_PPP2_IX,
2631         FW_STAT_TX_PORT_PPP3_IX,
2632         FW_STAT_TX_PORT_PPP4_IX,
2633         FW_STAT_TX_PORT_PPP5_IX,
2634         FW_STAT_TX_PORT_PPP6_IX,
2635         FW_STAT_TX_PORT_PPP7_IX,
2636         FW_NUM_PORT_TX_STATS
2637 };
2638
2639 enum fw_port_stat_rx_index {
2640         FW_STAT_RX_PORT_BYTES_IX = 0,
2641         FW_STAT_RX_PORT_FRAMES_IX,
2642         FW_STAT_RX_PORT_BCAST_IX,
2643         FW_STAT_RX_PORT_MCAST_IX,
2644         FW_STAT_RX_PORT_UCAST_IX,
2645         FW_STAT_RX_PORT_MTU_ERROR_IX,
2646         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2647         FW_STAT_RX_PORT_CRC_ERROR_IX,
2648         FW_STAT_RX_PORT_LEN_ERROR_IX,
2649         FW_STAT_RX_PORT_SYM_ERROR_IX,
2650         FW_STAT_RX_PORT_64B_IX,
2651         FW_STAT_RX_PORT_65B_127B_IX,
2652         FW_STAT_RX_PORT_128B_255B_IX,
2653         FW_STAT_RX_PORT_256B_511B_IX,
2654         FW_STAT_RX_PORT_512B_1023B_IX,
2655         FW_STAT_RX_PORT_1024B_1518B_IX,
2656         FW_STAT_RX_PORT_1519B_MAX_IX,
2657         FW_STAT_RX_PORT_PAUSE_IX,
2658         FW_STAT_RX_PORT_PPP0_IX,
2659         FW_STAT_RX_PORT_PPP1_IX,
2660         FW_STAT_RX_PORT_PPP2_IX,
2661         FW_STAT_RX_PORT_PPP3_IX,
2662         FW_STAT_RX_PORT_PPP4_IX,
2663         FW_STAT_RX_PORT_PPP5_IX,
2664         FW_STAT_RX_PORT_PPP6_IX,
2665         FW_STAT_RX_PORT_PPP7_IX,
2666         FW_STAT_RX_PORT_LESS_64B_IX,
2667         FW_STAT_RX_PORT_MAC_ERROR_IX,
2668         FW_NUM_PORT_RX_STATS
2669 };
2670
2671 /* port stats */
2672 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2673
2674 struct fw_port_stats_cmd {
2675         __be32 op_to_portid;
2676         __be32 retval_len16;
2677         union fw_port_stats {
2678                 struct fw_port_stats_ctl {
2679                         u8 nstats_bg_bm;
2680                         u8 tx_ix;
2681                         __be16 r6;
2682                         __be32 r7;
2683                         __be64 stat0;
2684                         __be64 stat1;
2685                         __be64 stat2;
2686                         __be64 stat3;
2687                         __be64 stat4;
2688                         __be64 stat5;
2689                 } ctl;
2690                 struct fw_port_stats_all {
2691                         __be64 tx_bytes;
2692                         __be64 tx_frames;
2693                         __be64 tx_bcast;
2694                         __be64 tx_mcast;
2695                         __be64 tx_ucast;
2696                         __be64 tx_error;
2697                         __be64 tx_64b;
2698                         __be64 tx_65b_127b;
2699                         __be64 tx_128b_255b;
2700                         __be64 tx_256b_511b;
2701                         __be64 tx_512b_1023b;
2702                         __be64 tx_1024b_1518b;
2703                         __be64 tx_1519b_max;
2704                         __be64 tx_drop;
2705                         __be64 tx_pause;
2706                         __be64 tx_ppp0;
2707                         __be64 tx_ppp1;
2708                         __be64 tx_ppp2;
2709                         __be64 tx_ppp3;
2710                         __be64 tx_ppp4;
2711                         __be64 tx_ppp5;
2712                         __be64 tx_ppp6;
2713                         __be64 tx_ppp7;
2714                         __be64 rx_bytes;
2715                         __be64 rx_frames;
2716                         __be64 rx_bcast;
2717                         __be64 rx_mcast;
2718                         __be64 rx_ucast;
2719                         __be64 rx_mtu_error;
2720                         __be64 rx_mtu_crc_error;
2721                         __be64 rx_crc_error;
2722                         __be64 rx_len_error;
2723                         __be64 rx_sym_error;
2724                         __be64 rx_64b;
2725                         __be64 rx_65b_127b;
2726                         __be64 rx_128b_255b;
2727                         __be64 rx_256b_511b;
2728                         __be64 rx_512b_1023b;
2729                         __be64 rx_1024b_1518b;
2730                         __be64 rx_1519b_max;
2731                         __be64 rx_pause;
2732                         __be64 rx_ppp0;
2733                         __be64 rx_ppp1;
2734                         __be64 rx_ppp2;
2735                         __be64 rx_ppp3;
2736                         __be64 rx_ppp4;
2737                         __be64 rx_ppp5;
2738                         __be64 rx_ppp6;
2739                         __be64 rx_ppp7;
2740                         __be64 rx_less_64b;
2741                         __be64 rx_bg_drop;
2742                         __be64 rx_bg_trunc;
2743                 } all;
2744         } u;
2745 };
2746
2747 /* port loopback stats */
2748 #define FW_NUM_LB_STATS 16
2749 enum fw_port_lb_stats_index {
2750         FW_STAT_LB_PORT_BYTES_IX,
2751         FW_STAT_LB_PORT_FRAMES_IX,
2752         FW_STAT_LB_PORT_BCAST_IX,
2753         FW_STAT_LB_PORT_MCAST_IX,
2754         FW_STAT_LB_PORT_UCAST_IX,
2755         FW_STAT_LB_PORT_ERROR_IX,
2756         FW_STAT_LB_PORT_64B_IX,
2757         FW_STAT_LB_PORT_65B_127B_IX,
2758         FW_STAT_LB_PORT_128B_255B_IX,
2759         FW_STAT_LB_PORT_256B_511B_IX,
2760         FW_STAT_LB_PORT_512B_1023B_IX,
2761         FW_STAT_LB_PORT_1024B_1518B_IX,
2762         FW_STAT_LB_PORT_1519B_MAX_IX,
2763         FW_STAT_LB_PORT_DROP_FRAMES_IX
2764 };
2765
2766 struct fw_port_lb_stats_cmd {
2767         __be32 op_to_lbport;
2768         __be32 retval_len16;
2769         union fw_port_lb_stats {
2770                 struct fw_port_lb_stats_ctl {
2771                         u8 nstats_bg_bm;
2772                         u8 ix_pkd;
2773                         __be16 r6;
2774                         __be32 r7;
2775                         __be64 stat0;
2776                         __be64 stat1;
2777                         __be64 stat2;
2778                         __be64 stat3;
2779                         __be64 stat4;
2780                         __be64 stat5;
2781                 } ctl;
2782                 struct fw_port_lb_stats_all {
2783                         __be64 tx_bytes;
2784                         __be64 tx_frames;
2785                         __be64 tx_bcast;
2786                         __be64 tx_mcast;
2787                         __be64 tx_ucast;
2788                         __be64 tx_error;
2789                         __be64 tx_64b;
2790                         __be64 tx_65b_127b;
2791                         __be64 tx_128b_255b;
2792                         __be64 tx_256b_511b;
2793                         __be64 tx_512b_1023b;
2794                         __be64 tx_1024b_1518b;
2795                         __be64 tx_1519b_max;
2796                         __be64 rx_lb_drop;
2797                         __be64 rx_lb_trunc;
2798                 } all;
2799         } u;
2800 };
2801
2802 struct fw_rss_ind_tbl_cmd {
2803         __be32 op_to_viid;
2804         __be32 retval_len16;
2805         __be16 niqid;
2806         __be16 startidx;
2807         __be32 r3;
2808         __be32 iq0_to_iq2;
2809         __be32 iq3_to_iq5;
2810         __be32 iq6_to_iq8;
2811         __be32 iq9_to_iq11;
2812         __be32 iq12_to_iq14;
2813         __be32 iq15_to_iq17;
2814         __be32 iq18_to_iq20;
2815         __be32 iq21_to_iq23;
2816         __be32 iq24_to_iq26;
2817         __be32 iq27_to_iq29;
2818         __be32 iq30_iq31;
2819         __be32 r15_lo;
2820 };
2821
2822 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2823 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2824
2825 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2826 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2827
2828 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2829 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2830
2831 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2832 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2833
2834 struct fw_rss_glb_config_cmd {
2835         __be32 op_to_write;
2836         __be32 retval_len16;
2837         union fw_rss_glb_config {
2838                 struct fw_rss_glb_config_manual {
2839                         __be32 mode_pkd;
2840                         __be32 r3;
2841                         __be64 r4;
2842                         __be64 r5;
2843                 } manual;
2844                 struct fw_rss_glb_config_basicvirtual {
2845                         __be32 mode_pkd;
2846                         __be32 synmapen_to_hashtoeplitz;
2847                         __be64 r8;
2848                         __be64 r9;
2849                 } basicvirtual;
2850         } u;
2851 };
2852
2853 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2854 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2855 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2856 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2857         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2858
2859 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2860 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2861
2862 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2863 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2864         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2865 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2866         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2867
2868 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2869 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2870         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2871 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2872         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2873
2874 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2875 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2876         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2877 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2878         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2879
2880 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2881 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2882         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2883 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2884         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2885
2886 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2887 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2888         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2889 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2890         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2891
2892 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2893 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2894         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2895 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2896         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2897
2898 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2899 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2900         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2901 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2902         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2903
2904 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2905 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2906         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2907 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2908         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2909
2910 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2911 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2912         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2913 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2914         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2915
2916 struct fw_rss_vi_config_cmd {
2917         __be32 op_to_viid;
2918 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2919         __be32 retval_len16;
2920         union fw_rss_vi_config {
2921                 struct fw_rss_vi_config_manual {
2922                         __be64 r3;
2923                         __be64 r4;
2924                         __be64 r5;
2925                 } manual;
2926                 struct fw_rss_vi_config_basicvirtual {
2927                         __be32 r6;
2928                         __be32 defaultq_to_udpen;
2929                         __be64 r9;
2930                         __be64 r10;
2931                 } basicvirtual;
2932         } u;
2933 };
2934
2935 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2936 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2937
2938 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2939 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2940 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2941         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2942 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2943         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2944          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2945
2946 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2947 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2948         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2949 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2950         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2951
2952 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2953 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2954         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2955 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2956         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2957
2958 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2959 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2960         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2961 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2962         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2963
2964 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2965 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2966         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2967 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2968         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2969
2970 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2971 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2972 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2973
2974 enum fw_sched_sc {
2975         FW_SCHED_SC_PARAMS              = 1,
2976 };
2977
2978 struct fw_sched_cmd {
2979         __be32 op_to_write;
2980         __be32 retval_len16;
2981         union fw_sched {
2982                 struct fw_sched_config {
2983                         __u8   sc;
2984                         __u8   type;
2985                         __u8   minmaxen;
2986                         __u8   r3[5];
2987                         __u8   nclasses[4];
2988                         __be32 r4;
2989                 } config;
2990                 struct fw_sched_params {
2991                         __u8   sc;
2992                         __u8   type;
2993                         __u8   level;
2994                         __u8   mode;
2995                         __u8   unit;
2996                         __u8   rate;
2997                         __u8   ch;
2998                         __u8   cl;
2999                         __be32 min;
3000                         __be32 max;
3001                         __be16 weight;
3002                         __be16 pktsize;
3003                         __be16 burstsize;
3004                         __be16 r4;
3005                 } params;
3006         } u;
3007 };
3008
3009 struct fw_clip_cmd {
3010         __be32 op_to_write;
3011         __be32 alloc_to_len16;
3012         __be64 ip_hi;
3013         __be64 ip_lo;
3014         __be32 r4[2];
3015 };
3016
3017 #define FW_CLIP_CMD_ALLOC_S     31
3018 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
3019 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
3020
3021 #define FW_CLIP_CMD_FREE_S      30
3022 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
3023 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
3024
3025 enum fw_error_type {
3026         FW_ERROR_TYPE_EXCEPTION         = 0x0,
3027         FW_ERROR_TYPE_HWMODULE          = 0x1,
3028         FW_ERROR_TYPE_WR                = 0x2,
3029         FW_ERROR_TYPE_ACL               = 0x3,
3030 };
3031
3032 struct fw_error_cmd {
3033         __be32 op_to_type;
3034         __be32 len16_pkd;
3035         union fw_error {
3036                 struct fw_error_exception {
3037                         __be32 info[6];
3038                 } exception;
3039                 struct fw_error_hwmodule {
3040                         __be32 regaddr;
3041                         __be32 regval;
3042                 } hwmodule;
3043                 struct fw_error_wr {
3044                         __be16 cidx;
3045                         __be16 pfn_vfn;
3046                         __be32 eqid;
3047                         u8 wrhdr[16];
3048                 } wr;
3049                 struct fw_error_acl {
3050                         __be16 cidx;
3051                         __be16 pfn_vfn;
3052                         __be32 eqid;
3053                         __be16 mv_pkd;
3054                         u8 val[6];
3055                         __be64 r4;
3056                 } acl;
3057         } u;
3058 };
3059
3060 struct fw_debug_cmd {
3061         __be32 op_type;
3062         __be32 len16_pkd;
3063         union fw_debug {
3064                 struct fw_debug_assert {
3065                         __be32 fcid;
3066                         __be32 line;
3067                         __be32 x;
3068                         __be32 y;
3069                         u8 filename_0_7[8];
3070                         u8 filename_8_15[8];
3071                         __be64 r3;
3072                 } assert;
3073                 struct fw_debug_prt {
3074                         __be16 dprtstridx;
3075                         __be16 r3[3];
3076                         __be32 dprtstrparam0;
3077                         __be32 dprtstrparam1;
3078                         __be32 dprtstrparam2;
3079                         __be32 dprtstrparam3;
3080                 } prt;
3081         } u;
3082 };
3083
3084 #define FW_DEBUG_CMD_TYPE_S     0
3085 #define FW_DEBUG_CMD_TYPE_M     0xff
3086 #define FW_DEBUG_CMD_TYPE_G(x)  \
3087         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3088
3089 #define PCIE_FW_ERR_S           31
3090 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3091 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3092
3093 #define PCIE_FW_INIT_S          30
3094 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3095 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3096
3097 #define PCIE_FW_HALT_S          29
3098 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3099 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3100
3101 #define PCIE_FW_EVAL_S          24
3102 #define PCIE_FW_EVAL_M          0x7
3103 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3104
3105 #define PCIE_FW_MASTER_VLD_S    15
3106 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3107 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3108
3109 #define PCIE_FW_MASTER_S        12
3110 #define PCIE_FW_MASTER_M        0x7
3111 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3112 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3113
3114 struct fw_hdr {
3115         u8 ver;
3116         u8 chip;                        /* terminator chip type */
3117         __be16  len512;                 /* bin length in units of 512-bytes */
3118         __be32  fw_ver;                 /* firmware version */
3119         __be32  tp_microcode_ver;
3120         u8 intfver_nic;
3121         u8 intfver_vnic;
3122         u8 intfver_ofld;
3123         u8 intfver_ri;
3124         u8 intfver_iscsipdu;
3125         u8 intfver_iscsi;
3126         u8 intfver_fcoepdu;
3127         u8 intfver_fcoe;
3128         __u32   reserved2;
3129         __u32   reserved3;
3130         __u32   reserved4;
3131         __be32  flags;
3132         __be32  reserved6[23];
3133 };
3134
3135 enum fw_hdr_chip {
3136         FW_HDR_CHIP_T4,
3137         FW_HDR_CHIP_T5,
3138         FW_HDR_CHIP_T6
3139 };
3140
3141 #define FW_HDR_FW_VER_MAJOR_S   24
3142 #define FW_HDR_FW_VER_MAJOR_M   0xff
3143 #define FW_HDR_FW_VER_MAJOR_V(x) \
3144         ((x) << FW_HDR_FW_VER_MAJOR_S)
3145 #define FW_HDR_FW_VER_MAJOR_G(x) \
3146         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3147
3148 #define FW_HDR_FW_VER_MINOR_S   16
3149 #define FW_HDR_FW_VER_MINOR_M   0xff
3150 #define FW_HDR_FW_VER_MINOR_V(x) \
3151         ((x) << FW_HDR_FW_VER_MINOR_S)
3152 #define FW_HDR_FW_VER_MINOR_G(x) \
3153         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3154
3155 #define FW_HDR_FW_VER_MICRO_S   8
3156 #define FW_HDR_FW_VER_MICRO_M   0xff
3157 #define FW_HDR_FW_VER_MICRO_V(x) \
3158         ((x) << FW_HDR_FW_VER_MICRO_S)
3159 #define FW_HDR_FW_VER_MICRO_G(x) \
3160         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3161
3162 #define FW_HDR_FW_VER_BUILD_S   0
3163 #define FW_HDR_FW_VER_BUILD_M   0xff
3164 #define FW_HDR_FW_VER_BUILD_V(x) \
3165         ((x) << FW_HDR_FW_VER_BUILD_S)
3166 #define FW_HDR_FW_VER_BUILD_G(x) \
3167         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3168
3169 enum fw_hdr_intfver {
3170         FW_HDR_INTFVER_NIC      = 0x00,
3171         FW_HDR_INTFVER_VNIC     = 0x00,
3172         FW_HDR_INTFVER_OFLD     = 0x00,
3173         FW_HDR_INTFVER_RI       = 0x00,
3174         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3175         FW_HDR_INTFVER_ISCSI    = 0x00,
3176         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3177         FW_HDR_INTFVER_FCOE     = 0x00,
3178 };
3179
3180 enum fw_hdr_flags {
3181         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3182 };
3183
3184 /* length of the formatting string  */
3185 #define FW_DEVLOG_FMT_LEN       192
3186
3187 /* maximum number of the formatting string parameters */
3188 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3189
3190 /* priority levels */
3191 enum fw_devlog_level {
3192         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3193         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3194         FW_DEVLOG_LEVEL_ERR     = 0x2,
3195         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3196         FW_DEVLOG_LEVEL_INFO    = 0x4,
3197         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3198         FW_DEVLOG_LEVEL_MAX     = 0x5,
3199 };
3200
3201 /* facilities that may send a log message */
3202 enum fw_devlog_facility {
3203         FW_DEVLOG_FACILITY_CORE         = 0x00,
3204         FW_DEVLOG_FACILITY_CF           = 0x01,
3205         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3206         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3207         FW_DEVLOG_FACILITY_RES          = 0x06,
3208         FW_DEVLOG_FACILITY_HW           = 0x08,
3209         FW_DEVLOG_FACILITY_FLR          = 0x10,
3210         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3211         FW_DEVLOG_FACILITY_PHY          = 0x14,
3212         FW_DEVLOG_FACILITY_MAC          = 0x16,
3213         FW_DEVLOG_FACILITY_PORT         = 0x18,
3214         FW_DEVLOG_FACILITY_VI           = 0x1A,
3215         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3216         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3217         FW_DEVLOG_FACILITY_TM           = 0x20,
3218         FW_DEVLOG_FACILITY_QFC          = 0x22,
3219         FW_DEVLOG_FACILITY_DCB          = 0x24,
3220         FW_DEVLOG_FACILITY_ETH          = 0x26,
3221         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3222         FW_DEVLOG_FACILITY_RI           = 0x2A,
3223         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3224         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3225         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3226         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3227         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3228         FW_DEVLOG_FACILITY_MAX          = 0x34,
3229 };
3230
3231 /* log message format */
3232 struct fw_devlog_e {
3233         __be64  timestamp;
3234         __be32  seqno;
3235         __be16  reserved1;
3236         __u8    level;
3237         __u8    facility;
3238         __u8    fmt[FW_DEVLOG_FMT_LEN];
3239         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3240         __be32  reserved3[4];
3241 };
3242
3243 struct fw_devlog_cmd {
3244         __be32 op_to_write;
3245         __be32 retval_len16;
3246         __u8   level;
3247         __u8   r2[7];
3248         __be32 memtype_devlog_memaddr16_devlog;
3249         __be32 memsize_devlog;
3250         __be32 r3[2];
3251 };
3252
3253 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3254 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3255 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3256         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3257          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3258
3259 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3260 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3261 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3262         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3263          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3264
3265 /* P C I E   F W   P F 7   R E G I S T E R */
3266
3267 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3268  * access the "devlog" which needing to contact firmware.  The encoding is
3269  * mostly the same as that returned by the DEVLOG command except for the size
3270  * which is encoded as the number of entries in multiples-1 of 128 here rather
3271  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3272  * and 15 means 2048.  This of course in turn constrains the allowed values
3273  * for the devlog size ...
3274  */
3275 #define PCIE_FW_PF_DEVLOG               7
3276
3277 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3278 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3279 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3280         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3281 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3282         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3283          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3284
3285 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3286 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3287 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3288 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3289         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3290
3291 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3292 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3293 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3294 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3295         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3296
3297 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3298
3299 struct fw_crypto_lookaside_wr {
3300         __be32 op_to_cctx_size;
3301         __be32 len16_pkd;
3302         __be32 session_id;
3303         __be32 rx_chid_to_rx_q_id;
3304         __be32 key_addr;
3305         __be32 pld_size_hash_size;
3306         __be64 cookie;
3307 };
3308
3309 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3310 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3311 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3312         ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3313 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3314         (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3315          FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3316
3317 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3318 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3319 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3320         ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3321 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3322         (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3323          FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3324 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3325
3326 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3327 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3328 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3329         ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3330 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3331         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3332          FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3333
3334 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3335 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3336 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3337         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3338 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3339         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3340          FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3341
3342 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3343 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3344 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3345         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3346 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3347         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3348          FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3349
3350 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3351 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3352 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3353         ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3354 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3355         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3356          FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3357
3358 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3359 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3360 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3361         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3362 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3363         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3364          FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3365
3366 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3367 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3368 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3369         ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3370 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3371         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3372
3373 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3374 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3375 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3376         ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3377 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3378         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3379          FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3380
3381 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3382 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3383 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3384         ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3385 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3386         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3387
3388 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3389 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3390 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3391         ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3392 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3393         (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3394          FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3395
3396 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3397 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3398 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3399         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3400 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3401         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3402          FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3403
3404 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3405 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3406 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3407         ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3408 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3409         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3410          FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3411
3412 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3413 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3414 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3415         ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3416 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3417         (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3418          FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3419
3420 #endif /* _T4FW_INTERFACE_H_ */