2 * Copyright (C) 2005 - 2016 Broadcom
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 char *be_misconfig_evt_port_state[] = {
23 "Physical Link is functional",
24 "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
25 "Optics of two types installed – Remove one optic or install matching pair of optics.",
26 "Incompatible optics – Replace with compatible optics for card to function.",
27 "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
28 "Uncertified optics – Replace with Avago-certified optics to enable link operation."
31 static char *be_port_misconfig_evt_severity[] = {
38 static char *phy_state_oper_desc[] = {
39 "Link is non-operational",
40 "Link is operational",
44 static struct be_cmd_priv_map cmd_priv_map[] = {
46 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
48 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 OPCODE_COMMON_GET_FLOW_CONTROL,
54 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
58 OPCODE_COMMON_SET_FLOW_CONTROL,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
64 OPCODE_ETH_GET_PPORT_STATS,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
70 OPCODE_COMMON_GET_PHY_DETAILS,
72 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
73 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
76 OPCODE_LOWLEVEL_HOST_DDR_DMA,
77 CMD_SUBSYSTEM_LOWLEVEL,
78 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
81 OPCODE_LOWLEVEL_LOOPBACK_TEST,
82 CMD_SUBSYSTEM_LOWLEVEL,
83 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
86 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
87 CMD_SUBSYSTEM_LOWLEVEL,
88 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
91 OPCODE_COMMON_SET_HSW_CONFIG,
93 BE_PRIV_DEVCFG | BE_PRIV_VHADM
96 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
102 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
105 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
106 u32 cmd_privileges = adapter->cmd_privileges;
108 for (i = 0; i < num_entries; i++)
109 if (opcode == cmd_priv_map[i].opcode &&
110 subsystem == cmd_priv_map[i].subsystem)
111 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
117 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
119 return wrb->payload.embedded_payload;
122 static int be_mcc_notify(struct be_adapter *adapter)
124 struct be_queue_info *mccq = &adapter->mcc_obj.q;
127 if (be_check_error(adapter, BE_ERROR_ANY))
130 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
131 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
134 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
139 /* To check if valid bit is set, check the entire word as we don't know
140 * the endianness of the data (old entry is host endian while a new entry is
142 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
146 if (compl->flags != 0) {
147 flags = le32_to_cpu(compl->flags);
148 if (flags & CQE_FLAGS_VALID_MASK) {
149 compl->flags = flags;
156 /* Need to reset the entire word that houses the valid bit */
157 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
162 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
167 addr = ((addr << 16) << 16) | tag0;
171 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
173 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
174 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
175 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
176 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
177 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
178 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
179 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
185 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
186 * loop (has not issued be_mcc_notify_wait())
188 static void be_async_cmd_process(struct be_adapter *adapter,
189 struct be_mcc_compl *compl,
190 struct be_cmd_resp_hdr *resp_hdr)
192 enum mcc_base_status base_status = base_status(compl->status);
193 u8 opcode = 0, subsystem = 0;
196 opcode = resp_hdr->opcode;
197 subsystem = resp_hdr->subsystem;
200 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
201 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
202 complete(&adapter->et_cmd_compl);
206 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
207 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
208 complete(&adapter->et_cmd_compl);
212 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
213 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
214 subsystem == CMD_SUBSYSTEM_COMMON) {
215 adapter->flash_status = compl->status;
216 complete(&adapter->et_cmd_compl);
220 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
221 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
222 subsystem == CMD_SUBSYSTEM_ETH &&
223 base_status == MCC_STATUS_SUCCESS) {
224 be_parse_stats(adapter);
225 adapter->stats_cmd_sent = false;
229 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
230 subsystem == CMD_SUBSYSTEM_COMMON) {
231 if (base_status == MCC_STATUS_SUCCESS) {
232 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
234 adapter->hwmon_info.be_on_die_temp =
235 resp->on_die_temperature;
237 adapter->be_get_temp_freq = 0;
238 adapter->hwmon_info.be_on_die_temp =
245 static int be_mcc_compl_process(struct be_adapter *adapter,
246 struct be_mcc_compl *compl)
248 enum mcc_base_status base_status;
249 enum mcc_addl_status addl_status;
250 struct be_cmd_resp_hdr *resp_hdr;
251 u8 opcode = 0, subsystem = 0;
253 /* Just swap the status to host endian; mcc tag is opaquely copied
255 be_dws_le_to_cpu(compl, 4);
257 base_status = base_status(compl->status);
258 addl_status = addl_status(compl->status);
260 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
262 opcode = resp_hdr->opcode;
263 subsystem = resp_hdr->subsystem;
266 be_async_cmd_process(adapter, compl, resp_hdr);
268 if (base_status != MCC_STATUS_SUCCESS &&
269 !be_skip_err_log(opcode, base_status, addl_status)) {
270 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
271 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
272 dev_warn(&adapter->pdev->dev,
273 "VF is not privileged to issue opcode %d-%d\n",
276 dev_err(&adapter->pdev->dev,
277 "opcode %d-%d failed:status %d-%d\n",
278 opcode, subsystem, base_status, addl_status);
281 return compl->status;
284 /* Link state evt is a string of bytes; no need for endian swapping */
285 static void be_async_link_state_process(struct be_adapter *adapter,
286 struct be_mcc_compl *compl)
288 struct be_async_event_link_state *evt =
289 (struct be_async_event_link_state *)compl;
291 /* When link status changes, link speed must be re-queried from FW */
292 adapter->phy.link_speed = -1;
294 /* On BEx the FW does not send a separate link status
295 * notification for physical and logical link.
296 * On other chips just process the logical link
297 * status notification
299 if (!BEx_chip(adapter) &&
300 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
303 /* For the initial link status do not rely on the ASYNC event as
304 * it may not be received in some cases.
306 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
307 be_link_status_update(adapter,
308 evt->port_link_status & LINK_STATUS_MASK);
311 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
312 struct be_mcc_compl *compl)
314 struct be_async_event_misconfig_port *evt =
315 (struct be_async_event_misconfig_port *)compl;
316 u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
317 u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
318 u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
319 struct device *dev = &adapter->pdev->dev;
320 u8 msg_severity = DEFAULT_MSG_SEVERITY;
325 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
327 if (new_phy_state == adapter->phy_state)
330 adapter->phy_state = new_phy_state;
332 /* for older fw that doesn't populate link effect data */
333 if (!sfp_misconfig_evt_word2)
337 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
339 if (phy_state_info & PHY_STATE_INFO_VALID) {
340 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
342 if (be_phy_unqualified(new_phy_state))
343 phy_oper_state = (phy_state_info & PHY_STATE_OPER);
347 /* Log an error message that would allow a user to determine
348 * whether the SFPs have an issue
350 if (be_phy_state_unknown(new_phy_state))
351 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
352 "Port %c: Unrecognized Optics state: 0x%x. %s",
355 phy_state_oper_desc[phy_oper_state]);
357 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
360 be_misconfig_evt_port_state[new_phy_state],
361 phy_state_oper_desc[phy_oper_state]);
363 /* Log Vendor name and part no. if a misconfigured SFP is detected */
364 if (be_phy_misconfigured(new_phy_state))
365 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
368 /* Grp5 CoS Priority evt */
369 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
370 struct be_mcc_compl *compl)
372 struct be_async_event_grp5_cos_priority *evt =
373 (struct be_async_event_grp5_cos_priority *)compl;
376 adapter->vlan_prio_bmap = evt->available_priority_bmap;
377 adapter->recommended_prio_bits =
378 evt->reco_default_priority << VLAN_PRIO_SHIFT;
382 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
383 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
384 struct be_mcc_compl *compl)
386 struct be_async_event_grp5_qos_link_speed *evt =
387 (struct be_async_event_grp5_qos_link_speed *)compl;
389 if (adapter->phy.link_speed >= 0 &&
390 evt->physical_port == adapter->port_num)
391 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
395 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
396 struct be_mcc_compl *compl)
398 struct be_async_event_grp5_pvid_state *evt =
399 (struct be_async_event_grp5_pvid_state *)compl;
402 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
403 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
409 #define MGMT_ENABLE_MASK 0x4
410 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
411 struct be_mcc_compl *compl)
413 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
414 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
416 if (evt_dw1 & MGMT_ENABLE_MASK) {
417 adapter->flags |= BE_FLAGS_OS2BMC;
418 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
420 adapter->flags &= ~BE_FLAGS_OS2BMC;
424 static void be_async_grp5_evt_process(struct be_adapter *adapter,
425 struct be_mcc_compl *compl)
427 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
428 ASYNC_EVENT_TYPE_MASK;
430 switch (event_type) {
431 case ASYNC_EVENT_COS_PRIORITY:
432 be_async_grp5_cos_priority_process(adapter, compl);
434 case ASYNC_EVENT_QOS_SPEED:
435 be_async_grp5_qos_speed_process(adapter, compl);
437 case ASYNC_EVENT_PVID_STATE:
438 be_async_grp5_pvid_state_process(adapter, compl);
440 /* Async event to disable/enable os2bmc and/or mac-learning */
441 case ASYNC_EVENT_FW_CONTROL:
442 be_async_grp5_fw_control_process(adapter, compl);
449 static void be_async_dbg_evt_process(struct be_adapter *adapter,
450 struct be_mcc_compl *cmp)
453 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
455 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
456 ASYNC_EVENT_TYPE_MASK;
458 switch (event_type) {
459 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
461 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
462 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
465 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
471 static void be_async_sliport_evt_process(struct be_adapter *adapter,
472 struct be_mcc_compl *cmp)
474 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
475 ASYNC_EVENT_TYPE_MASK;
477 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
478 be_async_port_misconfig_event_process(adapter, cmp);
481 static inline bool is_link_state_evt(u32 flags)
483 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
484 ASYNC_EVENT_CODE_LINK_STATE;
487 static inline bool is_grp5_evt(u32 flags)
489 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
490 ASYNC_EVENT_CODE_GRP_5;
493 static inline bool is_dbg_evt(u32 flags)
495 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
496 ASYNC_EVENT_CODE_QNQ;
499 static inline bool is_sliport_evt(u32 flags)
501 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
502 ASYNC_EVENT_CODE_SLIPORT;
505 static void be_mcc_event_process(struct be_adapter *adapter,
506 struct be_mcc_compl *compl)
508 if (is_link_state_evt(compl->flags))
509 be_async_link_state_process(adapter, compl);
510 else if (is_grp5_evt(compl->flags))
511 be_async_grp5_evt_process(adapter, compl);
512 else if (is_dbg_evt(compl->flags))
513 be_async_dbg_evt_process(adapter, compl);
514 else if (is_sliport_evt(compl->flags))
515 be_async_sliport_evt_process(adapter, compl);
518 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
520 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
521 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
523 if (be_mcc_compl_is_new(compl)) {
524 queue_tail_inc(mcc_cq);
530 void be_async_mcc_enable(struct be_adapter *adapter)
532 spin_lock_bh(&adapter->mcc_cq_lock);
534 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
535 adapter->mcc_obj.rearm_cq = true;
537 spin_unlock_bh(&adapter->mcc_cq_lock);
540 void be_async_mcc_disable(struct be_adapter *adapter)
542 spin_lock_bh(&adapter->mcc_cq_lock);
544 adapter->mcc_obj.rearm_cq = false;
545 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
547 spin_unlock_bh(&adapter->mcc_cq_lock);
550 int be_process_mcc(struct be_adapter *adapter)
552 struct be_mcc_compl *compl;
553 int num = 0, status = 0;
554 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
556 spin_lock(&adapter->mcc_cq_lock);
558 while ((compl = be_mcc_compl_get(adapter))) {
559 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
560 be_mcc_event_process(adapter, compl);
561 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
562 status = be_mcc_compl_process(adapter, compl);
563 atomic_dec(&mcc_obj->q.used);
565 be_mcc_compl_use(compl);
570 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
572 spin_unlock(&adapter->mcc_cq_lock);
576 /* Wait till no more pending mcc requests are present */
577 static int be_mcc_wait_compl(struct be_adapter *adapter)
579 #define mcc_timeout 12000 /* 12s timeout */
581 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
583 for (i = 0; i < mcc_timeout; i++) {
584 if (be_check_error(adapter, BE_ERROR_ANY))
588 status = be_process_mcc(adapter);
591 if (atomic_read(&mcc_obj->q.used) == 0)
593 usleep_range(500, 1000);
595 if (i == mcc_timeout) {
596 dev_err(&adapter->pdev->dev, "FW not responding\n");
597 be_set_error(adapter, BE_ERROR_FW);
603 /* Notify MCC requests and wait for completion */
604 static int be_mcc_notify_wait(struct be_adapter *adapter)
607 struct be_mcc_wrb *wrb;
608 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
609 u32 index = mcc_obj->q.head;
610 struct be_cmd_resp_hdr *resp;
612 index_dec(&index, mcc_obj->q.len);
613 wrb = queue_index_node(&mcc_obj->q, index);
615 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
617 status = be_mcc_notify(adapter);
621 status = be_mcc_wait_compl(adapter);
625 status = (resp->base_status |
626 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
627 CQE_ADDL_STATUS_SHIFT));
632 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
638 if (be_check_error(adapter, BE_ERROR_ANY))
641 ready = ioread32(db);
642 if (ready == 0xffffffff)
645 ready &= MPU_MAILBOX_DB_RDY_MASK;
650 dev_err(&adapter->pdev->dev, "FW not responding\n");
651 be_set_error(adapter, BE_ERROR_FW);
652 be_detect_error(adapter);
664 * Insert the mailbox address into the doorbell in two steps
665 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
667 static int be_mbox_notify_wait(struct be_adapter *adapter)
671 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
672 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
673 struct be_mcc_mailbox *mbox = mbox_mem->va;
674 struct be_mcc_compl *compl = &mbox->compl;
676 /* wait for ready to be set */
677 status = be_mbox_db_ready_wait(adapter, db);
681 val |= MPU_MAILBOX_DB_HI_MASK;
682 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
683 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
686 /* wait for ready to be set */
687 status = be_mbox_db_ready_wait(adapter, db);
692 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
693 val |= (u32)(mbox_mem->dma >> 4) << 2;
696 status = be_mbox_db_ready_wait(adapter, db);
700 /* A cq entry has been made now */
701 if (be_mcc_compl_is_new(compl)) {
702 status = be_mcc_compl_process(adapter, &mbox->compl);
703 be_mcc_compl_use(compl);
707 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
713 u16 be_POST_stage_get(struct be_adapter *adapter)
717 if (BEx_chip(adapter))
718 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
720 pci_read_config_dword(adapter->pdev,
721 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
723 return sem & POST_STAGE_MASK;
726 static int lancer_wait_ready(struct be_adapter *adapter)
728 #define SLIPORT_READY_TIMEOUT 30
732 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
733 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
734 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
737 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
738 !(sliport_status & SLIPORT_STATUS_RN_MASK))
744 return sliport_status ? : -1;
747 int be_fw_wait_ready(struct be_adapter *adapter)
750 int status, timeout = 0;
751 struct device *dev = &adapter->pdev->dev;
753 if (lancer_chip(adapter)) {
754 status = lancer_wait_ready(adapter);
763 /* There's no means to poll POST state on BE2/3 VFs */
764 if (BEx_chip(adapter) && be_virtfn(adapter))
767 stage = be_POST_stage_get(adapter);
768 if (stage == POST_STAGE_ARMFW_RDY)
771 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
772 if (msleep_interruptible(2000)) {
773 dev_err(dev, "Waiting for POST aborted\n");
777 } while (timeout < 60);
780 dev_err(dev, "POST timeout; stage=%#x\n", stage);
784 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
786 return &wrb->payload.sgl[0];
789 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
791 wrb->tag0 = addr & 0xFFFFFFFF;
792 wrb->tag1 = upper_32_bits(addr);
795 /* Don't touch the hdr after it's prepared */
796 /* mem will be NULL for embedded commands */
797 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
798 u8 subsystem, u8 opcode, int cmd_len,
799 struct be_mcc_wrb *wrb,
800 struct be_dma_mem *mem)
804 req_hdr->opcode = opcode;
805 req_hdr->subsystem = subsystem;
806 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
807 req_hdr->version = 0;
808 fill_wrb_tags(wrb, (ulong) req_hdr);
809 wrb->payload_length = cmd_len;
811 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
812 MCC_WRB_SGE_CNT_SHIFT;
813 sge = nonembedded_sgl(wrb);
814 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
815 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
816 sge->len = cpu_to_le32(mem->size);
818 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
819 be_dws_cpu_to_le(wrb, 8);
822 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
823 struct be_dma_mem *mem)
825 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
826 u64 dma = (u64)mem->dma;
828 for (i = 0; i < buf_pages; i++) {
829 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
830 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
835 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
837 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
838 struct be_mcc_wrb *wrb
839 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
840 memset(wrb, 0, sizeof(*wrb));
844 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
846 struct be_queue_info *mccq = &adapter->mcc_obj.q;
847 struct be_mcc_wrb *wrb;
852 if (atomic_read(&mccq->used) >= mccq->len)
855 wrb = queue_head_node(mccq);
856 queue_head_inc(mccq);
857 atomic_inc(&mccq->used);
858 memset(wrb, 0, sizeof(*wrb));
862 static bool use_mcc(struct be_adapter *adapter)
864 return adapter->mcc_obj.q.created;
867 /* Must be used only in process context */
868 static int be_cmd_lock(struct be_adapter *adapter)
870 if (use_mcc(adapter)) {
871 mutex_lock(&adapter->mcc_lock);
874 return mutex_lock_interruptible(&adapter->mbox_lock);
878 /* Must be used only in process context */
879 static void be_cmd_unlock(struct be_adapter *adapter)
881 if (use_mcc(adapter))
882 return mutex_unlock(&adapter->mcc_lock);
884 return mutex_unlock(&adapter->mbox_lock);
887 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
888 struct be_mcc_wrb *wrb)
890 struct be_mcc_wrb *dest_wrb;
892 if (use_mcc(adapter)) {
893 dest_wrb = wrb_from_mccq(adapter);
897 dest_wrb = wrb_from_mbox(adapter);
900 memcpy(dest_wrb, wrb, sizeof(*wrb));
901 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
902 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
907 /* Must be used only in process context */
908 static int be_cmd_notify_wait(struct be_adapter *adapter,
909 struct be_mcc_wrb *wrb)
911 struct be_mcc_wrb *dest_wrb;
914 status = be_cmd_lock(adapter);
918 dest_wrb = be_cmd_copy(adapter, wrb);
924 if (use_mcc(adapter))
925 status = be_mcc_notify_wait(adapter);
927 status = be_mbox_notify_wait(adapter);
930 memcpy(wrb, dest_wrb, sizeof(*wrb));
933 be_cmd_unlock(adapter);
937 /* Tell fw we're about to start firing cmds by writing a
938 * special pattern across the wrb hdr; uses mbox
940 int be_cmd_fw_init(struct be_adapter *adapter)
945 if (lancer_chip(adapter))
948 if (mutex_lock_interruptible(&adapter->mbox_lock))
951 wrb = (u8 *)wrb_from_mbox(adapter);
961 status = be_mbox_notify_wait(adapter);
963 mutex_unlock(&adapter->mbox_lock);
967 /* Tell fw we're done with firing cmds by writing a
968 * special pattern across the wrb hdr; uses mbox
970 int be_cmd_fw_clean(struct be_adapter *adapter)
975 if (lancer_chip(adapter))
978 if (mutex_lock_interruptible(&adapter->mbox_lock))
981 wrb = (u8 *)wrb_from_mbox(adapter);
991 status = be_mbox_notify_wait(adapter);
993 mutex_unlock(&adapter->mbox_lock);
997 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
999 struct be_mcc_wrb *wrb;
1000 struct be_cmd_req_eq_create *req;
1001 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
1002 int status, ver = 0;
1004 if (mutex_lock_interruptible(&adapter->mbox_lock))
1007 wrb = wrb_from_mbox(adapter);
1008 req = embedded_payload(wrb);
1010 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1011 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1014 /* Support for EQ_CREATEv2 available only SH-R onwards */
1015 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1018 req->hdr.version = ver;
1019 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1021 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1023 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1024 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1025 __ilog2_u32(eqo->q.len / 256));
1026 be_dws_cpu_to_le(req->context, sizeof(req->context));
1028 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1030 status = be_mbox_notify_wait(adapter);
1032 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1034 eqo->q.id = le16_to_cpu(resp->eq_id);
1036 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1037 eqo->q.created = true;
1040 mutex_unlock(&adapter->mbox_lock);
1045 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1046 bool permanent, u32 if_handle, u32 pmac_id)
1048 struct be_mcc_wrb *wrb;
1049 struct be_cmd_req_mac_query *req;
1052 mutex_lock(&adapter->mcc_lock);
1054 wrb = wrb_from_mccq(adapter);
1059 req = embedded_payload(wrb);
1061 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1062 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1064 req->type = MAC_ADDRESS_TYPE_NETWORK;
1068 req->if_id = cpu_to_le16((u16)if_handle);
1069 req->pmac_id = cpu_to_le32(pmac_id);
1073 status = be_mcc_notify_wait(adapter);
1075 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1077 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1081 mutex_unlock(&adapter->mcc_lock);
1085 /* Uses synchronous MCCQ */
1086 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1087 u32 if_id, u32 *pmac_id, u32 domain)
1089 struct be_mcc_wrb *wrb;
1090 struct be_cmd_req_pmac_add *req;
1093 mutex_lock(&adapter->mcc_lock);
1095 wrb = wrb_from_mccq(adapter);
1100 req = embedded_payload(wrb);
1102 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1103 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1106 req->hdr.domain = domain;
1107 req->if_id = cpu_to_le32(if_id);
1108 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1110 status = be_mcc_notify_wait(adapter);
1112 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1114 *pmac_id = le32_to_cpu(resp->pmac_id);
1118 mutex_unlock(&adapter->mcc_lock);
1120 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1126 /* Uses synchronous MCCQ */
1127 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1129 struct be_mcc_wrb *wrb;
1130 struct be_cmd_req_pmac_del *req;
1136 mutex_lock(&adapter->mcc_lock);
1138 wrb = wrb_from_mccq(adapter);
1143 req = embedded_payload(wrb);
1145 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1146 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1149 req->hdr.domain = dom;
1150 req->if_id = cpu_to_le32(if_id);
1151 req->pmac_id = cpu_to_le32(pmac_id);
1153 status = be_mcc_notify_wait(adapter);
1156 mutex_unlock(&adapter->mcc_lock);
1161 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1162 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1164 struct be_mcc_wrb *wrb;
1165 struct be_cmd_req_cq_create *req;
1166 struct be_dma_mem *q_mem = &cq->dma_mem;
1170 if (mutex_lock_interruptible(&adapter->mbox_lock))
1173 wrb = wrb_from_mbox(adapter);
1174 req = embedded_payload(wrb);
1175 ctxt = &req->context;
1177 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1178 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1181 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1183 if (BEx_chip(adapter)) {
1184 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1186 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1188 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1189 __ilog2_u32(cq->len / 256));
1190 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1191 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1192 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1194 req->hdr.version = 2;
1195 req->page_size = 1; /* 1 for 4K */
1197 /* coalesce-wm field in this cmd is not relevant to Lancer.
1198 * Lancer uses COMMON_MODIFY_CQ to set this field
1200 if (!lancer_chip(adapter))
1201 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1203 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1205 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1206 __ilog2_u32(cq->len / 256));
1207 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1208 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1209 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1212 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1214 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1216 status = be_mbox_notify_wait(adapter);
1218 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1220 cq->id = le16_to_cpu(resp->cq_id);
1224 mutex_unlock(&adapter->mbox_lock);
1229 static u32 be_encoded_q_len(int q_len)
1231 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1233 if (len_encoded == 16)
1238 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1239 struct be_queue_info *mccq,
1240 struct be_queue_info *cq)
1242 struct be_mcc_wrb *wrb;
1243 struct be_cmd_req_mcc_ext_create *req;
1244 struct be_dma_mem *q_mem = &mccq->dma_mem;
1248 if (mutex_lock_interruptible(&adapter->mbox_lock))
1251 wrb = wrb_from_mbox(adapter);
1252 req = embedded_payload(wrb);
1253 ctxt = &req->context;
1255 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1256 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1259 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1260 if (BEx_chip(adapter)) {
1261 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1262 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1263 be_encoded_q_len(mccq->len));
1264 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1266 req->hdr.version = 1;
1267 req->cq_id = cpu_to_le16(cq->id);
1269 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1270 be_encoded_q_len(mccq->len));
1271 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1272 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1274 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1278 /* Subscribe to Link State, Sliport Event and Group 5 Events
1279 * (bits 1, 5 and 17 set)
1281 req->async_event_bitmap[0] =
1282 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1283 BIT(ASYNC_EVENT_CODE_GRP_5) |
1284 BIT(ASYNC_EVENT_CODE_QNQ) |
1285 BIT(ASYNC_EVENT_CODE_SLIPORT));
1287 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1289 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1291 status = be_mbox_notify_wait(adapter);
1293 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1295 mccq->id = le16_to_cpu(resp->id);
1296 mccq->created = true;
1298 mutex_unlock(&adapter->mbox_lock);
1303 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1304 struct be_queue_info *mccq,
1305 struct be_queue_info *cq)
1307 struct be_mcc_wrb *wrb;
1308 struct be_cmd_req_mcc_create *req;
1309 struct be_dma_mem *q_mem = &mccq->dma_mem;
1313 if (mutex_lock_interruptible(&adapter->mbox_lock))
1316 wrb = wrb_from_mbox(adapter);
1317 req = embedded_payload(wrb);
1318 ctxt = &req->context;
1320 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1321 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1324 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1326 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1327 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1328 be_encoded_q_len(mccq->len));
1329 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1331 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1333 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1335 status = be_mbox_notify_wait(adapter);
1337 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1339 mccq->id = le16_to_cpu(resp->id);
1340 mccq->created = true;
1343 mutex_unlock(&adapter->mbox_lock);
1347 int be_cmd_mccq_create(struct be_adapter *adapter,
1348 struct be_queue_info *mccq, struct be_queue_info *cq)
1352 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1353 if (status && BEx_chip(adapter)) {
1354 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1355 "or newer to avoid conflicting priorities between NIC "
1356 "and FCoE traffic");
1357 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1362 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1364 struct be_mcc_wrb wrb = {0};
1365 struct be_cmd_req_eth_tx_create *req;
1366 struct be_queue_info *txq = &txo->q;
1367 struct be_queue_info *cq = &txo->cq;
1368 struct be_dma_mem *q_mem = &txq->dma_mem;
1369 int status, ver = 0;
1371 req = embedded_payload(&wrb);
1372 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1373 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1375 if (lancer_chip(adapter)) {
1376 req->hdr.version = 1;
1377 } else if (BEx_chip(adapter)) {
1378 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1379 req->hdr.version = 2;
1380 } else { /* For SH */
1381 req->hdr.version = 2;
1384 if (req->hdr.version > 0)
1385 req->if_id = cpu_to_le16(adapter->if_handle);
1386 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1387 req->ulp_num = BE_ULP1_NUM;
1388 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1389 req->cq_id = cpu_to_le16(cq->id);
1390 req->queue_size = be_encoded_q_len(txq->len);
1391 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1392 ver = req->hdr.version;
1394 status = be_cmd_notify_wait(adapter, &wrb);
1396 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1398 txq->id = le16_to_cpu(resp->cid);
1400 txo->db_offset = le32_to_cpu(resp->db_offset);
1402 txo->db_offset = DB_TXULP1_OFFSET;
1403 txq->created = true;
1410 int be_cmd_rxq_create(struct be_adapter *adapter,
1411 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1412 u32 if_id, u32 rss, u8 *rss_id)
1414 struct be_mcc_wrb *wrb;
1415 struct be_cmd_req_eth_rx_create *req;
1416 struct be_dma_mem *q_mem = &rxq->dma_mem;
1419 mutex_lock(&adapter->mcc_lock);
1421 wrb = wrb_from_mccq(adapter);
1426 req = embedded_payload(wrb);
1428 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1429 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1431 req->cq_id = cpu_to_le16(cq_id);
1432 req->frag_size = fls(frag_size) - 1;
1434 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1435 req->interface_id = cpu_to_le32(if_id);
1436 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1437 req->rss_queue = cpu_to_le32(rss);
1439 status = be_mcc_notify_wait(adapter);
1441 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1443 rxq->id = le16_to_cpu(resp->id);
1444 rxq->created = true;
1445 *rss_id = resp->rss_id;
1449 mutex_unlock(&adapter->mcc_lock);
1453 /* Generic destroyer function for all types of queues
1456 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1459 struct be_mcc_wrb *wrb;
1460 struct be_cmd_req_q_destroy *req;
1461 u8 subsys = 0, opcode = 0;
1464 if (mutex_lock_interruptible(&adapter->mbox_lock))
1467 wrb = wrb_from_mbox(adapter);
1468 req = embedded_payload(wrb);
1470 switch (queue_type) {
1472 subsys = CMD_SUBSYSTEM_COMMON;
1473 opcode = OPCODE_COMMON_EQ_DESTROY;
1476 subsys = CMD_SUBSYSTEM_COMMON;
1477 opcode = OPCODE_COMMON_CQ_DESTROY;
1480 subsys = CMD_SUBSYSTEM_ETH;
1481 opcode = OPCODE_ETH_TX_DESTROY;
1484 subsys = CMD_SUBSYSTEM_ETH;
1485 opcode = OPCODE_ETH_RX_DESTROY;
1488 subsys = CMD_SUBSYSTEM_COMMON;
1489 opcode = OPCODE_COMMON_MCC_DESTROY;
1495 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1497 req->id = cpu_to_le16(q->id);
1499 status = be_mbox_notify_wait(adapter);
1502 mutex_unlock(&adapter->mbox_lock);
1507 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1509 struct be_mcc_wrb *wrb;
1510 struct be_cmd_req_q_destroy *req;
1513 mutex_lock(&adapter->mcc_lock);
1515 wrb = wrb_from_mccq(adapter);
1520 req = embedded_payload(wrb);
1522 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1523 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1524 req->id = cpu_to_le16(q->id);
1526 status = be_mcc_notify_wait(adapter);
1530 mutex_unlock(&adapter->mcc_lock);
1534 /* Create an rx filtering policy configuration on an i/f
1535 * Will use MBOX only if MCCQ has not been created.
1537 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1538 u32 *if_handle, u32 domain)
1540 struct be_mcc_wrb wrb = {0};
1541 struct be_cmd_req_if_create *req;
1544 req = embedded_payload(&wrb);
1545 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1546 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1547 sizeof(*req), &wrb, NULL);
1548 req->hdr.domain = domain;
1549 req->capability_flags = cpu_to_le32(cap_flags);
1550 req->enable_flags = cpu_to_le32(en_flags);
1551 req->pmac_invalid = true;
1553 status = be_cmd_notify_wait(adapter, &wrb);
1555 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1557 *if_handle = le32_to_cpu(resp->interface_id);
1559 /* Hack to retrieve VF's pmac-id on BE3 */
1560 if (BE3_chip(adapter) && be_virtfn(adapter))
1561 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1566 /* Uses MCCQ if available else MBOX */
1567 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1569 struct be_mcc_wrb wrb = {0};
1570 struct be_cmd_req_if_destroy *req;
1573 if (interface_id == -1)
1576 req = embedded_payload(&wrb);
1578 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1579 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1580 sizeof(*req), &wrb, NULL);
1581 req->hdr.domain = domain;
1582 req->interface_id = cpu_to_le32(interface_id);
1584 status = be_cmd_notify_wait(adapter, &wrb);
1588 /* Get stats is a non embedded command: the request is not embedded inside
1589 * WRB but is a separate dma memory block
1590 * Uses asynchronous MCC
1592 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1594 struct be_mcc_wrb *wrb;
1595 struct be_cmd_req_hdr *hdr;
1598 mutex_lock(&adapter->mcc_lock);
1600 wrb = wrb_from_mccq(adapter);
1605 hdr = nonemb_cmd->va;
1607 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1608 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1611 /* version 1 of the cmd is not supported only by BE2 */
1612 if (BE2_chip(adapter))
1614 if (BE3_chip(adapter) || lancer_chip(adapter))
1619 status = be_mcc_notify(adapter);
1623 adapter->stats_cmd_sent = true;
1626 mutex_unlock(&adapter->mcc_lock);
1631 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1632 struct be_dma_mem *nonemb_cmd)
1634 struct be_mcc_wrb *wrb;
1635 struct lancer_cmd_req_pport_stats *req;
1638 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1642 mutex_lock(&adapter->mcc_lock);
1644 wrb = wrb_from_mccq(adapter);
1649 req = nonemb_cmd->va;
1651 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1652 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1655 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1656 req->cmd_params.params.reset_stats = 0;
1658 status = be_mcc_notify(adapter);
1662 adapter->stats_cmd_sent = true;
1665 mutex_unlock(&adapter->mcc_lock);
1669 static int be_mac_to_link_speed(int mac_speed)
1671 switch (mac_speed) {
1672 case PHY_LINK_SPEED_ZERO:
1674 case PHY_LINK_SPEED_10MBPS:
1676 case PHY_LINK_SPEED_100MBPS:
1678 case PHY_LINK_SPEED_1GBPS:
1680 case PHY_LINK_SPEED_10GBPS:
1682 case PHY_LINK_SPEED_20GBPS:
1684 case PHY_LINK_SPEED_25GBPS:
1686 case PHY_LINK_SPEED_40GBPS:
1692 /* Uses synchronous mcc
1693 * Returns link_speed in Mbps
1695 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1696 u8 *link_status, u32 dom)
1698 struct be_mcc_wrb *wrb;
1699 struct be_cmd_req_link_status *req;
1702 mutex_lock(&adapter->mcc_lock);
1705 *link_status = LINK_DOWN;
1707 wrb = wrb_from_mccq(adapter);
1712 req = embedded_payload(wrb);
1714 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1715 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1716 sizeof(*req), wrb, NULL);
1718 /* version 1 of the cmd is not supported only by BE2 */
1719 if (!BE2_chip(adapter))
1720 req->hdr.version = 1;
1722 req->hdr.domain = dom;
1724 status = be_mcc_notify_wait(adapter);
1726 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1729 *link_speed = resp->link_speed ?
1730 le16_to_cpu(resp->link_speed) * 10 :
1731 be_mac_to_link_speed(resp->mac_speed);
1733 if (!resp->logical_link_status)
1737 *link_status = resp->logical_link_status;
1741 mutex_unlock(&adapter->mcc_lock);
1745 /* Uses synchronous mcc */
1746 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1748 struct be_mcc_wrb *wrb;
1749 struct be_cmd_req_get_cntl_addnl_attribs *req;
1752 mutex_lock(&adapter->mcc_lock);
1754 wrb = wrb_from_mccq(adapter);
1759 req = embedded_payload(wrb);
1761 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1762 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1763 sizeof(*req), wrb, NULL);
1765 status = be_mcc_notify(adapter);
1767 mutex_unlock(&adapter->mcc_lock);
1771 /* Uses synchronous mcc */
1772 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1774 struct be_mcc_wrb wrb = {0};
1775 struct be_cmd_req_get_fat *req;
1778 req = embedded_payload(&wrb);
1780 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1781 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1783 req->fat_operation = cpu_to_le32(QUERY_FAT);
1784 status = be_cmd_notify_wait(adapter, &wrb);
1786 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1788 if (dump_size && resp->log_size)
1789 *dump_size = le32_to_cpu(resp->log_size) -
1795 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1797 struct be_dma_mem get_fat_cmd;
1798 struct be_mcc_wrb *wrb;
1799 struct be_cmd_req_get_fat *req;
1800 u32 offset = 0, total_size, buf_size,
1801 log_offset = sizeof(u32), payload_len;
1807 total_size = buf_len;
1809 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1810 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1812 &get_fat_cmd.dma, GFP_ATOMIC);
1813 if (!get_fat_cmd.va)
1816 mutex_lock(&adapter->mcc_lock);
1818 while (total_size) {
1819 buf_size = min(total_size, (u32)60*1024);
1820 total_size -= buf_size;
1822 wrb = wrb_from_mccq(adapter);
1827 req = get_fat_cmd.va;
1829 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1830 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1831 OPCODE_COMMON_MANAGE_FAT, payload_len,
1834 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1835 req->read_log_offset = cpu_to_le32(log_offset);
1836 req->read_log_length = cpu_to_le32(buf_size);
1837 req->data_buffer_size = cpu_to_le32(buf_size);
1839 status = be_mcc_notify_wait(adapter);
1841 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1843 memcpy(buf + offset,
1845 le32_to_cpu(resp->read_log_length));
1847 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1851 log_offset += buf_size;
1854 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1855 get_fat_cmd.va, get_fat_cmd.dma);
1856 mutex_unlock(&adapter->mcc_lock);
1860 /* Uses synchronous mcc */
1861 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1863 struct be_mcc_wrb *wrb;
1864 struct be_cmd_req_get_fw_version *req;
1867 mutex_lock(&adapter->mcc_lock);
1869 wrb = wrb_from_mccq(adapter);
1875 req = embedded_payload(wrb);
1877 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1878 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1880 status = be_mcc_notify_wait(adapter);
1882 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1884 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1885 sizeof(adapter->fw_ver));
1886 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1887 sizeof(adapter->fw_on_flash));
1890 mutex_unlock(&adapter->mcc_lock);
1894 /* set the EQ delay interval of an EQ to specified value
1897 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1898 struct be_set_eqd *set_eqd, int num)
1900 struct be_mcc_wrb *wrb;
1901 struct be_cmd_req_modify_eq_delay *req;
1904 mutex_lock(&adapter->mcc_lock);
1906 wrb = wrb_from_mccq(adapter);
1911 req = embedded_payload(wrb);
1913 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1914 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1917 req->num_eq = cpu_to_le32(num);
1918 for (i = 0; i < num; i++) {
1919 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1920 req->set_eqd[i].phase = 0;
1921 req->set_eqd[i].delay_multiplier =
1922 cpu_to_le32(set_eqd[i].delay_multiplier);
1925 status = be_mcc_notify(adapter);
1927 mutex_unlock(&adapter->mcc_lock);
1931 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1937 num_eqs = min(num, 8);
1938 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1946 /* Uses sycnhronous mcc */
1947 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1948 u32 num, u32 domain)
1950 struct be_mcc_wrb *wrb;
1951 struct be_cmd_req_vlan_config *req;
1954 mutex_lock(&adapter->mcc_lock);
1956 wrb = wrb_from_mccq(adapter);
1961 req = embedded_payload(wrb);
1963 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1964 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1966 req->hdr.domain = domain;
1968 req->interface_id = if_id;
1969 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1970 req->num_vlan = num;
1971 memcpy(req->normal_vlan, vtag_array,
1972 req->num_vlan * sizeof(vtag_array[0]));
1974 status = be_mcc_notify_wait(adapter);
1976 mutex_unlock(&adapter->mcc_lock);
1980 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1982 struct be_mcc_wrb *wrb;
1983 struct be_dma_mem *mem = &adapter->rx_filter;
1984 struct be_cmd_req_rx_filter *req = mem->va;
1987 mutex_lock(&adapter->mcc_lock);
1989 wrb = wrb_from_mccq(adapter);
1994 memset(req, 0, sizeof(*req));
1995 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1996 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1999 req->if_id = cpu_to_le32(adapter->if_handle);
2000 req->if_flags_mask = cpu_to_le32(flags);
2001 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
2003 if (flags & BE_IF_FLAGS_MULTICAST) {
2006 /* Reset mcast promisc mode if already set by setting mask
2007 * and not setting flags field
2009 req->if_flags_mask |=
2010 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2011 be_if_cap_flags(adapter));
2012 req->mcast_num = cpu_to_le32(adapter->mc_count);
2013 for (i = 0; i < adapter->mc_count; i++)
2014 ether_addr_copy(req->mcast_mac[i].byte,
2015 adapter->mc_list[i].mac);
2018 status = be_mcc_notify_wait(adapter);
2020 mutex_unlock(&adapter->mcc_lock);
2024 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2026 struct device *dev = &adapter->pdev->dev;
2028 if ((flags & be_if_cap_flags(adapter)) != flags) {
2029 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2030 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2031 be_if_cap_flags(adapter));
2033 flags &= be_if_cap_flags(adapter);
2037 return __be_cmd_rx_filter(adapter, flags, value);
2040 /* Uses synchrounous mcc */
2041 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2043 struct be_mcc_wrb *wrb;
2044 struct be_cmd_req_set_flow_control *req;
2047 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2048 CMD_SUBSYSTEM_COMMON))
2051 mutex_lock(&adapter->mcc_lock);
2053 wrb = wrb_from_mccq(adapter);
2058 req = embedded_payload(wrb);
2060 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2061 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2064 req->hdr.version = 1;
2065 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2066 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2068 status = be_mcc_notify_wait(adapter);
2071 mutex_unlock(&adapter->mcc_lock);
2073 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2080 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2082 struct be_mcc_wrb *wrb;
2083 struct be_cmd_req_get_flow_control *req;
2086 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2087 CMD_SUBSYSTEM_COMMON))
2090 mutex_lock(&adapter->mcc_lock);
2092 wrb = wrb_from_mccq(adapter);
2097 req = embedded_payload(wrb);
2099 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2100 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2103 status = be_mcc_notify_wait(adapter);
2105 struct be_cmd_resp_get_flow_control *resp =
2106 embedded_payload(wrb);
2108 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2109 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2113 mutex_unlock(&adapter->mcc_lock);
2118 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2120 struct be_mcc_wrb *wrb;
2121 struct be_cmd_req_query_fw_cfg *req;
2124 if (mutex_lock_interruptible(&adapter->mbox_lock))
2127 wrb = wrb_from_mbox(adapter);
2128 req = embedded_payload(wrb);
2130 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2131 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2132 sizeof(*req), wrb, NULL);
2134 status = be_mbox_notify_wait(adapter);
2136 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2138 adapter->port_num = le32_to_cpu(resp->phys_port);
2139 adapter->function_mode = le32_to_cpu(resp->function_mode);
2140 adapter->function_caps = le32_to_cpu(resp->function_caps);
2141 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2142 dev_info(&adapter->pdev->dev,
2143 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2144 adapter->function_mode, adapter->function_caps);
2147 mutex_unlock(&adapter->mbox_lock);
2152 int be_cmd_reset_function(struct be_adapter *adapter)
2154 struct be_mcc_wrb *wrb;
2155 struct be_cmd_req_hdr *req;
2158 if (lancer_chip(adapter)) {
2159 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2160 adapter->db + SLIPORT_CONTROL_OFFSET);
2161 status = lancer_wait_ready(adapter);
2163 dev_err(&adapter->pdev->dev,
2164 "Adapter in non recoverable error\n");
2168 if (mutex_lock_interruptible(&adapter->mbox_lock))
2171 wrb = wrb_from_mbox(adapter);
2172 req = embedded_payload(wrb);
2174 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2175 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2178 status = be_mbox_notify_wait(adapter);
2180 mutex_unlock(&adapter->mbox_lock);
2184 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2185 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2187 struct be_mcc_wrb *wrb;
2188 struct be_cmd_req_rss_config *req;
2191 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2194 mutex_lock(&adapter->mcc_lock);
2196 wrb = wrb_from_mccq(adapter);
2201 req = embedded_payload(wrb);
2203 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2204 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2206 req->if_id = cpu_to_le32(adapter->if_handle);
2207 req->enable_rss = cpu_to_le16(rss_hash_opts);
2208 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2210 if (!BEx_chip(adapter))
2211 req->hdr.version = 1;
2213 memcpy(req->cpu_table, rsstable, table_size);
2214 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2215 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2217 status = be_mcc_notify_wait(adapter);
2219 mutex_unlock(&adapter->mcc_lock);
2224 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2225 u8 bcn, u8 sts, u8 state)
2227 struct be_mcc_wrb *wrb;
2228 struct be_cmd_req_enable_disable_beacon *req;
2231 mutex_lock(&adapter->mcc_lock);
2233 wrb = wrb_from_mccq(adapter);
2238 req = embedded_payload(wrb);
2240 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2241 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2242 sizeof(*req), wrb, NULL);
2244 req->port_num = port_num;
2245 req->beacon_state = state;
2246 req->beacon_duration = bcn;
2247 req->status_duration = sts;
2249 status = be_mcc_notify_wait(adapter);
2252 mutex_unlock(&adapter->mcc_lock);
2257 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2259 struct be_mcc_wrb *wrb;
2260 struct be_cmd_req_get_beacon_state *req;
2263 mutex_lock(&adapter->mcc_lock);
2265 wrb = wrb_from_mccq(adapter);
2270 req = embedded_payload(wrb);
2272 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2273 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2276 req->port_num = port_num;
2278 status = be_mcc_notify_wait(adapter);
2280 struct be_cmd_resp_get_beacon_state *resp =
2281 embedded_payload(wrb);
2283 *state = resp->beacon_state;
2287 mutex_unlock(&adapter->mcc_lock);
2292 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2293 u8 page_num, u8 *data)
2295 struct be_dma_mem cmd;
2296 struct be_mcc_wrb *wrb;
2297 struct be_cmd_req_port_type *req;
2300 if (page_num > TR_PAGE_A2)
2303 cmd.size = sizeof(struct be_cmd_resp_port_type);
2304 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2307 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2311 mutex_lock(&adapter->mcc_lock);
2313 wrb = wrb_from_mccq(adapter);
2320 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2321 OPCODE_COMMON_READ_TRANSRECV_DATA,
2322 cmd.size, wrb, &cmd);
2324 req->port = cpu_to_le32(adapter->hba_port_num);
2325 req->page_num = cpu_to_le32(page_num);
2326 status = be_mcc_notify_wait(adapter);
2328 struct be_cmd_resp_port_type *resp = cmd.va;
2330 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2333 mutex_unlock(&adapter->mcc_lock);
2334 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2338 static int lancer_cmd_write_object(struct be_adapter *adapter,
2339 struct be_dma_mem *cmd, u32 data_size,
2340 u32 data_offset, const char *obj_name,
2341 u32 *data_written, u8 *change_status,
2344 struct be_mcc_wrb *wrb;
2345 struct lancer_cmd_req_write_object *req;
2346 struct lancer_cmd_resp_write_object *resp;
2350 mutex_lock(&adapter->mcc_lock);
2351 adapter->flash_status = 0;
2353 wrb = wrb_from_mccq(adapter);
2359 req = embedded_payload(wrb);
2361 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2362 OPCODE_COMMON_WRITE_OBJECT,
2363 sizeof(struct lancer_cmd_req_write_object), wrb,
2366 ctxt = &req->context;
2367 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2368 write_length, ctxt, data_size);
2371 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2374 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2377 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2378 req->write_offset = cpu_to_le32(data_offset);
2379 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2380 req->descriptor_count = cpu_to_le32(1);
2381 req->buf_len = cpu_to_le32(data_size);
2382 req->addr_low = cpu_to_le32((cmd->dma +
2383 sizeof(struct lancer_cmd_req_write_object))
2385 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2386 sizeof(struct lancer_cmd_req_write_object)));
2388 status = be_mcc_notify(adapter);
2392 mutex_unlock(&adapter->mcc_lock);
2394 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2395 msecs_to_jiffies(60000)))
2396 status = -ETIMEDOUT;
2398 status = adapter->flash_status;
2400 resp = embedded_payload(wrb);
2402 *data_written = le32_to_cpu(resp->actual_write_len);
2403 *change_status = resp->change_status;
2405 *addn_status = resp->additional_status;
2411 mutex_unlock(&adapter->mcc_lock);
2415 int be_cmd_query_cable_type(struct be_adapter *adapter)
2417 u8 page_data[PAGE_DATA_LEN];
2420 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2423 switch (adapter->phy.interface_type) {
2425 adapter->phy.cable_type =
2426 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2428 case PHY_TYPE_SFP_PLUS_10GB:
2429 adapter->phy.cable_type =
2430 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2433 adapter->phy.cable_type = 0;
2440 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2442 u8 page_data[PAGE_DATA_LEN];
2445 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2448 strlcpy(adapter->phy.vendor_name, page_data +
2449 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2450 strlcpy(adapter->phy.vendor_pn,
2451 page_data + SFP_VENDOR_PN_OFFSET,
2452 SFP_VENDOR_NAME_LEN - 1);
2458 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2459 const char *obj_name)
2461 struct lancer_cmd_req_delete_object *req;
2462 struct be_mcc_wrb *wrb;
2465 mutex_lock(&adapter->mcc_lock);
2467 wrb = wrb_from_mccq(adapter);
2473 req = embedded_payload(wrb);
2475 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2476 OPCODE_COMMON_DELETE_OBJECT,
2477 sizeof(*req), wrb, NULL);
2479 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2481 status = be_mcc_notify_wait(adapter);
2483 mutex_unlock(&adapter->mcc_lock);
2487 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2488 u32 data_size, u32 data_offset, const char *obj_name,
2489 u32 *data_read, u32 *eof, u8 *addn_status)
2491 struct be_mcc_wrb *wrb;
2492 struct lancer_cmd_req_read_object *req;
2493 struct lancer_cmd_resp_read_object *resp;
2496 mutex_lock(&adapter->mcc_lock);
2498 wrb = wrb_from_mccq(adapter);
2504 req = embedded_payload(wrb);
2506 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2507 OPCODE_COMMON_READ_OBJECT,
2508 sizeof(struct lancer_cmd_req_read_object), wrb,
2511 req->desired_read_len = cpu_to_le32(data_size);
2512 req->read_offset = cpu_to_le32(data_offset);
2513 strcpy(req->object_name, obj_name);
2514 req->descriptor_count = cpu_to_le32(1);
2515 req->buf_len = cpu_to_le32(data_size);
2516 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2517 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2519 status = be_mcc_notify_wait(adapter);
2521 resp = embedded_payload(wrb);
2523 *data_read = le32_to_cpu(resp->actual_read_len);
2524 *eof = le32_to_cpu(resp->eof);
2526 *addn_status = resp->additional_status;
2530 mutex_unlock(&adapter->mcc_lock);
2534 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2535 struct be_dma_mem *cmd, u32 flash_type,
2536 u32 flash_opcode, u32 img_offset, u32 buf_size)
2538 struct be_mcc_wrb *wrb;
2539 struct be_cmd_write_flashrom *req;
2542 mutex_lock(&adapter->mcc_lock);
2543 adapter->flash_status = 0;
2545 wrb = wrb_from_mccq(adapter);
2552 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2553 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2556 req->params.op_type = cpu_to_le32(flash_type);
2557 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2558 req->params.offset = cpu_to_le32(img_offset);
2560 req->params.op_code = cpu_to_le32(flash_opcode);
2561 req->params.data_buf_size = cpu_to_le32(buf_size);
2563 status = be_mcc_notify(adapter);
2567 mutex_unlock(&adapter->mcc_lock);
2569 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2570 msecs_to_jiffies(40000)))
2571 status = -ETIMEDOUT;
2573 status = adapter->flash_status;
2578 mutex_unlock(&adapter->mcc_lock);
2582 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2583 u16 img_optype, u32 img_offset, u32 crc_offset)
2585 struct be_cmd_read_flash_crc *req;
2586 struct be_mcc_wrb *wrb;
2589 mutex_lock(&adapter->mcc_lock);
2591 wrb = wrb_from_mccq(adapter);
2596 req = embedded_payload(wrb);
2598 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2599 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2602 req->params.op_type = cpu_to_le32(img_optype);
2603 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2604 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2606 req->params.offset = cpu_to_le32(crc_offset);
2608 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2609 req->params.data_buf_size = cpu_to_le32(0x4);
2611 status = be_mcc_notify_wait(adapter);
2613 memcpy(flashed_crc, req->crc, 4);
2616 mutex_unlock(&adapter->mcc_lock);
2620 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2622 static bool phy_flashing_required(struct be_adapter *adapter)
2624 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2625 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2628 static bool is_comp_in_ufi(struct be_adapter *adapter,
2629 struct flash_section_info *fsec, int type)
2631 int i = 0, img_type = 0;
2632 struct flash_section_info_g2 *fsec_g2 = NULL;
2634 if (BE2_chip(adapter))
2635 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2637 for (i = 0; i < MAX_FLASH_COMP; i++) {
2639 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2641 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2643 if (img_type == type)
2649 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2651 const struct firmware *fw)
2653 struct flash_section_info *fsec = NULL;
2654 const u8 *p = fw->data;
2657 while (p < (fw->data + fw->size)) {
2658 fsec = (struct flash_section_info *)p;
2659 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2666 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2667 u32 img_offset, u32 img_size, int hdr_size,
2668 u16 img_optype, bool *crc_match)
2674 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2679 crc_offset = hdr_size + img_offset + img_size - 4;
2681 /* Skip flashing, if crc of flashed region matches */
2682 if (!memcmp(crc, p + crc_offset, 4))
2690 static int be_flash(struct be_adapter *adapter, const u8 *img,
2691 struct be_dma_mem *flash_cmd, int optype, int img_size,
2694 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2695 struct be_cmd_write_flashrom *req = flash_cmd->va;
2698 while (total_bytes) {
2699 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2701 total_bytes -= num_bytes;
2704 if (optype == OPTYPE_PHY_FW)
2705 flash_op = FLASHROM_OPER_PHY_FLASH;
2707 flash_op = FLASHROM_OPER_FLASH;
2709 if (optype == OPTYPE_PHY_FW)
2710 flash_op = FLASHROM_OPER_PHY_SAVE;
2712 flash_op = FLASHROM_OPER_SAVE;
2715 memcpy(req->data_buf, img, num_bytes);
2717 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2718 flash_op, img_offset +
2719 bytes_sent, num_bytes);
2720 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2721 optype == OPTYPE_PHY_FW)
2726 bytes_sent += num_bytes;
2731 #define NCSI_UPDATE_LOG "NCSI section update is not supported in FW ver %s\n"
2732 static bool be_fw_ncsi_supported(char *ver)
2734 int v1[4] = {3, 102, 148, 0}; /* Min ver that supports NCSI FW */
2738 if (sscanf(ver, "%d.%d.%d.%d", &v2[0], &v2[1], &v2[2], &v2[3]) != 4)
2741 for (i = 0; i < 4; i++) {
2744 else if (v1[i] > v2[i])
2751 /* For BE2, BE3 and BE3-R */
2752 static int be_flash_BEx(struct be_adapter *adapter,
2753 const struct firmware *fw,
2754 struct be_dma_mem *flash_cmd, int num_of_images)
2756 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2757 struct device *dev = &adapter->pdev->dev;
2758 struct flash_section_info *fsec = NULL;
2759 int status, i, filehdr_size, num_comp;
2760 const struct flash_comp *pflashcomp;
2764 struct flash_comp gen3_flash_types[] = {
2765 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2766 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2767 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2768 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2769 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2770 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2771 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2772 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2773 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2774 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2775 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2776 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2777 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2778 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2779 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2780 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2781 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2782 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2783 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2784 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2787 struct flash_comp gen2_flash_types[] = {
2788 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2789 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2790 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2791 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2792 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2793 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2794 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2795 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2796 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2797 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2798 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2799 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2800 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2801 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2802 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2803 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2806 if (BE3_chip(adapter)) {
2807 pflashcomp = gen3_flash_types;
2808 filehdr_size = sizeof(struct flash_file_hdr_g3);
2809 num_comp = ARRAY_SIZE(gen3_flash_types);
2811 pflashcomp = gen2_flash_types;
2812 filehdr_size = sizeof(struct flash_file_hdr_g2);
2813 num_comp = ARRAY_SIZE(gen2_flash_types);
2817 /* Get flash section info*/
2818 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2820 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2823 for (i = 0; i < num_comp; i++) {
2824 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2827 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2828 !be_fw_ncsi_supported(adapter->fw_ver)) {
2829 dev_info(dev, NCSI_UPDATE_LOG, adapter->fw_ver);
2833 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2834 !phy_flashing_required(adapter))
2837 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2838 status = be_check_flash_crc(adapter, fw->data,
2839 pflashcomp[i].offset,
2843 OPTYPE_REDBOOT, &crc_match);
2846 "Could not get CRC for 0x%x region\n",
2847 pflashcomp[i].optype);
2855 p = fw->data + filehdr_size + pflashcomp[i].offset +
2857 if (p + pflashcomp[i].size > fw->data + fw->size)
2860 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2861 pflashcomp[i].size, 0);
2863 dev_err(dev, "Flashing section type 0x%x failed\n",
2864 pflashcomp[i].img_type);
2871 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2873 u32 img_type = le32_to_cpu(fsec_entry.type);
2874 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2876 if (img_optype != 0xFFFF)
2880 case IMAGE_FIRMWARE_ISCSI:
2881 img_optype = OPTYPE_ISCSI_ACTIVE;
2883 case IMAGE_BOOT_CODE:
2884 img_optype = OPTYPE_REDBOOT;
2886 case IMAGE_OPTION_ROM_ISCSI:
2887 img_optype = OPTYPE_BIOS;
2889 case IMAGE_OPTION_ROM_PXE:
2890 img_optype = OPTYPE_PXE_BIOS;
2892 case IMAGE_OPTION_ROM_FCOE:
2893 img_optype = OPTYPE_FCOE_BIOS;
2895 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2896 img_optype = OPTYPE_ISCSI_BACKUP;
2899 img_optype = OPTYPE_NCSI_FW;
2901 case IMAGE_FLASHISM_JUMPVECTOR:
2902 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2904 case IMAGE_FIRMWARE_PHY:
2905 img_optype = OPTYPE_SH_PHY_FW;
2907 case IMAGE_REDBOOT_DIR:
2908 img_optype = OPTYPE_REDBOOT_DIR;
2910 case IMAGE_REDBOOT_CONFIG:
2911 img_optype = OPTYPE_REDBOOT_CONFIG;
2914 img_optype = OPTYPE_UFI_DIR;
2923 static int be_flash_skyhawk(struct be_adapter *adapter,
2924 const struct firmware *fw,
2925 struct be_dma_mem *flash_cmd, int num_of_images)
2927 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2928 bool crc_match, old_fw_img, flash_offset_support = true;
2929 struct device *dev = &adapter->pdev->dev;
2930 struct flash_section_info *fsec = NULL;
2931 u32 img_offset, img_size, img_type;
2932 u16 img_optype, flash_optype;
2933 int status, i, filehdr_size;
2936 filehdr_size = sizeof(struct flash_file_hdr_g3);
2937 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2939 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2944 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2945 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2946 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2947 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2948 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2949 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2951 if (img_optype == 0xFFFF)
2954 if (flash_offset_support)
2955 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2957 flash_optype = img_optype;
2959 /* Don't bother verifying CRC if an old FW image is being
2965 status = be_check_flash_crc(adapter, fw->data, img_offset,
2966 img_size, filehdr_size +
2967 img_hdrs_size, flash_optype,
2969 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2970 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2971 /* The current FW image on the card does not support
2972 * OFFSET based flashing. Retry using older mechanism
2973 * of OPTYPE based flashing
2975 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2976 flash_offset_support = false;
2980 /* The current FW image on the card does not recognize
2981 * the new FLASH op_type. The FW download is partially
2982 * complete. Reboot the server now to enable FW image
2983 * to recognize the new FLASH op_type. To complete the
2984 * remaining process, download the same FW again after
2987 dev_err(dev, "Flash incomplete. Reset the server\n");
2988 dev_err(dev, "Download FW image again after reset\n");
2990 } else if (status) {
2991 dev_err(dev, "Could not get CRC for 0x%x region\n",
3000 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
3001 if (p + img_size > fw->data + fw->size)
3004 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
3007 /* The current FW image on the card does not support OFFSET
3008 * based flashing. Retry using older mechanism of OPTYPE based
3011 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
3012 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
3013 flash_offset_support = false;
3017 /* For old FW images ignore ILLEGAL_FIELD error or errors on
3021 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3022 (img_optype == OPTYPE_UFI_DIR &&
3023 base_status(status) == MCC_STATUS_FAILED))) {
3025 } else if (status) {
3026 dev_err(dev, "Flashing section type 0x%x failed\n",
3029 switch (addl_status(status)) {
3030 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3032 "Digital signature missing in FW\n");
3034 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3036 "Invalid digital signature in FW\n");
3046 int lancer_fw_download(struct be_adapter *adapter,
3047 const struct firmware *fw)
3049 struct device *dev = &adapter->pdev->dev;
3050 struct be_dma_mem flash_cmd;
3051 const u8 *data_ptr = NULL;
3052 u8 *dest_image_ptr = NULL;
3053 size_t image_size = 0;
3055 u32 data_written = 0;
3061 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3062 dev_err(dev, "FW image size should be multiple of 4\n");
3066 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3067 + LANCER_FW_DOWNLOAD_CHUNK;
3068 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3069 &flash_cmd.dma, GFP_KERNEL);
3073 dest_image_ptr = flash_cmd.va +
3074 sizeof(struct lancer_cmd_req_write_object);
3075 image_size = fw->size;
3076 data_ptr = fw->data;
3078 while (image_size) {
3079 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3081 /* Copy the image chunk content. */
3082 memcpy(dest_image_ptr, data_ptr, chunk_size);
3084 status = lancer_cmd_write_object(adapter, &flash_cmd,
3086 LANCER_FW_DOWNLOAD_LOCATION,
3087 &data_written, &change_status,
3092 offset += data_written;
3093 data_ptr += data_written;
3094 image_size -= data_written;
3098 /* Commit the FW written */
3099 status = lancer_cmd_write_object(adapter, &flash_cmd,
3101 LANCER_FW_DOWNLOAD_LOCATION,
3102 &data_written, &change_status,
3106 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3108 dev_err(dev, "Firmware load error\n");
3109 return be_cmd_status(status);
3112 dev_info(dev, "Firmware flashed successfully\n");
3114 if (change_status == LANCER_FW_RESET_NEEDED) {
3115 dev_info(dev, "Resetting adapter to activate new FW\n");
3116 status = lancer_physdev_ctrl(adapter,
3117 PHYSDEV_CONTROL_FW_RESET_MASK);
3119 dev_err(dev, "Adapter busy, could not reset FW\n");
3120 dev_err(dev, "Reboot server to activate new FW\n");
3122 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3123 dev_info(dev, "Reboot server to activate new FW\n");
3129 /* Check if the flash image file is compatible with the adapter that
3132 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3133 struct flash_file_hdr_g3 *fhdr)
3136 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3140 /* First letter of the build version is used to identify
3141 * which chip this image file is meant for.
3143 switch (fhdr->build[0]) {
3144 case BLD_STR_UFI_TYPE_SH:
3145 if (!skyhawk_chip(adapter))
3148 case BLD_STR_UFI_TYPE_BE3:
3149 if (!BE3_chip(adapter))
3152 case BLD_STR_UFI_TYPE_BE2:
3153 if (!BE2_chip(adapter))
3160 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3161 * asic_rev of the chips it is compatible with.
3162 * When asic_type_rev is 0 the image is compatible only with
3163 * pre-BE3-R chips (asic_rev < 0x10)
3165 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3166 return adapter->asic_rev < 0x10;
3168 return (fhdr->asic_type_rev >= adapter->asic_rev);
3171 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3173 struct device *dev = &adapter->pdev->dev;
3174 struct flash_file_hdr_g3 *fhdr3;
3175 struct image_hdr *img_hdr_ptr;
3176 int status = 0, i, num_imgs;
3177 struct be_dma_mem flash_cmd;
3179 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3180 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3181 dev_err(dev, "Flash image is not compatible with adapter\n");
3185 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3186 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3191 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3192 for (i = 0; i < num_imgs; i++) {
3193 img_hdr_ptr = (struct image_hdr *)(fw->data +
3194 (sizeof(struct flash_file_hdr_g3) +
3195 i * sizeof(struct image_hdr)));
3196 if (!BE2_chip(adapter) &&
3197 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3200 if (skyhawk_chip(adapter))
3201 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3204 status = be_flash_BEx(adapter, fw, &flash_cmd,
3208 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3210 dev_info(dev, "Firmware flashed successfully\n");
3215 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3216 struct be_dma_mem *nonemb_cmd)
3218 struct be_mcc_wrb *wrb;
3219 struct be_cmd_req_acpi_wol_magic_config *req;
3222 mutex_lock(&adapter->mcc_lock);
3224 wrb = wrb_from_mccq(adapter);
3229 req = nonemb_cmd->va;
3231 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3232 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3234 memcpy(req->magic_mac, mac, ETH_ALEN);
3236 status = be_mcc_notify_wait(adapter);
3239 mutex_unlock(&adapter->mcc_lock);
3243 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3244 u8 loopback_type, u8 enable)
3246 struct be_mcc_wrb *wrb;
3247 struct be_cmd_req_set_lmode *req;
3250 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3251 CMD_SUBSYSTEM_LOWLEVEL))
3254 mutex_lock(&adapter->mcc_lock);
3256 wrb = wrb_from_mccq(adapter);
3262 req = embedded_payload(wrb);
3264 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3265 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3268 req->src_port = port_num;
3269 req->dest_port = port_num;
3270 req->loopback_type = loopback_type;
3271 req->loopback_state = enable;
3273 status = be_mcc_notify(adapter);
3277 mutex_unlock(&adapter->mcc_lock);
3279 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3280 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3281 status = -ETIMEDOUT;
3286 mutex_unlock(&adapter->mcc_lock);
3290 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3291 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3294 struct be_mcc_wrb *wrb;
3295 struct be_cmd_req_loopback_test *req;
3296 struct be_cmd_resp_loopback_test *resp;
3299 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3300 CMD_SUBSYSTEM_LOWLEVEL))
3303 mutex_lock(&adapter->mcc_lock);
3305 wrb = wrb_from_mccq(adapter);
3311 req = embedded_payload(wrb);
3313 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3314 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3317 req->hdr.timeout = cpu_to_le32(15);
3318 req->pattern = cpu_to_le64(pattern);
3319 req->src_port = cpu_to_le32(port_num);
3320 req->dest_port = cpu_to_le32(port_num);
3321 req->pkt_size = cpu_to_le32(pkt_size);
3322 req->num_pkts = cpu_to_le32(num_pkts);
3323 req->loopback_type = cpu_to_le32(loopback_type);
3325 status = be_mcc_notify(adapter);
3329 mutex_unlock(&adapter->mcc_lock);
3331 wait_for_completion(&adapter->et_cmd_compl);
3332 resp = embedded_payload(wrb);
3333 status = le32_to_cpu(resp->status);
3337 mutex_unlock(&adapter->mcc_lock);
3341 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3342 u32 byte_cnt, struct be_dma_mem *cmd)
3344 struct be_mcc_wrb *wrb;
3345 struct be_cmd_req_ddrdma_test *req;
3349 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3350 CMD_SUBSYSTEM_LOWLEVEL))
3353 mutex_lock(&adapter->mcc_lock);
3355 wrb = wrb_from_mccq(adapter);
3361 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3362 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3365 req->pattern = cpu_to_le64(pattern);
3366 req->byte_count = cpu_to_le32(byte_cnt);
3367 for (i = 0; i < byte_cnt; i++) {
3368 req->snd_buff[i] = (u8)(pattern >> (j*8));
3374 status = be_mcc_notify_wait(adapter);
3377 struct be_cmd_resp_ddrdma_test *resp;
3380 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3387 mutex_unlock(&adapter->mcc_lock);
3391 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3392 struct be_dma_mem *nonemb_cmd)
3394 struct be_mcc_wrb *wrb;
3395 struct be_cmd_req_seeprom_read *req;
3398 mutex_lock(&adapter->mcc_lock);
3400 wrb = wrb_from_mccq(adapter);
3405 req = nonemb_cmd->va;
3407 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3408 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3411 status = be_mcc_notify_wait(adapter);
3414 mutex_unlock(&adapter->mcc_lock);
3418 int be_cmd_get_phy_info(struct be_adapter *adapter)
3420 struct be_mcc_wrb *wrb;
3421 struct be_cmd_req_get_phy_info *req;
3422 struct be_dma_mem cmd;
3425 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3426 CMD_SUBSYSTEM_COMMON))
3429 mutex_lock(&adapter->mcc_lock);
3431 wrb = wrb_from_mccq(adapter);
3436 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3437 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3440 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3447 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3448 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3451 status = be_mcc_notify_wait(adapter);
3453 struct be_phy_info *resp_phy_info =
3454 cmd.va + sizeof(struct be_cmd_req_hdr);
3456 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3457 adapter->phy.interface_type =
3458 le16_to_cpu(resp_phy_info->interface_type);
3459 adapter->phy.auto_speeds_supported =
3460 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3461 adapter->phy.fixed_speeds_supported =
3462 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3463 adapter->phy.misc_params =
3464 le32_to_cpu(resp_phy_info->misc_params);
3466 if (BE2_chip(adapter)) {
3467 adapter->phy.fixed_speeds_supported =
3468 BE_SUPPORTED_SPEED_10GBPS |
3469 BE_SUPPORTED_SPEED_1GBPS;
3472 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3474 mutex_unlock(&adapter->mcc_lock);
3478 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3480 struct be_mcc_wrb *wrb;
3481 struct be_cmd_req_set_qos *req;
3484 mutex_lock(&adapter->mcc_lock);
3486 wrb = wrb_from_mccq(adapter);
3492 req = embedded_payload(wrb);
3494 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3495 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3497 req->hdr.domain = domain;
3498 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3499 req->max_bps_nic = cpu_to_le32(bps);
3501 status = be_mcc_notify_wait(adapter);
3504 mutex_unlock(&adapter->mcc_lock);
3508 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3510 struct be_mcc_wrb *wrb;
3511 struct be_cmd_req_cntl_attribs *req;
3512 struct be_cmd_resp_cntl_attribs *resp;
3514 int payload_len = max(sizeof(*req), sizeof(*resp));
3515 struct mgmt_controller_attrib *attribs;
3516 struct be_dma_mem attribs_cmd;
3519 if (mutex_lock_interruptible(&adapter->mbox_lock))
3522 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3523 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3524 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3526 &attribs_cmd.dma, GFP_ATOMIC);
3527 if (!attribs_cmd.va) {
3528 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3533 wrb = wrb_from_mbox(adapter);
3538 req = attribs_cmd.va;
3540 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3541 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3544 status = be_mbox_notify_wait(adapter);
3546 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3547 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3548 serial_num = attribs->hba_attribs.controller_serial_number;
3549 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3550 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3552 /* For BEx, since GET_FUNC_CONFIG command is not
3553 * supported, we read funcnum here as a workaround.
3555 if (BEx_chip(adapter))
3556 adapter->pf_num = attribs->hba_attribs.pci_funcnum;
3560 mutex_unlock(&adapter->mbox_lock);
3562 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3563 attribs_cmd.va, attribs_cmd.dma);
3568 int be_cmd_req_native_mode(struct be_adapter *adapter)
3570 struct be_mcc_wrb *wrb;
3571 struct be_cmd_req_set_func_cap *req;
3574 if (mutex_lock_interruptible(&adapter->mbox_lock))
3577 wrb = wrb_from_mbox(adapter);
3583 req = embedded_payload(wrb);
3585 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3586 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3587 sizeof(*req), wrb, NULL);
3589 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3590 CAPABILITY_BE3_NATIVE_ERX_API);
3591 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3593 status = be_mbox_notify_wait(adapter);
3595 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3597 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3598 CAPABILITY_BE3_NATIVE_ERX_API;
3599 if (!adapter->be3_native)
3600 dev_warn(&adapter->pdev->dev,
3601 "adapter not in advanced mode\n");
3604 mutex_unlock(&adapter->mbox_lock);
3608 /* Get privilege(s) for a function */
3609 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3612 struct be_mcc_wrb *wrb;
3613 struct be_cmd_req_get_fn_privileges *req;
3616 mutex_lock(&adapter->mcc_lock);
3618 wrb = wrb_from_mccq(adapter);
3624 req = embedded_payload(wrb);
3626 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3627 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3630 req->hdr.domain = domain;
3632 status = be_mcc_notify_wait(adapter);
3634 struct be_cmd_resp_get_fn_privileges *resp =
3635 embedded_payload(wrb);
3637 *privilege = le32_to_cpu(resp->privilege_mask);
3639 /* In UMC mode FW does not return right privileges.
3640 * Override with correct privilege equivalent to PF.
3642 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3644 *privilege = MAX_PRIVILEGES;
3648 mutex_unlock(&adapter->mcc_lock);
3652 /* Set privilege(s) for a function */
3653 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3656 struct be_mcc_wrb *wrb;
3657 struct be_cmd_req_set_fn_privileges *req;
3660 mutex_lock(&adapter->mcc_lock);
3662 wrb = wrb_from_mccq(adapter);
3668 req = embedded_payload(wrb);
3669 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3670 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3672 req->hdr.domain = domain;
3673 if (lancer_chip(adapter))
3674 req->privileges_lancer = cpu_to_le32(privileges);
3676 req->privileges = cpu_to_le32(privileges);
3678 status = be_mcc_notify_wait(adapter);
3680 mutex_unlock(&adapter->mcc_lock);
3684 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3685 * pmac_id_valid: false => pmac_id or MAC address is requested.
3686 * If pmac_id is returned, pmac_id_valid is returned as true
3688 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3689 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3692 struct be_mcc_wrb *wrb;
3693 struct be_cmd_req_get_mac_list *req;
3696 struct be_dma_mem get_mac_list_cmd;
3699 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3700 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3701 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3702 get_mac_list_cmd.size,
3703 &get_mac_list_cmd.dma,
3706 if (!get_mac_list_cmd.va) {
3707 dev_err(&adapter->pdev->dev,
3708 "Memory allocation failure during GET_MAC_LIST\n");
3712 mutex_lock(&adapter->mcc_lock);
3714 wrb = wrb_from_mccq(adapter);
3720 req = get_mac_list_cmd.va;
3722 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3723 OPCODE_COMMON_GET_MAC_LIST,
3724 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3725 req->hdr.domain = domain;
3726 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3727 if (*pmac_id_valid) {
3728 req->mac_id = cpu_to_le32(*pmac_id);
3729 req->iface_id = cpu_to_le16(if_handle);
3730 req->perm_override = 0;
3732 req->perm_override = 1;
3735 status = be_mcc_notify_wait(adapter);
3737 struct be_cmd_resp_get_mac_list *resp =
3738 get_mac_list_cmd.va;
3740 if (*pmac_id_valid) {
3741 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3746 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3747 /* Mac list returned could contain one or more active mac_ids
3748 * or one or more true or pseudo permanent mac addresses.
3749 * If an active mac_id is present, return first active mac_id
3752 for (i = 0; i < mac_count; i++) {
3753 struct get_list_macaddr *mac_entry;
3757 mac_entry = &resp->macaddr_list[i];
3758 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3759 /* mac_id is a 32 bit value and mac_addr size
3762 if (mac_addr_size == sizeof(u32)) {
3763 *pmac_id_valid = true;
3764 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3765 *pmac_id = le32_to_cpu(mac_id);
3769 /* If no active mac_id found, return first mac addr */
3770 *pmac_id_valid = false;
3771 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3776 mutex_unlock(&adapter->mcc_lock);
3777 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3778 get_mac_list_cmd.va, get_mac_list_cmd.dma);
3782 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3783 u8 *mac, u32 if_handle, bool active, u32 domain)
3786 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3788 if (BEx_chip(adapter))
3789 return be_cmd_mac_addr_query(adapter, mac, false,
3790 if_handle, curr_pmac_id);
3792 /* Fetch the MAC address using pmac_id */
3793 return be_cmd_get_mac_from_list(adapter, mac, &active,
3798 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3801 bool pmac_valid = false;
3805 if (BEx_chip(adapter)) {
3806 if (be_physfn(adapter))
3807 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3810 status = be_cmd_mac_addr_query(adapter, mac, false,
3811 adapter->if_handle, 0);
3813 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3814 NULL, adapter->if_handle, 0);
3820 /* Uses synchronous MCCQ */
3821 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3822 u8 mac_count, u32 domain)
3824 struct be_mcc_wrb *wrb;
3825 struct be_cmd_req_set_mac_list *req;
3827 struct be_dma_mem cmd;
3829 memset(&cmd, 0, sizeof(struct be_dma_mem));
3830 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3831 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3836 mutex_lock(&adapter->mcc_lock);
3838 wrb = wrb_from_mccq(adapter);
3845 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3846 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3849 req->hdr.domain = domain;
3850 req->mac_count = mac_count;
3852 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3854 status = be_mcc_notify_wait(adapter);
3857 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3858 mutex_unlock(&adapter->mcc_lock);
3862 /* Wrapper to delete any active MACs and provision the new mac.
3863 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3864 * current list are active.
3866 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3868 bool active_mac = false;
3869 u8 old_mac[ETH_ALEN];
3873 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3874 &pmac_id, if_id, dom);
3876 if (!status && active_mac)
3877 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3879 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3882 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3883 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3885 struct be_mcc_wrb *wrb;
3886 struct be_cmd_req_set_hsw_config *req;
3890 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3891 CMD_SUBSYSTEM_COMMON))
3894 mutex_lock(&adapter->mcc_lock);
3896 wrb = wrb_from_mccq(adapter);
3902 req = embedded_payload(wrb);
3903 ctxt = &req->context;
3905 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3906 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3909 req->hdr.domain = domain;
3910 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3912 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3913 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3916 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3917 ctxt, adapter->hba_port_num);
3918 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3919 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3923 /* Enable/disable both mac and vlan spoof checking */
3924 if (!BEx_chip(adapter) && spoofchk) {
3925 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3927 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3931 be_dws_cpu_to_le(req->context, sizeof(req->context));
3932 status = be_mcc_notify_wait(adapter);
3935 mutex_unlock(&adapter->mcc_lock);
3939 /* Get Hyper switch config */
3940 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3941 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3943 struct be_mcc_wrb *wrb;
3944 struct be_cmd_req_get_hsw_config *req;
3949 mutex_lock(&adapter->mcc_lock);
3951 wrb = wrb_from_mccq(adapter);
3957 req = embedded_payload(wrb);
3958 ctxt = &req->context;
3960 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3961 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3964 req->hdr.domain = domain;
3965 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3967 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3969 if (!BEx_chip(adapter) && mode) {
3970 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3971 ctxt, adapter->hba_port_num);
3972 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3974 be_dws_cpu_to_le(req->context, sizeof(req->context));
3976 status = be_mcc_notify_wait(adapter);
3978 struct be_cmd_resp_get_hsw_config *resp =
3979 embedded_payload(wrb);
3981 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3982 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3983 pvid, &resp->context);
3985 *pvid = le16_to_cpu(vid);
3987 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3988 port_fwd_type, &resp->context);
3991 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3992 spoofchk, &resp->context);
3996 mutex_unlock(&adapter->mcc_lock);
4000 static bool be_is_wol_excluded(struct be_adapter *adapter)
4002 struct pci_dev *pdev = adapter->pdev;
4004 if (be_virtfn(adapter))
4007 switch (pdev->subsystem_device) {
4008 case OC_SUBSYS_DEVICE_ID1:
4009 case OC_SUBSYS_DEVICE_ID2:
4010 case OC_SUBSYS_DEVICE_ID3:
4011 case OC_SUBSYS_DEVICE_ID4:
4018 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
4020 struct be_mcc_wrb *wrb;
4021 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
4023 struct be_dma_mem cmd;
4025 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4029 if (be_is_wol_excluded(adapter))
4032 if (mutex_lock_interruptible(&adapter->mbox_lock))
4035 memset(&cmd, 0, sizeof(struct be_dma_mem));
4036 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
4037 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4040 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4045 wrb = wrb_from_mbox(adapter);
4053 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4054 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4055 sizeof(*req), wrb, &cmd);
4057 req->hdr.version = 1;
4058 req->query_options = BE_GET_WOL_CAP;
4060 status = be_mbox_notify_wait(adapter);
4062 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4064 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4066 adapter->wol_cap = resp->wol_settings;
4068 /* Non-zero macaddr indicates WOL is enabled */
4069 if (adapter->wol_cap & BE_WOL_CAP &&
4070 !is_zero_ether_addr(resp->magic_mac))
4071 adapter->wol_en = true;
4074 mutex_unlock(&adapter->mbox_lock);
4076 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4082 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4084 struct be_dma_mem extfat_cmd;
4085 struct be_fat_conf_params *cfgs;
4089 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4090 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4091 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4092 extfat_cmd.size, &extfat_cmd.dma,
4097 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4101 cfgs = (struct be_fat_conf_params *)
4102 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4103 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4104 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4106 for (j = 0; j < num_modes; j++) {
4107 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4108 cfgs->module[i].trace_lvl[j].dbg_lvl =
4113 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4115 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4120 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4122 struct be_dma_mem extfat_cmd;
4123 struct be_fat_conf_params *cfgs;
4127 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4128 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4129 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4130 extfat_cmd.size, &extfat_cmd.dma,
4133 if (!extfat_cmd.va) {
4134 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4139 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4141 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4142 sizeof(struct be_cmd_resp_hdr));
4144 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4145 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4146 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4149 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4155 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4156 struct be_dma_mem *cmd)
4158 struct be_mcc_wrb *wrb;
4159 struct be_cmd_req_get_ext_fat_caps *req;
4162 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4163 CMD_SUBSYSTEM_COMMON))
4166 if (mutex_lock_interruptible(&adapter->mbox_lock))
4169 wrb = wrb_from_mbox(adapter);
4176 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4177 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4178 cmd->size, wrb, cmd);
4179 req->parameter_type = cpu_to_le32(1);
4181 status = be_mbox_notify_wait(adapter);
4183 mutex_unlock(&adapter->mbox_lock);
4187 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4188 struct be_dma_mem *cmd,
4189 struct be_fat_conf_params *configs)
4191 struct be_mcc_wrb *wrb;
4192 struct be_cmd_req_set_ext_fat_caps *req;
4195 mutex_lock(&adapter->mcc_lock);
4197 wrb = wrb_from_mccq(adapter);
4204 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4205 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4206 OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
4207 cmd->size, wrb, cmd);
4209 status = be_mcc_notify_wait(adapter);
4211 mutex_unlock(&adapter->mcc_lock);
4215 int be_cmd_query_port_name(struct be_adapter *adapter)
4217 struct be_cmd_req_get_port_name *req;
4218 struct be_mcc_wrb *wrb;
4221 if (mutex_lock_interruptible(&adapter->mbox_lock))
4224 wrb = wrb_from_mbox(adapter);
4225 req = embedded_payload(wrb);
4227 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4228 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4230 if (!BEx_chip(adapter))
4231 req->hdr.version = 1;
4233 status = be_mbox_notify_wait(adapter);
4235 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4237 adapter->port_name = resp->port_name[adapter->hba_port_num];
4239 adapter->port_name = adapter->hba_port_num + '0';
4242 mutex_unlock(&adapter->mbox_lock);
4246 /* When more than 1 NIC descriptor is present in the descriptor list,
4247 * the caller must specify the pf_num to obtain the NIC descriptor
4248 * corresponding to its pci function.
4249 * get_vft must be true when the caller wants the VF-template desc of the
4251 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4252 * that only it's NIC descriptor is present in the descriptor list.
4254 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4255 bool get_vft, u8 pf_num)
4257 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4258 struct be_nic_res_desc *nic;
4261 for (i = 0; i < desc_count; i++) {
4262 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4263 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4264 nic = (struct be_nic_res_desc *)hdr;
4266 if ((pf_num == PF_NUM_IGNORE ||
4267 nic->pf_num == pf_num) &&
4268 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4271 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4272 hdr = (void *)hdr + hdr->desc_len;
4277 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4280 return be_get_nic_desc(buf, desc_count, true, pf_num);
4283 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4286 return be_get_nic_desc(buf, desc_count, false, pf_num);
4289 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4292 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4293 struct be_pcie_res_desc *pcie;
4296 for (i = 0; i < desc_count; i++) {
4297 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4298 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4299 pcie = (struct be_pcie_res_desc *)hdr;
4300 if (pcie->pf_num == pf_num)
4304 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4305 hdr = (void *)hdr + hdr->desc_len;
4310 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4312 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4315 for (i = 0; i < desc_count; i++) {
4316 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4317 return (struct be_port_res_desc *)hdr;
4319 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4320 hdr = (void *)hdr + hdr->desc_len;
4325 static void be_copy_nic_desc(struct be_resources *res,
4326 struct be_nic_res_desc *desc)
4328 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4329 res->max_vlans = le16_to_cpu(desc->vlan_count);
4330 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4331 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4332 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4333 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4334 res->max_evt_qs = le16_to_cpu(desc->eq_count);
4335 res->max_cq_count = le16_to_cpu(desc->cq_count);
4336 res->max_iface_count = le16_to_cpu(desc->iface_count);
4337 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4338 /* Clear flags that driver is not interested in */
4339 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4340 BE_IF_CAP_FLAGS_WANT;
4344 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4346 struct be_mcc_wrb *wrb;
4347 struct be_cmd_req_get_func_config *req;
4349 struct be_dma_mem cmd;
4351 if (mutex_lock_interruptible(&adapter->mbox_lock))
4354 memset(&cmd, 0, sizeof(struct be_dma_mem));
4355 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4356 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4359 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4364 wrb = wrb_from_mbox(adapter);
4372 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4373 OPCODE_COMMON_GET_FUNC_CONFIG,
4374 cmd.size, wrb, &cmd);
4376 if (skyhawk_chip(adapter))
4377 req->hdr.version = 1;
4379 status = be_mbox_notify_wait(adapter);
4381 struct be_cmd_resp_get_func_config *resp = cmd.va;
4382 u32 desc_count = le32_to_cpu(resp->desc_count);
4383 struct be_nic_res_desc *desc;
4385 /* GET_FUNC_CONFIG returns resource descriptors of the
4386 * current function only. So, pf_num should be set to
4389 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4396 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4397 adapter->pf_num = desc->pf_num;
4398 adapter->vf_num = desc->vf_num;
4401 be_copy_nic_desc(res, desc);
4404 mutex_unlock(&adapter->mbox_lock);
4406 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4411 /* This routine returns a list of all the NIC PF_nums in the adapter */
4412 static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4414 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4415 struct be_pcie_res_desc *pcie = NULL;
4417 u16 nic_pf_count = 0;
4419 for (i = 0; i < desc_count; i++) {
4420 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4421 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4422 pcie = (struct be_pcie_res_desc *)hdr;
4423 if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4424 pcie->pf_type == MISSION_RDMA)) {
4425 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4429 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4430 hdr = (void *)hdr + hdr->desc_len;
4432 return nic_pf_count;
4435 /* Will use MBOX only if MCCQ has not been created */
4436 int be_cmd_get_profile_config(struct be_adapter *adapter,
4437 struct be_resources *res,
4438 struct be_port_resources *port_res,
4439 u8 profile_type, u8 query, u8 domain)
4441 struct be_cmd_resp_get_profile_config *resp;
4442 struct be_cmd_req_get_profile_config *req;
4443 struct be_nic_res_desc *vf_res;
4444 struct be_pcie_res_desc *pcie;
4445 struct be_port_res_desc *port;
4446 struct be_nic_res_desc *nic;
4447 struct be_mcc_wrb wrb = {0};
4448 struct be_dma_mem cmd;
4452 memset(&cmd, 0, sizeof(struct be_dma_mem));
4453 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4454 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4460 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4461 OPCODE_COMMON_GET_PROFILE_CONFIG,
4462 cmd.size, &wrb, &cmd);
4464 if (!lancer_chip(adapter))
4465 req->hdr.version = 1;
4466 req->type = profile_type;
4467 req->hdr.domain = domain;
4469 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4470 * descriptors with all bits set to "1" for the fields which can be
4471 * modified using SET_PROFILE_CONFIG cmd.
4473 if (query == RESOURCE_MODIFIABLE)
4474 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4476 status = be_cmd_notify_wait(adapter, &wrb);
4481 desc_count = le16_to_cpu(resp->desc_count);
4484 u16 nic_pf_cnt = 0, i;
4485 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4487 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4491 for (i = 0; i < nic_pf_cnt; i++) {
4492 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4493 nic_pf_num_list[i]);
4494 if (nic->link_param == adapter->port_num) {
4495 port_res->nic_pfs++;
4496 pcie = be_get_pcie_desc(resp->func_param,
4498 nic_pf_num_list[i]);
4499 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4505 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4508 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4510 port = be_get_port_desc(resp->func_param, desc_count);
4512 adapter->mc_type = port->mc_type;
4514 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4517 be_copy_nic_desc(res, nic);
4519 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4522 res->vf_if_cap_flags = vf_res->cap_flags;
4525 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4530 /* Will use MBOX only if MCCQ has not been created */
4531 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4532 int size, int count, u8 version, u8 domain)
4534 struct be_cmd_req_set_profile_config *req;
4535 struct be_mcc_wrb wrb = {0};
4536 struct be_dma_mem cmd;
4539 memset(&cmd, 0, sizeof(struct be_dma_mem));
4540 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4541 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4547 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4548 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4550 req->hdr.version = version;
4551 req->hdr.domain = domain;
4552 req->desc_count = cpu_to_le32(count);
4553 memcpy(req->desc, desc, size);
4555 status = be_cmd_notify_wait(adapter, &wrb);
4558 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4563 /* Mark all fields invalid */
4564 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4566 memset(nic, 0, sizeof(*nic));
4567 nic->unicast_mac_count = 0xFFFF;
4568 nic->mcc_count = 0xFFFF;
4569 nic->vlan_count = 0xFFFF;
4570 nic->mcast_mac_count = 0xFFFF;
4571 nic->txq_count = 0xFFFF;
4572 nic->rq_count = 0xFFFF;
4573 nic->rssq_count = 0xFFFF;
4574 nic->lro_count = 0xFFFF;
4575 nic->cq_count = 0xFFFF;
4576 nic->toe_conn_count = 0xFFFF;
4577 nic->eq_count = 0xFFFF;
4578 nic->iface_count = 0xFFFF;
4579 nic->link_param = 0xFF;
4580 nic->channel_id_param = cpu_to_le16(0xF000);
4581 nic->acpi_params = 0xFF;
4582 nic->wol_param = 0x0F;
4583 nic->tunnel_iface_count = 0xFFFF;
4584 nic->direct_tenant_iface_count = 0xFFFF;
4585 nic->bw_min = 0xFFFFFFFF;
4586 nic->bw_max = 0xFFFFFFFF;
4589 /* Mark all fields invalid */
4590 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4592 memset(pcie, 0, sizeof(*pcie));
4593 pcie->sriov_state = 0xFF;
4594 pcie->pf_state = 0xFF;
4595 pcie->pf_type = 0xFF;
4596 pcie->num_vfs = 0xFFFF;
4599 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4602 struct be_nic_res_desc nic_desc;
4606 if (BE3_chip(adapter))
4607 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4609 be_reset_nic_desc(&nic_desc);
4610 nic_desc.pf_num = adapter->pf_num;
4611 nic_desc.vf_num = domain;
4612 nic_desc.bw_min = 0;
4613 if (lancer_chip(adapter)) {
4614 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4615 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4616 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4618 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4621 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4622 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4623 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4624 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4625 nic_desc.bw_max = cpu_to_le32(bw_percent);
4628 return be_cmd_set_profile_config(adapter, &nic_desc,
4629 nic_desc.hdr.desc_len,
4630 1, version, domain);
4633 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4634 struct be_resources pool_res, u16 num_vfs,
4635 struct be_resources *vft_res)
4638 struct be_pcie_res_desc pcie;
4639 struct be_nic_res_desc nic_vft;
4642 /* PF PCIE descriptor */
4643 be_reset_pcie_desc(&desc.pcie);
4644 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4645 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4646 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4647 desc.pcie.pf_num = adapter->pdev->devfn;
4648 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4649 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4651 /* VF NIC Template descriptor */
4652 be_reset_nic_desc(&desc.nic_vft);
4653 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4654 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4655 desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4656 BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4657 desc.nic_vft.pf_num = adapter->pdev->devfn;
4658 desc.nic_vft.vf_num = 0;
4659 desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4660 desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4661 desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4662 desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4663 desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4665 if (vft_res->max_uc_mac)
4666 desc.nic_vft.unicast_mac_count =
4667 cpu_to_le16(vft_res->max_uc_mac);
4668 if (vft_res->max_vlans)
4669 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4670 if (vft_res->max_iface_count)
4671 desc.nic_vft.iface_count =
4672 cpu_to_le16(vft_res->max_iface_count);
4673 if (vft_res->max_mcc_count)
4674 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
4676 return be_cmd_set_profile_config(adapter, &desc,
4677 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4680 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4682 struct be_mcc_wrb *wrb;
4683 struct be_cmd_req_manage_iface_filters *req;
4686 if (iface == 0xFFFFFFFF)
4689 mutex_lock(&adapter->mcc_lock);
4691 wrb = wrb_from_mccq(adapter);
4696 req = embedded_payload(wrb);
4698 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4699 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4702 req->target_iface_id = cpu_to_le32(iface);
4704 status = be_mcc_notify_wait(adapter);
4706 mutex_unlock(&adapter->mcc_lock);
4710 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4712 struct be_port_res_desc port_desc;
4714 memset(&port_desc, 0, sizeof(port_desc));
4715 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4716 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4717 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4718 port_desc.link_num = adapter->hba_port_num;
4720 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4722 port_desc.nv_port = swab16(port);
4724 port_desc.nv_flags = NV_TYPE_DISABLED;
4725 port_desc.nv_port = 0;
4728 return be_cmd_set_profile_config(adapter, &port_desc,
4729 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4732 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4735 struct be_mcc_wrb *wrb;
4736 struct be_cmd_req_get_iface_list *req;
4737 struct be_cmd_resp_get_iface_list *resp;
4740 mutex_lock(&adapter->mcc_lock);
4742 wrb = wrb_from_mccq(adapter);
4747 req = embedded_payload(wrb);
4749 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4750 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4752 req->hdr.domain = vf_num + 1;
4754 status = be_mcc_notify_wait(adapter);
4756 resp = (struct be_cmd_resp_get_iface_list *)req;
4757 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4761 mutex_unlock(&adapter->mcc_lock);
4765 static int lancer_wait_idle(struct be_adapter *adapter)
4767 #define SLIPORT_IDLE_TIMEOUT 30
4771 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4772 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4773 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4779 if (i == SLIPORT_IDLE_TIMEOUT)
4785 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4789 status = lancer_wait_idle(adapter);
4793 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4798 /* Routine to check whether dump image is present or not */
4799 bool dump_present(struct be_adapter *adapter)
4801 u32 sliport_status = 0;
4803 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4804 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4807 int lancer_initiate_dump(struct be_adapter *adapter)
4809 struct device *dev = &adapter->pdev->dev;
4812 if (dump_present(adapter)) {
4813 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4817 /* give firmware reset and diagnostic dump */
4818 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4819 PHYSDEV_CONTROL_DD_MASK);
4821 dev_err(dev, "FW reset failed\n");
4825 status = lancer_wait_idle(adapter);
4829 if (!dump_present(adapter)) {
4830 dev_err(dev, "FW dump not generated\n");
4837 int lancer_delete_dump(struct be_adapter *adapter)
4841 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4842 return be_cmd_status(status);
4846 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4848 struct be_mcc_wrb *wrb;
4849 struct be_cmd_enable_disable_vf *req;
4852 if (BEx_chip(adapter))
4855 mutex_lock(&adapter->mcc_lock);
4857 wrb = wrb_from_mccq(adapter);
4863 req = embedded_payload(wrb);
4865 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4866 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4869 req->hdr.domain = domain;
4871 status = be_mcc_notify_wait(adapter);
4873 mutex_unlock(&adapter->mcc_lock);
4877 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4879 struct be_mcc_wrb *wrb;
4880 struct be_cmd_req_intr_set *req;
4883 if (mutex_lock_interruptible(&adapter->mbox_lock))
4886 wrb = wrb_from_mbox(adapter);
4888 req = embedded_payload(wrb);
4890 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4891 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4894 req->intr_enabled = intr_enable;
4896 status = be_mbox_notify_wait(adapter);
4898 mutex_unlock(&adapter->mbox_lock);
4903 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4905 struct be_cmd_req_get_active_profile *req;
4906 struct be_mcc_wrb *wrb;
4909 if (mutex_lock_interruptible(&adapter->mbox_lock))
4912 wrb = wrb_from_mbox(adapter);
4918 req = embedded_payload(wrb);
4920 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4921 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4924 status = be_mbox_notify_wait(adapter);
4926 struct be_cmd_resp_get_active_profile *resp =
4927 embedded_payload(wrb);
4929 *profile_id = le16_to_cpu(resp->active_profile_id);
4933 mutex_unlock(&adapter->mbox_lock);
4938 __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4939 int link_state, int version, u8 domain)
4941 struct be_mcc_wrb *wrb;
4942 struct be_cmd_req_set_ll_link *req;
4945 mutex_lock(&adapter->mcc_lock);
4947 wrb = wrb_from_mccq(adapter);
4953 req = embedded_payload(wrb);
4955 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4956 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4957 sizeof(*req), wrb, NULL);
4959 req->hdr.version = version;
4960 req->hdr.domain = domain;
4962 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4963 link_state == IFLA_VF_LINK_STATE_AUTO)
4964 req->link_config |= PLINK_ENABLE;
4966 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4967 req->link_config |= PLINK_TRACK;
4969 status = be_mcc_notify_wait(adapter);
4971 mutex_unlock(&adapter->mcc_lock);
4975 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4976 int link_state, u8 domain)
4980 if (BEx_chip(adapter))
4983 status = __be_cmd_set_logical_link_config(adapter, link_state,
4986 /* Version 2 of the command will not be recognized by older FW.
4987 * On such a failure issue version 1 of the command.
4989 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4990 status = __be_cmd_set_logical_link_config(adapter, link_state,
4995 int be_cmd_set_features(struct be_adapter *adapter)
4997 struct be_cmd_resp_set_features *resp;
4998 struct be_cmd_req_set_features *req;
4999 struct be_mcc_wrb *wrb;
5002 if (mutex_lock_interruptible(&adapter->mcc_lock))
5005 wrb = wrb_from_mccq(adapter);
5011 req = embedded_payload(wrb);
5013 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
5014 OPCODE_COMMON_SET_FEATURES,
5015 sizeof(*req), wrb, NULL);
5017 req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
5018 req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
5019 req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
5021 status = be_mcc_notify_wait(adapter);
5025 resp = embedded_payload(wrb);
5027 adapter->error_recovery.ue_to_poll_time =
5028 le16_to_cpu(resp->parameter.resp.ue2rp);
5029 adapter->error_recovery.ue_to_reset_time =
5030 le16_to_cpu(resp->parameter.resp.ue2sr);
5031 adapter->error_recovery.recovery_supported = true;
5033 /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5034 * returns this error in older firmware versions
5036 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5037 base_status(status) == MCC_STATUS_INVALID_LENGTH)
5038 dev_info(&adapter->pdev->dev,
5039 "Adapter does not support HW error recovery\n");
5041 mutex_unlock(&adapter->mcc_lock);
5045 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
5046 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
5048 struct be_adapter *adapter = netdev_priv(netdev_handle);
5049 struct be_mcc_wrb *wrb;
5050 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
5051 struct be_cmd_req_hdr *req;
5052 struct be_cmd_resp_hdr *resp;
5055 mutex_lock(&adapter->mcc_lock);
5057 wrb = wrb_from_mccq(adapter);
5062 req = embedded_payload(wrb);
5063 resp = embedded_payload(wrb);
5065 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5066 hdr->opcode, wrb_payload_size, wrb, NULL);
5067 memcpy(req, wrb_payload, wrb_payload_size);
5068 be_dws_cpu_to_le(req, wrb_payload_size);
5070 status = be_mcc_notify_wait(adapter);
5072 *cmd_status = (status & 0xffff);
5075 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5076 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5078 mutex_unlock(&adapter->mcc_lock);
5081 EXPORT_SYMBOL(be_roce_mcc_cmd);