drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/device.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/vmalloc.h>
  24
  25 #include "hns_dsaf_mac.h"
  26 #include "hns_dsaf_main.h"
  27 #include "hns_dsaf_ppe.h"
  28 #include "hns_dsaf_rcb.h"
  29 #include "hns_dsaf_misc.h"
  30
  31 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  32         [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  33         [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  34         [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  35         [DSAF_MODE_DISABLE_SP] = "single-port",
  36 };
  37
  38 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
  39         { "HISI00B1", 0 },
  40         { "HISI00B2", 0 },
  41         { },
  42 };
  43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
  44
  45 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  46 {
  47         int ret, i;
  48         u32 desc_num;
  49         u32 buf_size;
  50         u32 reset_offset = 0;
  51         u32 res_idx = 0;
  52         const char *mode_str;
  53         struct regmap *syscon;
  54         struct resource *res;
  55         struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
  56         struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
  57
  58         if (dev_of_node(dsaf_dev->dev)) {
  59                 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  60                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  61                 else
  62                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  63         } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
  64                 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
  65                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  66                 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
  67                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  68                 else
  69                         return -ENXIO;
  70         } else {
  71                 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
  72                 return -ENXIO;
  73         }
  74
  75         ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
  76         if (ret) {
  77                 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  78                 return ret;
  79         }
  80         for (i = 0; i < DSAF_MODE_MAX; i++) {
  81                 if (g_dsaf_mode_match[i] &&
  82                     !strcmp(mode_str, g_dsaf_mode_match[i]))
  83                         break;
  84         }
  85         if (i >= DSAF_MODE_MAX ||
  86             i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  87                 dev_err(dsaf_dev->dev,
  88                         "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  89                 return -EINVAL;
  90         }
  91         dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  92
  93         if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  94                 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  95         else
  96                 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  97
  98         if ((i == DSAF_MODE_ENABLE_16VM) ||
  99             (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
 100             (i == DSAF_MODE_DISABLE_6PORT_2VM))
 101                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
 102         else
 103                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
 104
 105         if (dev_of_node(dsaf_dev->dev)) {
 106                 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
 107                 syscon = syscon_node_to_regmap(np_temp);
 108                 of_node_put(np_temp);
 109                 if (IS_ERR_OR_NULL(syscon)) {
 110                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 111                                                     res_idx++);
 112                         if (!res) {
 113                                 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
 114                                 return -ENOMEM;
 115                         }
 116
 117                         dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
 118                                                                   res);
 119                         if (IS_ERR(dsaf_dev->sc_base))
 120                                 return PTR_ERR(dsaf_dev->sc_base);
 121
 122                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 123                                                     res_idx++);
 124                         if (!res) {
 125                                 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
 126                                 return -ENOMEM;
 127                         }
 128
 129                         dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
 130                                                                    res);
 131                         if (IS_ERR(dsaf_dev->sds_base))
 132                                 return PTR_ERR(dsaf_dev->sds_base);
 133                 } else {
 134                         dsaf_dev->sub_ctrl = syscon;
 135                 }
 136         }
 137
 138         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
 139         if (!res) {
 140                 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
 141                 if (!res) {
 142                         dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
 143                         return -ENOMEM;
 144                 }
 145         }
 146         dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
 147         if (IS_ERR(dsaf_dev->ppe_base))
 148                 return PTR_ERR(dsaf_dev->ppe_base);
 149         dsaf_dev->ppe_paddr = res->start;
 150
 151         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 152                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 153                                                    "dsaf-base");
 154                 if (!res) {
 155                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 156                                                     res_idx);
 157                         if (!res) {
 158                                 dev_err(dsaf_dev->dev,
 159                                         "dsaf-base info is needed!\n");
 160                                 return -ENOMEM;
 161                         }
 162                 }
 163                 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
 164                 if (IS_ERR(dsaf_dev->io_base))
 165                         return PTR_ERR(dsaf_dev->io_base);
 166         }
 167
 168         ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
 169         if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
 170             desc_num > HNS_DSAF_MAX_DESC_CNT) {
 171                 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
 172                         desc_num, ret);
 173                 return -EINVAL;
 174         }
 175         dsaf_dev->desc_num = desc_num;
 176
 177         ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
 178                                        &reset_offset);
 179         if (ret < 0) {
 180                 dev_dbg(dsaf_dev->dev,
 181                         "get reset-field-offset fail, ret=%d!\r\n", ret);
 182         }
 183         dsaf_dev->reset_offset = reset_offset;
 184
 185         ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
 186         if (ret < 0) {
 187                 dev_err(dsaf_dev->dev,
 188                         "get buf-size fail, ret=%d!\r\n", ret);
 189                 return ret;
 190         }
 191         dsaf_dev->buf_size = buf_size;
 192
 193         dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
 194         if (dsaf_dev->buf_size_type < 0) {
 195                 dev_err(dsaf_dev->dev,
 196                         "buf_size(%d) is wrong!\n", buf_size);
 197                 return -EINVAL;
 198         }
 199
 200         dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
 201         if (!dsaf_dev->misc_op)
 202                 return -ENOMEM;
 203
 204         if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
 205                 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
 206         else
 207                 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
 208
 209         return 0;
 210 }
 211
 212 /**
 213  * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
 214  * @dsaf_id: dsa fabric id
 215  */
 216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
 217 {
 218         dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
 219 }
 220
 221 /**
 222  * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
 223  * @dsaf_id: dsa fabric id
 224  * @hns_dsaf_reg_cnt_clr_ce: config value
 225  */
 226 static void
 227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
 228 {
 229         dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
 230                          DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
 231 }
 232
 233 /**
 234  * hns_ppe_qid_cfg - config ppe qid
 235  * @dsaf_id: dsa fabric id
 236  * @pppe_qid_cfg: value array
 237  */
 238 static void
 239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
 240 {
 241         u32 i;
 242
 243         for (i = 0; i < DSAF_COMM_CHN; i++) {
 244                 dsaf_set_dev_field(dsaf_dev,
 245                                    DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
 246                                    DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
 247                                    qid_cfg);
 248         }
 249 }
 250
 251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
 252 {
 253         u16 max_q_per_vf, max_vfn;
 254         u32 q_id, q_num_per_port;
 255         u32 i;
 256
 257         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 258         q_num_per_port = max_vfn * max_q_per_vf;
 259
 260         for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
 261                 dsaf_set_dev_field(dsaf_dev,
 262                                    DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
 263                                    0xff, 0, q_id);
 264                 q_id += q_num_per_port;
 265         }
 266 }
 267
 268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
 269 {
 270         u16 max_q_per_vf, max_vfn;
 271         u32 q_id, q_num_per_port;
 272         u32 mac_id;
 273
 274         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 275                 return;
 276
 277         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 278         q_num_per_port = max_vfn * max_q_per_vf;
 279
 280         for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
 281                 dsaf_set_dev_field(dsaf_dev,
 282                                    DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 283                                    DSAFV2_SERDES_LBK_QID_M,
 284                                    DSAFV2_SERDES_LBK_QID_S,
 285                                    q_id);
 286                 q_id += q_num_per_port;
 287         }
 288 }
 289
 290 /**
 291  * hns_dsaf_sw_port_type_cfg - cfg sw type
 292  * @dsaf_id: dsa fabric id
 293  * @psw_port_type: array
 294  */
 295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
 296                                       enum dsaf_sw_port_type port_type)
 297 {
 298         u32 i;
 299
 300         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
 301                 dsaf_set_dev_field(dsaf_dev,
 302                                    DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
 303                                    DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
 304                                    port_type);
 305         }
 306 }
 307
 308 /**
 309  * hns_dsaf_stp_port_type_cfg - cfg stp type
 310  * @dsaf_id: dsa fabric id
 311  * @pstp_port_type: array
 312  */
 313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
 314                                        enum dsaf_stp_port_type port_type)
 315 {
 316         u32 i;
 317
 318         for (i = 0; i < DSAF_COMM_CHN; i++) {
 319                 dsaf_set_dev_field(dsaf_dev,
 320                                    DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
 321                                    DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
 322                                    port_type);
 323         }
 324 }
 325
 326 #define HNS_DSAF_SBM_NUM(dev) \
 327         (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
 328 /**
 329  * hns_dsaf_sbm_cfg - config sbm
 330  * @dsaf_id: dsa fabric id
 331  */
 332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
 333 {
 334         u32 o_sbm_cfg;
 335         u32 i;
 336
 337         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 338                 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
 339                                           DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
 340                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
 341                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
 342                 dsaf_write_dev(dsaf_dev,
 343                                DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
 344         }
 345 }
 346
 347 /**
 348  * hns_dsaf_sbm_cfg_mib_en - config sbm
 349  * @dsaf_id: dsa fabric id
 350  */
 351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
 352 {
 353         u32 sbm_cfg_mib_en;
 354         u32 i;
 355         u32 reg;
 356         u32 read_cnt;
 357
 358         /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
 359         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 360                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 361                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
 362         }
 363
 364         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 365                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 366                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
 367         }
 368
 369         /* waitint for all sbm enable finished */
 370         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 371                 read_cnt = 0;
 372                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 373                 do {
 374                         udelay(1);
 375                         sbm_cfg_mib_en = dsaf_get_dev_bit(
 376                                         dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
 377                         read_cnt++;
 378                 } while (sbm_cfg_mib_en == 0 &&
 379                         read_cnt < DSAF_CFG_READ_CNT);
 380
 381                 if (sbm_cfg_mib_en == 0) {
 382                         dev_err(dsaf_dev->dev,
 383                                 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
 384                                 dsaf_dev->ae_dev.name, i);
 385                         return -ENODEV;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 /**
 393  * hns_dsaf_sbm_bp_wl_cfg - config sbm
 394  * @dsaf_id: dsa fabric id
 395  */
 396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 397 {
 398         u32 o_sbm_bp_cfg;
 399         u32 reg;
 400         u32 i;
 401
 402         /* XGE */
 403         for (i = 0; i < DSAF_XGE_NUM; i++) {
 404                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 405                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 406                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
 407                                DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
 408                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 409                                DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 410                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 411                                DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 412                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 413
 414                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 415                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 416                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 417                                DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 418                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 419                                DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 420                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 421
 422                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 423                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 424                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 425                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
 426                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 427                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
 428                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 429
 430                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 431                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 432                 dsaf_set_field(o_sbm_bp_cfg,
 433                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 434                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
 435                 dsaf_set_field(o_sbm_bp_cfg,
 436                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 437                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
 438                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 439
 440                 /* for no enable pfc mode */
 441                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 442                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 443                 dsaf_set_field(o_sbm_bp_cfg,
 444                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 445                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
 446                 dsaf_set_field(o_sbm_bp_cfg,
 447                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 448                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
 449                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 450         }
 451
 452         /* PPE */
 453         for (i = 0; i < DSAF_COMM_CHN; i++) {
 454                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 455                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 456                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 457                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
 458                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 459                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
 460                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 461         }
 462
 463         /* RoCEE */
 464         for (i = 0; i < DSAF_COMM_CHN; i++) {
 465                 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 466                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 467                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 468                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
 469                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 470                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
 471                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 472         }
 473 }
 474
 475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 476 {
 477         u32 o_sbm_bp_cfg;
 478         u32 reg;
 479         u32 i;
 480
 481         /* XGE */
 482         for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
 483                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 484                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 485                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
 486                                DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
 487                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 488                                DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 489                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 490                                DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 491                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 492
 493                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 494                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 495                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 496                                DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 497                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 498                                DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 499                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 500
 501                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 502                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 503                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
 504                                DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
 505                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
 506                                DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
 507                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 508
 509                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 510                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 511                 dsaf_set_field(o_sbm_bp_cfg,
 512                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 513                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 48);
 514                 dsaf_set_field(o_sbm_bp_cfg,
 515                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 516                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 80);
 517                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 518
 519                 /* for no enable pfc mode */
 520                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 521                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 522                 dsaf_set_field(o_sbm_bp_cfg,
 523                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
 524                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 192);
 525                 dsaf_set_field(o_sbm_bp_cfg,
 526                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
 527                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 240);
 528                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 529         }
 530
 531         /* PPE */
 532         for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
 533                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 534                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 535                 dsaf_set_field(o_sbm_bp_cfg,
 536                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
 537                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
 538                 dsaf_set_field(o_sbm_bp_cfg,
 539                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
 540                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
 541                 dsaf_set_field(o_sbm_bp_cfg,
 542                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
 543                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
 544                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 545         }
 546
 547         /* RoCEE */
 548         for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
 549                 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 550                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 551                 dsaf_set_field(o_sbm_bp_cfg,
 552                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
 553                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
 554                 dsaf_set_field(o_sbm_bp_cfg,
 555                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
 556                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
 557                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 558         }
 559 }
 560
 561 /**
 562  * hns_dsaf_voq_bp_all_thrd_cfg -  voq
 563  * @dsaf_id: dsa fabric id
 564  */
 565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
 566 {
 567         u32 voq_bp_all_thrd;
 568         u32 i;
 569
 570         for (i = 0; i < DSAF_VOQ_NUM; i++) {
 571                 voq_bp_all_thrd = dsaf_read_dev(
 572                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
 573                 if (i < DSAF_XGE_NUM) {
 574                         dsaf_set_field(voq_bp_all_thrd,
 575                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 576                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
 577                         dsaf_set_field(voq_bp_all_thrd,
 578                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 579                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
 580                 } else {
 581                         dsaf_set_field(voq_bp_all_thrd,
 582                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 583                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
 584                         dsaf_set_field(voq_bp_all_thrd,
 585                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 586                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
 587                 }
 588                 dsaf_write_dev(
 589                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
 590                         voq_bp_all_thrd);
 591         }
 592 }
 593
 594 /**
 595  * hns_dsaf_tbl_tcam_data_cfg - tbl
 596  * @dsaf_id: dsa fabric id
 597  * @ptbl_tcam_data: addr
 598  */
 599 static void hns_dsaf_tbl_tcam_data_cfg(
 600         struct dsaf_device *dsaf_dev,
 601         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 602 {
 603         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
 604                        ptbl_tcam_data->tbl_tcam_data_low);
 605         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
 606                        ptbl_tcam_data->tbl_tcam_data_high);
 607 }
 608
 609 /**
 610  * dsaf_tbl_tcam_mcast_cfg - tbl
 611  * @dsaf_id: dsa fabric id
 612  * @ptbl_tcam_mcast: addr
 613  */
 614 static void hns_dsaf_tbl_tcam_mcast_cfg(
 615         struct dsaf_device *dsaf_dev,
 616         struct dsaf_tbl_tcam_mcast_cfg *mcast)
 617 {
 618         u32 mcast_cfg4;
 619
 620         mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
 621         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
 622                      mcast->tbl_mcast_item_vld);
 623         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
 624                      mcast->tbl_mcast_old_en);
 625         dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
 626                        DSAF_TBL_MCAST_CFG4_VM128_112_S,
 627                        mcast->tbl_mcast_port_msk[4]);
 628         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
 629
 630         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
 631                        mcast->tbl_mcast_port_msk[3]);
 632
 633         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
 634                        mcast->tbl_mcast_port_msk[2]);
 635
 636         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
 637                        mcast->tbl_mcast_port_msk[1]);
 638
 639         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
 640                        mcast->tbl_mcast_port_msk[0]);
 641 }
 642
 643 /**
 644  * hns_dsaf_tbl_tcam_ucast_cfg - tbl
 645  * @dsaf_id: dsa fabric id
 646  * @ptbl_tcam_ucast: addr
 647  */
 648 static void hns_dsaf_tbl_tcam_ucast_cfg(
 649         struct dsaf_device *dsaf_dev,
 650         struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
 651 {
 652         u32 ucast_cfg1;
 653
 654         ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
 655         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
 656                      tbl_tcam_ucast->tbl_ucast_mac_discard);
 657         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
 658                      tbl_tcam_ucast->tbl_ucast_item_vld);
 659         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
 660                      tbl_tcam_ucast->tbl_ucast_old_en);
 661         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
 662                      tbl_tcam_ucast->tbl_ucast_dvc);
 663         dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 664                        DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
 665                        tbl_tcam_ucast->tbl_ucast_out_port);
 666         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
 667 }
 668
 669 /**
 670  * hns_dsaf_tbl_line_cfg - tbl
 671  * @dsaf_id: dsa fabric id
 672  * @ptbl_lin: addr
 673  */
 674 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
 675                                   struct dsaf_tbl_line_cfg *tbl_lin)
 676 {
 677         u32 tbl_line;
 678
 679         tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
 680         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
 681                      tbl_lin->tbl_line_mac_discard);
 682         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
 683                      tbl_lin->tbl_line_dvc);
 684         dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
 685                        DSAF_TBL_LINE_CFG_OUT_PORT_S,
 686                        tbl_lin->tbl_line_out_port);
 687         dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
 688 }
 689
 690 /**
 691  * hns_dsaf_tbl_tcam_mcast_pul - tbl
 692  * @dsaf_id: dsa fabric id
 693  */
 694 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
 695 {
 696         u32 o_tbl_pul;
 697
 698         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 699         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 700         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 701         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 702         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 703 }
 704
 705 /**
 706  * hns_dsaf_tbl_line_pul - tbl
 707  * @dsaf_id: dsa fabric id
 708  */
 709 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
 710 {
 711         u32 tbl_pul;
 712
 713         tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 714         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
 715         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 716         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
 717         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 718 }
 719
 720 /**
 721  * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
 722  * @dsaf_id: dsa fabric id
 723  */
 724 static void hns_dsaf_tbl_tcam_data_mcast_pul(
 725         struct dsaf_device *dsaf_dev)
 726 {
 727         u32 o_tbl_pul;
 728
 729         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 730         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 731         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 732         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 733         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 734         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 735         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 736 }
 737
 738 /**
 739  * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
 740  * @dsaf_id: dsa fabric id
 741  */
 742 static void hns_dsaf_tbl_tcam_data_ucast_pul(
 743         struct dsaf_device *dsaf_dev)
 744 {
 745         u32 o_tbl_pul;
 746
 747         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 748         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 749         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
 750         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 751         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 752         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
 753         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 754 }
 755
 756 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
 757 {
 758         if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
 759                 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
 760                                  DSAF_CFG_MIX_MODE_S, !!en);
 761 }
 762
 763 /**
 764  * hns_dsaf_tbl_stat_en - tbl
 765  * @dsaf_id: dsa fabric id
 766  * @ptbl_stat_en: addr
 767  */
 768 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
 769 {
 770         u32 o_tbl_ctrl;
 771
 772         o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
 773         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
 774         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
 775         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
 776         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
 777         dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
 778 }
 779
 780 /**
 781  * hns_dsaf_rocee_bp_en - rocee back press enable
 782  * @dsaf_id: dsa fabric id
 783  */
 784 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
 785 {
 786         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 787                 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
 788                                  DSAF_FC_XGE_TX_PAUSE_S, 1);
 789 }
 790
 791 /* set msk for dsaf exception irq*/
 792 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
 793                                      u32 chnn_num, u32 mask_set)
 794 {
 795         dsaf_write_dev(dsaf_dev,
 796                        DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
 797 }
 798
 799 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
 800                                      u32 chnn_num, u32 msk_set)
 801 {
 802         dsaf_write_dev(dsaf_dev,
 803                        DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
 804 }
 805
 806 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
 807                                        u32 chnn, u32 msk_set)
 808 {
 809         dsaf_write_dev(dsaf_dev,
 810                        DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
 811 }
 812
 813 static void
 814 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
 815 {
 816         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
 817 }
 818
 819 /* clr dsaf exception irq*/
 820 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
 821                                      u32 chnn_num, u32 int_src)
 822 {
 823         dsaf_write_dev(dsaf_dev,
 824                        DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
 825 }
 826
 827 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
 828                                      u32 chnn, u32 int_src)
 829 {
 830         dsaf_write_dev(dsaf_dev,
 831                        DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 832 }
 833
 834 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
 835                                        u32 chnn, u32 int_src)
 836 {
 837         dsaf_write_dev(dsaf_dev,
 838                        DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 839 }
 840
 841 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
 842                                      u32 int_src)
 843 {
 844         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
 845 }
 846
 847 /**
 848  * hns_dsaf_single_line_tbl_cfg - INT
 849  * @dsaf_id: dsa fabric id
 850  * @address:
 851  * @ptbl_line:
 852  */
 853 static void hns_dsaf_single_line_tbl_cfg(
 854         struct dsaf_device *dsaf_dev,
 855         u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
 856 {
 857         spin_lock_bh(&dsaf_dev->tcam_lock);
 858
 859         /*Write Addr*/
 860         hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
 861
 862         /*Write Line*/
 863         hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
 864
 865         /*Write Plus*/
 866         hns_dsaf_tbl_line_pul(dsaf_dev);
 867
 868         spin_unlock_bh(&dsaf_dev->tcam_lock);
 869 }
 870
 871 /**
 872  * hns_dsaf_tcam_uc_cfg - INT
 873  * @dsaf_id: dsa fabric id
 874  * @address,
 875  * @ptbl_tcam_data,
 876  */
 877 static void hns_dsaf_tcam_uc_cfg(
 878         struct dsaf_device *dsaf_dev, u32 address,
 879         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 880         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 881 {
 882         spin_lock_bh(&dsaf_dev->tcam_lock);
 883
 884         /*Write Addr*/
 885         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 886         /*Write Tcam Data*/
 887         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 888         /*Write Tcam Ucast*/
 889         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
 890         /*Write Plus*/
 891         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 892
 893         spin_unlock_bh(&dsaf_dev->tcam_lock);
 894 }
 895
 896 /**
 897  * hns_dsaf_tcam_mc_cfg - INT
 898  * @dsaf_id: dsa fabric id
 899  * @address,
 900  * @ptbl_tcam_data,
 901  * @ptbl_tcam_mcast,
 902  */
 903 static void hns_dsaf_tcam_mc_cfg(
 904         struct dsaf_device *dsaf_dev, u32 address,
 905         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 906         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
 907 {
 908         spin_lock_bh(&dsaf_dev->tcam_lock);
 909
 910         /*Write Addr*/
 911         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 912         /*Write Tcam Data*/
 913         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 914         /*Write Tcam Mcast*/
 915         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
 916         /*Write Plus*/
 917         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 918
 919         spin_unlock_bh(&dsaf_dev->tcam_lock);
 920 }
 921
 922 /**
 923  * hns_dsaf_tcam_mc_invld - INT
 924  * @dsaf_id: dsa fabric id
 925  * @address
 926  */
 927 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
 928 {
 929         spin_lock_bh(&dsaf_dev->tcam_lock);
 930
 931         /*Write Addr*/
 932         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 933
 934         /*write tcam mcast*/
 935         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
 936         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
 937         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
 938         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
 939         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
 940
 941         /*Write Plus*/
 942         hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
 943
 944         spin_unlock_bh(&dsaf_dev->tcam_lock);
 945 }
 946
 947 /**
 948  * hns_dsaf_tcam_uc_get - INT
 949  * @dsaf_id: dsa fabric id
 950  * @address
 951  * @ptbl_tcam_data
 952  * @ptbl_tcam_ucast
 953  */
 954 static void hns_dsaf_tcam_uc_get(
 955         struct dsaf_device *dsaf_dev, u32 address,
 956         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 957         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 958 {
 959         u32 tcam_read_data0;
 960         u32 tcam_read_data4;
 961
 962         spin_lock_bh(&dsaf_dev->tcam_lock);
 963
 964         /*Write Addr*/
 965         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 966
 967         /*read tcam item puls*/
 968         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
 969
 970         /*read tcam data*/
 971         ptbl_tcam_data->tbl_tcam_data_high
 972                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
 973         ptbl_tcam_data->tbl_tcam_data_low
 974                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
 975
 976         /*read tcam mcast*/
 977         tcam_read_data0 = dsaf_read_dev(dsaf_dev,
 978                                         DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
 979         tcam_read_data4 = dsaf_read_dev(dsaf_dev,
 980                                         DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
 981
 982         ptbl_tcam_ucast->tbl_ucast_item_vld
 983                 = dsaf_get_bit(tcam_read_data4,
 984                                DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
 985         ptbl_tcam_ucast->tbl_ucast_old_en
 986                 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
 987         ptbl_tcam_ucast->tbl_ucast_mac_discard
 988                 = dsaf_get_bit(tcam_read_data0,
 989                                DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
 990         ptbl_tcam_ucast->tbl_ucast_out_port
 991                 = dsaf_get_field(tcam_read_data0,
 992                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 993                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
 994         ptbl_tcam_ucast->tbl_ucast_dvc
 995                 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
 996
 997         spin_unlock_bh(&dsaf_dev->tcam_lock);
 998 }
 999
1000 /**
1001  * hns_dsaf_tcam_mc_get - INT
1002  * @dsaf_id: dsa fabric id
1003  * @address
1004  * @ptbl_tcam_data
1005  * @ptbl_tcam_ucast
1006  */
1007 static void hns_dsaf_tcam_mc_get(
1008         struct dsaf_device *dsaf_dev, u32 address,
1009         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1010         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1011 {
1012         u32 data_tmp;
1013
1014         spin_lock_bh(&dsaf_dev->tcam_lock);
1015
1016         /*Write Addr*/
1017         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1018
1019         /*read tcam item puls*/
1020         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1021
1022         /*read tcam data*/
1023         ptbl_tcam_data->tbl_tcam_data_high =
1024                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1025         ptbl_tcam_data->tbl_tcam_data_low =
1026                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1027
1028         /*read tcam mcast*/
1029         ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1030                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1031         ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1032                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1033         ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1034                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1035         ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1036                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1037
1038         data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1039         ptbl_tcam_mcast->tbl_mcast_item_vld =
1040                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1041         ptbl_tcam_mcast->tbl_mcast_old_en =
1042                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1043         ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1044                 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1045                                DSAF_TBL_MCAST_CFG4_VM128_112_S);
1046
1047         spin_unlock_bh(&dsaf_dev->tcam_lock);
1048 }
1049
1050 /**
1051  * hns_dsaf_tbl_line_init - INT
1052  * @dsaf_id: dsa fabric id
1053  */
1054 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1055 {
1056         u32 i;
1057         /* defaultly set all lineal mac table entry resulting discard */
1058         struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1059
1060         for (i = 0; i < DSAF_LINE_SUM; i++)
1061                 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1062 }
1063
1064 /**
1065  * hns_dsaf_tbl_tcam_init - INT
1066  * @dsaf_id: dsa fabric id
1067  */
1068 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1069 {
1070         u32 i;
1071         struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1072         struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1073
1074         /*tcam tbl*/
1075         for (i = 0; i < DSAF_TCAM_SUM; i++)
1076                 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1077 }
1078
1079 /**
1080  * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1081  * @mac_cb: mac contrl block
1082  */
1083 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1084                                 int mac_id, int tc_en)
1085 {
1086         dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1087 }
1088
1089 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1090                                    int mac_id, int tx_en, int rx_en)
1091 {
1092         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1093                 if (!tx_en || !rx_en)
1094                         dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1095
1096                 return;
1097         }
1098
1099         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1100                          DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1101         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1102                          DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1103 }
1104
1105 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1106                                  u32 en)
1107 {
1108         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1109                 if (!en) {
1110                         dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1111                         return -EINVAL;
1112                 }
1113         }
1114
1115         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1116                          DSAF_MAC_PAUSE_RX_EN_B, !!en);
1117
1118         return 0;
1119 }
1120
1121 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1122                                   u32 *en)
1123 {
1124         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1125                 *en = 1;
1126         else
1127                 *en = dsaf_get_dev_bit(dsaf_dev,
1128                                        DSAF_PAUSE_CFG_REG + mac_id * 4,
1129                                        DSAF_MAC_PAUSE_RX_EN_B);
1130 }
1131
1132 /**
1133  * hns_dsaf_tbl_tcam_init - INT
1134  * @dsaf_id: dsa fabric id
1135  * @dsaf_mode
1136  */
1137 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1138 {
1139         u32 i;
1140         u32 o_dsaf_cfg;
1141         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1142
1143         o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1144         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1145         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1146         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1147         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1148         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1149         dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1150
1151         hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1152         hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1153
1154         /* set 22 queue per tx ppe engine, only used in switch mode */
1155         hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1156
1157         /* set promisc def queue id */
1158         hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1159
1160         /* set inner loopback queue id */
1161         hns_dsaf_inner_qid_cfg(dsaf_dev);
1162
1163         /* in non switch mode, set all port to access mode */
1164         hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1165
1166         /*set dsaf pfc  to 0 for parseing rx pause*/
1167         for (i = 0; i < DSAF_COMM_CHN; i++) {
1168                 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1169                 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1170         }
1171
1172         /*msk and  clr exception irqs */
1173         for (i = 0; i < DSAF_COMM_CHN; i++) {
1174                 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1175                 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1176                 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1177
1178                 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1179                 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1180                 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1181         }
1182         hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1183         hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1184 }
1185
1186 /**
1187  * hns_dsaf_inode_init - INT
1188  * @dsaf_id: dsa fabric id
1189  */
1190 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1191 {
1192         u32 reg;
1193         u32 tc_cfg;
1194         u32 i;
1195
1196         if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1197                 tc_cfg = HNS_DSAF_I4TC_CFG;
1198         else
1199                 tc_cfg = HNS_DSAF_I8TC_CFG;
1200
1201         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1202                 for (i = 0; i < DSAF_INODE_NUM; i++) {
1203                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1204                         dsaf_set_dev_field(dsaf_dev, reg,
1205                                            DSAF_INODE_IN_PORT_NUM_M,
1206                                            DSAF_INODE_IN_PORT_NUM_S,
1207                                            i % DSAF_XGE_NUM);
1208                 }
1209         } else {
1210                 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1211                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1212                         dsaf_set_dev_field(dsaf_dev, reg,
1213                                            DSAF_INODE_IN_PORT_NUM_M,
1214                                            DSAF_INODE_IN_PORT_NUM_S, 0);
1215                         dsaf_set_dev_field(dsaf_dev, reg,
1216                                            DSAFV2_INODE_IN_PORT1_NUM_M,
1217                                            DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1218                         dsaf_set_dev_field(dsaf_dev, reg,
1219                                            DSAFV2_INODE_IN_PORT2_NUM_M,
1220                                            DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1221                         dsaf_set_dev_field(dsaf_dev, reg,
1222                                            DSAFV2_INODE_IN_PORT3_NUM_M,
1223                                            DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1224                         dsaf_set_dev_field(dsaf_dev, reg,
1225                                            DSAFV2_INODE_IN_PORT4_NUM_M,
1226                                            DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1227                         dsaf_set_dev_field(dsaf_dev, reg,
1228                                            DSAFV2_INODE_IN_PORT5_NUM_M,
1229                                            DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1230                 }
1231         }
1232         for (i = 0; i < DSAF_INODE_NUM; i++) {
1233                 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1234                 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1235         }
1236 }
1237
1238 /**
1239  * hns_dsaf_sbm_init - INT
1240  * @dsaf_id: dsa fabric id
1241  */
1242 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1243 {
1244         u32 flag;
1245         u32 finish_msk;
1246         u32 cnt = 0;
1247         int ret;
1248
1249         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1250                 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1251                 finish_msk = DSAF_SRAM_INIT_OVER_M;
1252         } else {
1253                 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1254                 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1255         }
1256
1257         /* enable sbm chanel, disable sbm chanel shcut function*/
1258         hns_dsaf_sbm_cfg(dsaf_dev);
1259
1260         /* enable sbm mib */
1261         ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1262         if (ret) {
1263                 dev_err(dsaf_dev->dev,
1264                         "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1265                         dsaf_dev->ae_dev.name, ret);
1266                 return ret;
1267         }
1268
1269         /* enable sbm initial link sram */
1270         hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1271
1272         do {
1273                 usleep_range(200, 210);/*udelay(200);*/
1274                 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1275                                           finish_msk, DSAF_SRAM_INIT_OVER_S);
1276                 cnt++;
1277         } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1278                  cnt < DSAF_CFG_READ_CNT);
1279
1280         if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1281                 dev_err(dsaf_dev->dev,
1282                         "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1283                         dsaf_dev->ae_dev.name, flag, cnt);
1284                 return -ENODEV;
1285         }
1286
1287         hns_dsaf_rocee_bp_en(dsaf_dev);
1288
1289         return 0;
1290 }
1291
1292 /**
1293  * hns_dsaf_tbl_init - INT
1294  * @dsaf_id: dsa fabric id
1295  */
1296 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1297 {
1298         hns_dsaf_tbl_stat_en(dsaf_dev);
1299
1300         hns_dsaf_tbl_tcam_init(dsaf_dev);
1301         hns_dsaf_tbl_line_init(dsaf_dev);
1302 }
1303
1304 /**
1305  * hns_dsaf_voq_init - INT
1306  * @dsaf_id: dsa fabric id
1307  */
1308 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1309 {
1310         hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1311 }
1312
1313 /**
1314  * hns_dsaf_init_hw - init dsa fabric hardware
1315  * @dsaf_dev: dsa fabric device struct pointer
1316  */
1317 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1318 {
1319         int ret;
1320
1321         dev_dbg(dsaf_dev->dev,
1322                 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1323
1324         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1325         mdelay(10);
1326         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1327
1328         hns_dsaf_comm_init(dsaf_dev);
1329
1330         /*init XBAR_INODE*/
1331         hns_dsaf_inode_init(dsaf_dev);
1332
1333         /*init SBM*/
1334         ret = hns_dsaf_sbm_init(dsaf_dev);
1335         if (ret)
1336                 return ret;
1337
1338         /*init TBL*/
1339         hns_dsaf_tbl_init(dsaf_dev);
1340
1341         /*init VOQ*/
1342         hns_dsaf_voq_init(dsaf_dev);
1343
1344         return 0;
1345 }
1346
1347 /**
1348  * hns_dsaf_remove_hw - uninit dsa fabric hardware
1349  * @dsaf_dev: dsa fabric device struct pointer
1350  */
1351 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1352 {
1353         /*reset*/
1354         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1355 }
1356
1357 /**
1358  * hns_dsaf_init - init dsa fabric
1359  * @dsaf_dev: dsa fabric device struct pointer
1360  * retuen 0 - success , negative --fail
1361  */
1362 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1363 {
1364         struct dsaf_drv_priv *priv =
1365             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1366         u32 i;
1367         int ret;
1368
1369         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1370                 return 0;
1371
1372         spin_lock_init(&dsaf_dev->tcam_lock);
1373         ret = hns_dsaf_init_hw(dsaf_dev);
1374         if (ret)
1375                 return ret;
1376
1377         /* malloc mem for tcam mac key(vlan+mac) */
1378         priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl)
1379                   * DSAF_TCAM_SUM);
1380         if (!priv->soft_mac_tbl) {
1381                 ret = -ENOMEM;
1382                 goto remove_hw;
1383         }
1384
1385         /*all entry invall */
1386         for (i = 0; i < DSAF_TCAM_SUM; i++)
1387                 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1388
1389         return 0;
1390
1391 remove_hw:
1392         hns_dsaf_remove_hw(dsaf_dev);
1393         return ret;
1394 }
1395
1396 /**
1397  * hns_dsaf_free - free dsa fabric
1398  * @dsaf_dev: dsa fabric device struct pointer
1399  */
1400 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1401 {
1402         struct dsaf_drv_priv *priv =
1403             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1404
1405         hns_dsaf_remove_hw(dsaf_dev);
1406
1407         /* free all mac mem */
1408         vfree(priv->soft_mac_tbl);
1409         priv->soft_mac_tbl = NULL;
1410 }
1411
1412 /**
1413  * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1414  * @dsaf_dev: dsa fabric device struct pointer
1415  * @mac_key: mac entry struct pointer
1416  */
1417 static u16 hns_dsaf_find_soft_mac_entry(
1418         struct dsaf_device *dsaf_dev,
1419         struct dsaf_drv_tbl_tcam_key *mac_key)
1420 {
1421         struct dsaf_drv_priv *priv =
1422             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1423         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1424         u32 i;
1425
1426         soft_mac_entry = priv->soft_mac_tbl;
1427         for (i = 0; i < DSAF_TCAM_SUM; i++) {
1428                 /* invall tab entry */
1429                 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1430                     (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1431                     (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1432                         /* return find result --soft index */
1433                         return soft_mac_entry->index;
1434
1435                 soft_mac_entry++;
1436         }
1437         return DSAF_INVALID_ENTRY_IDX;
1438 }
1439
1440 /**
1441  * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1442  * @dsaf_dev: dsa fabric device struct pointer
1443  */
1444 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1445 {
1446         struct dsaf_drv_priv *priv =
1447             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1448         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1449         u32 i;
1450
1451         soft_mac_entry = priv->soft_mac_tbl;
1452         for (i = 0; i < DSAF_TCAM_SUM; i++) {
1453                 /* inv all entry */
1454                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1455                         /* return find result --soft index */
1456                         return i;
1457
1458                 soft_mac_entry++;
1459         }
1460         return DSAF_INVALID_ENTRY_IDX;
1461 }
1462
1463 /**
1464  * hns_dsaf_set_mac_key - set mac key
1465  * @dsaf_dev: dsa fabric device struct pointer
1466  * @mac_key: tcam key pointer
1467  * @vlan_id: vlan id
1468  * @in_port_num: input port num
1469  * @addr: mac addr
1470  */
1471 static void hns_dsaf_set_mac_key(
1472         struct dsaf_device *dsaf_dev,
1473         struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1474         u8 *addr)
1475 {
1476         u8 port;
1477
1478         if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1479                 /*DSAF mode : in port id fixed 0*/
1480                 port = 0;
1481         else
1482                 /*non-dsaf mode*/
1483                 port = in_port_num;
1484
1485         mac_key->high.bits.mac_0 = addr[0];
1486         mac_key->high.bits.mac_1 = addr[1];
1487         mac_key->high.bits.mac_2 = addr[2];
1488         mac_key->high.bits.mac_3 = addr[3];
1489         mac_key->low.bits.mac_4 = addr[4];
1490         mac_key->low.bits.mac_5 = addr[5];
1491         mac_key->low.bits.vlan = vlan_id;
1492         mac_key->low.bits.port = port;
1493 }
1494
1495 /**
1496  * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1497  * @dsaf_dev: dsa fabric device struct pointer
1498  * @mac_entry: uc-mac entry
1499  */
1500 int hns_dsaf_set_mac_uc_entry(
1501         struct dsaf_device *dsaf_dev,
1502         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1503 {
1504         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1505         struct dsaf_drv_tbl_tcam_key mac_key;
1506         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1507         struct dsaf_drv_priv *priv =
1508             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1509         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1510
1511         /* mac addr check */
1512         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1513             MAC_IS_BROADCAST(mac_entry->addr) ||
1514             MAC_IS_MULTICAST(mac_entry->addr)) {
1515                 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1516                         dsaf_dev->ae_dev.name, mac_entry->addr);
1517                 return -EINVAL;
1518         }
1519
1520         /* config key */
1521         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1522                              mac_entry->in_port_num, mac_entry->addr);
1523
1524         /* entry ie exist? */
1525         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1526         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1527                 /*if has not inv entry,find a empty entry */
1528                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1529                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1530                         /* has not empty,return error */
1531                         dev_err(dsaf_dev->dev,
1532                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1533                                 dsaf_dev->ae_dev.name,
1534                                 mac_key.high.val, mac_key.low.val);
1535                         return -EINVAL;
1536                 }
1537         }
1538
1539         dev_dbg(dsaf_dev->dev,
1540                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1541                 dsaf_dev->ae_dev.name, mac_key.high.val,
1542                 mac_key.low.val, entry_index);
1543
1544         /* config hardware entry */
1545         mac_data.tbl_ucast_item_vld = 1;
1546         mac_data.tbl_ucast_mac_discard = 0;
1547         mac_data.tbl_ucast_old_en = 0;
1548         /* default config dvc to 0 */
1549         mac_data.tbl_ucast_dvc = 0;
1550         mac_data.tbl_ucast_out_port = mac_entry->port_num;
1551         hns_dsaf_tcam_uc_cfg(
1552                 dsaf_dev, entry_index,
1553                 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1554
1555         /* config software entry */
1556         soft_mac_entry += entry_index;
1557         soft_mac_entry->index = entry_index;
1558         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1559         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1560
1561         return 0;
1562 }
1563
1564 /**
1565  * hns_dsaf_set_mac_mc_entry - set mac mc-entry
1566  * @dsaf_dev: dsa fabric device struct pointer
1567  * @mac_entry: mc-mac entry
1568  */
1569 int hns_dsaf_set_mac_mc_entry(
1570         struct dsaf_device *dsaf_dev,
1571         struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1572 {
1573         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1574         struct dsaf_drv_tbl_tcam_key mac_key;
1575         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1576         struct dsaf_drv_priv *priv =
1577             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1578         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1579         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1580
1581         /* mac addr check */
1582         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1583                 dev_err(dsaf_dev->dev, "set uc %s Mac %pM err!\n",
1584                         dsaf_dev->ae_dev.name, mac_entry->addr);
1585                 return -EINVAL;
1586         }
1587
1588         /*config key */
1589         hns_dsaf_set_mac_key(dsaf_dev, &mac_key,
1590                              mac_entry->in_vlan_id,
1591                              mac_entry->in_port_num, mac_entry->addr);
1592
1593         /* entry ie exist? */
1594         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1595         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1596                 /*if hasnot, find enpty entry*/
1597                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1598                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1599                         /*if hasnot empty, error*/
1600                         dev_err(dsaf_dev->dev,
1601                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1602                                 dsaf_dev->ae_dev.name,
1603                                 mac_key.high.val, mac_key.low.val);
1604                         return -EINVAL;
1605                 }
1606
1607                 /* config hardware entry */
1608                 memset(mac_data.tbl_mcast_port_msk,
1609                        0, sizeof(mac_data.tbl_mcast_port_msk));
1610         } else {
1611                 /* config hardware entry */
1612                 hns_dsaf_tcam_mc_get(
1613                         dsaf_dev, entry_index,
1614                         (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1615         }
1616         mac_data.tbl_mcast_old_en = 0;
1617         mac_data.tbl_mcast_item_vld = 1;
1618         dsaf_set_field(mac_data.tbl_mcast_port_msk[0],
1619                        0x3F, 0, mac_entry->port_mask[0]);
1620
1621         dev_dbg(dsaf_dev->dev,
1622                 "set_uc_entry, %s key(%#x:%#x) entry_index%d\n",
1623                 dsaf_dev->ae_dev.name, mac_key.high.val,
1624                 mac_key.low.val, entry_index);
1625
1626         hns_dsaf_tcam_mc_cfg(
1627                 dsaf_dev, entry_index,
1628                 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1629
1630         /* config software entry */
1631         soft_mac_entry += entry_index;
1632         soft_mac_entry->index = entry_index;
1633         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1634         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1635
1636         return 0;
1637 }
1638
1639 /**
1640  * hns_dsaf_add_mac_mc_port - add mac mc-port
1641  * @dsaf_dev: dsa fabric device struct pointer
1642  * @mac_entry: mc-mac entry
1643  */
1644 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1645                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1646 {
1647         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1648         struct dsaf_drv_tbl_tcam_key mac_key;
1649         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1650         struct dsaf_drv_priv *priv =
1651             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1652         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1653         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1654         int mskid;
1655
1656         /*chechk mac addr */
1657         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1658                 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1659                         mac_entry->addr);
1660                 return -EINVAL;
1661         }
1662
1663         /*config key */
1664         hns_dsaf_set_mac_key(
1665                 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1666                 mac_entry->in_port_num, mac_entry->addr);
1667
1668         memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1669
1670         /*check exist? */
1671         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1672         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1673                 /*if hasnot , find a empty*/
1674                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1675                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1676                         /*if hasnot empty, error*/
1677                         dev_err(dsaf_dev->dev,
1678                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1679                                 dsaf_dev->ae_dev.name, mac_key.high.val,
1680                                 mac_key.low.val);
1681                         return -EINVAL;
1682                 }
1683         } else {
1684                 /*if exist, add in */
1685                 hns_dsaf_tcam_mc_get(
1686                         dsaf_dev, entry_index,
1687                         (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1688         }
1689         /* config hardware entry */
1690         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1691                 mskid = mac_entry->port_num;
1692         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1693                 mskid = mac_entry->port_num -
1694                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1695         } else {
1696                 dev_err(dsaf_dev->dev,
1697                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1698                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1699                         mac_key.high.val, mac_key.low.val);
1700                 return -EINVAL;
1701         }
1702         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1703         mac_data.tbl_mcast_old_en = 0;
1704         mac_data.tbl_mcast_item_vld = 1;
1705
1706         dev_dbg(dsaf_dev->dev,
1707                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1708                 dsaf_dev->ae_dev.name, mac_key.high.val,
1709                 mac_key.low.val, entry_index);
1710
1711         hns_dsaf_tcam_mc_cfg(
1712                 dsaf_dev, entry_index,
1713                 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1714
1715         /*config software entry */
1716         soft_mac_entry += entry_index;
1717         soft_mac_entry->index = entry_index;
1718         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1719         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1720
1721         return 0;
1722 }
1723
1724 /**
1725  * hns_dsaf_del_mac_entry - del mac mc-port
1726  * @dsaf_dev: dsa fabric device struct pointer
1727  * @vlan_id: vlian id
1728  * @in_port_num: input port num
1729  * @addr : mac addr
1730  */
1731 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1732                            u8 in_port_num, u8 *addr)
1733 {
1734         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1735         struct dsaf_drv_tbl_tcam_key mac_key;
1736         struct dsaf_drv_priv *priv =
1737             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1738         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1739
1740         /*check mac addr */
1741         if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1742                 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1743                         addr);
1744                 return -EINVAL;
1745         }
1746
1747         /*config key */
1748         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1749
1750         /*exist ?*/
1751         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1752         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1753                 /*not exist, error */
1754                 dev_err(dsaf_dev->dev,
1755                         "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1756                         dsaf_dev->ae_dev.name,
1757                         mac_key.high.val, mac_key.low.val);
1758                 return -EINVAL;
1759         }
1760         dev_dbg(dsaf_dev->dev,
1761                 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1762                 dsaf_dev->ae_dev.name, mac_key.high.val,
1763                 mac_key.low.val, entry_index);
1764
1765         /*do del opt*/
1766         hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1767
1768         /*del soft emtry */
1769         soft_mac_entry += entry_index;
1770         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1771
1772         return 0;
1773 }
1774
1775 /**
1776  * hns_dsaf_del_mac_mc_port - del mac mc- port
1777  * @dsaf_dev: dsa fabric device struct pointer
1778  * @mac_entry: mac entry
1779  */
1780 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1781                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1782 {
1783         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1784         struct dsaf_drv_tbl_tcam_key mac_key;
1785         struct dsaf_drv_priv *priv =
1786             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1787         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1788         u16 vlan_id;
1789         u8 in_port_num;
1790         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1791         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1792         int mskid;
1793         const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1794
1795         if (!(void *)mac_entry) {
1796                 dev_err(dsaf_dev->dev,
1797                         "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1798                 return -EINVAL;
1799         }
1800
1801         /*get key info*/
1802         vlan_id = mac_entry->in_vlan_id;
1803         in_port_num = mac_entry->in_port_num;
1804
1805         /*check mac addr */
1806         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1807                 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1808                         mac_entry->addr);
1809                 return -EINVAL;
1810         }
1811
1812         /*config key */
1813         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num,
1814                              mac_entry->addr);
1815
1816         /*check is exist? */
1817         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1818         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1819                 /*find none */
1820                 dev_err(dsaf_dev->dev,
1821                         "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1822                         dsaf_dev->ae_dev.name,
1823                         mac_key.high.val, mac_key.low.val);
1824                 return -EINVAL;
1825         }
1826
1827         dev_dbg(dsaf_dev->dev,
1828                 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1829                 dsaf_dev->ae_dev.name, mac_key.high.val,
1830                 mac_key.low.val, entry_index);
1831
1832         /*read entry*/
1833         hns_dsaf_tcam_mc_get(
1834                 dsaf_dev, entry_index,
1835                 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1836
1837         /*del the port*/
1838         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1839                 mskid = mac_entry->port_num;
1840         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1841                 mskid = mac_entry->port_num -
1842                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1843         } else {
1844                 dev_err(dsaf_dev->dev,
1845                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1846                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1847                         mac_key.high.val, mac_key.low.val);
1848                 return -EINVAL;
1849         }
1850         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1851
1852         /*check non port, do del entry */
1853         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1854                     sizeof(mac_data.tbl_mcast_port_msk))) {
1855                 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1856
1857                 /* del soft entry */
1858                 soft_mac_entry += entry_index;
1859                 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1860         } else { /* not zer, just del port, updata*/
1861                 hns_dsaf_tcam_mc_cfg(
1862                         dsaf_dev, entry_index,
1863                         (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1864         }
1865
1866         return 0;
1867 }
1868
1869 /**
1870  * hns_dsaf_get_mac_uc_entry - get mac uc entry
1871  * @dsaf_dev: dsa fabric device struct pointer
1872  * @mac_entry: mac entry
1873  */
1874 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
1875                               struct dsaf_drv_mac_single_dest_entry *mac_entry)
1876 {
1877         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1878         struct dsaf_drv_tbl_tcam_key mac_key;
1879
1880         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1881
1882         /* check macaddr */
1883         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1884             MAC_IS_BROADCAST(mac_entry->addr)) {
1885                 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
1886                         mac_entry->addr);
1887                 return -EINVAL;
1888         }
1889
1890         /*config key */
1891         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1892                              mac_entry->in_port_num, mac_entry->addr);
1893
1894         /*check exist? */
1895         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1896         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1897                 /*find none, error */
1898                 dev_err(dsaf_dev->dev,
1899                         "get_uc_entry failed, %s Mac key(%#x:%#x)\n",
1900                         dsaf_dev->ae_dev.name,
1901                         mac_key.high.val, mac_key.low.val);
1902                 return -EINVAL;
1903         }
1904         dev_dbg(dsaf_dev->dev,
1905                 "get_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1906                 dsaf_dev->ae_dev.name, mac_key.high.val,
1907                 mac_key.low.val, entry_index);
1908
1909         /*read entry*/
1910         hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
1911                              (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
1912         mac_entry->port_num = mac_data.tbl_ucast_out_port;
1913
1914         return 0;
1915 }
1916
1917 /**
1918  * hns_dsaf_get_mac_mc_entry - get mac mc entry
1919  * @dsaf_dev: dsa fabric device struct pointer
1920  * @mac_entry: mac entry
1921  */
1922 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
1923                               struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1924 {
1925         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1926         struct dsaf_drv_tbl_tcam_key mac_key;
1927
1928         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1929
1930         /*check mac addr */
1931         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1932             MAC_IS_BROADCAST(mac_entry->addr)) {
1933                 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
1934                         mac_entry->addr);
1935                 return -EINVAL;
1936         }
1937
1938         /*config key */
1939         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1940                              mac_entry->in_port_num, mac_entry->addr);
1941
1942         /*check exist? */
1943         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1944         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1945                 /* find none, error */
1946                 dev_err(dsaf_dev->dev,
1947                         "get_mac_uc_entry failed, %s Mac key(%#x:%#x)\n",
1948                         dsaf_dev->ae_dev.name, mac_key.high.val,
1949                         mac_key.low.val);
1950                 return -EINVAL;
1951         }
1952         dev_dbg(dsaf_dev->dev,
1953                 "get_mac_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1954                 dsaf_dev->ae_dev.name, mac_key.high.val,
1955                 mac_key.low.val, entry_index);
1956
1957         /*read entry */
1958         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
1959                              (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
1960
1961         mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
1962         return 0;
1963 }
1964
1965 /**
1966  * hns_dsaf_get_mac_entry_by_index - get mac entry by tab index
1967  * @dsaf_dev: dsa fabric device struct pointer
1968  * @entry_index: tab entry index
1969  * @mac_entry: mac entry
1970  */
1971 int hns_dsaf_get_mac_entry_by_index(
1972         struct dsaf_device *dsaf_dev,
1973         u16 entry_index, struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1974 {
1975         struct dsaf_drv_tbl_tcam_key mac_key;
1976
1977         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1978         struct dsaf_tbl_tcam_ucast_cfg mac_uc_data;
1979         char mac_addr[MAC_NUM_OCTETS_PER_ADDR] = {0};
1980
1981         if (entry_index >= DSAF_TCAM_SUM) {
1982                 /* find none, del error */
1983                 dev_err(dsaf_dev->dev, "get_uc_entry failed, %s\n",
1984                         dsaf_dev->ae_dev.name);
1985                 return -EINVAL;
1986         }
1987
1988         /* mc entry, do read opt */
1989         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
1990                              (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
1991
1992         mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
1993
1994         /***get mac addr*/
1995         mac_addr[0] = mac_key.high.bits.mac_0;
1996         mac_addr[1] = mac_key.high.bits.mac_1;
1997         mac_addr[2] = mac_key.high.bits.mac_2;
1998         mac_addr[3] = mac_key.high.bits.mac_3;
1999         mac_addr[4] = mac_key.low.bits.mac_4;
2000         mac_addr[5] = mac_key.low.bits.mac_5;
2001         /**is mc or uc*/
2002         if (MAC_IS_MULTICAST((u8 *)mac_addr) ||
2003             MAC_IS_L3_MULTICAST((u8 *)mac_addr)) {
2004                 /**mc donot do*/
2005         } else {
2006                 /*is not mc, just uc... */
2007                 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
2008                                      (struct dsaf_tbl_tcam_data *)&mac_key,
2009                                      &mac_uc_data);
2010                 mac_entry->port_mask[0] = (1 << mac_uc_data.tbl_ucast_out_port);
2011         }
2012
2013         return 0;
2014 }
2015
2016 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2017                                               size_t sizeof_priv)
2018 {
2019         struct dsaf_device *dsaf_dev;
2020
2021         dsaf_dev = devm_kzalloc(dev,
2022                                 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2023         if (unlikely(!dsaf_dev)) {
2024                 dsaf_dev = ERR_PTR(-ENOMEM);
2025         } else {
2026                 dsaf_dev->dev = dev;
2027                 dev_set_drvdata(dev, dsaf_dev);
2028         }
2029
2030         return dsaf_dev;
2031 }
2032
2033 /**
2034  * hns_dsaf_free_dev - free dev mem
2035  * @dev: struct device pointer
2036  */
2037 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2038 {
2039         (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2040 }
2041
2042 /**
2043  * dsaf_pfc_unit_cnt - set pfc unit count
2044  * @dsaf_id: dsa fabric id
2045  * @pport_rate:  value array
2046  * @pdsaf_pfc_unit_cnt:  value array
2047  */
2048 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int  mac_id,
2049                                   enum dsaf_port_rate_mode rate)
2050 {
2051         u32 unit_cnt;
2052
2053         switch (rate) {
2054         case DSAF_PORT_RATE_10000:
2055                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2056                 break;
2057         case DSAF_PORT_RATE_1000:
2058                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2059                 break;
2060         case DSAF_PORT_RATE_2500:
2061                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2062                 break;
2063         default:
2064                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2065         }
2066
2067         dsaf_set_dev_field(dsaf_dev,
2068                            (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2069                            DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2070                            unit_cnt);
2071 }
2072
2073 /**
2074  * dsaf_port_work_rate_cfg - fifo
2075  * @dsaf_id: dsa fabric id
2076  * @xge_ge_work_mode
2077  */
2078 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2079                                  enum dsaf_port_rate_mode rate_mode)
2080 {
2081         u32 port_work_mode;
2082
2083         port_work_mode = dsaf_read_dev(
2084                 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2085
2086         if (rate_mode == DSAF_PORT_RATE_10000)
2087                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2088         else
2089                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2090
2091         dsaf_write_dev(dsaf_dev,
2092                        DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2093                        port_work_mode);
2094
2095         hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2096 }
2097
2098 /**
2099  * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2100  * @mac_cb: mac contrl block
2101  */
2102 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2103 {
2104         enum dsaf_port_rate_mode mode;
2105         struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2106         int mac_id = mac_cb->mac_id;
2107
2108         if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2109                 return;
2110         if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2111                 mode = DSAF_PORT_RATE_10000;
2112         else
2113                 mode = DSAF_PORT_RATE_1000;
2114
2115         hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2116 }
2117
2118 static u32 hns_dsaf_get_inode_prio_reg(int index)
2119 {
2120         int base_index, offset;
2121         u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2122
2123         base_index = (index + 1) / DSAF_REG_PER_ZONE;
2124         offset = (index + 1) % DSAF_REG_PER_ZONE;
2125
2126         return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2127                 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2128 }
2129
2130 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2131 {
2132         struct dsaf_hw_stats *hw_stats
2133                 = &dsaf_dev->hw_stats[node_num];
2134         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2135         int i;
2136         u32 reg_tmp;
2137
2138         hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2139                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2140         hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2141                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2142         hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2143                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2144         hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2145                 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2146
2147         reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2148                             DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2149         hw_stats->rx_pause_frame +=
2150                 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2151
2152         hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2153                 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2154         hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2155                 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2156         hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2157                 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2158         hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2159                 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2160         hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2161                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2162         hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2163                 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2164
2165         hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2166                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
2167         hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2168                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
2169
2170         /* pfc pause frame statistics stored in dsaf inode*/
2171         if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2172                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2173                         reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2174                         hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2175                                 reg_tmp + 0x4 * (u64)node_num);
2176                         hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2177                                 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2178                                 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2179                                 0xF0 * (u64)node_num);
2180                 }
2181         }
2182         hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2183                 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2184 }
2185
2186 /**
2187  *hns_dsaf_get_regs - dump dsaf regs
2188  *@dsaf_dev: dsaf device
2189  *@data:data for value of regs
2190  */
2191 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2192 {
2193         u32 i = 0;
2194         u32 j;
2195         u32 *p = data;
2196         u32 reg_tmp;
2197         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2198
2199         /* dsaf common registers */
2200         p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2201         p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2202         p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2203         p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2204         p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2205         p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2206         p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2207         p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2208         p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2209
2210         p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2211         p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2212         p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2213         p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2214         p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2215         p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2216         p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2217         p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2218         p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2219         p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2220         p[19] =  dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2221         p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2222         p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2223         p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2224         p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2225
2226         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2227                 p[24 + i] = dsaf_read_dev(ddev,
2228                                 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2229
2230         p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2231
2232         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2233                 p[33 + i] = dsaf_read_dev(ddev,
2234                                 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2235
2236         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2237                 p[41 + i] = dsaf_read_dev(ddev,
2238                                 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2239
2240         /* dsaf inode registers */
2241         p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2242
2243         p[171] = dsaf_read_dev(ddev,
2244                         DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2245
2246         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2247                 j = i * DSAF_COMM_CHN + port;
2248                 p[172 + i] = dsaf_read_dev(ddev,
2249                                 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2250                 p[175 + i] = dsaf_read_dev(ddev,
2251                                 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2252                 p[178 + i] = dsaf_read_dev(ddev,
2253                                 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2254                 p[181 + i] = dsaf_read_dev(ddev,
2255                                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2256                 p[184 + i] = dsaf_read_dev(ddev,
2257                                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2258                 p[187 + i] = dsaf_read_dev(ddev,
2259                                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2260                 p[190 + i] = dsaf_read_dev(ddev,
2261                                 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2262                 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2263                                     DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2264                 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2265                 p[196 + i] = dsaf_read_dev(ddev,
2266                                 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2267                 p[199 + i] = dsaf_read_dev(ddev,
2268                                 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2269                 p[202 + i] = dsaf_read_dev(ddev,
2270                                 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2271                 p[205 + i] = dsaf_read_dev(ddev,
2272                                 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2273                 p[208 + i] = dsaf_read_dev(ddev,
2274                                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2275                 p[211 + i] = dsaf_read_dev(ddev,
2276                         DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2277                 p[214 + i] = dsaf_read_dev(ddev,
2278                                 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2279                 p[217 + i] = dsaf_read_dev(ddev,
2280                                 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2281                 p[220 + i] = dsaf_read_dev(ddev,
2282                                 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2283                 p[223 + i] = dsaf_read_dev(ddev,
2284                                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2285                 p[224 + i] = dsaf_read_dev(ddev,
2286                                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2287         }
2288
2289         p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2290
2291         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2292                 j = i * DSAF_COMM_CHN + port;
2293                 p[228 + i] = dsaf_read_dev(ddev,
2294                                 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2295         }
2296
2297         p[231] = dsaf_read_dev(ddev,
2298                 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
2299
2300         /* dsaf inode registers */
2301         for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2302                 j = i * DSAF_COMM_CHN + port;
2303                 p[232 + i] = dsaf_read_dev(ddev,
2304                                 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2305                 p[235 + i] = dsaf_read_dev(ddev,
2306                                 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2307                 p[238 + i] = dsaf_read_dev(ddev,
2308                                 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2309                 p[241 + i] = dsaf_read_dev(ddev,
2310                                 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2311                 p[244 + i] = dsaf_read_dev(ddev,
2312                                 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2313                 p[245 + i] = dsaf_read_dev(ddev,
2314                                 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2315                 p[248 + i] = dsaf_read_dev(ddev,
2316                                 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2317                 p[251 + i] = dsaf_read_dev(ddev,
2318                                 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2319                 p[254 + i] = dsaf_read_dev(ddev,
2320                                 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2321                 p[257 + i] = dsaf_read_dev(ddev,
2322                                 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2323                 p[260 + i] = dsaf_read_dev(ddev,
2324                                 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2325                 p[263 + i] = dsaf_read_dev(ddev,
2326                                 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2327                 p[266 + i] = dsaf_read_dev(ddev,
2328                                 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2329                 p[269 + i] = dsaf_read_dev(ddev,
2330                                 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2331                 p[272 + i] = dsaf_read_dev(ddev,
2332                                 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2333                 p[275 + i] = dsaf_read_dev(ddev,
2334                                 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2335                 p[278 + i] = dsaf_read_dev(ddev,
2336                                 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2337                 p[281 + i] = dsaf_read_dev(ddev,
2338                                 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2339                 p[284 + i] = dsaf_read_dev(ddev,
2340                                 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2341                 p[287 + i] = dsaf_read_dev(ddev,
2342                                 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2343                 p[290 + i] = dsaf_read_dev(ddev,
2344                                 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2345                 p[293 + i] = dsaf_read_dev(ddev,
2346                                 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2347                 p[296 + i] = dsaf_read_dev(ddev,
2348                                 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2349                 p[299 + i] = dsaf_read_dev(ddev,
2350                                 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2351                 p[302 + i] = dsaf_read_dev(ddev,
2352                                 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2353                 p[305 + i] = dsaf_read_dev(ddev,
2354                                 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2355                 p[308 + i] = dsaf_read_dev(ddev,
2356                                 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2357         }
2358
2359         /* dsaf onode registers */
2360         for (i = 0; i < DSAF_XOD_NUM; i++) {
2361                 p[311 + i] = dsaf_read_dev(ddev,
2362                                 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2363                 p[319 + i] = dsaf_read_dev(ddev,
2364                                 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2365                 p[327 + i] = dsaf_read_dev(ddev,
2366                                 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2367                 p[335 + i] = dsaf_read_dev(ddev,
2368                                 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2369                 p[343 + i] = dsaf_read_dev(ddev,
2370                                 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2371                 p[351 + i] = dsaf_read_dev(ddev,
2372                                 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2373         }
2374
2375         p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2376         p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2377         p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2378
2379         for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2380                 j = i * DSAF_COMM_CHN + port;
2381                 p[362 + i] = dsaf_read_dev(ddev,
2382                                 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2383                 p[365 + i] = dsaf_read_dev(ddev,
2384                                 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2385                 p[368 + i] = dsaf_read_dev(ddev,
2386                                 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2387                 p[371 + i] = dsaf_read_dev(ddev,
2388                                 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2389                 p[374 + i] = dsaf_read_dev(ddev,
2390                                 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2391                 p[377 + i] = dsaf_read_dev(ddev,
2392                                 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2393                 p[380 + i] = dsaf_read_dev(ddev,
2394                                 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2395                 p[383 + i] = dsaf_read_dev(ddev,
2396                                 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2397                 p[386 + i] = dsaf_read_dev(ddev,
2398                                 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2399                 p[389 + i] = dsaf_read_dev(ddev,
2400                                 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2401         }
2402
2403         p[392] = dsaf_read_dev(ddev,
2404                 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2405         p[393] = dsaf_read_dev(ddev,
2406                 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2407         p[394] = dsaf_read_dev(ddev,
2408                 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2409         p[395] = dsaf_read_dev(ddev,
2410                 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2411         p[396] = dsaf_read_dev(ddev,
2412                 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2413         p[397] = dsaf_read_dev(ddev,
2414                 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2415         p[398] = dsaf_read_dev(ddev,
2416                 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2417         p[399] = dsaf_read_dev(ddev,
2418                 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2419         p[400] = dsaf_read_dev(ddev,
2420                 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2421         p[401] = dsaf_read_dev(ddev,
2422                 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2423         p[402] = dsaf_read_dev(ddev,
2424                 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2425         p[403] = dsaf_read_dev(ddev,
2426                 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2427         p[404] = dsaf_read_dev(ddev,
2428                 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2429
2430         /* dsaf voq registers */
2431         for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2432                 j = (i * DSAF_COMM_CHN + port) * 0x90;
2433                 p[405 + i] = dsaf_read_dev(ddev,
2434                         DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2435                 p[408 + i] = dsaf_read_dev(ddev,
2436                         DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2437                 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2438                 p[414 + i] = dsaf_read_dev(ddev,
2439                         DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2440                 p[417 + i] = dsaf_read_dev(ddev,
2441                         DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2442                 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2443                 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2444                 p[426 + i] = dsaf_read_dev(ddev,
2445                         DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2446                 p[429 + i] = dsaf_read_dev(ddev,
2447                         DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2448                 p[432 + i] = dsaf_read_dev(ddev,
2449                         DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2450                 p[435 + i] = dsaf_read_dev(ddev,
2451                         DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2452                 p[438 + i] = dsaf_read_dev(ddev,
2453                         DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2454         }
2455
2456         /* dsaf tbl registers */
2457         p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2458         p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2459         p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2460         p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2461         p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2462         p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2463         p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2464         p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2465         p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2466         p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2467         p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2468         p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2469         p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2470         p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2471         p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2472         p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2473         p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2474         p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2475         p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2476         p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2477         p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2478         p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2479         p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2480
2481         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2482                 j = i * 0x8;
2483                 p[464 + 2 * i] = dsaf_read_dev(ddev,
2484                         DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2485                 p[465 + 2 * i] = dsaf_read_dev(ddev,
2486                         DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2487         }
2488
2489         p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2490         p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2491         p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2492         p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2493         p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2494         p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2495         p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2496         p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2497         p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2498         p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2499         p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2500         p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2501
2502         /* dsaf other registers */
2503         p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2504         p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2505         p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2506         p[495] = dsaf_read_dev(ddev,
2507                 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2508         p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2509         p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2510
2511         if (!is_ver1)
2512                 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2513
2514         /* mark end of dsaf regs */
2515         for (i = 499; i < 504; i++)
2516                 p[i] = 0xdddddddd;
2517 }
2518
2519 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2520                                              struct dsaf_device *dsaf_dev)
2521 {
2522         char *buff = data;
2523         int i;
2524         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2525
2526         snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2527         buff += ETH_GSTRING_LEN;
2528         snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2529         buff += ETH_GSTRING_LEN;
2530         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2531         buff += ETH_GSTRING_LEN;
2532         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2533         buff += ETH_GSTRING_LEN;
2534         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2535         buff += ETH_GSTRING_LEN;
2536         snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2537         buff += ETH_GSTRING_LEN;
2538         snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2539         buff += ETH_GSTRING_LEN;
2540         snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2541         buff += ETH_GSTRING_LEN;
2542         snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2543         buff += ETH_GSTRING_LEN;
2544         snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2545         buff += ETH_GSTRING_LEN;
2546         snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2547         buff += ETH_GSTRING_LEN;
2548         snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2549         buff += ETH_GSTRING_LEN;
2550         snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2551         buff += ETH_GSTRING_LEN;
2552         if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2553                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2554                         snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2555                                  ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2556                                  node, i);
2557                         snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2558                                  ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2559                                  node, i);
2560                         buff += ETH_GSTRING_LEN;
2561                 }
2562                 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2563         }
2564         snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2565         buff += ETH_GSTRING_LEN;
2566
2567         return buff;
2568 }
2569
2570 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2571                                     int node_num)
2572 {
2573         u64 *p = data;
2574         int i;
2575         struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2576         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2577
2578         p[0] = hw_stats->pad_drop;
2579         p[1] = hw_stats->man_pkts;
2580         p[2] = hw_stats->rx_pkts;
2581         p[3] = hw_stats->rx_pkt_id;
2582         p[4] = hw_stats->rx_pause_frame;
2583         p[5] = hw_stats->release_buf_num;
2584         p[6] = hw_stats->sbm_drop;
2585         p[7] = hw_stats->crc_false;
2586         p[8] = hw_stats->bp_drop;
2587         p[9] = hw_stats->rslt_drop;
2588         p[10] = hw_stats->local_addr_false;
2589         p[11] = hw_stats->vlan_drop;
2590         p[12] = hw_stats->stp_drop;
2591         if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2592                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2593                         p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2594                         p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2595                 }
2596                 p[29] = hw_stats->tx_pkts;
2597                 return &p[30];
2598         }
2599
2600         p[13] = hw_stats->tx_pkts;
2601         return &p[14];
2602 }
2603
2604 /**
2605  *hns_dsaf_get_stats - get dsaf statistic
2606  *@ddev: dsaf device
2607  *@data:statistic value
2608  *@port: port num
2609  */
2610 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2611 {
2612         u64 *p = data;
2613         int node_num = port;
2614
2615         /* for ge/xge node info */
2616         p = hns_dsaf_get_node_stats(ddev, p, node_num);
2617
2618         /* for ppe node info */
2619         node_num = port + DSAF_PPE_INODE_BASE;
2620         (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2621 }
2622
2623 /**
2624  *hns_dsaf_get_sset_count - get dsaf string set count
2625  *@stringset: type of values in data
2626  *return dsaf string name count
2627  */
2628 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2629 {
2630         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2631
2632         if (stringset == ETH_SS_STATS) {
2633                 if (is_ver1)
2634                         return DSAF_STATIC_NUM;
2635                 else
2636                         return DSAF_V2_STATIC_NUM;
2637         }
2638         return 0;
2639 }
2640
2641 /**
2642  *hns_dsaf_get_strings - get dsaf string set
2643  *@stringset:srting set index
2644  *@data:strings name value
2645  *@port:port index
2646  */
2647 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2648                           struct dsaf_device *dsaf_dev)
2649 {
2650         char *buff = (char *)data;
2651         int node = port;
2652
2653         if (stringset != ETH_SS_STATS)
2654                 return;
2655
2656         /* for ge/xge node info */
2657         buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2658
2659         /* for ppe node info */
2660         node = port + DSAF_PPE_INODE_BASE;
2661         (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2662 }
2663
2664 /**
2665  *hns_dsaf_get_sset_count - get dsaf regs count
2666  *return dsaf regs count
2667  */
2668 int hns_dsaf_get_regs_count(void)
2669 {
2670         return DSAF_DUMP_REGS_NUM;
2671 }
2672
2673 /**
2674  * dsaf_probe - probo dsaf dev
2675  * @pdev: dasf platform device
2676  * retuen 0 - success , negative --fail
2677  */
2678 static int hns_dsaf_probe(struct platform_device *pdev)
2679 {
2680         struct dsaf_device *dsaf_dev;
2681         int ret;
2682
2683         dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2684         if (IS_ERR(dsaf_dev)) {
2685                 ret = PTR_ERR(dsaf_dev);
2686                 dev_err(&pdev->dev,
2687                         "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2688                 return ret;
2689         }
2690
2691         ret = hns_dsaf_get_cfg(dsaf_dev);
2692         if (ret)
2693                 goto free_dev;
2694
2695         ret = hns_dsaf_init(dsaf_dev);
2696         if (ret)
2697                 goto free_dev;
2698
2699         ret = hns_mac_init(dsaf_dev);
2700         if (ret)
2701                 goto uninit_dsaf;
2702
2703         ret = hns_ppe_init(dsaf_dev);
2704         if (ret)
2705                 goto uninit_mac;
2706
2707         ret = hns_dsaf_ae_init(dsaf_dev);
2708         if (ret)
2709                 goto uninit_ppe;
2710
2711         return 0;
2712
2713 uninit_ppe:
2714         hns_ppe_uninit(dsaf_dev);
2715
2716 uninit_mac:
2717         hns_mac_uninit(dsaf_dev);
2718
2719 uninit_dsaf:
2720         hns_dsaf_free(dsaf_dev);
2721
2722 free_dev:
2723         hns_dsaf_free_dev(dsaf_dev);
2724
2725         return ret;
2726 }
2727
2728 /**
2729  * dsaf_remove - remove dsaf dev
2730  * @pdev: dasf platform device
2731  */
2732 static int hns_dsaf_remove(struct platform_device *pdev)
2733 {
2734         struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
2735
2736         hns_dsaf_ae_uninit(dsaf_dev);
2737
2738         hns_ppe_uninit(dsaf_dev);
2739
2740         hns_mac_uninit(dsaf_dev);
2741
2742         hns_dsaf_free(dsaf_dev);
2743
2744         hns_dsaf_free_dev(dsaf_dev);
2745
2746         return 0;
2747 }
2748
2749 static const struct of_device_id g_dsaf_match[] = {
2750         {.compatible = "hisilicon,hns-dsaf-v1"},
2751         {.compatible = "hisilicon,hns-dsaf-v2"},
2752         {}
2753 };
2754 MODULE_DEVICE_TABLE(of, g_dsaf_match);
2755
2756 static struct platform_driver g_dsaf_driver = {
2757         .probe = hns_dsaf_probe,
2758         .remove = hns_dsaf_remove,
2759         .driver = {
2760                 .name = DSAF_DRV_NAME,
2761                 .of_match_table = g_dsaf_match,
2762                 .acpi_match_table = hns_dsaf_acpi_match,
2763         },
2764 };
2765
2766 module_platform_driver(g_dsaf_driver);
2767
2768 /**
2769  * hns_dsaf_roce_reset - reset dsaf and roce
2770  * @dsaf_fwnode: Pointer to framework node for the dasf
2771  * @enable: false - request reset , true - drop reset
2772  * retuen 0 - success , negative -fail
2773  */
2774 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
2775 {
2776         struct dsaf_device *dsaf_dev;
2777         struct platform_device *pdev;
2778         u32 mp;
2779         u32 sl;
2780         u32 credit;
2781         int i;
2782         const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2783                 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2784                 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2785                 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2786                 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2787                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2788                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2789                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2790                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2791         };
2792         const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2793                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2794                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2795                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2796                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2797                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2798                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2799                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2800                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2801         };
2802
2803         /* find the platform device corresponding to fwnode */
2804         if (is_of_node(dsaf_fwnode)) {
2805                 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
2806         } else if (is_acpi_device_node(dsaf_fwnode)) {
2807                 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
2808         } else {
2809                 pr_err("fwnode is neither OF or ACPI type\n");
2810                 return -EINVAL;
2811         }
2812
2813         /* check if we were a success in fetching pdev */
2814         if (!pdev) {
2815                 pr_err("couldn't find platform device for node\n");
2816                 return -ENODEV;
2817         }
2818
2819         /* retrieve the dsaf_device from the driver data */
2820         dsaf_dev = dev_get_drvdata(&pdev->dev);
2821         if (!dsaf_dev) {
2822                 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
2823                 return -ENODEV;
2824         }
2825
2826         /* now, make sure we are running on compatible SoC */
2827         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
2828                 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
2829                         dsaf_dev->ae_dev.name);
2830                 return -ENODEV;
2831         }
2832
2833         /* do reset or de-reset according to the flag */
2834         if (!dereset) {
2835                 /* reset rocee-channels in dsaf and rocee */
2836                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2837                                                       false);
2838                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
2839         } else {
2840                 /* configure dsaf tx roce correspond to port map and sl map */
2841                 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
2842                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2843                         dsaf_set_field(mp, 7 << i * 3, i * 3,
2844                                        port_map[i][DSAF_ROCE_6PORT_MODE]);
2845                 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
2846                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
2847
2848                 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
2849                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2850                         dsaf_set_field(sl, 3 << i * 2, i * 2,
2851                                        sl_map[i][DSAF_ROCE_6PORT_MODE]);
2852                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
2853
2854                 /* de-reset rocee-channels in dsaf and rocee */
2855                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2856                                                       true);
2857                 msleep(SRST_TIME_INTERVAL);
2858                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
2859
2860                 /* enable dsaf channel rocee credit */
2861                 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
2862                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
2863                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2864
2865                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
2866                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2867         }
2868         return 0;
2869 }
2870 EXPORT_SYMBOL(hns_dsaf_roce_reset);
2871
2872 MODULE_LICENSE("GPL");
2873 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2874 MODULE_DESCRIPTION("HNS DSAF driver");
2875 MODULE_VERSION(DSAF_MOD_VERSION);