drivers/net/ethernet/intel/igb/igb_ptp.c

   1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
   2  *
   3  * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/device.h>
  20 #include <linux/pci.h>
  21 #include <linux/ptp_classify.h>
  22 #include <linux/clocksource.h>
  23
  24 #include "igb.h"
  25
  26 #define INCVALUE_MASK           0x7fffffff
  27 #define ISGN                    0x80000000
  28
  29 /* The 82580 timesync updates the system timer every 8ns by 8ns,
  30  * and this update value cannot be reprogrammed.
  31  *
  32  * Neither the 82576 nor the 82580 offer registers wide enough to hold
  33  * nanoseconds time values for very long. For the 82580, SYSTIM always
  34  * counts nanoseconds, but the upper 24 bits are not availible. The
  35  * frequency is adjusted by changing the 32 bit fractional nanoseconds
  36  * register, TIMINCA.
  37  *
  38  * For the 82576, the SYSTIM register time unit is affect by the
  39  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
  40  * field are needed to provide the nominal 16 nanosecond period,
  41  * leaving 19 bits for fractional nanoseconds.
  42  *
  43  * We scale the NIC clock cycle by a large factor so that relatively
  44  * small clock corrections can be added or subtracted at each clock
  45  * tick. The drawbacks of a large factor are a) that the clock
  46  * register overflows more quickly (not such a big deal) and b) that
  47  * the increment per tick has to fit into 24 bits.  As a result we
  48  * need to use a shift of 19 so we can fit a value of 16 into the
  49  * TIMINCA register.
  50  *
  51  *
  52  *             SYSTIMH            SYSTIML
  53  *        +--------------+   +---+---+------+
  54  *  82576 |      32      |   | 8 | 5 |  19  |
  55  *        +--------------+   +---+---+------+
  56  *         \________ 45 bits _______/  fract
  57  *
  58  *        +----------+---+   +--------------+
  59  *  82580 |    24    | 8 |   |      32      |
  60  *        +----------+---+   +--------------+
  61  *          reserved  \______ 40 bits _____/
  62  *
  63  *
  64  * The 45 bit 82576 SYSTIM overflows every
  65  *   2^45 * 10^-9 / 3600 = 9.77 hours.
  66  *
  67  * The 40 bit 82580 SYSTIM overflows every
  68  *   2^40 * 10^-9 /  60  = 18.3 minutes.
  69  */
  70
  71 #define IGB_SYSTIM_OVERFLOW_PERIOD      (HZ * 60 * 9)
  72 #define IGB_PTP_TX_TIMEOUT              (HZ * 15)
  73 #define INCPERIOD_82576                 (1 << E1000_TIMINCA_16NS_SHIFT)
  74 #define INCVALUE_82576_MASK             ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
  75 #define INCVALUE_82576                  (16 << IGB_82576_TSYNC_SHIFT)
  76 #define IGB_NBITS_82580                 40
  77
  78 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
  79
  80 /* SYSTIM read access for the 82576 */
  81 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
  82 {
  83         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
  84         struct e1000_hw *hw = &igb->hw;
  85         u64 val;
  86         u32 lo, hi;
  87
  88         lo = rd32(E1000_SYSTIML);
  89         hi = rd32(E1000_SYSTIMH);
  90
  91         val = ((u64) hi) << 32;
  92         val |= lo;
  93
  94         return val;
  95 }
  96
  97 /* SYSTIM read access for the 82580 */
  98 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
  99 {
 100         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
 101         struct e1000_hw *hw = &igb->hw;
 102         u32 lo, hi;
 103         u64 val;
 104
 105         /* The timestamp latches on lowest register read. For the 82580
 106          * the lowest register is SYSTIMR instead of SYSTIML.  However we only
 107          * need to provide nanosecond resolution, so we just ignore it.
 108          */
 109         rd32(E1000_SYSTIMR);
 110         lo = rd32(E1000_SYSTIML);
 111         hi = rd32(E1000_SYSTIMH);
 112
 113         val = ((u64) hi) << 32;
 114         val |= lo;
 115
 116         return val;
 117 }
 118
 119 /* SYSTIM read access for I210/I211 */
 120 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts)
 121 {
 122         struct e1000_hw *hw = &adapter->hw;
 123         u32 sec, nsec;
 124
 125         /* The timestamp latches on lowest register read. For I210/I211, the
 126          * lowest register is SYSTIMR. Since we only need to provide nanosecond
 127          * resolution, we can ignore it.
 128          */
 129         rd32(E1000_SYSTIMR);
 130         nsec = rd32(E1000_SYSTIML);
 131         sec = rd32(E1000_SYSTIMH);
 132
 133         ts->tv_sec = sec;
 134         ts->tv_nsec = nsec;
 135 }
 136
 137 static void igb_ptp_write_i210(struct igb_adapter *adapter,
 138                                const struct timespec *ts)
 139 {
 140         struct e1000_hw *hw = &adapter->hw;
 141
 142         /* Writing the SYSTIMR register is not necessary as it only provides
 143          * sub-nanosecond resolution.
 144          */
 145         wr32(E1000_SYSTIML, ts->tv_nsec);
 146         wr32(E1000_SYSTIMH, ts->tv_sec);
 147 }
 148
 149 /**
 150  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
 151  * @adapter: board private structure
 152  * @hwtstamps: timestamp structure to update
 153  * @systim: unsigned 64bit system time value.
 154  *
 155  * We need to convert the system time value stored in the RX/TXSTMP registers
 156  * into a hwtstamp which can be used by the upper level timestamping functions.
 157  *
 158  * The 'tmreg_lock' spinlock is used to protect the consistency of the
 159  * system time value. This is needed because reading the 64 bit time
 160  * value involves reading two (or three) 32 bit registers. The first
 161  * read latches the value. Ditto for writing.
 162  *
 163  * In addition, here have extended the system time with an overflow
 164  * counter in software.
 165  **/
 166 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
 167                                        struct skb_shared_hwtstamps *hwtstamps,
 168                                        u64 systim)
 169 {
 170         unsigned long flags;
 171         u64 ns;
 172
 173         switch (adapter->hw.mac.type) {
 174         case e1000_82576:
 175         case e1000_82580:
 176         case e1000_i354:
 177         case e1000_i350:
 178                 spin_lock_irqsave(&adapter->tmreg_lock, flags);
 179
 180                 ns = timecounter_cyc2time(&adapter->tc, systim);
 181
 182                 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 183
 184                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 185                 hwtstamps->hwtstamp = ns_to_ktime(ns);
 186                 break;
 187         case e1000_i210:
 188         case e1000_i211:
 189                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 190                 /* Upper 32 bits contain s, lower 32 bits contain ns. */
 191                 hwtstamps->hwtstamp = ktime_set(systim >> 32,
 192                                                 systim & 0xFFFFFFFF);
 193                 break;
 194         default:
 195                 break;
 196         }
 197 }
 198
 199 /* PTP clock operations */
 200 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
 201 {
 202         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 203                                                ptp_caps);
 204         struct e1000_hw *hw = &igb->hw;
 205         int neg_adj = 0;
 206         u64 rate;
 207         u32 incvalue;
 208
 209         if (ppb < 0) {
 210                 neg_adj = 1;
 211                 ppb = -ppb;
 212         }
 213         rate = ppb;
 214         rate <<= 14;
 215         rate = div_u64(rate, 1953125);
 216
 217         incvalue = 16 << IGB_82576_TSYNC_SHIFT;
 218
 219         if (neg_adj)
 220                 incvalue -= rate;
 221         else
 222                 incvalue += rate;
 223
 224         wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
 225
 226         return 0;
 227 }
 228
 229 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
 230 {
 231         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 232                                                ptp_caps);
 233         struct e1000_hw *hw = &igb->hw;
 234         int neg_adj = 0;
 235         u64 rate;
 236         u32 inca;
 237
 238         if (ppb < 0) {
 239                 neg_adj = 1;
 240                 ppb = -ppb;
 241         }
 242         rate = ppb;
 243         rate <<= 26;
 244         rate = div_u64(rate, 1953125);
 245
 246         inca = rate & INCVALUE_MASK;
 247         if (neg_adj)
 248                 inca |= ISGN;
 249
 250         wr32(E1000_TIMINCA, inca);
 251
 252         return 0;
 253 }
 254
 255 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
 256 {
 257         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 258                                                ptp_caps);
 259         unsigned long flags;
 260
 261         spin_lock_irqsave(&igb->tmreg_lock, flags);
 262         timecounter_adjtime(&igb->tc, delta);
 263         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 264
 265         return 0;
 266 }
 267
 268 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
 269 {
 270         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 271                                                ptp_caps);
 272         unsigned long flags;
 273         struct timespec now, then = ns_to_timespec(delta);
 274
 275         spin_lock_irqsave(&igb->tmreg_lock, flags);
 276
 277         igb_ptp_read_i210(igb, &now);
 278         now = timespec_add(now, then);
 279         igb_ptp_write_i210(igb, (const struct timespec *)&now);
 280
 281         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
 287                                  struct timespec *ts)
 288 {
 289         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 290                                                ptp_caps);
 291         unsigned long flags;
 292         u64 ns;
 293         u32 remainder;
 294
 295         spin_lock_irqsave(&igb->tmreg_lock, flags);
 296
 297         ns = timecounter_read(&igb->tc);
 298
 299         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 300
 301         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 302         ts->tv_nsec = remainder;
 303
 304         return 0;
 305 }
 306
 307 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
 308                                 struct timespec *ts)
 309 {
 310         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 311                                                ptp_caps);
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&igb->tmreg_lock, flags);
 315
 316         igb_ptp_read_i210(igb, ts);
 317
 318         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 319
 320         return 0;
 321 }
 322
 323 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
 324                                  const struct timespec *ts)
 325 {
 326         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 327                                                ptp_caps);
 328         unsigned long flags;
 329         u64 ns;
 330
 331         ns = ts->tv_sec * 1000000000ULL;
 332         ns += ts->tv_nsec;
 333
 334         spin_lock_irqsave(&igb->tmreg_lock, flags);
 335
 336         timecounter_init(&igb->tc, &igb->cc, ns);
 337
 338         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 339
 340         return 0;
 341 }
 342
 343 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
 344                                 const struct timespec *ts)
 345 {
 346         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 347                                                ptp_caps);
 348         unsigned long flags;
 349
 350         spin_lock_irqsave(&igb->tmreg_lock, flags);
 351
 352         igb_ptp_write_i210(igb, ts);
 353
 354         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 355
 356         return 0;
 357 }
 358
 359 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
 360                                   struct ptp_clock_request *rq, int on)
 361 {
 362         return -EOPNOTSUPP;
 363 }
 364
 365 /**
 366  * igb_ptp_tx_work
 367  * @work: pointer to work struct
 368  *
 369  * This work function polls the TSYNCTXCTL valid bit to determine when a
 370  * timestamp has been taken for the current stored skb.
 371  **/
 372 static void igb_ptp_tx_work(struct work_struct *work)
 373 {
 374         struct igb_adapter *adapter = container_of(work, struct igb_adapter,
 375                                                    ptp_tx_work);
 376         struct e1000_hw *hw = &adapter->hw;
 377         u32 tsynctxctl;
 378
 379         if (!adapter->ptp_tx_skb)
 380                 return;
 381
 382         if (time_is_before_jiffies(adapter->ptp_tx_start +
 383                                    IGB_PTP_TX_TIMEOUT)) {
 384                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 385                 adapter->ptp_tx_skb = NULL;
 386                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 387                 adapter->tx_hwtstamp_timeouts++;
 388                 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
 389                 return;
 390         }
 391
 392         tsynctxctl = rd32(E1000_TSYNCTXCTL);
 393         if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
 394                 igb_ptp_tx_hwtstamp(adapter);
 395         else
 396                 /* reschedule to check later */
 397                 schedule_work(&adapter->ptp_tx_work);
 398 }
 399
 400 static void igb_ptp_overflow_check(struct work_struct *work)
 401 {
 402         struct igb_adapter *igb =
 403                 container_of(work, struct igb_adapter, ptp_overflow_work.work);
 404         struct timespec ts;
 405
 406         igb->ptp_caps.gettime(&igb->ptp_caps, &ts);
 407
 408         pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
 409
 410         schedule_delayed_work(&igb->ptp_overflow_work,
 411                               IGB_SYSTIM_OVERFLOW_PERIOD);
 412 }
 413
 414 /**
 415  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
 416  * @adapter: private network adapter structure
 417  *
 418  * This watchdog task is scheduled to detect error case where hardware has
 419  * dropped an Rx packet that was timestamped when the ring is full. The
 420  * particular error is rare but leaves the device in a state unable to timestamp
 421  * any future packets.
 422  **/
 423 void igb_ptp_rx_hang(struct igb_adapter *adapter)
 424 {
 425         struct e1000_hw *hw = &adapter->hw;
 426         u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
 427         unsigned long rx_event;
 428
 429         if (hw->mac.type != e1000_82576)
 430                 return;
 431
 432         /* If we don't have a valid timestamp in the registers, just update the
 433          * timeout counter and exit
 434          */
 435         if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
 436                 adapter->last_rx_ptp_check = jiffies;
 437                 return;
 438         }
 439
 440         /* Determine the most recent watchdog or rx_timestamp event */
 441         rx_event = adapter->last_rx_ptp_check;
 442         if (time_after(adapter->last_rx_timestamp, rx_event))
 443                 rx_event = adapter->last_rx_timestamp;
 444
 445         /* Only need to read the high RXSTMP register to clear the lock */
 446         if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 447                 rd32(E1000_RXSTMPH);
 448                 adapter->last_rx_ptp_check = jiffies;
 449                 adapter->rx_hwtstamp_cleared++;
 450                 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
 451         }
 452 }
 453
 454 /**
 455  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 456  * @adapter: Board private structure.
 457  *
 458  * If we were asked to do hardware stamping and such a time stamp is
 459  * available, then it must have been for this skb here because we only
 460  * allow only one such packet into the queue.
 461  **/
 462 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
 463 {
 464         struct e1000_hw *hw = &adapter->hw;
 465         struct skb_shared_hwtstamps shhwtstamps;
 466         u64 regval;
 467
 468         regval = rd32(E1000_TXSTMPL);
 469         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
 470
 471         igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
 472         skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
 473         dev_kfree_skb_any(adapter->ptp_tx_skb);
 474         adapter->ptp_tx_skb = NULL;
 475         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 476 }
 477
 478 /**
 479  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
 480  * @q_vector: Pointer to interrupt specific structure
 481  * @va: Pointer to address containing Rx buffer
 482  * @skb: Buffer containing timestamp and packet
 483  *
 484  * This function is meant to retrieve a timestamp from the first buffer of an
 485  * incoming frame.  The value is stored in little endian format starting on
 486  * byte 8.
 487  **/
 488 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
 489                          unsigned char *va,
 490                          struct sk_buff *skb)
 491 {
 492         __le64 *regval = (__le64 *)va;
 493
 494         /* The timestamp is recorded in little endian format.
 495          * DWORD: 0        1        2        3
 496          * Field: Reserved Reserved SYSTIML  SYSTIMH
 497          */
 498         igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
 499                                    le64_to_cpu(regval[1]));
 500 }
 501
 502 /**
 503  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
 504  * @q_vector: Pointer to interrupt specific structure
 505  * @skb: Buffer containing timestamp and packet
 506  *
 507  * This function is meant to retrieve a timestamp from the internal registers
 508  * of the adapter and store it in the skb.
 509  **/
 510 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
 511                          struct sk_buff *skb)
 512 {
 513         struct igb_adapter *adapter = q_vector->adapter;
 514         struct e1000_hw *hw = &adapter->hw;
 515         u64 regval;
 516
 517         /* If this bit is set, then the RX registers contain the time stamp. No
 518          * other packet will be time stamped until we read these registers, so
 519          * read the registers to make them available again. Because only one
 520          * packet can be time stamped at a time, we know that the register
 521          * values must belong to this one here and therefore we don't need to
 522          * compare any of the additional attributes stored for it.
 523          *
 524          * If nothing went wrong, then it should have a shared tx_flags that we
 525          * can turn into a skb_shared_hwtstamps.
 526          */
 527         if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
 528                 return;
 529
 530         regval = rd32(E1000_RXSTMPL);
 531         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
 532
 533         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 534
 535         /* Update the last_rx_timestamp timer in order to enable watchdog check
 536          * for error case of latched timestamp on a dropped packet.
 537          */
 538         adapter->last_rx_timestamp = jiffies;
 539 }
 540
 541 /**
 542  * igb_ptp_get_ts_config - get hardware time stamping config
 543  * @netdev:
 544  * @ifreq:
 545  *
 546  * Get the hwtstamp_config settings to return to the user. Rather than attempt
 547  * to deconstruct the settings from the registers, just return a shadow copy
 548  * of the last known settings.
 549  **/
 550 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
 551 {
 552         struct igb_adapter *adapter = netdev_priv(netdev);
 553         struct hwtstamp_config *config = &adapter->tstamp_config;
 554
 555         return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
 556                 -EFAULT : 0;
 557 }
 558
 559 /**
 560  * igb_ptp_set_timestamp_mode - setup hardware for timestamping
 561  * @adapter: networking device structure
 562  * @config: hwtstamp configuration
 563  *
 564  * Outgoing time stamping can be enabled and disabled. Play nice and
 565  * disable it when requested, although it shouldn't case any overhead
 566  * when no packet needs it. At most one packet in the queue may be
 567  * marked for time stamping, otherwise it would be impossible to tell
 568  * for sure to which packet the hardware time stamp belongs.
 569  *
 570  * Incoming time stamping has to be configured via the hardware
 571  * filters. Not all combinations are supported, in particular event
 572  * type has to be specified. Matching the kind of event packet is
 573  * not supported, with the exception of "all V2 events regardless of
 574  * level 2 or 4".
 575  */
 576 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
 577                                       struct hwtstamp_config *config)
 578 {
 579         struct e1000_hw *hw = &adapter->hw;
 580         u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
 581         u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 582         u32 tsync_rx_cfg = 0;
 583         bool is_l4 = false;
 584         bool is_l2 = false;
 585         u32 regval;
 586
 587         /* reserved for future extensions */
 588         if (config->flags)
 589                 return -EINVAL;
 590
 591         switch (config->tx_type) {
 592         case HWTSTAMP_TX_OFF:
 593                 tsync_tx_ctl = 0;
 594         case HWTSTAMP_TX_ON:
 595                 break;
 596         default:
 597                 return -ERANGE;
 598         }
 599
 600         switch (config->rx_filter) {
 601         case HWTSTAMP_FILTER_NONE:
 602                 tsync_rx_ctl = 0;
 603                 break;
 604         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 605                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 606                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
 607                 is_l4 = true;
 608                 break;
 609         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 610                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 611                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
 612                 is_l4 = true;
 613                 break;
 614         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 615         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 616         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 617         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 618         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 619         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 620         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 621         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 622         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 623                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
 624                 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 625                 is_l2 = true;
 626                 is_l4 = true;
 627                 break;
 628         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 629         case HWTSTAMP_FILTER_ALL:
 630                 /* 82576 cannot timestamp all packets, which it needs to do to
 631                  * support both V1 Sync and Delay_Req messages
 632                  */
 633                 if (hw->mac.type != e1000_82576) {
 634                         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 635                         config->rx_filter = HWTSTAMP_FILTER_ALL;
 636                         break;
 637                 }
 638                 /* fall through */
 639         default:
 640                 config->rx_filter = HWTSTAMP_FILTER_NONE;
 641                 return -ERANGE;
 642         }
 643
 644         if (hw->mac.type == e1000_82575) {
 645                 if (tsync_rx_ctl | tsync_tx_ctl)
 646                         return -EINVAL;
 647                 return 0;
 648         }
 649
 650         /* Per-packet timestamping only works if all packets are
 651          * timestamped, so enable timestamping in all packets as
 652          * long as one Rx filter was configured.
 653          */
 654         if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
 655                 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 656                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 657                 config->rx_filter = HWTSTAMP_FILTER_ALL;
 658                 is_l2 = true;
 659                 is_l4 = true;
 660
 661                 if ((hw->mac.type == e1000_i210) ||
 662                     (hw->mac.type == e1000_i211)) {
 663                         regval = rd32(E1000_RXPBS);
 664                         regval |= E1000_RXPBS_CFG_TS_EN;
 665                         wr32(E1000_RXPBS, regval);
 666                 }
 667         }
 668
 669         /* enable/disable TX */
 670         regval = rd32(E1000_TSYNCTXCTL);
 671         regval &= ~E1000_TSYNCTXCTL_ENABLED;
 672         regval |= tsync_tx_ctl;
 673         wr32(E1000_TSYNCTXCTL, regval);
 674
 675         /* enable/disable RX */
 676         regval = rd32(E1000_TSYNCRXCTL);
 677         regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
 678         regval |= tsync_rx_ctl;
 679         wr32(E1000_TSYNCRXCTL, regval);
 680
 681         /* define which PTP packets are time stamped */
 682         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
 683
 684         /* define ethertype filter for timestamped packets */
 685         if (is_l2)
 686                 wr32(E1000_ETQF(3),
 687                      (E1000_ETQF_FILTER_ENABLE | /* enable filter */
 688                       E1000_ETQF_1588 | /* enable timestamping */
 689                       ETH_P_1588));     /* 1588 eth protocol type */
 690         else
 691                 wr32(E1000_ETQF(3), 0);
 692
 693         /* L4 Queue Filter[3]: filter by destination port and protocol */
 694         if (is_l4) {
 695                 u32 ftqf = (IPPROTO_UDP /* UDP */
 696                         | E1000_FTQF_VF_BP /* VF not compared */
 697                         | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
 698                         | E1000_FTQF_MASK); /* mask all inputs */
 699                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
 700
 701                 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
 702                 wr32(E1000_IMIREXT(3),
 703                      (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
 704                 if (hw->mac.type == e1000_82576) {
 705                         /* enable source port check */
 706                         wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
 707                         ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
 708                 }
 709                 wr32(E1000_FTQF(3), ftqf);
 710         } else {
 711                 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
 712         }
 713         wrfl();
 714
 715         /* clear TX/RX time stamp registers, just to be sure */
 716         regval = rd32(E1000_TXSTMPL);
 717         regval = rd32(E1000_TXSTMPH);
 718         regval = rd32(E1000_RXSTMPL);
 719         regval = rd32(E1000_RXSTMPH);
 720
 721         return 0;
 722 }
 723
 724 /**
 725  * igb_ptp_set_ts_config - set hardware time stamping config
 726  * @netdev:
 727  * @ifreq:
 728  *
 729  **/
 730 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
 731 {
 732         struct igb_adapter *adapter = netdev_priv(netdev);
 733         struct hwtstamp_config config;
 734         int err;
 735
 736         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 737                 return -EFAULT;
 738
 739         err = igb_ptp_set_timestamp_mode(adapter, &config);
 740         if (err)
 741                 return err;
 742
 743         /* save these settings for future reference */
 744         memcpy(&adapter->tstamp_config, &config,
 745                sizeof(adapter->tstamp_config));
 746
 747         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 748                 -EFAULT : 0;
 749 }
 750
 751 void igb_ptp_init(struct igb_adapter *adapter)
 752 {
 753         struct e1000_hw *hw = &adapter->hw;
 754         struct net_device *netdev = adapter->netdev;
 755
 756         switch (hw->mac.type) {
 757         case e1000_82576:
 758                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 759                 adapter->ptp_caps.owner = THIS_MODULE;
 760                 adapter->ptp_caps.max_adj = 999999881;
 761                 adapter->ptp_caps.n_ext_ts = 0;
 762                 adapter->ptp_caps.pps = 0;
 763                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
 764                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
 765                 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
 766                 adapter->ptp_caps.settime = igb_ptp_settime_82576;
 767                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
 768                 adapter->cc.read = igb_ptp_read_82576;
 769                 adapter->cc.mask = CLOCKSOURCE_MASK(64);
 770                 adapter->cc.mult = 1;
 771                 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
 772                 /* Dial the nominal frequency. */
 773                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
 774                 break;
 775         case e1000_82580:
 776         case e1000_i354:
 777         case e1000_i350:
 778                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 779                 adapter->ptp_caps.owner = THIS_MODULE;
 780                 adapter->ptp_caps.max_adj = 62499999;
 781                 adapter->ptp_caps.n_ext_ts = 0;
 782                 adapter->ptp_caps.pps = 0;
 783                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 784                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
 785                 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
 786                 adapter->ptp_caps.settime = igb_ptp_settime_82576;
 787                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
 788                 adapter->cc.read = igb_ptp_read_82580;
 789                 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
 790                 adapter->cc.mult = 1;
 791                 adapter->cc.shift = 0;
 792                 /* Enable the timer functions by clearing bit 31. */
 793                 wr32(E1000_TSAUXC, 0x0);
 794                 break;
 795         case e1000_i210:
 796         case e1000_i211:
 797                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 798                 adapter->ptp_caps.owner = THIS_MODULE;
 799                 adapter->ptp_caps.max_adj = 62499999;
 800                 adapter->ptp_caps.n_ext_ts = 0;
 801                 adapter->ptp_caps.pps = 0;
 802                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 803                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
 804                 adapter->ptp_caps.gettime = igb_ptp_gettime_i210;
 805                 adapter->ptp_caps.settime = igb_ptp_settime_i210;
 806                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
 807                 /* Enable the timer functions by clearing bit 31. */
 808                 wr32(E1000_TSAUXC, 0x0);
 809                 break;
 810         default:
 811                 adapter->ptp_clock = NULL;
 812                 return;
 813         }
 814
 815         wrfl();
 816
 817         spin_lock_init(&adapter->tmreg_lock);
 818         INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
 819
 820         /* Initialize the clock and overflow work for devices that need it. */
 821         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
 822                 struct timespec ts = ktime_to_timespec(ktime_get_real());
 823
 824                 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
 825         } else {
 826                 timecounter_init(&adapter->tc, &adapter->cc,
 827                                  ktime_to_ns(ktime_get_real()));
 828
 829                 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
 830                                   igb_ptp_overflow_check);
 831
 832                 schedule_delayed_work(&adapter->ptp_overflow_work,
 833                                       IGB_SYSTIM_OVERFLOW_PERIOD);
 834         }
 835
 836         /* Initialize the time sync interrupts for devices that support it. */
 837         if (hw->mac.type >= e1000_82580) {
 838                 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
 839                 wr32(E1000_IMS, E1000_IMS_TS);
 840         }
 841
 842         adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
 843         adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
 844
 845         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 846                                                 &adapter->pdev->dev);
 847         if (IS_ERR(adapter->ptp_clock)) {
 848                 adapter->ptp_clock = NULL;
 849                 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
 850         } else {
 851                 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
 852                          adapter->netdev->name);
 853                 adapter->flags |= IGB_FLAG_PTP;
 854         }
 855 }
 856
 857 /**
 858  * igb_ptp_stop - Disable PTP device and stop the overflow check.
 859  * @adapter: Board private structure.
 860  *
 861  * This function stops the PTP support and cancels the delayed work.
 862  **/
 863 void igb_ptp_stop(struct igb_adapter *adapter)
 864 {
 865         switch (adapter->hw.mac.type) {
 866         case e1000_82576:
 867         case e1000_82580:
 868         case e1000_i354:
 869         case e1000_i350:
 870                 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
 871                 break;
 872         case e1000_i210:
 873         case e1000_i211:
 874                 /* No delayed work to cancel. */
 875                 break;
 876         default:
 877                 return;
 878         }
 879
 880         cancel_work_sync(&adapter->ptp_tx_work);
 881         if (adapter->ptp_tx_skb) {
 882                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 883                 adapter->ptp_tx_skb = NULL;
 884                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 885         }
 886
 887         if (adapter->ptp_clock) {
 888                 ptp_clock_unregister(adapter->ptp_clock);
 889                 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
 890                          adapter->netdev->name);
 891                 adapter->flags &= ~IGB_FLAG_PTP;
 892         }
 893 }
 894
 895 /**
 896  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
 897  * @adapter: Board private structure.
 898  *
 899  * This function handles the reset work required to re-enable the PTP device.
 900  **/
 901 void igb_ptp_reset(struct igb_adapter *adapter)
 902 {
 903         struct e1000_hw *hw = &adapter->hw;
 904
 905         if (!(adapter->flags & IGB_FLAG_PTP))
 906                 return;
 907
 908         /* reset the tstamp_config */
 909         igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
 910
 911         switch (adapter->hw.mac.type) {
 912         case e1000_82576:
 913                 /* Dial the nominal frequency. */
 914                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
 915                 break;
 916         case e1000_82580:
 917         case e1000_i354:
 918         case e1000_i350:
 919         case e1000_i210:
 920         case e1000_i211:
 921                 /* Enable the timer functions and interrupts. */
 922                 wr32(E1000_TSAUXC, 0x0);
 923                 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
 924                 wr32(E1000_IMS, E1000_IMS_TS);
 925                 break;
 926         default:
 927                 /* No work to do. */
 928                 return;
 929         }
 930
 931         /* Re-initialize the timer. */
 932         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
 933                 struct timespec ts = ktime_to_timespec(ktime_get_real());
 934
 935                 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
 936         } else {
 937                 timecounter_init(&adapter->tc, &adapter->cc,
 938                                  ktime_to_ns(ktime_get_real()));
 939         }
 940 }