1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/ptp_classify.h>
32 * The 82599 and the X540 do not have true 64bit nanosecond scale
33 * counter registers. Instead, SYSTIME is defined by a fixed point
34 * system which allows the user to define the scale counter increment
35 * value at every level change of the oscillator driving the SYSTIME
36 * value. For both devices the TIMINCA:IV field defines this
37 * increment. On the X540 device, 31 bits are provided. However on the
38 * 82599 only provides 24 bits. The time unit is determined by the
39 * clock frequency of the oscillator in combination with the TIMINCA
40 * register. When these devices link at 10Gb the oscillator has a
41 * period of 6.4ns. In order to convert the scale counter into
42 * nanoseconds the cyclecounter and timecounter structures are
43 * used. The SYSTIME registers need to be converted to ns values by use
44 * of only a right shift (division by power of 2). The following math
45 * determines the largest incvalue that will fit into the available
46 * bits in the TIMINCA register.
48 * PeriodWidth: Number of bits to store the clock period
49 * MaxWidth: The maximum width value of the TIMINCA register
50 * Period: The clock period for the oscillator
51 * round(): discard the fractional portion of the calculation
53 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
55 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
56 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
58 * The period also changes based on the link speed:
59 * At 10Gb link or no link, the period remains the same.
60 * At 1Gb link, the period is multiplied by 10. (64ns)
61 * At 100Mb link, the period is multiplied by 100. (640ns)
63 * The calculated value allows us to right shift the SYSTIME register
64 * value in order to quickly convert it into a nanosecond clock,
65 * while allowing for the maximum possible adjustment value.
67 * These diagrams are only for the 10Gb link period
70 * +--------------+ +--------------+
71 * X540 | 32 | | 1 | 3 | 28 |
72 * *--------------+ +--------------+
73 * \________ 36 bits ______/ fract
75 * +--------------+ +--------------+
76 * 82599 | 32 | | 8 | 3 | 21 |
77 * *--------------+ +--------------+
78 * \________ 43 bits ______/ fract
80 * The 36 bit X540 SYSTIME overflows every
81 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
83 * The 43 bit 82599 SYSTIME overflows every
84 * 2^43 * 10^-9 / 3600 = 2.4 hours
86 #define IXGBE_INCVAL_10GB 0x66666666
87 #define IXGBE_INCVAL_1GB 0x40000000
88 #define IXGBE_INCVAL_100 0x50000000
90 #define IXGBE_INCVAL_SHIFT_10GB 28
91 #define IXGBE_INCVAL_SHIFT_1GB 24
92 #define IXGBE_INCVAL_SHIFT_100 21
94 #define IXGBE_INCVAL_SHIFT_82599 7
95 #define IXGBE_INCPER_SHIFT_82599 24
96 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
101 /* half of a one second clock period, for use with PPS signal. We have to use
102 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in
103 * order to force at least 64bits of precision for shifting
105 #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
108 * ixgbe_ptp_setup_sdp
109 * @hw: the hardware private structure
111 * this function enables or disables the clock out feature on SDP0 for
112 * the X540 device. It will create a 1second periodic output that can
113 * be used as the PPS (via an interrupt).
115 * It calculates when the systime will be on an exact second, and then
116 * aligns the start of the PPS signal to that value. The shift is
117 * necessary because it can change based on the link speed.
119 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
121 struct ixgbe_hw *hw = &adapter->hw;
122 int shift = adapter->cc.shift;
123 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
124 u64 ns = 0, clock_edge = 0;
126 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
127 (hw->mac.type == ixgbe_mac_X540)) {
129 /* disable the pin first */
130 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
131 IXGBE_WRITE_FLUSH(hw);
133 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
136 * enable the SDP0 pin as output, and connected to the
137 * native function for Timesync (ClockOut)
139 esdp |= (IXGBE_ESDP_SDP0_DIR |
140 IXGBE_ESDP_SDP0_NATIVE);
143 * enable the Clock Out feature on SDP0, and allow
144 * interrupts to occur when the pin changes
146 tsauxc = (IXGBE_TSAUXC_EN_CLK |
147 IXGBE_TSAUXC_SYNCLK |
148 IXGBE_TSAUXC_SDP0_INT);
150 /* clock period (or pulse length) */
151 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
152 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
155 * Account for the cyclecounter wrap-around value by
156 * using the converted ns value of the current time to
157 * check for when the next aligned second would occur.
159 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
160 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
161 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
163 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
164 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
166 /* specify the initial clock start time */
167 trgttiml = (u32)clock_edge;
168 trgttimh = (u32)(clock_edge >> 32);
170 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
171 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
172 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
173 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
178 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
181 IXGBE_WRITE_FLUSH(hw);
185 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
186 * @cc: the cyclecounter structure
188 * this function reads the cyclecounter registers and is called by the
189 * cyclecounter structure used to construct a ns counter from the
190 * arbitrary fixed point registers
192 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
194 struct ixgbe_adapter *adapter =
195 container_of(cc, struct ixgbe_adapter, cc);
196 struct ixgbe_hw *hw = &adapter->hw;
199 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
200 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
207 * @ptp: the ptp clock structure
208 * @ppb: parts per billion adjustment from base
210 * adjust the frequency of the ptp cycle counter by the
211 * indicated ppb from the base frequency.
213 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
215 struct ixgbe_adapter *adapter =
216 container_of(ptp, struct ixgbe_adapter, ptp_caps);
217 struct ixgbe_hw *hw = &adapter->hw;
228 incval = ACCESS_ONCE(adapter->base_incval);
232 diff = div_u64(freq, 1000000000ULL);
234 incval = neg_adj ? (incval - diff) : (incval + diff);
236 switch (hw->mac.type) {
238 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
240 case ixgbe_mac_82599EB:
241 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
242 (1 << IXGBE_INCPER_SHIFT_82599) |
254 * @ptp: the ptp clock structure
255 * @delta: offset to adjust the cycle counter by
257 * adjust the timer by resetting the timecounter structure.
259 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
261 struct ixgbe_adapter *adapter =
262 container_of(ptp, struct ixgbe_adapter, ptp_caps);
265 spin_lock_irqsave(&adapter->tmreg_lock, flags);
266 timecounter_adjtime(&adapter->tc, delta);
267 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
269 ixgbe_ptp_setup_sdp(adapter);
276 * @ptp: the ptp clock structure
277 * @ts: timespec structure to hold the current time value
279 * read the timecounter and return the correct value on ns,
280 * after converting it into a struct timespec.
282 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
284 struct ixgbe_adapter *adapter =
285 container_of(ptp, struct ixgbe_adapter, ptp_caps);
290 spin_lock_irqsave(&adapter->tmreg_lock, flags);
291 ns = timecounter_read(&adapter->tc);
292 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
294 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
295 ts->tv_nsec = remainder;
302 * @ptp: the ptp clock structure
303 * @ts: the timespec containing the new time for the cycle counter
305 * reset the timecounter to use a new base value instead of the kernel
308 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
309 const struct timespec *ts)
311 struct ixgbe_adapter *adapter =
312 container_of(ptp, struct ixgbe_adapter, ptp_caps);
316 ns = ts->tv_sec * 1000000000ULL;
319 /* reset the timecounter */
320 spin_lock_irqsave(&adapter->tmreg_lock, flags);
321 timecounter_init(&adapter->tc, &adapter->cc, ns);
322 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
324 ixgbe_ptp_setup_sdp(adapter);
329 * ixgbe_ptp_feature_enable
330 * @ptp: the ptp clock structure
331 * @rq: the requested feature to change
332 * @on: whether to enable or disable the feature
334 * enable (or disable) ancillary features of the phc subsystem.
335 * our driver only supports the PPS feature on the X540
337 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
338 struct ptp_clock_request *rq, int on)
340 struct ixgbe_adapter *adapter =
341 container_of(ptp, struct ixgbe_adapter, ptp_caps);
344 * When PPS is enabled, unmask the interrupt for the ClockOut
345 * feature, so that the interrupt handler can send the PPS
346 * event when the clock SDP triggers. Clear mask when PPS is
349 if (rq->type == PTP_CLK_REQ_PPS) {
350 switch (adapter->hw.mac.type) {
353 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
355 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
357 ixgbe_ptp_setup_sdp(adapter);
368 * ixgbe_ptp_check_pps_event
369 * @adapter: the private adapter structure
370 * @eicr: the interrupt cause register value
372 * This function is called by the interrupt routine when checking for
373 * interrupts. It will check and handle a pps event.
375 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
377 struct ixgbe_hw *hw = &adapter->hw;
378 struct ptp_clock_event event;
380 event.type = PTP_CLOCK_PPS;
382 /* this check is necessary in case the interrupt was enabled via some
383 * alternative means (ex. debug_fs). Better to check here than
384 * everywhere that calls this function.
386 if (!adapter->ptp_clock)
389 switch (hw->mac.type) {
391 ptp_clock_event(adapter->ptp_clock, &event);
399 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
400 * @adapter: private adapter struct
402 * this watchdog task periodically reads the timecounter
403 * in order to prevent missing when the system time registers wrap
404 * around. This needs to be run approximately twice a minute.
406 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
408 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
409 IXGBE_OVERFLOW_PERIOD);
413 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
414 adapter->last_overflow_check = jiffies;
419 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
420 * @adapter: private network adapter structure
422 * this watchdog task is scheduled to detect error case where hardware has
423 * dropped an Rx packet that was timestamped when the ring is full. The
424 * particular error is rare but leaves the device in a state unable to timestamp
425 * any future packets.
427 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
429 struct ixgbe_hw *hw = &adapter->hw;
430 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
431 unsigned long rx_event;
433 /* if we don't have a valid timestamp in the registers, just update the
434 * timeout counter and exit
436 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
437 adapter->last_rx_ptp_check = jiffies;
441 /* determine the most recent watchdog or rx_timestamp event */
442 rx_event = adapter->last_rx_ptp_check;
443 if (time_after(adapter->last_rx_timestamp, rx_event))
444 rx_event = adapter->last_rx_timestamp;
446 /* only need to read the high RXSTMP register to clear the lock */
447 if (time_is_before_jiffies(rx_event + 5*HZ)) {
448 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
449 adapter->last_rx_ptp_check = jiffies;
451 e_warn(drv, "clearing RX Timestamp hang\n");
456 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
457 * @adapter: the private adapter struct
459 * if the timestamp is valid, we convert it into the timecounter ns
460 * value, then store that result into the shhwtstamps structure which
461 * is passed up the network stack
463 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
465 struct ixgbe_hw *hw = &adapter->hw;
466 struct skb_shared_hwtstamps shhwtstamps;
470 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
471 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
473 spin_lock_irqsave(&adapter->tmreg_lock, flags);
474 ns = timecounter_cyc2time(&adapter->tc, regval);
475 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
477 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
478 shhwtstamps.hwtstamp = ns_to_ktime(ns);
479 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
481 dev_kfree_skb_any(adapter->ptp_tx_skb);
482 adapter->ptp_tx_skb = NULL;
483 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
487 * ixgbe_ptp_tx_hwtstamp_work
488 * @work: pointer to the work struct
490 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
491 * timestamp has been taken for the current skb. It is necesary, because the
492 * descriptor's "done" bit does not correlate with the timestamp event.
494 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
496 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
498 struct ixgbe_hw *hw = &adapter->hw;
499 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
500 IXGBE_PTP_TX_TIMEOUT);
504 dev_kfree_skb_any(adapter->ptp_tx_skb);
505 adapter->ptp_tx_skb = NULL;
506 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
507 e_warn(drv, "clearing Tx Timestamp hang\n");
511 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
512 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
513 ixgbe_ptp_tx_hwtstamp(adapter);
515 /* reschedule to keep checking if it's not available yet */
516 schedule_work(&adapter->ptp_tx_work);
520 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
521 * @adapter: pointer to adapter struct
522 * @skb: particular skb to send timestamp with
524 * if the timestamp is valid, we convert it into the timecounter ns
525 * value, then store that result into the shhwtstamps structure which
526 * is passed up the network stack
528 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
530 struct ixgbe_hw *hw = &adapter->hw;
531 struct skb_shared_hwtstamps *shhwtstamps;
536 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
537 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
540 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
541 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
543 spin_lock_irqsave(&adapter->tmreg_lock, flags);
544 ns = timecounter_cyc2time(&adapter->tc, regval);
545 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
547 shhwtstamps = skb_hwtstamps(skb);
548 shhwtstamps->hwtstamp = ns_to_ktime(ns);
550 /* Update the last_rx_timestamp timer in order to enable watchdog check
551 * for error case of latched timestamp on a dropped packet.
553 adapter->last_rx_timestamp = jiffies;
556 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
558 struct hwtstamp_config *config = &adapter->tstamp_config;
560 return copy_to_user(ifr->ifr_data, config,
561 sizeof(*config)) ? -EFAULT : 0;
565 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
566 * @adapter: the private ixgbe adapter structure
567 * @config: the hwtstamp configuration requested
569 * Outgoing time stamping can be enabled and disabled. Play nice and
570 * disable it when requested, although it shouldn't cause any overhead
571 * when no packet needs it. At most one packet in the queue may be
572 * marked for time stamping, otherwise it would be impossible to tell
573 * for sure to which packet the hardware time stamp belongs.
575 * Incoming time stamping has to be configured via the hardware
576 * filters. Not all combinations are supported, in particular event
577 * type has to be specified. Matching the kind of event packet is
578 * not supported, with the exception of "all V2 events regardless of
581 * Since hardware always timestamps Path delay packets when timestamping V2
582 * packets, regardless of the type specified in the register, only use V2
583 * Event mode. This more accurately tells the user what the hardware is going
586 * Note: this may modify the hwtstamp configuration towards a more general
587 * mode, if required to support the specifically requested mode.
589 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
590 struct hwtstamp_config *config)
592 struct ixgbe_hw *hw = &adapter->hw;
593 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
594 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
595 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
599 /* reserved for future extensions */
603 switch (config->tx_type) {
604 case HWTSTAMP_TX_OFF:
612 switch (config->rx_filter) {
613 case HWTSTAMP_FILTER_NONE:
617 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
618 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
619 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
621 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
622 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
623 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
625 case HWTSTAMP_FILTER_PTP_V2_EVENT:
626 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
627 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
628 case HWTSTAMP_FILTER_PTP_V2_SYNC:
629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
630 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
631 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
632 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
633 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
634 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
636 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
638 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
639 case HWTSTAMP_FILTER_ALL:
642 * register RXMTRL must be set in order to do V1 packets,
643 * therefore it is not possible to time stamp both V1 Sync and
644 * Delay_Req messages and hardware does not support
645 * timestamping all packets => return error
647 config->rx_filter = HWTSTAMP_FILTER_NONE;
651 if (hw->mac.type == ixgbe_mac_82598EB) {
652 if (tsync_rx_ctl | tsync_tx_ctl)
657 /* define ethertype filter for timestamping L2 packets */
659 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
660 (IXGBE_ETQF_FILTER_EN | /* enable filter */
661 IXGBE_ETQF_1588 | /* enable timestamping */
662 ETH_P_1588)); /* 1588 eth protocol type */
664 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
666 /* enable/disable TX */
667 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
668 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
669 regval |= tsync_tx_ctl;
670 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
672 /* enable/disable RX */
673 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
674 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
675 regval |= tsync_rx_ctl;
676 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
678 /* define which PTP packets are time stamped */
679 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
681 IXGBE_WRITE_FLUSH(hw);
683 /* clear TX/RX time stamp registers, just to be sure */
684 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
685 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
691 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
692 * @adapter: pointer to adapter struct
695 * Set hardware to requested mode. If unsupported, return an error with no
696 * changes. Otherwise, store the mode for future reference.
698 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
700 struct hwtstamp_config config;
703 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
706 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
710 /* save these settings for future reference */
711 memcpy(&adapter->tstamp_config, &config,
712 sizeof(adapter->tstamp_config));
714 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
719 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
720 * @adapter: pointer to the adapter structure
722 * This function should be called to set the proper values for the TIMINCA
723 * register and tell the cyclecounter structure what the tick rate of SYSTIME
724 * is. It does not directly modify SYSTIME registers or the timecounter
725 * structure. It should be called whenever a new TIMINCA value is necessary,
726 * such as during initialization or when the link speed changes.
728 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
730 struct ixgbe_hw *hw = &adapter->hw;
736 * Scale the NIC cycle counter by a large factor so that
737 * relatively small corrections to the frequency can be added
738 * or subtracted. The drawbacks of a large factor include
739 * (a) the clock register overflows more quickly, (b) the cycle
740 * counter structure must be able to convert the systime value
741 * to nanoseconds using only a multiplier and a right-shift,
742 * and (c) the value must fit within the timinca register space
743 * => math based on internal DMA clock rate and available bits
745 * Note that when there is no link, internal DMA clock is same as when
746 * link speed is 10Gb. Set the registers correctly even when link is
747 * down to preserve the clock setting
749 switch (adapter->link_speed) {
750 case IXGBE_LINK_SPEED_100_FULL:
751 incval = IXGBE_INCVAL_100;
752 shift = IXGBE_INCVAL_SHIFT_100;
754 case IXGBE_LINK_SPEED_1GB_FULL:
755 incval = IXGBE_INCVAL_1GB;
756 shift = IXGBE_INCVAL_SHIFT_1GB;
758 case IXGBE_LINK_SPEED_10GB_FULL:
760 incval = IXGBE_INCVAL_10GB;
761 shift = IXGBE_INCVAL_SHIFT_10GB;
766 * Modify the calculated values to fit within the correct
767 * number of bits specified by the hardware. The 82599 doesn't
768 * have the same space as the X540, so bitshift the calculated
771 switch (hw->mac.type) {
773 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
775 case ixgbe_mac_82599EB:
776 incval >>= IXGBE_INCVAL_SHIFT_82599;
777 shift -= IXGBE_INCVAL_SHIFT_82599;
778 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
779 (1 << IXGBE_INCPER_SHIFT_82599) |
783 /* other devices aren't supported */
787 /* update the base incval used to calculate frequency adjustment */
788 ACCESS_ONCE(adapter->base_incval) = incval;
791 /* need lock to prevent incorrect read while modifying cyclecounter */
792 spin_lock_irqsave(&adapter->tmreg_lock, flags);
794 memset(&adapter->cc, 0, sizeof(adapter->cc));
795 adapter->cc.read = ixgbe_ptp_read;
796 adapter->cc.mask = CLOCKSOURCE_MASK(64);
797 adapter->cc.shift = shift;
798 adapter->cc.mult = 1;
800 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
805 * @adapter: the ixgbe private board structure
807 * When the MAC resets, all the hardware bits for timesync are reset. This
808 * function is used to re-enable the device for PTP based on current settings.
809 * We do lose the current clock time, so just reset the cyclecounter to the
810 * system real clock time.
812 * This function will maintain hwtstamp_config settings, and resets the SDP
813 * output if it was enabled.
815 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
817 struct ixgbe_hw *hw = &adapter->hw;
820 /* set SYSTIME registers to 0 just in case */
821 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
822 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
823 IXGBE_WRITE_FLUSH(hw);
825 /* reset the hardware timestamping mode */
826 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
828 ixgbe_ptp_start_cyclecounter(adapter);
830 spin_lock_irqsave(&adapter->tmreg_lock, flags);
832 /* reset the ns time counter */
833 timecounter_init(&adapter->tc, &adapter->cc,
834 ktime_to_ns(ktime_get_real()));
836 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
839 * Now that the shift has been calculated and the systime
840 * registers reset, (re-)enable the Clock out feature
842 ixgbe_ptp_setup_sdp(adapter);
846 * ixgbe_ptp_create_clock
847 * @adapter: the ixgbe private adapter structure
849 * This function performs setup of the user entry point function table and
850 * initializes the PTP clock device, which is used to access the clock-like
851 * features of the PTP core. It will be called by ixgbe_ptp_init, only if
852 * there isn't already a clock device (such as after a suspend/resume cycle,
853 * where the clock device wasn't destroyed).
855 static int ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
857 struct net_device *netdev = adapter->netdev;
860 /* do nothing if we already have a clock device */
861 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
864 switch (adapter->hw.mac.type) {
866 snprintf(adapter->ptp_caps.name,
867 sizeof(adapter->ptp_caps.name),
869 adapter->ptp_caps.owner = THIS_MODULE;
870 adapter->ptp_caps.max_adj = 250000000;
871 adapter->ptp_caps.n_alarm = 0;
872 adapter->ptp_caps.n_ext_ts = 0;
873 adapter->ptp_caps.n_per_out = 0;
874 adapter->ptp_caps.pps = 1;
875 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
876 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
877 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
878 adapter->ptp_caps.settime = ixgbe_ptp_settime;
879 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
881 case ixgbe_mac_82599EB:
882 snprintf(adapter->ptp_caps.name,
883 sizeof(adapter->ptp_caps.name),
885 adapter->ptp_caps.owner = THIS_MODULE;
886 adapter->ptp_caps.max_adj = 250000000;
887 adapter->ptp_caps.n_alarm = 0;
888 adapter->ptp_caps.n_ext_ts = 0;
889 adapter->ptp_caps.n_per_out = 0;
890 adapter->ptp_caps.pps = 0;
891 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
892 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
893 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
894 adapter->ptp_caps.settime = ixgbe_ptp_settime;
895 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
898 adapter->ptp_clock = NULL;
902 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
903 &adapter->pdev->dev);
904 if (IS_ERR(adapter->ptp_clock)) {
905 err = PTR_ERR(adapter->ptp_clock);
906 adapter->ptp_clock = NULL;
907 e_dev_err("ptp_clock_register failed\n");
910 e_dev_info("registered PHC device on %s\n", netdev->name);
912 /* set default timestamp mode to disabled here. We do this in
913 * create_clock instead of init, because we don't want to override the
914 * previous settings during a resume cycle.
916 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
917 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
924 * @adapter: the ixgbe private adapter structure
926 * This function performs the required steps for enabling PTP
927 * support. If PTP support has already been loaded it simply calls the
928 * cyclecounter init routine and exits.
930 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
932 /* initialize the spin lock first since we can't control when a user
933 * will call the entry functions once we have initialized the clock
936 spin_lock_init(&adapter->tmreg_lock);
938 /* obtain a PTP device, or re-use an existing device */
939 if (ixgbe_ptp_create_clock(adapter))
942 /* we have a clock so we can initialize work now */
943 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
945 /* reset the PTP related hardware bits */
946 ixgbe_ptp_reset(adapter);
948 /* enter the IXGBE_PTP_RUNNING state */
949 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
955 * ixgbe_ptp_suspend - stop PTP work items
956 * @ adapter: pointer to adapter struct
958 * this function suspends PTP activity, and prevents more PTP work from being
959 * generated, but does not destroy the PTP clock device.
961 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
963 /* Leave the IXGBE_PTP_RUNNING state. */
964 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
967 /* since this might be called in suspend, we don't clear the state,
968 * but simply reset the auxiliary PPS signal control register
970 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TSAUXC, 0x0);
972 /* ensure that we cancel any pending PTP Tx work item in progress */
973 cancel_work_sync(&adapter->ptp_tx_work);
974 if (adapter->ptp_tx_skb) {
975 dev_kfree_skb_any(adapter->ptp_tx_skb);
976 adapter->ptp_tx_skb = NULL;
977 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
982 * ixgbe_ptp_stop - close the PTP device
983 * @adapter: pointer to adapter struct
985 * completely destroy the PTP device, should only be called when the device is
986 * being fully closed.
988 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
990 /* first, suspend PTP activity */
991 ixgbe_ptp_suspend(adapter);
993 /* disable the PTP clock device */
994 if (adapter->ptp_clock) {
995 ptp_clock_unregister(adapter->ptp_clock);
996 adapter->ptp_clock = NULL;
997 e_dev_info("removed PHC on %s\n",
998 adapter->netdev->name);