2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos = true;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
60 switch (sizeof (dest)) { \
61 case 1: (dest) = *(u8 *) __p; break; \
62 case 2: (dest) = be16_to_cpup(__p); break; \
63 case 4: (dest) = be32_to_cpup(__p); break; \
64 case 8: val = get_unaligned((u64 *)__p); \
65 (dest) = be64_to_cpu(val); break; \
66 default: __buggy_use_of_MLX4_GET(); \
70 #define MLX4_PUT(dest, source, offset) \
72 void *__d = ((char *) (dest) + (offset)); \
73 switch (sizeof(source)) { \
74 case 1: *(u8 *) __d = (source); break; \
75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
78 default: __buggy_use_of_MLX4_PUT(); \
82 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
84 static const char *fname[] = {
85 [ 0] = "RC transport",
86 [ 1] = "UC transport",
87 [ 2] = "UD transport",
88 [ 3] = "XRC transport",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [12] = "Dual Port Different Protocol (DPDP) support",
94 [15] = "Big LSO headers",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
101 [30] = "IBoE support",
102 [32] = "Unicast loopback support",
103 [34] = "FCS header control",
104 [37] = "Wake On LAN (port1) support",
105 [38] = "Wake On LAN (port2) support",
106 [40] = "UDP RSS support",
107 [41] = "Unicast VEP steering support",
108 [42] = "Multicast VEP steering support",
109 [48] = "Counters support",
110 [52] = "RSS IP fragments support",
111 [53] = "Port ETS Scheduler support",
112 [55] = "Port link type sensing support",
113 [59] = "Port management change event support",
114 [61] = "64 byte EQE support",
115 [62] = "64 byte CQE support",
119 mlx4_dbg(dev, "DEV_CAP flags:\n");
120 for (i = 0; i < ARRAY_SIZE(fname); ++i)
121 if (fname[i] && (flags & (1LL << i)))
122 mlx4_dbg(dev, " %s\n", fname[i]);
125 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 static const char * const fname[] = {
129 [1] = "RSS Toeplitz Hash Function support",
130 [2] = "RSS XOR Hash Function support",
131 [3] = "Device managed flow steering support",
132 [4] = "Automatic MAC reassignment support",
133 [5] = "Time stamping support",
134 [6] = "VST (control vlan insertion/stripping) support",
135 [7] = "FSM (MAC anti-spoofing) support",
136 [8] = "Dynamic QP updates support",
137 [9] = "Device managed flow steering IPoIB support",
138 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
139 [11] = "MAD DEMUX (Secure-Host) support",
140 [12] = "Large cache line (>64B) CQE stride support",
141 [13] = "Large cache line (>64B) EQE stride support",
142 [14] = "Ethernet protocol control support",
143 [15] = "Ethernet Backplane autoneg support",
144 [16] = "CONFIG DEV support",
145 [17] = "Asymmetric EQs support",
146 [18] = "More than 80 VFs support",
147 [19] = "Performance optimized for limited rule configuration flow steering support",
148 [20] = "Recoverable error events support",
149 [21] = "Port Remap support",
150 [22] = "QCN support",
151 [23] = "QP rate limiting support",
152 [24] = "Ethernet Flow control statistics support",
153 [25] = "Granular QoS per VF support",
154 [26] = "Port ETS Scheduler support",
155 [27] = "Port beacon support",
156 [28] = "RX-ALL support",
157 [29] = "802.1ad offload support",
158 [31] = "Modifying loopback source checks using UPDATE_QP support",
159 [32] = "Loopback source checks support",
160 [33] = "RoCEv2 support",
161 [34] = "DMFS Sniffer support (UC & MC)",
162 [36] = "sl to vl mapping table change event support"
166 for (i = 0; i < ARRAY_SIZE(fname); ++i)
167 if (fname[i] && (flags & (1LL << i)))
168 mlx4_dbg(dev, " %s\n", fname[i]);
171 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
173 struct mlx4_cmd_mailbox *mailbox;
177 #define MOD_STAT_CFG_IN_SIZE 0x100
179 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
180 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
182 mailbox = mlx4_alloc_cmd_mailbox(dev);
184 return PTR_ERR(mailbox);
185 inbox = mailbox->buf;
187 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
188 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
190 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
191 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
193 mlx4_free_cmd_mailbox(dev, mailbox);
197 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
199 struct mlx4_cmd_mailbox *mailbox;
206 #define QUERY_FUNC_BUS_OFFSET 0x00
207 #define QUERY_FUNC_DEVICE_OFFSET 0x01
208 #define QUERY_FUNC_FUNCTION_OFFSET 0x01
209 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
210 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
211 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06
212 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
214 mailbox = mlx4_alloc_cmd_mailbox(dev);
216 return PTR_ERR(mailbox);
217 outbox = mailbox->buf;
221 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
223 MLX4_CMD_TIME_CLASS_A,
228 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
229 func->bus = field & 0xf;
230 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
231 func->device = field & 0xf1;
232 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
233 func->function = field & 0x7;
234 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
235 func->physical_function = field & 0xf;
236 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
237 func->rsvd_eqs = field16 & 0xffff;
238 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
239 func->max_eq = field16 & 0xffff;
240 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
241 func->rsvd_uars = field & 0x0f;
243 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
244 func->bus, func->device, func->function, func->physical_function,
245 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
248 mlx4_free_cmd_mailbox(dev, mailbox);
252 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
253 struct mlx4_vhcr *vhcr,
254 struct mlx4_cmd_mailbox *inbox,
255 struct mlx4_cmd_mailbox *outbox,
256 struct mlx4_cmd_info *cmd)
258 struct mlx4_priv *priv = mlx4_priv(dev);
260 u32 size, proxy_qp, qkey;
262 struct mlx4_func func;
264 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
265 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
266 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
267 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
268 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
269 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
270 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
271 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
272 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
273 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
274 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
275 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
276 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
278 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
279 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
280 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
281 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
282 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
283 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
285 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
287 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
288 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
289 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
290 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
291 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
292 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
294 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
295 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
297 /* when opcode modifier = 1 */
298 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
299 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
300 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
301 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
303 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
304 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
305 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
306 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
307 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
309 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
310 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
311 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
312 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
314 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
315 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
316 #define QUERY_FUNC_CAP_PHV_BIT 0x40
318 if (vhcr->op_modifier == 1) {
319 struct mlx4_active_ports actv_ports =
320 mlx4_get_active_ports(dev, slave);
321 int converted_port = mlx4_slave_convert_port(
322 dev, slave, vhcr->in_modifier);
324 if (converted_port < 0)
327 vhcr->in_modifier = converted_port;
328 /* phys-port = logical-port */
329 field = vhcr->in_modifier -
330 find_first_bit(actv_ports.ports, dev->caps.num_ports);
331 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
333 port = vhcr->in_modifier;
334 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
336 /* Set nic_info bit to mark new fields support */
337 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
339 if (mlx4_vf_smi_enabled(dev, slave, port) &&
340 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
341 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
342 MLX4_PUT(outbox->buf, qkey,
343 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
345 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
347 /* size is now the QP number */
348 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
349 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
352 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
354 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
356 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
358 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
359 QUERY_FUNC_CAP_PHYS_PORT_ID);
361 if (dev->caps.phv_bit[port]) {
362 field = QUERY_FUNC_CAP_PHV_BIT;
363 MLX4_PUT(outbox->buf, field,
364 QUERY_FUNC_CAP_FLAGS0_OFFSET);
367 } else if (vhcr->op_modifier == 0) {
368 struct mlx4_active_ports actv_ports =
369 mlx4_get_active_ports(dev, slave);
370 /* enable rdma and ethernet interfaces, new quota locations,
373 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
374 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX |
375 QUERY_FUNC_CAP_FLAG_RESD_LKEY);
376 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
379 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
380 dev->caps.num_ports);
381 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
383 size = dev->caps.function_caps; /* set PF behaviours */
384 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
386 field = 0; /* protected FMR support not available as yet */
387 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
389 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
390 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
391 size = dev->caps.num_qps;
392 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
394 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
395 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
396 size = dev->caps.num_srqs;
397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
399 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
400 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
401 size = dev->caps.num_cqs;
402 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
404 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
405 mlx4_QUERY_FUNC(dev, &func, slave)) {
406 size = vhcr->in_modifier &
407 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
409 rounddown_pow_of_two(dev->caps.num_eqs);
410 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
411 size = dev->caps.reserved_eqs;
412 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
414 size = vhcr->in_modifier &
415 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
417 rounddown_pow_of_two(func.max_eq);
418 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
419 size = func.rsvd_eqs;
420 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
423 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
424 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
425 size = dev->caps.num_mpts;
426 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
428 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
429 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
430 size = dev->caps.num_mtts;
431 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
433 size = dev->caps.num_mgms + dev->caps.num_amgms;
434 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
435 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
437 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
438 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
439 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
441 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00);
442 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
449 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
450 struct mlx4_func_cap *func_cap)
452 struct mlx4_cmd_mailbox *mailbox;
454 u8 field, op_modifier;
456 int err = 0, quotas = 0;
459 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
460 in_modifier = op_modifier ? gen_or_port :
461 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
463 mailbox = mlx4_alloc_cmd_mailbox(dev);
465 return PTR_ERR(mailbox);
467 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
468 MLX4_CMD_QUERY_FUNC_CAP,
469 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
473 outbox = mailbox->buf;
476 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
477 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
478 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
479 err = -EPROTONOSUPPORT;
482 func_cap->flags = field;
483 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
485 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
486 func_cap->num_ports = field;
488 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
489 func_cap->pf_context_behaviour = size;
492 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
493 func_cap->qp_quota = size & 0xFFFFFF;
495 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
496 func_cap->srq_quota = size & 0xFFFFFF;
498 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
499 func_cap->cq_quota = size & 0xFFFFFF;
501 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
502 func_cap->mpt_quota = size & 0xFFFFFF;
504 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
505 func_cap->mtt_quota = size & 0xFFFFFF;
507 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
508 func_cap->mcg_quota = size & 0xFFFFFF;
511 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
512 func_cap->qp_quota = size & 0xFFFFFF;
514 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
515 func_cap->srq_quota = size & 0xFFFFFF;
517 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
518 func_cap->cq_quota = size & 0xFFFFFF;
520 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
521 func_cap->mpt_quota = size & 0xFFFFFF;
523 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
524 func_cap->mtt_quota = size & 0xFFFFFF;
526 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
527 func_cap->mcg_quota = size & 0xFFFFFF;
529 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
530 func_cap->max_eq = size & 0xFFFFFF;
532 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
533 func_cap->reserved_eq = size & 0xFFFFFF;
535 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) {
536 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
537 func_cap->reserved_lkey = size;
539 func_cap->reserved_lkey = 0;
542 func_cap->extra_flags = 0;
544 /* Mailbox data from 0x6c and onward should only be treated if
545 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
547 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
548 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
549 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
550 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
551 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
552 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
558 /* logical port query */
559 if (gen_or_port > dev->caps.num_ports) {
564 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
565 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
566 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
567 mlx4_err(dev, "VLAN is enforced on this port\n");
568 err = -EPROTONOSUPPORT;
572 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
573 mlx4_err(dev, "Force mac is enabled on this port\n");
574 err = -EPROTONOSUPPORT;
577 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
578 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
579 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
580 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
581 err = -EPROTONOSUPPORT;
586 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
587 func_cap->physical_port = field;
588 if (func_cap->physical_port != gen_or_port) {
593 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
594 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
595 func_cap->qp0_qkey = qkey;
597 func_cap->qp0_qkey = 0;
600 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
601 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
603 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
604 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
606 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
607 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
609 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
610 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
612 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
613 MLX4_GET(func_cap->phys_port_id, outbox,
614 QUERY_FUNC_CAP_PHYS_PORT_ID);
616 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
617 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT);
619 /* All other resources are allocated by the master, but we still report
620 * 'num' and 'reserved' capabilities as follows:
621 * - num remains the maximum resource index
622 * - 'num - reserved' is the total available objects of a resource, but
623 * resource indices may be less than 'reserved'
624 * TODO: set per-resource quotas */
627 mlx4_free_cmd_mailbox(dev, mailbox);
632 static void disable_unsupported_roce_caps(void *buf);
634 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
636 struct mlx4_cmd_mailbox *mailbox;
639 u32 field32, flags, ext_flags;
645 #define QUERY_DEV_CAP_OUT_SIZE 0x100
646 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
647 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
648 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
649 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
650 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
651 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
652 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
653 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
654 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
655 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
656 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
657 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
658 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
659 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
660 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
661 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
662 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
663 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
664 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
665 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
666 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
667 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
668 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
669 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
670 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
671 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
672 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34
673 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
674 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
675 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
676 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
677 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
678 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
679 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
680 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
681 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
682 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
683 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
684 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
685 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
686 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
687 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
688 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
689 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
690 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
691 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
692 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
693 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
694 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
695 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
696 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
697 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
698 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
699 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
700 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
701 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
702 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70
703 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
704 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
705 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
706 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
707 #define QUERY_DEV_CAP_SL2VL_EVENT_OFFSET 0x78
708 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
709 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b
710 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
711 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
712 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
713 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
714 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
715 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
716 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
717 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
718 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
719 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
720 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
721 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
722 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96
723 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
724 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
725 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
726 #define QUERY_DEV_CAP_DIAG_RPRT_PER_PORT 0x9c
727 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
728 #define QUERY_DEV_CAP_VXLAN 0x9e
729 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
730 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
731 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
732 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
733 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
734 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
738 mailbox = mlx4_alloc_cmd_mailbox(dev);
740 return PTR_ERR(mailbox);
741 outbox = mailbox->buf;
743 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
744 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
748 if (mlx4_is_mfunc(dev))
749 disable_unsupported_roce_caps(outbox);
750 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
751 dev_cap->reserved_qps = 1 << (field & 0xf);
752 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
753 dev_cap->max_qps = 1 << (field & 0x1f);
754 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
755 dev_cap->reserved_srqs = 1 << (field >> 4);
756 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
757 dev_cap->max_srqs = 1 << (field & 0x1f);
758 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
759 dev_cap->max_cq_sz = 1 << field;
760 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
761 dev_cap->reserved_cqs = 1 << (field & 0xf);
762 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
763 dev_cap->max_cqs = 1 << (field & 0x1f);
764 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
765 dev_cap->max_mpts = 1 << (field & 0x3f);
766 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
767 dev_cap->reserved_eqs = 1 << (field & 0xf);
768 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
769 dev_cap->max_eqs = 1 << (field & 0xf);
770 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
771 dev_cap->reserved_mtts = 1 << (field >> 4);
772 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
773 dev_cap->max_mrw_sz = 1 << field;
774 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
775 dev_cap->reserved_mrws = 1 << (field & 0xf);
776 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
777 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
778 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
779 dev_cap->num_sys_eqs = size & 0xfff;
780 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
781 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
782 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
783 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
784 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
787 dev_cap->max_gso_sz = 0;
789 dev_cap->max_gso_sz = 1 << field;
791 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
793 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
795 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
798 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
799 dev_cap->max_rss_tbl_sz = 1 << field;
801 dev_cap->max_rss_tbl_sz = 0;
802 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
803 dev_cap->max_rdma_global = 1 << (field & 0x3f);
804 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
805 dev_cap->local_ca_ack_delay = field & 0x1f;
806 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
807 dev_cap->num_ports = field & 0xf;
808 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
809 dev_cap->max_msg_sz = 1 << (field & 0x1f);
810 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);
812 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;
813 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
815 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
816 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
818 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;
819 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
821 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;
822 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
824 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
825 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
826 dev_cap->fs_max_num_qp_per_entry = field;
827 MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET);
828 if (field & (1 << 5))
829 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT;
830 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
832 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
833 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
834 dev_cap->stat_rate_support = stat_rate;
835 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
837 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
838 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
839 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
840 dev_cap->flags = flags | (u64)ext_flags << 32;
841 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
842 dev_cap->reserved_uars = field >> 4;
843 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
844 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
845 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
846 dev_cap->min_page_sz = 1 << field;
848 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
850 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
851 dev_cap->bf_reg_size = 1 << (field & 0x1f);
852 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
853 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
855 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
857 dev_cap->bf_reg_size = 0;
860 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
861 dev_cap->max_sq_sg = field;
862 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
863 dev_cap->max_sq_desc_sz = size;
865 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
866 dev_cap->max_qp_per_mcg = 1 << field;
867 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
868 dev_cap->reserved_mgms = field & 0xf;
869 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
870 dev_cap->max_mcgs = 1 << field;
871 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
872 dev_cap->reserved_pds = field >> 4;
873 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
874 dev_cap->max_pds = 1 << (field & 0x3f);
875 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
876 dev_cap->reserved_xrcds = field >> 4;
877 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
878 dev_cap->max_xrcds = 1 << (field & 0x1f);
880 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
881 dev_cap->rdmarc_entry_sz = size;
882 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
883 dev_cap->qpc_entry_sz = size;
884 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
885 dev_cap->aux_entry_sz = size;
886 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
887 dev_cap->altc_entry_sz = size;
888 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
889 dev_cap->eqc_entry_sz = size;
890 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
891 dev_cap->cqc_entry_sz = size;
892 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
893 dev_cap->srq_entry_sz = size;
894 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
895 dev_cap->cmpt_entry_sz = size;
896 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
897 dev_cap->mtt_entry_sz = size;
898 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
899 dev_cap->dmpt_entry_sz = size;
901 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
902 dev_cap->max_srq_sz = 1 << field;
903 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
904 dev_cap->max_qp_sz = 1 << field;
905 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
906 dev_cap->resize_srq = field & 1;
907 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
908 dev_cap->max_rq_sg = field;
909 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
910 dev_cap->max_rq_desc_sz = size;
911 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
912 if (field & (1 << 4))
913 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;
914 if (field & (1 << 5))
915 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
916 if (field & (1 << 6))
917 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
918 if (field & (1 << 7))
919 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
920 MLX4_GET(dev_cap->bmme_flags, outbox,
921 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
922 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)
923 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
924 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
925 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
926 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
928 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
929 if (field & (1 << 2))
930 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
931 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);
933 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;
935 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;
937 MLX4_GET(dev_cap->reserved_lkey, outbox,
938 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
939 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
940 if (field32 & (1 << 0))
941 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
942 if (field32 & (1 << 7))
943 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
944 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT);
945 if (field32 & (1 << 17))
946 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;
947 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
949 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
950 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
952 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
953 if (field & (1 << 5))
954 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
955 MLX4_GET(dev_cap->max_icm_sz, outbox,
956 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
957 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
958 MLX4_GET(dev_cap->max_counters, outbox,
959 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
961 MLX4_GET(field32, outbox,
962 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
963 if (field32 & (1 << 0))
964 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
966 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
967 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET);
968 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
969 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
970 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET);
971 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
973 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
974 dev_cap->rl_caps.num_rates = size;
975 if (dev_cap->rl_caps.num_rates) {
976 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
977 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET);
978 dev_cap->rl_caps.max_val = size & 0xfff;
979 dev_cap->rl_caps.max_unit = size >> 14;
980 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET);
981 dev_cap->rl_caps.min_val = size & 0xfff;
982 dev_cap->rl_caps.min_unit = size >> 14;
985 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
986 if (field32 & (1 << 16))
987 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
988 if (field32 & (1 << 18))
989 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;
990 if (field32 & (1 << 19))
991 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;
992 if (field32 & (1 << 26))
993 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
994 if (field32 & (1 << 20))
995 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
996 if (field32 & (1 << 21))
997 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
999 for (i = 1; i <= dev_cap->num_ports; i++) {
1000 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
1006 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
1007 * we can't use any EQs whose doorbell falls on that page,
1008 * even if the EQ itself isn't reserved.
1010 if (dev_cap->num_sys_eqs == 0)
1011 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
1012 dev_cap->reserved_eqs);
1014 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
1017 mlx4_free_cmd_mailbox(dev, mailbox);
1021 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1023 if (dev_cap->bf_reg_size > 0)
1024 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
1025 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
1027 mlx4_dbg(dev, "BlueFlame not available\n");
1029 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
1030 dev_cap->bmme_flags, dev_cap->reserved_lkey);
1031 mlx4_dbg(dev, "Max ICM size %lld MB\n",
1032 (unsigned long long) dev_cap->max_icm_sz >> 20);
1033 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1034 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
1035 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1036 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
1037 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1038 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
1039 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
1040 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
1041 dev_cap->eqc_entry_sz);
1042 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1043 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
1044 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1045 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
1046 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1047 dev_cap->max_pds, dev_cap->reserved_mgms);
1048 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1049 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
1050 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
1051 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
1052 dev_cap->port_cap[1].max_port_width);
1053 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
1054 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
1055 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
1056 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
1057 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
1058 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
1059 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
1060 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n",
1061 dev_cap->dmfs_high_rate_qpn_base);
1062 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n",
1063 dev_cap->dmfs_high_rate_qpn_range);
1065 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1066 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;
1068 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n",
1069 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val,
1070 rl_caps->min_unit, rl_caps->min_val);
1073 dump_dev_cap_flags(dev, dev_cap->flags);
1074 dump_dev_cap_flags2(dev, dev_cap->flags2);
1077 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
1079 struct mlx4_cmd_mailbox *mailbox;
1085 mailbox = mlx4_alloc_cmd_mailbox(dev);
1086 if (IS_ERR(mailbox))
1087 return PTR_ERR(mailbox);
1088 outbox = mailbox->buf;
1090 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1091 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1092 MLX4_CMD_TIME_CLASS_A,
1098 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1099 port_cap->max_vl = field >> 4;
1100 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1101 port_cap->ib_mtu = field >> 4;
1102 port_cap->max_port_width = field & 0xf;
1103 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1104 port_cap->max_gids = 1 << (field & 0xf);
1105 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1106 port_cap->max_pkeys = 1 << (field & 0xf);
1108 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1109 #define QUERY_PORT_MTU_OFFSET 0x01
1110 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
1111 #define QUERY_PORT_WIDTH_OFFSET 0x06
1112 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1113 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1114 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
1115 #define QUERY_PORT_MAC_OFFSET 0x10
1116 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1117 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1118 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1120 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
1121 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1125 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1126 port_cap->link_state = (field & 0x80) >> 7;
1127 port_cap->supported_port_types = field & 3;
1128 port_cap->suggested_type = (field >> 3) & 1;
1129 port_cap->default_sense = (field >> 4) & 1;
1130 port_cap->dmfs_optimized_state = (field >> 5) & 1;
1131 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1132 port_cap->ib_mtu = field & 0xf;
1133 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1134 port_cap->max_port_width = field & 0xf;
1135 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1136 port_cap->max_gids = 1 << (field >> 4);
1137 port_cap->max_pkeys = 1 << (field & 0xf);
1138 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1139 port_cap->max_vl = field & 0xf;
1140 port_cap->max_tc_eth = field >> 4;
1141 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1142 port_cap->log_max_macs = field & 0xf;
1143 port_cap->log_max_vlans = field >> 4;
1144 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1145 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1146 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1147 port_cap->trans_type = field32 >> 24;
1148 port_cap->vendor_oui = field32 & 0xffffff;
1149 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1150 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1154 mlx4_free_cmd_mailbox(dev, mailbox);
1158 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28)
1159 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1160 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1161 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1163 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1164 struct mlx4_vhcr *vhcr,
1165 struct mlx4_cmd_mailbox *inbox,
1166 struct mlx4_cmd_mailbox *outbox,
1167 struct mlx4_cmd_info *cmd)
1173 u32 bmme_flags, field32;
1177 struct mlx4_active_ports actv_ports;
1179 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1180 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1184 disable_unsupported_roce_caps(outbox->buf);
1185 /* add port mng change event capability and disable mw type 1
1186 * unconditionally to slaves
1188 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1189 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
1190 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
1191 actv_ports = mlx4_get_active_ports(dev, slave);
1192 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1193 for (slave_port = 0, real_port = first_port;
1194 real_port < first_port +
1195 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1196 ++real_port, ++slave_port) {
1197 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1198 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1200 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1202 for (; slave_port < dev->caps.num_ports; ++slave_port)
1203 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1205 /* Not exposing RSS IP fragments to guests */
1206 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG;
1207 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1209 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1211 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1212 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1214 /* For guests, disable timestamp */
1215 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1217 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1219 /* For guests, disable vxlan tunneling and QoS support */
1220 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
1222 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1224 /* For guests, disable port BEACON */
1225 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1227 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1229 /* For guests, report Blueflame disabled */
1230 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1232 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1234 /* For guests, disable mw type 2 and port remap*/
1235 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1236 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1237 bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
1238 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1240 /* turn off device-managed steering capability if not enabled */
1241 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1242 MLX4_GET(field, outbox->buf,
1243 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1245 MLX4_PUT(outbox->buf, field,
1246 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1249 /* turn off ipoib managed steering for guests */
1250 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1252 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1254 /* turn off host side virt features (VST, FSM, etc) for guests */
1255 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1256 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1257 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS);
1258 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1260 /* turn off QCN for guests */
1261 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1263 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1265 /* turn off QP max-rate limiting for guests */
1267 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1269 /* turn off QoS per VF support for guests */
1270 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1272 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1274 /* turn off ignore FCS feature for guests */
1275 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1277 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1282 static void disable_unsupported_roce_caps(void *buf)
1286 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1287 flags &= ~(1UL << 31);
1288 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1289 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1290 flags &= ~(1UL << 24);
1291 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1292 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1293 flags &= ~(MLX4_FLAG_ROCE_V1_V2);
1294 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1297 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1298 struct mlx4_vhcr *vhcr,
1299 struct mlx4_cmd_mailbox *inbox,
1300 struct mlx4_cmd_mailbox *outbox,
1301 struct mlx4_cmd_info *cmd)
1303 struct mlx4_priv *priv = mlx4_priv(dev);
1308 int admin_link_state;
1309 int port = mlx4_slave_convert_port(dev, slave,
1310 vhcr->in_modifier & 0xFF);
1312 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
1313 #define MLX4_PORT_LINK_UP_MASK 0x80
1314 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1315 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
1320 /* Protect against untrusted guests: enforce that this is the
1321 * QUERY_PORT general query.
1323 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1326 vhcr->in_modifier = port;
1328 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1329 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1332 if (!err && dev->caps.function != slave) {
1333 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
1334 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1336 /* get port type - currently only eth is enabled */
1337 MLX4_GET(port_type, outbox->buf,
1338 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1340 /* No link sensing allowed */
1341 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1342 /* set port type to currently operating port type */
1343 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
1345 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1346 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1347 port_type |= MLX4_PORT_LINK_UP_MASK;
1348 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1349 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1350 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) {
1351 int other_port = (port == 1) ? 2 : 1;
1352 struct mlx4_port_cap port_cap;
1354 err = mlx4_QUERY_PORT(dev, other_port, &port_cap);
1357 port_type |= (port_cap.link_state << 7);
1360 MLX4_PUT(outbox->buf, port_type,
1361 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1363 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
1364 short_field = mlx4_get_slave_num_gids(dev, slave, port);
1366 short_field = 1; /* slave max gids */
1367 MLX4_PUT(outbox->buf, short_field,
1368 QUERY_PORT_CUR_MAX_GID_OFFSET);
1370 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1371 MLX4_PUT(outbox->buf, short_field,
1372 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1378 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1379 int *gid_tbl_len, int *pkey_tbl_len)
1381 struct mlx4_cmd_mailbox *mailbox;
1386 mailbox = mlx4_alloc_cmd_mailbox(dev);
1387 if (IS_ERR(mailbox))
1388 return PTR_ERR(mailbox);
1390 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1391 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1396 outbox = mailbox->buf;
1398 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1399 *gid_tbl_len = field;
1401 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1402 *pkey_tbl_len = field;
1405 mlx4_free_cmd_mailbox(dev, mailbox);
1408 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1410 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1412 struct mlx4_cmd_mailbox *mailbox;
1413 struct mlx4_icm_iter iter;
1421 mailbox = mlx4_alloc_cmd_mailbox(dev);
1422 if (IS_ERR(mailbox))
1423 return PTR_ERR(mailbox);
1424 pages = mailbox->buf;
1426 for (mlx4_icm_first(icm, &iter);
1427 !mlx4_icm_last(&iter);
1428 mlx4_icm_next(&iter)) {
1430 * We have to pass pages that are aligned to their
1431 * size, so find the least significant 1 in the
1432 * address or size and use that as our log2 size.
1434 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1435 if (lg < MLX4_ICM_PAGE_SHIFT) {
1436 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1438 (unsigned long long) mlx4_icm_addr(&iter),
1439 mlx4_icm_size(&iter));
1444 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1446 pages[nent * 2] = cpu_to_be64(virt);
1450 pages[nent * 2 + 1] =
1451 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1452 (lg - MLX4_ICM_PAGE_SHIFT));
1453 ts += 1 << (lg - 10);
1456 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1457 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1458 MLX4_CMD_TIME_CLASS_B,
1468 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1469 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1474 case MLX4_CMD_MAP_FA:
1475 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
1477 case MLX4_CMD_MAP_ICM_AUX:
1478 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
1480 case MLX4_CMD_MAP_ICM:
1481 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1482 tc, ts, (unsigned long long) virt - (ts << 10));
1487 mlx4_free_cmd_mailbox(dev, mailbox);
1491 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1493 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1496 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1498 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1499 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1503 int mlx4_RUN_FW(struct mlx4_dev *dev)
1505 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1506 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1509 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1511 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1512 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1513 struct mlx4_cmd_mailbox *mailbox;
1520 #define QUERY_FW_OUT_SIZE 0x100
1521 #define QUERY_FW_VER_OFFSET 0x00
1522 #define QUERY_FW_PPF_ID 0x09
1523 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1524 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1525 #define QUERY_FW_ERR_START_OFFSET 0x30
1526 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1527 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1529 #define QUERY_FW_SIZE_OFFSET 0x00
1530 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1531 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1533 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1534 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1536 #define QUERY_FW_CLOCK_OFFSET 0x50
1537 #define QUERY_FW_CLOCK_BAR 0x58
1539 mailbox = mlx4_alloc_cmd_mailbox(dev);
1540 if (IS_ERR(mailbox))
1541 return PTR_ERR(mailbox);
1542 outbox = mailbox->buf;
1544 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1545 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1549 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1551 * FW subminor version is at more significant bits than minor
1552 * version, so swap here.
1554 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1555 ((fw_ver & 0xffff0000ull) >> 16) |
1556 ((fw_ver & 0x0000ffffull) << 16);
1558 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1559 dev->caps.function = lg;
1561 if (mlx4_is_slave(dev))
1565 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1566 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1567 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1568 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
1570 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1571 (int) (dev->caps.fw_ver >> 32),
1572 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1573 (int) dev->caps.fw_ver & 0xffff);
1574 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
1575 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1580 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1581 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1583 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1584 cmd->max_cmds = 1 << lg;
1586 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1587 (int) (dev->caps.fw_ver >> 32),
1588 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1589 (int) dev->caps.fw_ver & 0xffff,
1590 cmd_if_rev, cmd->max_cmds);
1592 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1593 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1594 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1595 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1597 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1598 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1600 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1601 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1602 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1603 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1605 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1606 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1607 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1608 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1609 fw->comm_bar, fw->comm_base);
1610 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1612 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1613 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1614 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1615 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1616 fw->clock_bar, fw->clock_offset);
1619 * Round up number of system pages needed in case
1620 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1623 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1624 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1626 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1627 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1630 mlx4_free_cmd_mailbox(dev, mailbox);
1634 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1635 struct mlx4_vhcr *vhcr,
1636 struct mlx4_cmd_mailbox *inbox,
1637 struct mlx4_cmd_mailbox *outbox,
1638 struct mlx4_cmd_info *cmd)
1643 outbuf = outbox->buf;
1644 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1645 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1649 /* for slaves, set pci PPF ID to invalid and zero out everything
1650 * else except FW version */
1651 outbuf[0] = outbuf[1] = 0;
1652 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1653 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1658 static void get_board_id(void *vsd, char *board_id)
1662 #define VSD_OFFSET_SIG1 0x00
1663 #define VSD_OFFSET_SIG2 0xde
1664 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1665 #define VSD_OFFSET_TS_BOARD_ID 0x20
1667 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1669 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1671 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1672 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1673 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1676 * The board ID is a string but the firmware byte
1677 * swaps each 4-byte word before passing it back to
1678 * us. Therefore we need to swab it before printing.
1680 u32 *bid_u32 = (u32 *)board_id;
1682 for (i = 0; i < 4; ++i) {
1686 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4);
1687 val = get_unaligned(addr);
1689 put_unaligned(val, &bid_u32[i]);
1694 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1696 struct mlx4_cmd_mailbox *mailbox;
1700 #define QUERY_ADAPTER_OUT_SIZE 0x100
1701 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1702 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1704 mailbox = mlx4_alloc_cmd_mailbox(dev);
1705 if (IS_ERR(mailbox))
1706 return PTR_ERR(mailbox);
1707 outbox = mailbox->buf;
1709 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1710 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1714 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1716 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1720 mlx4_free_cmd_mailbox(dev, mailbox);
1724 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1726 struct mlx4_cmd_mailbox *mailbox;
1729 static const u8 a0_dmfs_hw_steering[] = {
1730 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0,
1731 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1,
1732 [MLX4_STEERING_DMFS_A0_STATIC] = 2,
1733 [MLX4_STEERING_DMFS_A0_DISABLE] = 3
1736 #define INIT_HCA_IN_SIZE 0x200
1737 #define INIT_HCA_VERSION_OFFSET 0x000
1738 #define INIT_HCA_VERSION 2
1739 #define INIT_HCA_VXLAN_OFFSET 0x0c
1740 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1741 #define INIT_HCA_FLAGS_OFFSET 0x014
1742 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
1743 #define INIT_HCA_QPC_OFFSET 0x020
1744 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1745 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1746 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1747 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1748 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1749 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1750 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1751 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
1752 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1753 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1754 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1755 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1756 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
1757 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1758 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1759 #define INIT_HCA_MCAST_OFFSET 0x0c0
1760 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1761 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1762 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1763 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1764 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1765 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1766 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1767 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1768 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1769 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
1770 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1771 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1772 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1773 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1774 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1775 #define INIT_HCA_TPT_OFFSET 0x0f0
1776 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1777 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1778 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1779 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1780 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1781 #define INIT_HCA_UAR_OFFSET 0x120
1782 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1783 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1785 mailbox = mlx4_alloc_cmd_mailbox(dev);
1786 if (IS_ERR(mailbox))
1787 return PTR_ERR(mailbox);
1788 inbox = mailbox->buf;
1790 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1792 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1793 (ilog2(cache_line_size()) - 4) << 5;
1795 #if defined(__LITTLE_ENDIAN)
1796 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1797 #elif defined(__BIG_ENDIAN)
1798 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1800 #error Host endianness not defined
1802 /* Check port for UD address vector: */
1803 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1805 /* Enable IPoIB checksumming if we can: */
1806 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1807 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1809 /* Enable QoS support if module parameter set */
1810 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)
1811 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1813 /* enable counters */
1814 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1815 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1817 /* Enable RSS spread to fragmented IP packets when supported */
1818 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG)
1819 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13);
1821 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1822 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1823 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1824 dev->caps.eqe_size = 64;
1825 dev->caps.eqe_factor = 1;
1827 dev->caps.eqe_size = 32;
1828 dev->caps.eqe_factor = 0;
1831 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1832 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1833 dev->caps.cqe_size = 64;
1834 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1836 dev->caps.cqe_size = 32;
1839 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1840 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1841 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1842 dev->caps.eqe_size = cache_line_size();
1843 dev->caps.cqe_size = cache_line_size();
1844 dev->caps.eqe_factor = 0;
1845 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1846 (ilog2(dev->caps.eqe_size) - 5)),
1847 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1849 /* User still need to know to support CQE > 32B */
1850 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1853 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1854 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1856 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1858 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1859 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1860 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1861 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1862 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1863 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1864 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1865 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1866 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1867 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1868 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
1869 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1870 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1872 /* steering attributes */
1873 if (dev->caps.steering_mode ==
1874 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1875 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1877 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1879 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1880 MLX4_PUT(inbox, param->log_mc_entry_sz,
1881 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1882 MLX4_PUT(inbox, param->log_mc_table_sz,
1883 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1884 /* Enable Ethernet flow steering
1885 * with udp unicast and tcp unicast
1887 if (dev->caps.dmfs_high_steer_mode !=
1888 MLX4_STEERING_DMFS_A0_STATIC)
1890 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1891 INIT_HCA_FS_ETH_BITS_OFFSET);
1892 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1893 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1894 /* Enable IPoIB flow steering
1895 * with udp unicast and tcp unicast
1897 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1898 INIT_HCA_FS_IB_BITS_OFFSET);
1899 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1900 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1902 if (dev->caps.dmfs_high_steer_mode !=
1903 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1905 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode]
1907 INIT_HCA_FS_A0_OFFSET);
1909 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1910 MLX4_PUT(inbox, param->log_mc_entry_sz,
1911 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1912 MLX4_PUT(inbox, param->log_mc_hash_sz,
1913 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1914 MLX4_PUT(inbox, param->log_mc_table_sz,
1915 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1916 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1917 MLX4_PUT(inbox, (u8) (1 << 3),
1918 INIT_HCA_UC_STEERING_OFFSET);
1921 /* TPT attributes */
1923 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1924 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1925 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1926 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1927 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1929 /* UAR attributes */
1931 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1932 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1934 /* set parser VXLAN attributes */
1935 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1936 u8 parser_params = 0;
1937 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1940 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
1941 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1944 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1946 mlx4_free_cmd_mailbox(dev, mailbox);
1950 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1951 struct mlx4_init_hca_param *param)
1953 struct mlx4_cmd_mailbox *mailbox;
1958 static const u8 a0_dmfs_query_hw_steering[] = {
1959 [0] = MLX4_STEERING_DMFS_A0_DEFAULT,
1960 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC,
1961 [2] = MLX4_STEERING_DMFS_A0_STATIC,
1962 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1965 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1966 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1968 mailbox = mlx4_alloc_cmd_mailbox(dev);
1969 if (IS_ERR(mailbox))
1970 return PTR_ERR(mailbox);
1971 outbox = mailbox->buf;
1973 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1975 MLX4_CMD_TIME_CLASS_B,
1976 !mlx4_is_slave(dev));
1980 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1981 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1983 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1985 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1986 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1987 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1988 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1989 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1990 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1991 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1992 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1993 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1994 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1995 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
1996 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1997 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1999 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
2000 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
2001 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2003 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
2004 if (byte_field & 0x8)
2005 param->steering_mode = MLX4_STEERING_MODE_B0;
2007 param->steering_mode = MLX4_STEERING_MODE_A0;
2010 if (dword_field & (1 << 13))
2011 param->rss_ip_frags = 1;
2013 /* steering attributes */
2014 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
2015 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
2016 MLX4_GET(param->log_mc_entry_sz, outbox,
2017 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
2018 MLX4_GET(param->log_mc_table_sz, outbox,
2019 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
2020 MLX4_GET(byte_field, outbox,
2021 INIT_HCA_FS_A0_OFFSET);
2022 param->dmfs_high_steer_mode =
2023 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3];
2025 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
2026 MLX4_GET(param->log_mc_entry_sz, outbox,
2027 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
2028 MLX4_GET(param->log_mc_hash_sz, outbox,
2029 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
2030 MLX4_GET(param->log_mc_table_sz, outbox,
2031 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
2034 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
2035 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
2036 if (byte_field & 0x20) /* 64-bytes eqe enabled */
2037 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
2038 if (byte_field & 0x40) /* 64-bytes cqe enabled */
2039 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
2041 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
2042 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
2044 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
2045 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
2046 param->cqe_size = 1 << ((byte_field &
2047 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
2048 param->eqe_size = 1 << (((byte_field &
2049 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
2052 /* TPT attributes */
2054 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
2055 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
2056 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
2057 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
2058 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
2060 /* UAR attributes */
2062 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2063 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
2065 /* phv_check enable */
2066 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET);
2067 if (byte_field & 0x2)
2068 param->phv_check_en = 1;
2070 mlx4_free_cmd_mailbox(dev, mailbox);
2075 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev)
2077 struct mlx4_cmd_mailbox *mailbox;
2081 mailbox = mlx4_alloc_cmd_mailbox(dev);
2082 if (IS_ERR(mailbox)) {
2083 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n");
2084 return PTR_ERR(mailbox);
2086 outbox = mailbox->buf;
2088 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2090 MLX4_CMD_TIME_CLASS_B,
2091 !mlx4_is_slave(dev));
2093 mlx4_warn(dev, "hca_core_clock update failed\n");
2097 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2100 mlx4_free_cmd_mailbox(dev, mailbox);
2105 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
2106 * and real QP0 are active, so that the paravirtualized QP0 is ready
2108 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
2110 struct mlx4_priv *priv = mlx4_priv(dev);
2111 /* irrelevant if not infiniband */
2112 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
2113 priv->mfunc.master.qp0_state[port].qp0_active)
2118 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
2119 struct mlx4_vhcr *vhcr,
2120 struct mlx4_cmd_mailbox *inbox,
2121 struct mlx4_cmd_mailbox *outbox,
2122 struct mlx4_cmd_info *cmd)
2124 struct mlx4_priv *priv = mlx4_priv(dev);
2125 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
2131 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
2134 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2135 /* Enable port only if it was previously disabled */
2136 if (!priv->mfunc.master.init_port_ref[port]) {
2137 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2138 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2142 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2144 if (slave == mlx4_master_func_num(dev)) {
2145 if (check_qp0_state(dev, slave, port) &&
2146 !priv->mfunc.master.qp0_state[port].port_active) {
2147 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2148 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2151 priv->mfunc.master.qp0_state[port].port_active = 1;
2152 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2155 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2157 ++priv->mfunc.master.init_port_ref[port];
2161 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
2163 struct mlx4_cmd_mailbox *mailbox;
2169 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
2170 #define INIT_PORT_IN_SIZE 256
2171 #define INIT_PORT_FLAGS_OFFSET 0x00
2172 #define INIT_PORT_FLAG_SIG (1 << 18)
2173 #define INIT_PORT_FLAG_NG (1 << 17)
2174 #define INIT_PORT_FLAG_G0 (1 << 16)
2175 #define INIT_PORT_VL_SHIFT 4
2176 #define INIT_PORT_PORT_WIDTH_SHIFT 8
2177 #define INIT_PORT_MTU_OFFSET 0x04
2178 #define INIT_PORT_MAX_GID_OFFSET 0x06
2179 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2180 #define INIT_PORT_GUID0_OFFSET 0x10
2181 #define INIT_PORT_NODE_GUID_OFFSET 0x18
2182 #define INIT_PORT_SI_GUID_OFFSET 0x20
2184 mailbox = mlx4_alloc_cmd_mailbox(dev);
2185 if (IS_ERR(mailbox))
2186 return PTR_ERR(mailbox);
2187 inbox = mailbox->buf;
2190 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
2191 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
2192 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
2194 field = 128 << dev->caps.ib_mtu_cap[port];
2195 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2196 field = dev->caps.gid_table_len[port];
2197 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2198 field = dev->caps.pkey_table_len[port];
2199 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
2201 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
2202 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2204 mlx4_free_cmd_mailbox(dev, mailbox);
2206 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2207 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2210 mlx4_hca_core_clock_update(dev);
2214 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
2216 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
2217 struct mlx4_vhcr *vhcr,
2218 struct mlx4_cmd_mailbox *inbox,
2219 struct mlx4_cmd_mailbox *outbox,
2220 struct mlx4_cmd_info *cmd)
2222 struct mlx4_priv *priv = mlx4_priv(dev);
2223 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
2229 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
2233 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2234 if (priv->mfunc.master.init_port_ref[port] == 1) {
2235 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2236 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2240 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2242 /* infiniband port */
2243 if (slave == mlx4_master_func_num(dev)) {
2244 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
2245 priv->mfunc.master.qp0_state[port].port_active) {
2246 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2247 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2250 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2251 priv->mfunc.master.qp0_state[port].port_active = 0;
2254 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2256 --priv->mfunc.master.init_port_ref[port];
2260 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
2262 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2263 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2265 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
2267 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
2269 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
2270 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
2273 struct mlx4_config_dev {
2274 __be32 update_flags;
2276 __be16 vxlan_udp_dport;
2278 __be16 roce_v2_entropy;
2279 __be16 roce_v2_udp_dport;
2287 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
2288 #define MLX4_ROCE_V2_UDP_DPORT BIT(3)
2289 #define MLX4_DISABLE_RX_PORT BIT(18)
2291 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2294 struct mlx4_cmd_mailbox *mailbox;
2296 mailbox = mlx4_alloc_cmd_mailbox(dev);
2297 if (IS_ERR(mailbox))
2298 return PTR_ERR(mailbox);
2300 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2302 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2303 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2305 mlx4_free_cmd_mailbox(dev, mailbox);
2309 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2312 struct mlx4_cmd_mailbox *mailbox;
2314 mailbox = mlx4_alloc_cmd_mailbox(dev);
2315 if (IS_ERR(mailbox))
2316 return PTR_ERR(mailbox);
2318 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2319 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2322 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2324 mlx4_free_cmd_mailbox(dev, mailbox);
2328 /* Conversion between the HW values and the actual functionality.
2329 * The value represented by the array index,
2330 * and the functionality determined by the flags.
2332 static const u8 config_dev_csum_flags[] = {
2334 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2335 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2336 MLX4_RX_CSUM_MODE_L4,
2337 [3] = MLX4_RX_CSUM_MODE_L4 |
2338 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2339 MLX4_RX_CSUM_MODE_MULTI_VLAN
2342 int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2343 struct mlx4_config_dev_params *params)
2345 struct mlx4_config_dev config_dev = {0};
2349 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2350 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2351 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2353 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2356 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2360 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2361 CONFIG_DEV_RX_CSUM_MODE_MASK;
2363 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2365 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2367 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2368 CONFIG_DEV_RX_CSUM_MODE_MASK;
2370 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2372 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2374 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2378 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2380 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2382 struct mlx4_config_dev config_dev;
2384 memset(&config_dev, 0, sizeof(config_dev));
2385 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2386 config_dev.vxlan_udp_dport = udp_port;
2388 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2390 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2392 #define CONFIG_DISABLE_RX_PORT BIT(15)
2393 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
2395 struct mlx4_config_dev config_dev;
2397 memset(&config_dev, 0, sizeof(config_dev));
2398 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
2400 config_dev.roce_flags =
2401 cpu_to_be32(CONFIG_DISABLE_RX_PORT);
2403 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2406 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port)
2408 struct mlx4_config_dev config_dev;
2410 memset(&config_dev, 0, sizeof(config_dev));
2411 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT);
2412 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port);
2414 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2416 EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port);
2418 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
2420 struct mlx4_cmd_mailbox *mailbox;
2427 mailbox = mlx4_alloc_cmd_mailbox(dev);
2428 if (IS_ERR(mailbox))
2432 v2p->v_port1 = cpu_to_be32(port1);
2433 v2p->v_port2 = cpu_to_be32(port2);
2435 err = mlx4_cmd(dev, mailbox->dma, 0,
2436 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
2437 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2439 mlx4_free_cmd_mailbox(dev, mailbox);
2444 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2446 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2447 MLX4_CMD_SET_ICM_SIZE,
2448 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2453 * Round up number of system pages needed in case
2454 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2456 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2457 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2462 int mlx4_NOP(struct mlx4_dev *dev)
2464 /* Input modifier of 0x1f means "finish as soon as possible." */
2465 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
2469 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
2471 u32 value[], size_t array_len, u8 port)
2473 struct mlx4_cmd_mailbox *mailbox;
2478 mailbox = mlx4_alloc_cmd_mailbox(dev);
2479 if (IS_ERR(mailbox))
2480 return PTR_ERR(mailbox);
2482 outbox = mailbox->buf;
2484 ret = mlx4_cmd_box(dev, 0, mailbox->dma, port, op_modifier,
2485 MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A,
2490 for (i = 0; i < array_len; i++) {
2491 if (offset[i] > MLX4_MAILBOX_SIZE) {
2496 MLX4_GET(value[i], outbox, offset[i]);
2500 mlx4_free_cmd_mailbox(dev, mailbox);
2503 EXPORT_SYMBOL(mlx4_query_diag_counters);
2505 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2509 struct mlx4_cmd_mailbox *mailbox;
2511 u32 guid_hi, guid_lo;
2513 #define MOD_STAT_CFG_PORT_OFFSET 8
2514 #define MOD_STAT_CFG_GUID_H 0X14
2515 #define MOD_STAT_CFG_GUID_L 0X1c
2517 mailbox = mlx4_alloc_cmd_mailbox(dev);
2518 if (IS_ERR(mailbox))
2519 return PTR_ERR(mailbox);
2520 outbox = mailbox->buf;
2522 for (port = 1; port <= dev->caps.num_ports; port++) {
2523 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2524 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2525 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2528 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2532 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2533 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2534 dev->caps.phys_port_id[port] = (u64)guid_lo |
2538 mlx4_free_cmd_mailbox(dev, mailbox);
2542 #define MLX4_WOL_SETUP_MODE (5 << 28)
2543 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2545 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2547 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
2548 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2551 EXPORT_SYMBOL_GPL(mlx4_wol_read);
2553 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2555 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2557 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
2558 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2560 EXPORT_SYMBOL_GPL(mlx4_wol_write);
2567 void mlx4_opreq_action(struct work_struct *work)
2569 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2571 struct mlx4_dev *dev = &priv->dev;
2572 int num_tasks = atomic_read(&priv->opreq_count);
2573 struct mlx4_cmd_mailbox *mailbox;
2574 struct mlx4_mgm *mgm;
2586 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
2587 #define GET_OP_REQ_TOKEN_OFFSET 0x14
2588 #define GET_OP_REQ_TYPE_OFFSET 0x1a
2589 #define GET_OP_REQ_DATA_OFFSET 0x20
2591 mailbox = mlx4_alloc_cmd_mailbox(dev);
2592 if (IS_ERR(mailbox)) {
2593 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2596 outbox = mailbox->buf;
2599 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2600 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2603 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
2607 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2608 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2609 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
2614 if (dev->caps.steering_mode ==
2615 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2616 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2620 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2621 GET_OP_REQ_DATA_OFFSET);
2622 num_qps = be32_to_cpu(mgm->members_count) &
2624 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2625 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2627 for (i = 0; i < num_qps; i++) {
2628 qp.qpn = be32_to_cpu(mgm->qp[i]);
2630 err = mlx4_multicast_detach(dev, &qp,
2634 err = mlx4_multicast_attach(dev, &qp,
2644 mlx4_warn(dev, "Bad type for required operation\n");
2648 err = mlx4_cmd(dev, 0, ((u32) err |
2649 (__force u32)cpu_to_be32(token) << 16),
2650 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2653 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2657 memset(outbox, 0, 0xffc);
2658 num_tasks = atomic_dec_return(&priv->opreq_count);
2662 mlx4_free_cmd_mailbox(dev, mailbox);
2665 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2666 struct mlx4_cmd_mailbox *mailbox)
2668 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2669 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2670 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2671 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2673 u32 set_attr_mask, getresp_attr_mask;
2674 u32 trap_attr_mask, traprepress_attr_mask;
2676 MLX4_GET(set_attr_mask, mailbox->buf,
2677 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2678 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2681 MLX4_GET(getresp_attr_mask, mailbox->buf,
2682 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2683 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2686 MLX4_GET(trap_attr_mask, mailbox->buf,
2687 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2688 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2691 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2692 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2693 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2694 traprepress_attr_mask);
2696 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2697 traprepress_attr_mask)
2703 int mlx4_config_mad_demux(struct mlx4_dev *dev)
2705 struct mlx4_cmd_mailbox *mailbox;
2708 /* Check if mad_demux is supported */
2709 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2712 mailbox = mlx4_alloc_cmd_mailbox(dev);
2713 if (IS_ERR(mailbox)) {
2714 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2718 /* Query mad_demux to find out which MADs are handled by internal sma */
2719 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2720 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2721 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2723 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2728 if (mlx4_check_smp_firewall_active(dev, mailbox))
2729 dev->flags |= MLX4_FLAG_SECURE_HOST;
2731 /* Config mad_demux to handle all MADs returned by the query above */
2732 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2733 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2734 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2736 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2740 if (dev->flags & MLX4_FLAG_SECURE_HOST)
2741 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2743 mlx4_free_cmd_mailbox(dev, mailbox);
2747 /* Access Reg commands */
2748 enum mlx4_access_reg_masks {
2749 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2750 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2751 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2754 struct mlx4_access_reg {
2764 #define MLX4_ACCESS_REG_HEADER_SIZE (20)
2765 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2766 } __attribute__((__packed__));
2769 * mlx4_ACCESS_REG - Generic access reg command.
2771 * @reg_id: register ID to access.
2772 * @method: Access method Read/Write.
2773 * @reg_len: register length to Read/Write in bytes.
2774 * @reg_data: reg_data pointer to Read/Write From/To.
2776 * Access ConnectX registers FW command.
2777 * Returns 0 on success and copies outbox mlx4_access_reg data
2778 * field into reg_data or a negative error code.
2780 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2781 enum mlx4_access_reg_method method,
2782 u16 reg_len, void *reg_data)
2784 struct mlx4_cmd_mailbox *inbox, *outbox;
2785 struct mlx4_access_reg *inbuf, *outbuf;
2788 inbox = mlx4_alloc_cmd_mailbox(dev);
2790 return PTR_ERR(inbox);
2792 outbox = mlx4_alloc_cmd_mailbox(dev);
2793 if (IS_ERR(outbox)) {
2794 mlx4_free_cmd_mailbox(dev, inbox);
2795 return PTR_ERR(outbox);
2799 outbuf = outbox->buf;
2801 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2802 inbuf->constant2 = 0x1;
2803 inbuf->reg_id = cpu_to_be16(reg_id);
2804 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2806 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2808 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2811 memcpy(inbuf->reg_data, reg_data, reg_len);
2812 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2813 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2818 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2819 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2821 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2826 memcpy(reg_data, outbuf->reg_data, reg_len);
2828 mlx4_free_cmd_mailbox(dev, inbox);
2829 mlx4_free_cmd_mailbox(dev, outbox);
2833 /* ConnectX registers IDs */
2835 MLX4_REG_ID_PTYS = 0x5004,
2839 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2842 * @method: Access method Read/Write.
2843 * @ptys_reg: PTYS register data pointer.
2845 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2847 * Returns 0 on success or a negative error code.
2849 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2850 enum mlx4_access_reg_method method,
2851 struct mlx4_ptys_reg *ptys_reg)
2853 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2854 method, sizeof(*ptys_reg), ptys_reg);
2856 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
2858 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2859 struct mlx4_vhcr *vhcr,
2860 struct mlx4_cmd_mailbox *inbox,
2861 struct mlx4_cmd_mailbox *outbox,
2862 struct mlx4_cmd_info *cmd)
2864 struct mlx4_access_reg *inbuf = inbox->buf;
2865 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2866 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2868 if (slave != mlx4_master_func_num(dev) &&
2869 method == MLX4_ACCESS_REG_WRITE)
2872 if (reg_id == MLX4_REG_ID_PTYS) {
2873 struct mlx4_ptys_reg *ptys_reg =
2874 (struct mlx4_ptys_reg *)inbuf->reg_data;
2876 ptys_reg->local_port =
2877 mlx4_slave_convert_port(dev, slave,
2878 ptys_reg->local_port);
2881 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2882 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2886 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit)
2888 #define SET_PORT_GEN_PHV_VALID 0x10
2889 #define SET_PORT_GEN_PHV_EN 0x80
2891 struct mlx4_cmd_mailbox *mailbox;
2892 struct mlx4_set_port_general_context *context;
2896 mailbox = mlx4_alloc_cmd_mailbox(dev);
2897 if (IS_ERR(mailbox))
2898 return PTR_ERR(mailbox);
2899 context = mailbox->buf;
2901 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID;
2903 context->phv_en |= SET_PORT_GEN_PHV_EN;
2905 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
2906 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
2907 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
2910 mlx4_free_cmd_mailbox(dev, mailbox);
2914 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv)
2917 struct mlx4_func_cap func_cap;
2919 memset(&func_cap, 0, sizeof(func_cap));
2920 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap);
2922 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT;
2925 EXPORT_SYMBOL(get_phv_bit);
2927 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val)
2931 if (mlx4_is_slave(dev))
2934 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2935 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2936 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val);
2938 dev->caps.phv_bit[port] = new_val;
2944 EXPORT_SYMBOL(set_phv_bit);
2946 void mlx4_replace_zero_macs(struct mlx4_dev *dev)
2949 u8 mac_addr[ETH_ALEN];
2951 dev->port_random_macs = 0;
2952 for (i = 1; i <= dev->caps.num_ports; ++i)
2953 if (!dev->caps.def_mac[i] &&
2954 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
2955 eth_random_addr(mac_addr);
2956 dev->port_random_macs |= 1 << i;
2957 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr);
2960 EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs);