2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 * Support for Copy Engine hardware, which is mainly used for
25 * communication between Host and Target over a PCIe interconnect.
29 * A single CopyEngine (CE) comprises two "rings":
33 * Each ring consists of a number of descriptors which specify
34 * an address, length, and meta-data.
36 * Typically, one side of the PCIe interconnect (Host or Target)
37 * controls one ring and the other side controls the other ring.
38 * The source side chooses when to initiate a transfer and it
39 * chooses what to send (buffer address, length). The destination
40 * side keeps a supply of "anonymous receive buffers" available and
41 * it handles incoming data as it arrives (when the destination
42 * recieves an interrupt).
44 * The sender may send a simple buffer (address/length) or it may
45 * send a small list of buffers. When a small list is sent, hardware
46 * "gathers" these and they end up in a single destination buffer
47 * with a single interrupt.
49 * There are several "contexts" managed by this layer -- more, it
50 * may seem -- than should be needed. These are provided mainly for
51 * maximum flexibility and especially to facilitate a simpler HIF
52 * implementation. There are per-CopyEngine recv, send, and watermark
53 * contexts. These are supplied by the caller when a recv, send,
54 * or watermark handler is established and they are echoed back to
55 * the caller when the respective callbacks are invoked. There is
56 * also a per-transfer context supplied by the caller when a buffer
57 * (or sendlist) is sent and when a buffer is enqueued for recv.
58 * These per-transfer contexts are echoed back to the caller when
59 * the buffer is sent/received.
62 static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
66 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);
69 static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
72 return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);
75 static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
79 ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);
82 static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
85 return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);
88 static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
91 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);
94 static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
98 ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);
101 static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
105 ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);
108 static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
112 u32 ctrl1_addr = ath10k_pci_read32((ar),
113 (ce_ctrl_addr) + CE_CTRL1_ADDRESS);
115 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
116 (ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) |
117 CE_CTRL1_DMAX_LENGTH_SET(n));
120 static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
124 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
126 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
127 (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
128 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));
131 static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
135 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
137 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
138 (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
139 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));
142 static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
145 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);
148 static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
152 ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);
155 static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
159 ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);
162 static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
166 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
168 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
169 (addr & ~SRC_WATERMARK_HIGH_MASK) |
170 SRC_WATERMARK_HIGH_SET(n));
173 static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
177 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
179 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
180 (addr & ~SRC_WATERMARK_LOW_MASK) |
181 SRC_WATERMARK_LOW_SET(n));
184 static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
188 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
190 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
191 (addr & ~DST_WATERMARK_HIGH_MASK) |
192 DST_WATERMARK_HIGH_SET(n));
195 static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
199 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
201 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
202 (addr & ~DST_WATERMARK_LOW_MASK) |
203 DST_WATERMARK_LOW_SET(n));
206 static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
209 u32 host_ie_addr = ath10k_pci_read32(ar,
210 ce_ctrl_addr + HOST_IE_ADDRESS);
212 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
213 host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
216 static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
219 u32 host_ie_addr = ath10k_pci_read32(ar,
220 ce_ctrl_addr + HOST_IE_ADDRESS);
222 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
223 host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
226 static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
229 u32 host_ie_addr = ath10k_pci_read32(ar,
230 ce_ctrl_addr + HOST_IE_ADDRESS);
232 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
233 host_ie_addr & ~CE_WATERMARK_MASK);
236 static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
239 u32 misc_ie_addr = ath10k_pci_read32(ar,
240 ce_ctrl_addr + MISC_IE_ADDRESS);
242 ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
243 misc_ie_addr | CE_ERROR_MASK);
246 static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
250 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);
255 * Guts of ath10k_ce_send, used by both ath10k_ce_send and
256 * ath10k_ce_sendlist_send.
257 * The caller takes responsibility for any needed locking.
259 static int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
260 void *per_transfer_context,
263 unsigned int transfer_id,
266 struct ath10k *ar = ce_state->ar;
267 struct ath10k_ce_ring *src_ring = ce_state->src_ring;
268 struct ce_desc *desc, *sdesc;
269 unsigned int nentries_mask = src_ring->nentries_mask;
270 unsigned int sw_index = src_ring->sw_index;
271 unsigned int write_index = src_ring->write_index;
272 u32 ctrl_addr = ce_state->ctrl_addr;
276 if (nbytes > ce_state->src_sz_max)
277 ath10k_warn("%s: send more we can (nbytes: %d, max: %d)\n",
278 __func__, nbytes, ce_state->src_sz_max);
282 if (unlikely(CE_RING_DELTA(nentries_mask,
283 write_index, sw_index - 1) <= 0)) {
288 desc = CE_SRC_RING_TO_DESC(src_ring->base_addr_owner_space,
290 sdesc = CE_SRC_RING_TO_DESC(src_ring->shadow_base, write_index);
292 desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA);
294 if (flags & CE_SEND_FLAG_GATHER)
295 desc_flags |= CE_DESC_FLAGS_GATHER;
296 if (flags & CE_SEND_FLAG_BYTE_SWAP)
297 desc_flags |= CE_DESC_FLAGS_BYTE_SWAP;
299 sdesc->addr = __cpu_to_le32(buffer);
300 sdesc->nbytes = __cpu_to_le16(nbytes);
301 sdesc->flags = __cpu_to_le16(desc_flags);
305 src_ring->per_transfer_context[write_index] = per_transfer_context;
307 /* Update Source Ring Write Index */
308 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
311 if (!(flags & CE_SEND_FLAG_GATHER))
312 ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
314 src_ring->write_index = write_index;
316 ath10k_pci_sleep(ar);
320 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
321 void *per_transfer_context,
324 unsigned int transfer_id,
327 struct ath10k *ar = ce_state->ar;
328 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
331 spin_lock_bh(&ar_pci->ce_lock);
332 ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
333 buffer, nbytes, transfer_id, flags);
334 spin_unlock_bh(&ar_pci->ce_lock);
339 void ath10k_ce_sendlist_buf_add(struct ce_sendlist *sendlist, u32 buffer,
340 unsigned int nbytes, u32 flags)
342 unsigned int num_items = sendlist->num_items;
343 struct ce_sendlist_item *item;
345 item = &sendlist->item[num_items];
347 item->u.nbytes = nbytes;
349 sendlist->num_items++;
352 int ath10k_ce_sendlist_send(struct ath10k_ce_pipe *ce_state,
353 void *per_transfer_context,
354 struct ce_sendlist *sendlist,
355 unsigned int transfer_id)
357 struct ath10k_ce_ring *src_ring = ce_state->src_ring;
358 struct ce_sendlist_item *item;
359 struct ath10k *ar = ce_state->ar;
360 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
361 unsigned int nentries_mask = src_ring->nentries_mask;
362 unsigned int num_items = sendlist->num_items;
363 unsigned int sw_index;
364 unsigned int write_index;
365 int i, delta, ret = -ENOMEM;
367 spin_lock_bh(&ar_pci->ce_lock);
369 sw_index = src_ring->sw_index;
370 write_index = src_ring->write_index;
372 delta = CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
374 if (delta >= num_items) {
376 * Handle all but the last item uniformly.
378 for (i = 0; i < num_items - 1; i++) {
379 item = &sendlist->item[i];
380 ret = ath10k_ce_send_nolock(ce_state,
381 CE_SENDLIST_ITEM_CTXT,
383 item->u.nbytes, transfer_id,
385 CE_SEND_FLAG_GATHER);
387 ath10k_warn("CE send failed for item: %d\n", i);
390 * Provide valid context pointer for final item.
392 item = &sendlist->item[i];
393 ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
394 (u32) item->data, item->u.nbytes,
395 transfer_id, item->flags);
397 ath10k_warn("CE send failed for last item: %d\n", i);
400 spin_unlock_bh(&ar_pci->ce_lock);
405 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
406 void *per_recv_context,
409 struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
410 u32 ctrl_addr = ce_state->ctrl_addr;
411 struct ath10k *ar = ce_state->ar;
412 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
413 unsigned int nentries_mask = dest_ring->nentries_mask;
414 unsigned int write_index;
415 unsigned int sw_index;
418 spin_lock_bh(&ar_pci->ce_lock);
419 write_index = dest_ring->write_index;
420 sw_index = dest_ring->sw_index;
424 if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) {
425 struct ce_desc *base = dest_ring->base_addr_owner_space;
426 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);
428 /* Update destination descriptor */
429 desc->addr = __cpu_to_le32(buffer);
432 dest_ring->per_transfer_context[write_index] =
435 /* Update Destination Ring Write Index */
436 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
437 ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
438 dest_ring->write_index = write_index;
443 ath10k_pci_sleep(ar);
444 spin_unlock_bh(&ar_pci->ce_lock);
450 * Guts of ath10k_ce_completed_recv_next.
451 * The caller takes responsibility for any necessary locking.
453 static int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
454 void **per_transfer_contextp,
456 unsigned int *nbytesp,
457 unsigned int *transfer_idp,
458 unsigned int *flagsp)
460 struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
461 unsigned int nentries_mask = dest_ring->nentries_mask;
462 unsigned int sw_index = dest_ring->sw_index;
464 struct ce_desc *base = dest_ring->base_addr_owner_space;
465 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index);
466 struct ce_desc sdesc;
469 /* Copy in one go for performance reasons */
472 nbytes = __le16_to_cpu(sdesc.nbytes);
475 * This closes a relatively unusual race where the Host
476 * sees the updated DRRI before the update to the
477 * corresponding descriptor has completed. We treat this
478 * as a descriptor that is not yet done.
485 /* Return data from completed destination descriptor */
486 *bufferp = __le32_to_cpu(sdesc.addr);
488 *transfer_idp = MS(__le16_to_cpu(sdesc.flags), CE_DESC_FLAGS_META_DATA);
490 if (__le16_to_cpu(sdesc.flags) & CE_DESC_FLAGS_BYTE_SWAP)
491 *flagsp = CE_RECV_FLAG_SWAPPED;
495 if (per_transfer_contextp)
496 *per_transfer_contextp =
497 dest_ring->per_transfer_context[sw_index];
500 dest_ring->per_transfer_context[sw_index] = NULL;
502 /* Update sw_index */
503 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
504 dest_ring->sw_index = sw_index;
509 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
510 void **per_transfer_contextp,
512 unsigned int *nbytesp,
513 unsigned int *transfer_idp,
514 unsigned int *flagsp)
516 struct ath10k *ar = ce_state->ar;
517 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
520 spin_lock_bh(&ar_pci->ce_lock);
521 ret = ath10k_ce_completed_recv_next_nolock(ce_state,
522 per_transfer_contextp,
524 transfer_idp, flagsp);
525 spin_unlock_bh(&ar_pci->ce_lock);
530 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
531 void **per_transfer_contextp,
534 struct ath10k_ce_ring *dest_ring;
535 unsigned int nentries_mask;
536 unsigned int sw_index;
537 unsigned int write_index;
540 struct ath10k_pci *ar_pci;
542 dest_ring = ce_state->dest_ring;
548 ar_pci = ath10k_pci_priv(ar);
550 spin_lock_bh(&ar_pci->ce_lock);
552 nentries_mask = dest_ring->nentries_mask;
553 sw_index = dest_ring->sw_index;
554 write_index = dest_ring->write_index;
555 if (write_index != sw_index) {
556 struct ce_desc *base = dest_ring->base_addr_owner_space;
557 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index);
559 /* Return data from completed destination descriptor */
560 *bufferp = __le32_to_cpu(desc->addr);
562 if (per_transfer_contextp)
563 *per_transfer_contextp =
564 dest_ring->per_transfer_context[sw_index];
567 dest_ring->per_transfer_context[sw_index] = NULL;
569 /* Update sw_index */
570 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
571 dest_ring->sw_index = sw_index;
577 spin_unlock_bh(&ar_pci->ce_lock);
583 * Guts of ath10k_ce_completed_send_next.
584 * The caller takes responsibility for any necessary locking.
586 static int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
587 void **per_transfer_contextp,
589 unsigned int *nbytesp,
590 unsigned int *transfer_idp)
592 struct ath10k_ce_ring *src_ring = ce_state->src_ring;
593 u32 ctrl_addr = ce_state->ctrl_addr;
594 struct ath10k *ar = ce_state->ar;
595 unsigned int nentries_mask = src_ring->nentries_mask;
596 unsigned int sw_index = src_ring->sw_index;
597 unsigned int read_index;
600 if (src_ring->hw_index == sw_index) {
602 * The SW completion index has caught up with the cached
603 * version of the HW completion index.
604 * Update the cached HW completion index to see whether
605 * the SW has really caught up to the HW, or if the cached
606 * value of the HW index has become stale.
610 ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
611 src_ring->hw_index &= nentries_mask;
612 ath10k_pci_sleep(ar);
614 read_index = src_ring->hw_index;
616 if ((read_index != sw_index) && (read_index != 0xffffffff)) {
617 struct ce_desc *sbase = src_ring->shadow_base;
618 struct ce_desc *sdesc = CE_SRC_RING_TO_DESC(sbase, sw_index);
620 /* Return data from completed source descriptor */
621 *bufferp = __le32_to_cpu(sdesc->addr);
622 *nbytesp = __le16_to_cpu(sdesc->nbytes);
623 *transfer_idp = MS(__le16_to_cpu(sdesc->flags),
624 CE_DESC_FLAGS_META_DATA);
626 if (per_transfer_contextp)
627 *per_transfer_contextp =
628 src_ring->per_transfer_context[sw_index];
631 src_ring->per_transfer_context[sw_index] = NULL;
633 /* Update sw_index */
634 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
635 src_ring->sw_index = sw_index;
642 /* NB: Modeled after ath10k_ce_completed_send_next */
643 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
644 void **per_transfer_contextp,
646 unsigned int *nbytesp,
647 unsigned int *transfer_idp)
649 struct ath10k_ce_ring *src_ring;
650 unsigned int nentries_mask;
651 unsigned int sw_index;
652 unsigned int write_index;
655 struct ath10k_pci *ar_pci;
657 src_ring = ce_state->src_ring;
663 ar_pci = ath10k_pci_priv(ar);
665 spin_lock_bh(&ar_pci->ce_lock);
667 nentries_mask = src_ring->nentries_mask;
668 sw_index = src_ring->sw_index;
669 write_index = src_ring->write_index;
671 if (write_index != sw_index) {
672 struct ce_desc *base = src_ring->base_addr_owner_space;
673 struct ce_desc *desc = CE_SRC_RING_TO_DESC(base, sw_index);
675 /* Return data from completed source descriptor */
676 *bufferp = __le32_to_cpu(desc->addr);
677 *nbytesp = __le16_to_cpu(desc->nbytes);
678 *transfer_idp = MS(__le16_to_cpu(desc->flags),
679 CE_DESC_FLAGS_META_DATA);
681 if (per_transfer_contextp)
682 *per_transfer_contextp =
683 src_ring->per_transfer_context[sw_index];
686 src_ring->per_transfer_context[sw_index] = NULL;
688 /* Update sw_index */
689 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
690 src_ring->sw_index = sw_index;
696 spin_unlock_bh(&ar_pci->ce_lock);
701 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
702 void **per_transfer_contextp,
704 unsigned int *nbytesp,
705 unsigned int *transfer_idp)
707 struct ath10k *ar = ce_state->ar;
708 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
711 spin_lock_bh(&ar_pci->ce_lock);
712 ret = ath10k_ce_completed_send_next_nolock(ce_state,
713 per_transfer_contextp,
716 spin_unlock_bh(&ar_pci->ce_lock);
722 * Guts of interrupt handler for per-engine interrupts on a particular CE.
724 * Invokes registered callbacks for recv_complete,
725 * send_complete, and watermarks.
727 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
729 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
730 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
731 u32 ctrl_addr = ce_state->ctrl_addr;
732 void *transfer_context;
739 spin_lock_bh(&ar_pci->ce_lock);
741 /* Clear the copy-complete interrupts that will be handled here. */
742 ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
743 HOST_IS_COPY_COMPLETE_MASK);
745 if (ce_state->recv_cb) {
747 * Pop completed recv buffers and call the registered
748 * recv callback for each
750 while (ath10k_ce_completed_recv_next_nolock(ce_state,
754 spin_unlock_bh(&ar_pci->ce_lock);
755 ce_state->recv_cb(ce_state, transfer_context, buf,
757 spin_lock_bh(&ar_pci->ce_lock);
761 if (ce_state->send_cb) {
763 * Pop completed send buffers and call the registered
764 * send callback for each
766 while (ath10k_ce_completed_send_next_nolock(ce_state,
771 spin_unlock_bh(&ar_pci->ce_lock);
772 ce_state->send_cb(ce_state, transfer_context,
774 spin_lock_bh(&ar_pci->ce_lock);
779 * Misc CE interrupts are not being handled, but still need
782 ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);
784 spin_unlock_bh(&ar_pci->ce_lock);
785 ath10k_pci_sleep(ar);
789 * Handler for per-engine interrupts on ALL active CEs.
790 * This is used in cases where the system is sharing a
791 * single interrput for all CEs
794 void ath10k_ce_per_engine_service_any(struct ath10k *ar)
796 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
801 intr_summary = CE_INTERRUPT_SUMMARY(ar);
803 for (ce_id = 0; intr_summary && (ce_id < ar_pci->ce_count); ce_id++) {
804 if (intr_summary & (1 << ce_id))
805 intr_summary &= ~(1 << ce_id);
807 /* no intr pending on this CE */
810 ath10k_ce_per_engine_service(ar, ce_id);
813 ath10k_pci_sleep(ar);
817 * Adjust interrupts for the copy complete handler.
818 * If it's needed for either send or recv, then unmask
819 * this interrupt; otherwise, mask it.
821 * Called with ce_lock held.
823 static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state,
824 int disable_copy_compl_intr)
826 u32 ctrl_addr = ce_state->ctrl_addr;
827 struct ath10k *ar = ce_state->ar;
831 if ((!disable_copy_compl_intr) &&
832 (ce_state->send_cb || ce_state->recv_cb))
833 ath10k_ce_copy_complete_inter_enable(ar, ctrl_addr);
835 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
837 ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
839 ath10k_pci_sleep(ar);
842 void ath10k_ce_disable_interrupts(struct ath10k *ar)
844 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
848 for (ce_id = 0; ce_id < ar_pci->ce_count; ce_id++) {
849 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
850 u32 ctrl_addr = ce_state->ctrl_addr;
852 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
854 ath10k_pci_sleep(ar);
857 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
858 void (*send_cb)(struct ath10k_ce_pipe *ce_state,
859 void *transfer_context,
862 unsigned int transfer_id),
863 int disable_interrupts)
865 struct ath10k *ar = ce_state->ar;
866 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
868 spin_lock_bh(&ar_pci->ce_lock);
869 ce_state->send_cb = send_cb;
870 ath10k_ce_per_engine_handler_adjust(ce_state, disable_interrupts);
871 spin_unlock_bh(&ar_pci->ce_lock);
874 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
875 void (*recv_cb)(struct ath10k_ce_pipe *ce_state,
876 void *transfer_context,
879 unsigned int transfer_id,
882 struct ath10k *ar = ce_state->ar;
883 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
885 spin_lock_bh(&ar_pci->ce_lock);
886 ce_state->recv_cb = recv_cb;
887 ath10k_ce_per_engine_handler_adjust(ce_state, 0);
888 spin_unlock_bh(&ar_pci->ce_lock);
891 static int ath10k_ce_init_src_ring(struct ath10k *ar,
893 struct ath10k_ce_pipe *ce_state,
894 const struct ce_attr *attr)
896 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
897 struct ath10k_ce_ring *src_ring;
898 unsigned int nentries = attr->src_nentries;
899 unsigned int ce_nbytes;
900 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
901 dma_addr_t base_addr;
904 nentries = roundup_pow_of_two(nentries);
906 if (ce_state->src_ring) {
907 WARN_ON(ce_state->src_ring->nentries != nentries);
911 ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
912 ptr = kzalloc(ce_nbytes, GFP_KERNEL);
916 ce_state->src_ring = (struct ath10k_ce_ring *)ptr;
917 src_ring = ce_state->src_ring;
919 ptr += sizeof(struct ath10k_ce_ring);
920 src_ring->nentries = nentries;
921 src_ring->nentries_mask = nentries - 1;
924 src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
925 src_ring->sw_index &= src_ring->nentries_mask;
926 src_ring->hw_index = src_ring->sw_index;
928 src_ring->write_index =
929 ath10k_ce_src_ring_write_index_get(ar, ctrl_addr);
930 src_ring->write_index &= src_ring->nentries_mask;
931 ath10k_pci_sleep(ar);
933 src_ring->per_transfer_context = (void **)ptr;
936 * Legacy platforms that do not support cache
937 * coherent DMA are unsupported
939 src_ring->base_addr_owner_space_unaligned =
940 pci_alloc_consistent(ar_pci->pdev,
941 (nentries * sizeof(struct ce_desc) +
944 if (!src_ring->base_addr_owner_space_unaligned) {
945 kfree(ce_state->src_ring);
946 ce_state->src_ring = NULL;
950 src_ring->base_addr_ce_space_unaligned = base_addr;
952 src_ring->base_addr_owner_space = PTR_ALIGN(
953 src_ring->base_addr_owner_space_unaligned,
955 src_ring->base_addr_ce_space = ALIGN(
956 src_ring->base_addr_ce_space_unaligned,
960 * Also allocate a shadow src ring in regular
961 * mem to use for faster access.
963 src_ring->shadow_base_unaligned =
964 kmalloc((nentries * sizeof(struct ce_desc) +
965 CE_DESC_RING_ALIGN), GFP_KERNEL);
966 if (!src_ring->shadow_base_unaligned) {
967 pci_free_consistent(ar_pci->pdev,
968 (nentries * sizeof(struct ce_desc) +
970 src_ring->base_addr_owner_space,
971 src_ring->base_addr_ce_space);
972 kfree(ce_state->src_ring);
973 ce_state->src_ring = NULL;
977 src_ring->shadow_base = PTR_ALIGN(
978 src_ring->shadow_base_unaligned,
982 ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr,
983 src_ring->base_addr_ce_space);
984 ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);
985 ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
986 ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0);
987 ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
988 ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
989 ath10k_pci_sleep(ar);
994 static int ath10k_ce_init_dest_ring(struct ath10k *ar,
996 struct ath10k_ce_pipe *ce_state,
997 const struct ce_attr *attr)
999 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1000 struct ath10k_ce_ring *dest_ring;
1001 unsigned int nentries = attr->dest_nentries;
1002 unsigned int ce_nbytes;
1003 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1004 dma_addr_t base_addr;
1007 nentries = roundup_pow_of_two(nentries);
1009 if (ce_state->dest_ring) {
1010 WARN_ON(ce_state->dest_ring->nentries != nentries);
1014 ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
1015 ptr = kzalloc(ce_nbytes, GFP_KERNEL);
1019 ce_state->dest_ring = (struct ath10k_ce_ring *)ptr;
1020 dest_ring = ce_state->dest_ring;
1022 ptr += sizeof(struct ath10k_ce_ring);
1023 dest_ring->nentries = nentries;
1024 dest_ring->nentries_mask = nentries - 1;
1026 ath10k_pci_wake(ar);
1027 dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr);
1028 dest_ring->sw_index &= dest_ring->nentries_mask;
1029 dest_ring->write_index =
1030 ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
1031 dest_ring->write_index &= dest_ring->nentries_mask;
1032 ath10k_pci_sleep(ar);
1034 dest_ring->per_transfer_context = (void **)ptr;
1037 * Legacy platforms that do not support cache
1038 * coherent DMA are unsupported
1040 dest_ring->base_addr_owner_space_unaligned =
1041 pci_alloc_consistent(ar_pci->pdev,
1042 (nentries * sizeof(struct ce_desc) +
1043 CE_DESC_RING_ALIGN),
1045 if (!dest_ring->base_addr_owner_space_unaligned) {
1046 kfree(ce_state->dest_ring);
1047 ce_state->dest_ring = NULL;
1051 dest_ring->base_addr_ce_space_unaligned = base_addr;
1054 * Correctly initialize memory to 0 to prevent garbage
1055 * data crashing system when download firmware
1057 memset(dest_ring->base_addr_owner_space_unaligned, 0,
1058 nentries * sizeof(struct ce_desc) + CE_DESC_RING_ALIGN);
1060 dest_ring->base_addr_owner_space = PTR_ALIGN(
1061 dest_ring->base_addr_owner_space_unaligned,
1062 CE_DESC_RING_ALIGN);
1063 dest_ring->base_addr_ce_space = ALIGN(
1064 dest_ring->base_addr_ce_space_unaligned,
1065 CE_DESC_RING_ALIGN);
1067 ath10k_pci_wake(ar);
1068 ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr,
1069 dest_ring->base_addr_ce_space);
1070 ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);
1071 ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
1072 ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
1073 ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
1074 ath10k_pci_sleep(ar);
1079 static struct ath10k_ce_pipe *ath10k_ce_init_state(struct ath10k *ar,
1081 const struct ce_attr *attr)
1083 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1084 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
1085 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1087 spin_lock_bh(&ar_pci->ce_lock);
1090 ce_state->id = ce_id;
1091 ce_state->ctrl_addr = ctrl_addr;
1092 ce_state->attr_flags = attr->flags;
1093 ce_state->src_sz_max = attr->src_sz_max;
1095 spin_unlock_bh(&ar_pci->ce_lock);
1101 * Initialize a Copy Engine based on caller-supplied attributes.
1102 * This may be called once to initialize both source and destination
1103 * rings or it may be called twice for separate source and destination
1104 * initialization. It may be that only one side or the other is
1105 * initialized by software/firmware.
1107 struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
1109 const struct ce_attr *attr)
1111 struct ath10k_ce_pipe *ce_state;
1112 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1115 ce_state = ath10k_ce_init_state(ar, ce_id, attr);
1117 ath10k_err("Failed to initialize CE state for ID: %d\n", ce_id);
1121 if (attr->src_nentries) {
1122 ret = ath10k_ce_init_src_ring(ar, ce_id, ce_state, attr);
1124 ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n",
1126 ath10k_ce_deinit(ce_state);
1131 if (attr->dest_nentries) {
1132 ret = ath10k_ce_init_dest_ring(ar, ce_id, ce_state, attr);
1134 ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n",
1136 ath10k_ce_deinit(ce_state);
1141 /* Enable CE error interrupts */
1142 ath10k_pci_wake(ar);
1143 ath10k_ce_error_intr_enable(ar, ctrl_addr);
1144 ath10k_pci_sleep(ar);
1149 void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state)
1151 struct ath10k *ar = ce_state->ar;
1152 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1154 if (ce_state->src_ring) {
1155 kfree(ce_state->src_ring->shadow_base_unaligned);
1156 pci_free_consistent(ar_pci->pdev,
1157 (ce_state->src_ring->nentries *
1158 sizeof(struct ce_desc) +
1159 CE_DESC_RING_ALIGN),
1160 ce_state->src_ring->base_addr_owner_space,
1161 ce_state->src_ring->base_addr_ce_space);
1162 kfree(ce_state->src_ring);
1165 if (ce_state->dest_ring) {
1166 pci_free_consistent(ar_pci->pdev,
1167 (ce_state->dest_ring->nentries *
1168 sizeof(struct ce_desc) +
1169 CE_DESC_RING_ALIGN),
1170 ce_state->dest_ring->base_addr_owner_space,
1171 ce_state->dest_ring->base_addr_ce_space);
1172 kfree(ce_state->dest_ring);
1175 ce_state->src_ring = NULL;
1176 ce_state->dest_ring = NULL;