2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 /* QCA988X 1.0 definitions (unsupported) */
24 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
26 /* QCA988X 2.0 definitions */
27 #define QCA988X_HW_2_0_VERSION 0x4100016c
28 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
29 #define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0"
30 #define QCA988X_HW_2_0_FW_FILE "firmware.bin"
31 #define QCA988X_HW_2_0_OTP_FILE "otp.bin"
32 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
33 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
35 #define ATH10K_FW_API2_FILE "firmware-2.bin"
37 /* includes also the null byte */
38 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
46 enum ath10k_fw_ie_type {
47 ATH10K_FW_IE_FW_VERSION = 0,
48 ATH10K_FW_IE_TIMESTAMP = 1,
49 ATH10K_FW_IE_FEATURES = 2,
50 ATH10K_FW_IE_FW_IMAGE = 3,
51 ATH10K_FW_IE_OTP_IMAGE = 4,
54 /* Known pecularities:
55 * - current FW doesn't support raw rx mode (last tested v599)
56 * - current FW dumps upon raw tx mode (last tested v599)
57 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
58 * - raw have FCS, nwifi doesn't
59 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
60 * param, llc/snap) are aligned to 4byte boundaries each */
61 enum ath10k_hw_txrx_mode {
62 ATH10K_HW_TXRX_RAW = 0,
63 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
64 ATH10K_HW_TXRX_ETHERNET = 2,
66 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
67 ATH10K_HW_TXRX_MGMT = 3,
70 enum ath10k_mcast2ucast_mode {
71 ATH10K_MCAST2UCAST_DISABLED = 0,
72 ATH10K_MCAST2UCAST_ENABLED = 1,
75 /* Target specific defines for MAIN firmware */
76 #define TARGET_NUM_VDEVS 8
77 #define TARGET_NUM_PEER_AST 2
78 #define TARGET_NUM_WDS_ENTRIES 32
79 #define TARGET_DMA_BURST_SIZE 0
80 #define TARGET_MAC_AGGR_DELIM 0
81 #define TARGET_AST_SKID_LIMIT 16
82 #define TARGET_NUM_PEERS 16
83 #define TARGET_NUM_OFFLOAD_PEERS 0
84 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
85 #define TARGET_NUM_PEER_KEYS 2
86 #define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS)))
87 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
88 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
89 #define TARGET_RX_TIMEOUT_LO_PRI 100
90 #define TARGET_RX_TIMEOUT_HI_PRI 40
92 /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
93 * avoid a very expensive re-alignment in mac80211. */
94 #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
96 #define TARGET_SCAN_MAX_PENDING_REQS 4
97 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
98 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
99 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
100 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
101 #define TARGET_NUM_MCAST_GROUPS 0
102 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
103 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
104 #define TARGET_TX_DBG_LOG_SIZE 1024
105 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
106 #define TARGET_VOW_CONFIG 0
107 #define TARGET_NUM_MSDU_DESC (1024 + 400)
108 #define TARGET_MAX_FRAG_ENTRIES 0
110 /* Target specific defines for 10.X firmware */
111 #define TARGET_10X_NUM_VDEVS 16
112 #define TARGET_10X_NUM_PEER_AST 2
113 #define TARGET_10X_NUM_WDS_ENTRIES 32
114 #define TARGET_10X_DMA_BURST_SIZE 0
115 #define TARGET_10X_MAC_AGGR_DELIM 0
116 #define TARGET_10X_AST_SKID_LIMIT 16
117 #define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS))
118 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
119 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
120 #define TARGET_10X_NUM_PEER_KEYS 2
121 #define TARGET_10X_NUM_TIDS 256
122 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
123 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
124 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
125 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
126 #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_ETHERNET
127 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
128 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
129 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
130 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
131 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
132 #define TARGET_10X_NUM_MCAST_GROUPS 0
133 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
134 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
135 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
136 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
137 #define TARGET_10X_VOW_CONFIG 0
138 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
139 #define TARGET_10X_MAX_FRAG_ENTRIES 0
141 /* Number of Copy Engines supported */
145 * Total number of PCIe MSI interrupts requested for all interrupt sources.
146 * PCIe standard forces this to be a power of 2.
147 * Some Host OS's limit MSI requests that can be granted to 8
148 * so for now we abide by this limit and avoid requesting more
151 #define MSI_NUM_REQUEST_LOG2 3
152 #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
155 * Granted MSIs are assigned as follows:
156 * Firmware uses the first
157 * Remaining MSIs, if any, are used by Copy Engines
158 * This mapping is known to both Target firmware and Host software.
159 * It may be changed as long as Host and Target are kept in sync.
161 /* MSI for firmware (errors, etc.) */
162 #define MSI_ASSIGN_FW 0
164 /* MSIs for Copy Engines */
165 #define MSI_ASSIGN_CE_INITIAL 1
166 #define MSI_ASSIGN_CE_MAX 7
169 #define RTC_STATE_V_ON 3
171 #define RTC_STATE_COLD_RESET_MASK 0x00000400
172 #define RTC_STATE_V_LSB 0
173 #define RTC_STATE_V_MASK 0x00000007
174 #define RTC_STATE_ADDRESS 0x0000
175 #define PCIE_SOC_WAKE_V_MASK 0x00000001
176 #define PCIE_SOC_WAKE_ADDRESS 0x0004
177 #define PCIE_SOC_WAKE_RESET 0x00000000
178 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
180 #define RTC_SOC_BASE_ADDRESS 0x00004000
181 #define RTC_WMAC_BASE_ADDRESS 0x00005000
182 #define MAC_COEX_BASE_ADDRESS 0x00006000
183 #define BT_COEX_BASE_ADDRESS 0x00007000
184 #define SOC_PCIE_BASE_ADDRESS 0x00008000
185 #define SOC_CORE_BASE_ADDRESS 0x00009000
186 #define WLAN_UART_BASE_ADDRESS 0x0000c000
187 #define WLAN_SI_BASE_ADDRESS 0x00010000
188 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
189 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
190 #define WLAN_MAC_BASE_ADDRESS 0x00020000
191 #define EFUSE_BASE_ADDRESS 0x00030000
192 #define FPGA_REG_BASE_ADDRESS 0x00039000
193 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
194 #define CE_WRAPPER_BASE_ADDRESS 0x00057000
195 #define CE0_BASE_ADDRESS 0x00057400
196 #define CE1_BASE_ADDRESS 0x00057800
197 #define CE2_BASE_ADDRESS 0x00057c00
198 #define CE3_BASE_ADDRESS 0x00058000
199 #define CE4_BASE_ADDRESS 0x00058400
200 #define CE5_BASE_ADDRESS 0x00058800
201 #define CE6_BASE_ADDRESS 0x00058c00
202 #define CE7_BASE_ADDRESS 0x00059000
203 #define DBI_BASE_ADDRESS 0x00060000
204 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
205 #define PCIE_LOCAL_BASE_ADDRESS 0x00080000
207 #define SOC_RESET_CONTROL_OFFSET 0x00000000
208 #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
209 #define SOC_CPU_CLOCK_OFFSET 0x00000020
210 #define SOC_CPU_CLOCK_STANDARD_LSB 0
211 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
212 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
213 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
214 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
215 #define SOC_LPO_CAL_OFFSET 0x000000e0
216 #define SOC_LPO_CAL_ENABLE_LSB 20
217 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
219 #define SOC_CHIP_ID_ADDRESS 0x000000ec
220 #define SOC_CHIP_ID_REV_LSB 8
221 #define SOC_CHIP_ID_REV_MASK 0x00000f00
223 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
224 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
225 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
226 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
228 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
229 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
230 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
231 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
232 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
233 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
234 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
235 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
237 #define CLOCK_GPIO_OFFSET 0xffffffff
238 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
239 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
241 #define SI_CONFIG_OFFSET 0x00000000
242 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
243 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
244 #define SI_CONFIG_I2C_LSB 16
245 #define SI_CONFIG_I2C_MASK 0x00010000
246 #define SI_CONFIG_POS_SAMPLE_LSB 7
247 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
248 #define SI_CONFIG_INACTIVE_DATA_LSB 5
249 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
250 #define SI_CONFIG_INACTIVE_CLK_LSB 4
251 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
252 #define SI_CONFIG_DIVIDER_LSB 0
253 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
254 #define SI_CS_OFFSET 0x00000004
255 #define SI_CS_DONE_ERR_MASK 0x00000400
256 #define SI_CS_DONE_INT_MASK 0x00000200
257 #define SI_CS_START_LSB 8
258 #define SI_CS_START_MASK 0x00000100
259 #define SI_CS_RX_CNT_LSB 4
260 #define SI_CS_RX_CNT_MASK 0x000000f0
261 #define SI_CS_TX_CNT_LSB 0
262 #define SI_CS_TX_CNT_MASK 0x0000000f
264 #define SI_TX_DATA0_OFFSET 0x00000008
265 #define SI_TX_DATA1_OFFSET 0x0000000c
266 #define SI_RX_DATA0_OFFSET 0x00000010
267 #define SI_RX_DATA1_OFFSET 0x00000014
269 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
270 #define CORE_CTRL_ADDRESS 0x0000
271 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
272 #define PCIE_INTR_CLR_ADDRESS 0x0014
273 #define SCRATCH_3_ADDRESS 0x0030
275 /* Firmware indications to the Host via SCRATCH_3 register. */
276 #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
277 #define FW_IND_EVENT_PENDING 1
278 #define FW_IND_INITIALIZED 2
280 /* HOST_REG interrupt from firmware */
281 #define PCIE_INTR_FIRMWARE_MASK 0x00000400
282 #define PCIE_INTR_CE_MASK_ALL 0x0007f800
284 #define DRAM_BASE_ADDRESS 0x00400000
288 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
289 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
290 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
291 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
292 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
293 #define RESET_CONTROL_MBOX_RST_MASK MISSING
294 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
295 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
296 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
297 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
298 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
299 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
300 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
301 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
302 #define LOCAL_SCRATCH_OFFSET 0x18
303 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
304 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
305 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
306 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
307 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
308 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
309 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
310 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
311 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
312 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
313 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
314 #define MBOX_BASE_ADDRESS MISSING
315 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
316 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
317 #define INT_STATUS_ENABLE_CPU_LSB MISSING
318 #define INT_STATUS_ENABLE_CPU_MASK MISSING
319 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
320 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
321 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
322 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
323 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
324 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
325 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
326 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
327 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
328 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
329 #define INT_STATUS_ENABLE_ADDRESS MISSING
330 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
331 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
332 #define HOST_INT_STATUS_ADDRESS MISSING
333 #define CPU_INT_STATUS_ADDRESS MISSING
334 #define ERROR_INT_STATUS_ADDRESS MISSING
335 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
336 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
337 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
338 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
339 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
340 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
341 #define COUNT_DEC_ADDRESS MISSING
342 #define HOST_INT_STATUS_CPU_MASK MISSING
343 #define HOST_INT_STATUS_CPU_LSB MISSING
344 #define HOST_INT_STATUS_ERROR_MASK MISSING
345 #define HOST_INT_STATUS_ERROR_LSB MISSING
346 #define HOST_INT_STATUS_COUNTER_MASK MISSING
347 #define HOST_INT_STATUS_COUNTER_LSB MISSING
348 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
349 #define WINDOW_DATA_ADDRESS MISSING
350 #define WINDOW_READ_ADDR_ADDRESS MISSING
351 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
353 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)