drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  33  *
  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-agn-hw.h"
  79 #include "iwl-fw-error-dump.h"
  80 #include "internal.h"
  81 #include "iwl-fh.h"
  82
  83 /* extended range in FW SRAM */
  84 #define IWL_FW_MEM_EXTENDED_START       0x40000
  85 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  86
  87 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  88 {
  89         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  90
  91         if (!trans_pcie->fw_mon_page)
  92                 return;
  93
  94         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  95                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  96         __free_pages(trans_pcie->fw_mon_page,
  97                      get_order(trans_pcie->fw_mon_size));
  98         trans_pcie->fw_mon_page = NULL;
  99         trans_pcie->fw_mon_phys = 0;
 100         trans_pcie->fw_mon_size = 0;
 101 }
 102
 103 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
 104 {
 105         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 106         struct page *page;
 107         dma_addr_t phys;
 108         u32 size;
 109         u8 power;
 110
 111         if (trans_pcie->fw_mon_page) {
 112                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 113                                            trans_pcie->fw_mon_size,
 114                                            DMA_FROM_DEVICE);
 115                 return;
 116         }
 117
 118         phys = 0;
 119         for (power = 26; power >= 11; power--) {
 120                 int order;
 121
 122                 size = BIT(power);
 123                 order = get_order(size);
 124                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 125                                    order);
 126                 if (!page)
 127                         continue;
 128
 129                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 130                                     DMA_FROM_DEVICE);
 131                 if (dma_mapping_error(trans->dev, phys)) {
 132                         __free_pages(page, order);
 133                         continue;
 134                 }
 135                 IWL_INFO(trans,
 136                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 137                          size, order);
 138                 break;
 139         }
 140
 141         if (WARN_ON_ONCE(!page))
 142                 return;
 143
 144         trans_pcie->fw_mon_page = page;
 145         trans_pcie->fw_mon_phys = phys;
 146         trans_pcie->fw_mon_size = size;
 147 }
 148
 149 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 150 {
 151         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 152                     ((reg & 0x0000ffff) | (2 << 28)));
 153         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 154 }
 155
 156 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 157 {
 158         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 159         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 160                     ((reg & 0x0000ffff) | (3 << 28)));
 161 }
 162
 163 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 164 {
 165         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 166                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 167                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 168                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 169         else
 170                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 171                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 172                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 173 }
 174
 175 /* PCI registers */
 176 #define PCI_CFG_RETRY_TIMEOUT   0x041
 177
 178 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 179 {
 180         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 181         u16 lctl;
 182         u16 cap;
 183
 184         /*
 185          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 186          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 187          * If so (likely), disable L0S, so device moves directly L0->L1;
 188          *    costs negligible amount of power savings.
 189          * If not (unlikely), enable L0S, so there is at least some
 190          *    power savings, even without L1.
 191          */
 192         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 193         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 194                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 195         else
 196                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 197         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 198
 199         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 200         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 201         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 202                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 203                  trans->ltr_enabled ? "En" : "Dis");
 204 }
 205
 206 /*
 207  * Start up NIC's basic functionality after it has been reset
 208  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 209  * NOTE:  This does not load uCode nor start the embedded processor
 210  */
 211 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 212 {
 213         int ret = 0;
 214         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 215
 216         /*
 217          * Use "set_bit" below rather than "write", to preserve any hardware
 218          * bits already set by default after reset.
 219          */
 220
 221         /* Disable L0S exit timer (platform NMI Work/Around) */
 222         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 223                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 224                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 225
 226         /*
 227          * Disable L0s without affecting L1;
 228          *  don't wait for ICH L0s (ICH bug W/A)
 229          */
 230         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 231                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 232
 233         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 234         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 235
 236         /*
 237          * Enable HAP INTA (interrupt from management bus) to
 238          * wake device's PCI Express link L1a -> L0s
 239          */
 240         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 241                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 242
 243         iwl_pcie_apm_config(trans);
 244
 245         /* Configure analog phase-lock-loop before activating to D0A */
 246         if (trans->cfg->base_params->pll_cfg_val)
 247                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 248                             trans->cfg->base_params->pll_cfg_val);
 249
 250         /*
 251          * Set "initialization complete" bit to move adapter from
 252          * D0U* --> D0A* (powered-up active) state.
 253          */
 254         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 255
 256         /*
 257          * Wait for clock stabilization; once stabilized, access to
 258          * device-internal resources is supported, e.g. iwl_write_prph()
 259          * and accesses to uCode SRAM.
 260          */
 261         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 262                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 263                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 264         if (ret < 0) {
 265                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 266                 goto out;
 267         }
 268
 269         if (trans->cfg->host_interrupt_operation_mode) {
 270                 /*
 271                  * This is a bit of an abuse - This is needed for 7260 / 3160
 272                  * only check host_interrupt_operation_mode even if this is
 273                  * not related to host_interrupt_operation_mode.
 274                  *
 275                  * Enable the oscillator to count wake up time for L1 exit. This
 276                  * consumes slightly more power (100uA) - but allows to be sure
 277                  * that we wake up from L1 on time.
 278                  *
 279                  * This looks weird: read twice the same register, discard the
 280                  * value, set a bit, and yet again, read that same register
 281                  * just to discard the value. But that's the way the hardware
 282                  * seems to like it.
 283                  */
 284                 iwl_read_prph(trans, OSC_CLK);
 285                 iwl_read_prph(trans, OSC_CLK);
 286                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 287                 iwl_read_prph(trans, OSC_CLK);
 288                 iwl_read_prph(trans, OSC_CLK);
 289         }
 290
 291         /*
 292          * Enable DMA clock and wait for it to stabilize.
 293          *
 294          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 295          * bits do not disable clocks.  This preserves any hardware
 296          * bits already set by default in "CLK_CTRL_REG" after reset.
 297          */
 298         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 299                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 300                                APMG_CLK_VAL_DMA_CLK_RQT);
 301                 udelay(20);
 302
 303                 /* Disable L1-Active */
 304                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 305                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 306
 307                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 308                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 309                                APMG_RTC_INT_STT_RFKILL);
 310         }
 311
 312         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 313
 314 out:
 315         return ret;
 316 }
 317
 318 /*
 319  * Enable LP XTAL to avoid HW bug where device may consume much power if
 320  * FW is not loaded after device reset. LP XTAL is disabled by default
 321  * after device HW reset. Do it only if XTAL is fed by internal source.
 322  * Configure device's "persistence" mode to avoid resetting XTAL again when
 323  * SHRD_HW_RST occurs in S3.
 324  */
 325 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 326 {
 327         int ret;
 328         u32 apmg_gp1_reg;
 329         u32 apmg_xtal_cfg_reg;
 330         u32 dl_cfg_reg;
 331
 332         /* Force XTAL ON */
 333         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 334                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 335
 336         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 337         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 338
 339         udelay(10);
 340
 341         /*
 342          * Set "initialization complete" bit to move adapter from
 343          * D0U* --> D0A* (powered-up active) state.
 344          */
 345         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 346
 347         /*
 348          * Wait for clock stabilization; once stabilized, access to
 349          * device-internal resources is possible.
 350          */
 351         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 352                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 353                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 354                            25000);
 355         if (WARN_ON(ret < 0)) {
 356                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 357                 /* Release XTAL ON request */
 358                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 359                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360                 return;
 361         }
 362
 363         /*
 364          * Clear "disable persistence" to avoid LP XTAL resetting when
 365          * SHRD_HW_RST is applied in S3.
 366          */
 367         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 368                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 369
 370         /*
 371          * Force APMG XTAL to be active to prevent its disabling by HW
 372          * caused by APMG idle state.
 373          */
 374         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 375                                                     SHR_APMG_XTAL_CFG_REG);
 376         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 377                                  apmg_xtal_cfg_reg |
 378                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 379
 380         /*
 381          * Reset entire device again - do controller reset (results in
 382          * SHRD_HW_RST). Turn MAC off before proceeding.
 383          */
 384         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 385
 386         udelay(10);
 387
 388         /* Enable LP XTAL by indirect access through CSR */
 389         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 390         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 391                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 392                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 393
 394         /* Clear delay line clock power up */
 395         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 396         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 397                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 398
 399         /*
 400          * Enable persistence mode to avoid LP XTAL resetting when
 401          * SHRD_HW_RST is applied in S3.
 402          */
 403         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 404                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 405
 406         /*
 407          * Clear "initialization complete" bit to move adapter from
 408          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 409          */
 410         iwl_clear_bit(trans, CSR_GP_CNTRL,
 411                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 412
 413         /* Activates XTAL resources monitor */
 414         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 415                                  CSR_MONITOR_XTAL_RESOURCES);
 416
 417         /* Release XTAL ON request */
 418         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 419                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 420         udelay(10);
 421
 422         /* Release APMG XTAL */
 423         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 424                                  apmg_xtal_cfg_reg &
 425                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 426 }
 427
 428 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 429 {
 430         int ret = 0;
 431
 432         /* stop device's busmaster DMA activity */
 433         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 434
 435         ret = iwl_poll_bit(trans, CSR_RESET,
 436                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 437                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 438         if (ret < 0)
 439                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 440
 441         IWL_DEBUG_INFO(trans, "stop master\n");
 442
 443         return ret;
 444 }
 445
 446 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 447 {
 448         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 449
 450         if (op_mode_leave) {
 451                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 452                         iwl_pcie_apm_init(trans);
 453
 454                 /* inform ME that we are leaving */
 455                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 456                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 457                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 458                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 459                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 460                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 461                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 462                 mdelay(5);
 463         }
 464
 465         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 466
 467         /* Stop device's DMA activity */
 468         iwl_pcie_apm_stop_master(trans);
 469
 470         if (trans->cfg->lp_xtal_workaround) {
 471                 iwl_pcie_apm_lp_xtal_enable(trans);
 472                 return;
 473         }
 474
 475         /* Reset the entire device */
 476         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 477
 478         udelay(10);
 479
 480         /*
 481          * Clear "initialization complete" bit to move adapter from
 482          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 483          */
 484         iwl_clear_bit(trans, CSR_GP_CNTRL,
 485                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 486 }
 487
 488 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 489 {
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         /* nic_init */
 493         spin_lock(&trans_pcie->irq_lock);
 494         iwl_pcie_apm_init(trans);
 495
 496         spin_unlock(&trans_pcie->irq_lock);
 497
 498         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 499                 iwl_pcie_set_pwr(trans, false);
 500
 501         iwl_op_mode_nic_config(trans->op_mode);
 502
 503         /* Allocate the RX queue, or reset if it is already allocated */
 504         iwl_pcie_rx_init(trans);
 505
 506         /* Allocate or reset and init all Tx and Command queues */
 507         if (iwl_pcie_tx_init(trans))
 508                 return -ENOMEM;
 509
 510         if (trans->cfg->base_params->shadow_reg_enable) {
 511                 /* enable shadow regs in HW */
 512                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 513                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 514         }
 515
 516         return 0;
 517 }
 518
 519 #define HW_READY_TIMEOUT (50)
 520
 521 /* Note: returns poll_bit return value, which is >= 0 if success */
 522 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 523 {
 524         int ret;
 525
 526         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 527                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 528
 529         /* See if we got it */
 530         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 531                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 532                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 533                            HW_READY_TIMEOUT);
 534
 535         if (ret >= 0)
 536                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 537
 538         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 539         return ret;
 540 }
 541
 542 /* Note: returns standard 0/-ERROR code */
 543 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 544 {
 545         int ret;
 546         int t = 0;
 547         int iter;
 548
 549         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 550
 551         ret = iwl_pcie_set_hw_ready(trans);
 552         /* If the card is ready, exit 0 */
 553         if (ret >= 0)
 554                 return 0;
 555
 556         for (iter = 0; iter < 10; iter++) {
 557                 /* If HW is not ready, prepare the conditions to check again */
 558                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 559                             CSR_HW_IF_CONFIG_REG_PREPARE);
 560
 561                 do {
 562                         ret = iwl_pcie_set_hw_ready(trans);
 563                         if (ret >= 0)
 564                                 return 0;
 565
 566                         usleep_range(200, 1000);
 567                         t += 200;
 568                 } while (t < 150000);
 569                 msleep(25);
 570         }
 571
 572         IWL_ERR(trans, "Couldn't prepare the card\n");
 573
 574         return ret;
 575 }
 576
 577 /*
 578  * ucode
 579  */
 580 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 581                                    dma_addr_t phy_addr, u32 byte_cnt)
 582 {
 583         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 584         int ret;
 585
 586         trans_pcie->ucode_write_complete = false;
 587
 588         iwl_write_direct32(trans,
 589                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 590                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 591
 592         iwl_write_direct32(trans,
 593                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 594                            dst_addr);
 595
 596         iwl_write_direct32(trans,
 597                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 598                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 599
 600         iwl_write_direct32(trans,
 601                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 602                            (iwl_get_dma_hi_addr(phy_addr)
 603                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 604
 605         iwl_write_direct32(trans,
 606                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 607                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 608                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 609                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 610
 611         iwl_write_direct32(trans,
 612                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 613                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 614                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 615                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 616
 617         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 618                                  trans_pcie->ucode_write_complete, 5 * HZ);
 619         if (!ret) {
 620                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 621                 return -ETIMEDOUT;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 628                             const struct fw_desc *section)
 629 {
 630         u8 *v_addr;
 631         dma_addr_t p_addr;
 632         u32 offset, chunk_sz = section->len;
 633         int ret = 0;
 634
 635         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 636                      section_num);
 637
 638         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 639                                     GFP_KERNEL | __GFP_NOWARN);
 640         if (!v_addr) {
 641                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 642                 chunk_sz = PAGE_SIZE;
 643                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 644                                             &p_addr, GFP_KERNEL);
 645                 if (!v_addr)
 646                         return -ENOMEM;
 647         }
 648
 649         for (offset = 0; offset < section->len; offset += chunk_sz) {
 650                 u32 copy_size, dst_addr;
 651                 bool extended_addr = false;
 652
 653                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 654                 dst_addr = section->offset + offset;
 655
 656                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 657                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 658                         extended_addr = true;
 659
 660                 if (extended_addr)
 661                         iwl_set_bits_prph(trans, LMPM_CHICK,
 662                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 663
 664                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 665                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 666                                                    copy_size);
 667
 668                 if (extended_addr)
 669                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 670                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 671
 672                 if (ret) {
 673                         IWL_ERR(trans,
 674                                 "Could not load the [%d] uCode section\n",
 675                                 section_num);
 676                         break;
 677                 }
 678         }
 679
 680         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 681         return ret;
 682 }
 683
 684 static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
 685                                             const struct fw_img *image,
 686                                             int cpu,
 687                                             int *first_ucode_section)
 688 {
 689         int shift_param;
 690         int i, ret = 0, sec_num = 0x1;
 691         u32 val, last_read_idx = 0;
 692
 693         if (cpu == 1) {
 694                 shift_param = 0;
 695                 *first_ucode_section = 0;
 696         } else {
 697                 shift_param = 16;
 698                 (*first_ucode_section)++;
 699         }
 700
 701         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 702                 last_read_idx = i;
 703
 704                 if (!image->sec[i].data ||
 705                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 706                         IWL_DEBUG_FW(trans,
 707                                      "Break since Data not valid or Empty section, sec = %d\n",
 708                                      i);
 709                         break;
 710                 }
 711
 712                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 713                 if (ret)
 714                         return ret;
 715
 716                 /* Notify the ucode of the loaded section number and status */
 717                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 718                 val = val | (sec_num << shift_param);
 719                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 720                 sec_num = (sec_num << 1) | 0x1;
 721         }
 722
 723         *first_ucode_section = last_read_idx;
 724
 725         return 0;
 726 }
 727
 728 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 729                                       const struct fw_img *image,
 730                                       int cpu,
 731                                       int *first_ucode_section)
 732 {
 733         int shift_param;
 734         int i, ret = 0;
 735         u32 last_read_idx = 0;
 736
 737         if (cpu == 1) {
 738                 shift_param = 0;
 739                 *first_ucode_section = 0;
 740         } else {
 741                 shift_param = 16;
 742                 (*first_ucode_section)++;
 743         }
 744
 745         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 746                 last_read_idx = i;
 747
 748                 if (!image->sec[i].data ||
 749                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 750                         IWL_DEBUG_FW(trans,
 751                                      "Break since Data not valid or Empty section, sec = %d\n",
 752                                      i);
 753                         break;
 754                 }
 755
 756                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 757                 if (ret)
 758                         return ret;
 759         }
 760
 761         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 762                 iwl_set_bits_prph(trans,
 763                                   CSR_UCODE_LOAD_STATUS_ADDR,
 764                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 765                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 766                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 767                                         shift_param);
 768
 769         *first_ucode_section = last_read_idx;
 770
 771         return 0;
 772 }
 773
 774 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 775 {
 776         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 777         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 778         int i;
 779
 780         if (dest->version)
 781                 IWL_ERR(trans,
 782                         "DBG DEST version is %d - expect issues\n",
 783                         dest->version);
 784
 785         IWL_INFO(trans, "Applying debug destination %s\n",
 786                  get_fw_dbg_mode_string(dest->monitor_mode));
 787
 788         if (dest->monitor_mode == EXTERNAL_MODE)
 789                 iwl_pcie_alloc_fw_monitor(trans);
 790         else
 791                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 792
 793         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 794                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 795                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 796
 797                 switch (dest->reg_ops[i].op) {
 798                 case CSR_ASSIGN:
 799                         iwl_write32(trans, addr, val);
 800                         break;
 801                 case CSR_SETBIT:
 802                         iwl_set_bit(trans, addr, BIT(val));
 803                         break;
 804                 case CSR_CLEARBIT:
 805                         iwl_clear_bit(trans, addr, BIT(val));
 806                         break;
 807                 case PRPH_ASSIGN:
 808                         iwl_write_prph(trans, addr, val);
 809                         break;
 810                 case PRPH_SETBIT:
 811                         iwl_set_bits_prph(trans, addr, BIT(val));
 812                         break;
 813                 case PRPH_CLEARBIT:
 814                         iwl_clear_bits_prph(trans, addr, BIT(val));
 815                         break;
 816                 default:
 817                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 818                                 dest->reg_ops[i].op);
 819                         break;
 820                 }
 821         }
 822
 823         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 824                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 825                                trans_pcie->fw_mon_phys >> dest->base_shift);
 826                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 827                                (trans_pcie->fw_mon_phys +
 828                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 829         }
 830 }
 831
 832 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 833                                 const struct fw_img *image)
 834 {
 835         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 836         int ret = 0;
 837         int first_ucode_section;
 838
 839         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 840                      image->is_dual_cpus ? "Dual" : "Single");
 841
 842         /* load to FW the binary non secured sections of CPU1 */
 843         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 844         if (ret)
 845                 return ret;
 846
 847         if (image->is_dual_cpus) {
 848                 /* set CPU2 header address */
 849                 iwl_write_prph(trans,
 850                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 851                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 852
 853                 /* load to FW the binary sections of CPU2 */
 854                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 855                                                  &first_ucode_section);
 856                 if (ret)
 857                         return ret;
 858         }
 859
 860         /* supported for 7000 only for the moment */
 861         if (iwlwifi_mod_params.fw_monitor &&
 862             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 863                 iwl_pcie_alloc_fw_monitor(trans);
 864
 865                 if (trans_pcie->fw_mon_size) {
 866                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 867                                        trans_pcie->fw_mon_phys >> 4);
 868                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 869                                        (trans_pcie->fw_mon_phys +
 870                                         trans_pcie->fw_mon_size) >> 4);
 871                 }
 872         } else if (trans->dbg_dest_tlv) {
 873                 iwl_pcie_apply_destination(trans);
 874         }
 875
 876         /* release CPU reset */
 877         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 878                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 879         else
 880                 iwl_write32(trans, CSR_RESET, 0);
 881
 882         return 0;
 883 }
 884
 885 static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
 886                                            const struct fw_img *image)
 887 {
 888         int ret = 0;
 889         int first_ucode_section;
 890         u32 reg;
 891
 892         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 893                      image->is_dual_cpus ? "Dual" : "Single");
 894
 895         /* configure the ucode to be ready to get the secured image */
 896         /* release CPU reset */
 897         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 898
 899         /* load to FW the binary Secured sections of CPU1 */
 900         ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
 901                                                &first_ucode_section);
 902         if (ret)
 903                 return ret;
 904
 905         /* load to FW the binary sections of CPU2 */
 906         ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
 907                                                &first_ucode_section);
 908         if (ret)
 909                 return ret;
 910
 911         /* Notify FW loading is done */
 912         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 913
 914         /* wait for image verification to complete  */
 915         ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
 916                                 LMPM_SECURE_BOOT_STATUS_SUCCESS,
 917                                 LMPM_SECURE_BOOT_STATUS_SUCCESS,
 918                                 LMPM_SECURE_TIME_OUT);
 919         if (ret < 0) {
 920                 reg = iwl_read_prph(trans,
 921                                     LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
 922
 923                 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
 924                         reg);
 925                 return ret;
 926         }
 927
 928         return 0;
 929 }
 930
 931 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 932                                    const struct fw_img *fw, bool run_in_rfkill)
 933 {
 934         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 935         int ret;
 936         bool hw_rfkill;
 937
 938         /* This may fail if AMT took ownership of the device */
 939         if (iwl_pcie_prepare_card_hw(trans)) {
 940                 IWL_WARN(trans, "Exit HW not ready\n");
 941                 return -EIO;
 942         }
 943
 944         iwl_enable_rfkill_int(trans);
 945
 946         /* If platform's RF_KILL switch is NOT set to KILL */
 947         hw_rfkill = iwl_is_rfkill_set(trans);
 948         if (hw_rfkill)
 949                 set_bit(STATUS_RFKILL, &trans->status);
 950         else
 951                 clear_bit(STATUS_RFKILL, &trans->status);
 952         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 953         if (hw_rfkill && !run_in_rfkill)
 954                 return -ERFKILL;
 955
 956         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 957
 958         ret = iwl_pcie_nic_init(trans);
 959         if (ret) {
 960                 IWL_ERR(trans, "Unable to init nic\n");
 961                 return ret;
 962         }
 963
 964         /* init ref_count to 1 (should be cleared when ucode is loaded) */
 965         trans_pcie->ref_count = 1;
 966
 967         /* make sure rfkill handshake bits are cleared */
 968         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 969         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 970                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 971
 972         /* clear (again), then enable host interrupts */
 973         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 974         iwl_enable_interrupts(trans);
 975
 976         /* really make sure rfkill handshake bits are cleared */
 977         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 978         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 979
 980         /* Load the given image to the HW */
 981         if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
 982             (CSR_HW_REV_STEP(trans->hw_rev) == SILICON_B_STEP))
 983                 return iwl_pcie_load_given_ucode_8000b(trans, fw);
 984         else
 985                 return iwl_pcie_load_given_ucode(trans, fw);
 986 }
 987
 988 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 989 {
 990         iwl_pcie_reset_ict(trans);
 991         iwl_pcie_tx_start(trans, scd_addr);
 992 }
 993
 994 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 995 {
 996         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 997         bool hw_rfkill, was_hw_rfkill;
 998
 999         was_hw_rfkill = iwl_is_rfkill_set(trans);
1000
1001         /* tell the device to stop sending interrupts */
1002         spin_lock(&trans_pcie->irq_lock);
1003         iwl_disable_interrupts(trans);
1004         spin_unlock(&trans_pcie->irq_lock);
1005
1006         /* device going down, Stop using ICT table */
1007         iwl_pcie_disable_ict(trans);
1008
1009         /*
1010          * If a HW restart happens during firmware loading,
1011          * then the firmware loading might call this function
1012          * and later it might be called again due to the
1013          * restart. So don't process again if the device is
1014          * already dead.
1015          */
1016         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1017                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1018                 iwl_pcie_tx_stop(trans);
1019                 iwl_pcie_rx_stop(trans);
1020
1021                 /* Power-down device's busmaster DMA clocks */
1022                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1023                                APMG_CLK_VAL_DMA_CLK_RQT);
1024                 udelay(5);
1025         }
1026
1027         /* Make sure (redundant) we've released our request to stay awake */
1028         iwl_clear_bit(trans, CSR_GP_CNTRL,
1029                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1030
1031         /* Stop the device, and put it in low power state */
1032         iwl_pcie_apm_stop(trans, false);
1033
1034         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1035          * Clean again the interrupt here
1036          */
1037         spin_lock(&trans_pcie->irq_lock);
1038         iwl_disable_interrupts(trans);
1039         spin_unlock(&trans_pcie->irq_lock);
1040
1041         /* stop and reset the on-board processor */
1042         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1043         udelay(20);
1044
1045         /* clear all status bits */
1046         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1047         clear_bit(STATUS_INT_ENABLED, &trans->status);
1048         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1049         clear_bit(STATUS_RFKILL, &trans->status);
1050
1051         /*
1052          * Even if we stop the HW, we still want the RF kill
1053          * interrupt
1054          */
1055         iwl_enable_rfkill_int(trans);
1056
1057         /*
1058          * Check again since the RF kill state may have changed while
1059          * all the interrupts were disabled, in this case we couldn't
1060          * receive the RF kill interrupt and update the state in the
1061          * op_mode.
1062          * Don't call the op_mode if the rkfill state hasn't changed.
1063          * This allows the op_mode to call stop_device from the rfkill
1064          * notification without endless recursion. Under very rare
1065          * circumstances, we might have a small recursion if the rfkill
1066          * state changed exactly now while we were called from stop_device.
1067          * This is very unlikely but can happen and is supported.
1068          */
1069         hw_rfkill = iwl_is_rfkill_set(trans);
1070         if (hw_rfkill)
1071                 set_bit(STATUS_RFKILL, &trans->status);
1072         else
1073                 clear_bit(STATUS_RFKILL, &trans->status);
1074         if (hw_rfkill != was_hw_rfkill)
1075                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1076
1077         /* re-take ownership to prevent other users from stealing the deivce */
1078         iwl_pcie_prepare_card_hw(trans);
1079 }
1080
1081 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1082 {
1083         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1084                 iwl_trans_pcie_stop_device(trans);
1085 }
1086
1087 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1088 {
1089         iwl_disable_interrupts(trans);
1090
1091         /*
1092          * in testing mode, the host stays awake and the
1093          * hardware won't be reset (not even partially)
1094          */
1095         if (test)
1096                 return;
1097
1098         iwl_pcie_disable_ict(trans);
1099
1100         iwl_clear_bit(trans, CSR_GP_CNTRL,
1101                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1102         iwl_clear_bit(trans, CSR_GP_CNTRL,
1103                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1104
1105         /*
1106          * reset TX queues -- some of their registers reset during S3
1107          * so if we don't reset everything here the D3 image would try
1108          * to execute some invalid memory upon resume
1109          */
1110         iwl_trans_pcie_tx_reset(trans);
1111
1112         iwl_pcie_set_pwr(trans, true);
1113 }
1114
1115 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1116                                     enum iwl_d3_status *status,
1117                                     bool test)
1118 {
1119         u32 val;
1120         int ret;
1121
1122         if (test) {
1123                 iwl_enable_interrupts(trans);
1124                 *status = IWL_D3_STATUS_ALIVE;
1125                 return 0;
1126         }
1127
1128         /*
1129          * Also enables interrupts - none will happen as the device doesn't
1130          * know we're waking it up, only when the opmode actually tells it
1131          * after this call.
1132          */
1133         iwl_pcie_reset_ict(trans);
1134
1135         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1136         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1137
1138         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1139                 udelay(2);
1140
1141         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1142                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1143                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1144                            25000);
1145         if (ret < 0) {
1146                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1147                 return ret;
1148         }
1149
1150         iwl_pcie_set_pwr(trans, false);
1151
1152         iwl_trans_pcie_tx_reset(trans);
1153
1154         ret = iwl_pcie_rx_init(trans);
1155         if (ret) {
1156                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1157                 return ret;
1158         }
1159
1160         val = iwl_read32(trans, CSR_RESET);
1161         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1162                 *status = IWL_D3_STATUS_RESET;
1163         else
1164                 *status = IWL_D3_STATUS_ALIVE;
1165
1166         return 0;
1167 }
1168
1169 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1170 {
1171         bool hw_rfkill;
1172         int err;
1173
1174         err = iwl_pcie_prepare_card_hw(trans);
1175         if (err) {
1176                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1177                 return err;
1178         }
1179
1180         /* Reset the entire device */
1181         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1182
1183         usleep_range(10, 15);
1184
1185         iwl_pcie_apm_init(trans);
1186
1187         /* From now on, the op_mode will be kept updated about RF kill state */
1188         iwl_enable_rfkill_int(trans);
1189
1190         hw_rfkill = iwl_is_rfkill_set(trans);
1191         if (hw_rfkill)
1192                 set_bit(STATUS_RFKILL, &trans->status);
1193         else
1194                 clear_bit(STATUS_RFKILL, &trans->status);
1195         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1196
1197         return 0;
1198 }
1199
1200 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1201 {
1202         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1203
1204         /* disable interrupts - don't enable HW RF kill interrupt */
1205         spin_lock(&trans_pcie->irq_lock);
1206         iwl_disable_interrupts(trans);
1207         spin_unlock(&trans_pcie->irq_lock);
1208
1209         iwl_pcie_apm_stop(trans, true);
1210
1211         spin_lock(&trans_pcie->irq_lock);
1212         iwl_disable_interrupts(trans);
1213         spin_unlock(&trans_pcie->irq_lock);
1214
1215         iwl_pcie_disable_ict(trans);
1216 }
1217
1218 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1219 {
1220         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1221 }
1222
1223 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1224 {
1225         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1226 }
1227
1228 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1229 {
1230         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1231 }
1232
1233 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1234 {
1235         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1236                                ((reg & 0x000FFFFF) | (3 << 24)));
1237         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1238 }
1239
1240 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1241                                       u32 val)
1242 {
1243         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1244                                ((addr & 0x000FFFFF) | (3 << 24)));
1245         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1246 }
1247
1248 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1249 {
1250         WARN_ON(1);
1251         return 0;
1252 }
1253
1254 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1255                                      const struct iwl_trans_config *trans_cfg)
1256 {
1257         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1258
1259         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1260         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1261         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1262                 trans_pcie->n_no_reclaim_cmds = 0;
1263         else
1264                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1265         if (trans_pcie->n_no_reclaim_cmds)
1266                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1267                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1268
1269         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1270         if (trans_pcie->rx_buf_size_8k)
1271                 trans_pcie->rx_page_order = get_order(8 * 1024);
1272         else
1273                 trans_pcie->rx_page_order = get_order(4 * 1024);
1274
1275         trans_pcie->wd_timeout =
1276                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1277
1278         trans_pcie->command_names = trans_cfg->command_names;
1279         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1280         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1281
1282         /* Initialize NAPI here - it should be before registering to mac80211
1283          * in the opmode but after the HW struct is allocated.
1284          * As this function may be called again in some corner cases don't
1285          * do anything if NAPI was already initialized.
1286          */
1287         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1288                 init_dummy_netdev(&trans_pcie->napi_dev);
1289                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1290                                      &trans_pcie->napi_dev,
1291                                      iwl_pcie_dummy_napi_poll, 64);
1292         }
1293 }
1294
1295 void iwl_trans_pcie_free(struct iwl_trans *trans)
1296 {
1297         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1298
1299         synchronize_irq(trans_pcie->pci_dev->irq);
1300
1301         iwl_pcie_tx_free(trans);
1302         iwl_pcie_rx_free(trans);
1303
1304         free_irq(trans_pcie->pci_dev->irq, trans);
1305         iwl_pcie_free_ict(trans);
1306
1307         pci_disable_msi(trans_pcie->pci_dev);
1308         iounmap(trans_pcie->hw_base);
1309         pci_release_regions(trans_pcie->pci_dev);
1310         pci_disable_device(trans_pcie->pci_dev);
1311         kmem_cache_destroy(trans->dev_cmd_pool);
1312
1313         if (trans_pcie->napi.poll)
1314                 netif_napi_del(&trans_pcie->napi);
1315
1316         iwl_pcie_free_fw_monitor(trans);
1317
1318         kfree(trans);
1319 }
1320
1321 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1322 {
1323         if (state)
1324                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1325         else
1326                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1327 }
1328
1329 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1330                                                 unsigned long *flags)
1331 {
1332         int ret;
1333         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1334
1335         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1336
1337         if (trans_pcie->cmd_in_flight)
1338                 goto out;
1339
1340         /* this bit wakes up the NIC */
1341         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1342                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1343         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1344                 udelay(2);
1345
1346         /*
1347          * These bits say the device is running, and should keep running for
1348          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1349          * but they do not indicate that embedded SRAM is restored yet;
1350          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1351          * to/from host DRAM when sleeping/waking for power-saving.
1352          * Each direction takes approximately 1/4 millisecond; with this
1353          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1354          * series of register accesses are expected (e.g. reading Event Log),
1355          * to keep device from sleeping.
1356          *
1357          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1358          * SRAM is okay/restored.  We don't check that here because this call
1359          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1360          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1361          *
1362          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1363          * and do not save/restore SRAM when power cycling.
1364          */
1365         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1366                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1367                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1368                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1369         if (unlikely(ret < 0)) {
1370                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1371                 if (!silent) {
1372                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1373                         WARN_ONCE(1,
1374                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1375                                   val);
1376                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1377                         return false;
1378                 }
1379         }
1380
1381 out:
1382         /*
1383          * Fool sparse by faking we release the lock - sparse will
1384          * track nic_access anyway.
1385          */
1386         __release(&trans_pcie->reg_lock);
1387         return true;
1388 }
1389
1390 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1391                                               unsigned long *flags)
1392 {
1393         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1394
1395         lockdep_assert_held(&trans_pcie->reg_lock);
1396
1397         /*
1398          * Fool sparse by faking we acquiring the lock - sparse will
1399          * track nic_access anyway.
1400          */
1401         __acquire(&trans_pcie->reg_lock);
1402
1403         if (trans_pcie->cmd_in_flight)
1404                 goto out;
1405
1406         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1407                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1408         /*
1409          * Above we read the CSR_GP_CNTRL register, which will flush
1410          * any previous writes, but we need the write that clears the
1411          * MAC_ACCESS_REQ bit to be performed before any other writes
1412          * scheduled on different CPUs (after we drop reg_lock).
1413          */
1414         mmiowb();
1415 out:
1416         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1417 }
1418
1419 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1420                                    void *buf, int dwords)
1421 {
1422         unsigned long flags;
1423         int offs, ret = 0;
1424         u32 *vals = buf;
1425
1426         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1427                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1428                 for (offs = 0; offs < dwords; offs++)
1429                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1430                 iwl_trans_release_nic_access(trans, &flags);
1431         } else {
1432                 ret = -EBUSY;
1433         }
1434         return ret;
1435 }
1436
1437 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1438                                     const void *buf, int dwords)
1439 {
1440         unsigned long flags;
1441         int offs, ret = 0;
1442         const u32 *vals = buf;
1443
1444         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1445                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1446                 for (offs = 0; offs < dwords; offs++)
1447                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1448                                     vals ? vals[offs] : 0);
1449                 iwl_trans_release_nic_access(trans, &flags);
1450         } else {
1451                 ret = -EBUSY;
1452         }
1453         return ret;
1454 }
1455
1456 #define IWL_FLUSH_WAIT_MS       2000
1457
1458 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1459 {
1460         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1461         struct iwl_txq *txq;
1462         struct iwl_queue *q;
1463         int cnt;
1464         unsigned long now = jiffies;
1465         u32 scd_sram_addr;
1466         u8 buf[16];
1467         int ret = 0;
1468
1469         /* waiting for all the tx frames complete might take a while */
1470         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1471                 u8 wr_ptr;
1472
1473                 if (cnt == trans_pcie->cmd_queue)
1474                         continue;
1475                 if (!test_bit(cnt, trans_pcie->queue_used))
1476                         continue;
1477                 if (!(BIT(cnt) & txq_bm))
1478                         continue;
1479
1480                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1481                 txq = &trans_pcie->txq[cnt];
1482                 q = &txq->q;
1483                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1484
1485                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1486                        !time_after(jiffies,
1487                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1488                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1489
1490                         if (WARN_ONCE(wr_ptr != write_ptr,
1491                                       "WR pointer moved while flushing %d -> %d\n",
1492                                       wr_ptr, write_ptr))
1493                                 return -ETIMEDOUT;
1494                         msleep(1);
1495                 }
1496
1497                 if (q->read_ptr != q->write_ptr) {
1498                         IWL_ERR(trans,
1499                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1500                         ret = -ETIMEDOUT;
1501                         break;
1502                 }
1503                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1504         }
1505
1506         if (!ret)
1507                 return 0;
1508
1509         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1510                 txq->q.read_ptr, txq->q.write_ptr);
1511
1512         scd_sram_addr = trans_pcie->scd_base_addr +
1513                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1514         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1515
1516         iwl_print_hex_error(trans, buf, sizeof(buf));
1517
1518         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1519                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1520                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1521
1522         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1523                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1524                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1525                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1526                 u32 tbl_dw =
1527                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1528                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1529
1530                 if (cnt & 0x1)
1531                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1532                 else
1533                         tbl_dw = tbl_dw & 0x0000FFFF;
1534
1535                 IWL_ERR(trans,
1536                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1537                         cnt, active ? "" : "in", fifo, tbl_dw,
1538                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1539                                 (TFD_QUEUE_SIZE_MAX - 1),
1540                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1541         }
1542
1543         return ret;
1544 }
1545
1546 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1547                                          u32 mask, u32 value)
1548 {
1549         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1550         unsigned long flags;
1551
1552         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1553         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1554         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1555 }
1556
1557 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1558 {
1559         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1560         unsigned long flags;
1561
1562         if (iwlwifi_mod_params.d0i3_disable)
1563                 return;
1564
1565         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1566         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1567         trans_pcie->ref_count++;
1568         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1569 }
1570
1571 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1572 {
1573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1574         unsigned long flags;
1575
1576         if (iwlwifi_mod_params.d0i3_disable)
1577                 return;
1578
1579         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1580         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1581         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1582                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1583                 return;
1584         }
1585         trans_pcie->ref_count--;
1586         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1587 }
1588
1589 static const char *get_csr_string(int cmd)
1590 {
1591 #define IWL_CMD(x) case x: return #x
1592         switch (cmd) {
1593         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1594         IWL_CMD(CSR_INT_COALESCING);
1595         IWL_CMD(CSR_INT);
1596         IWL_CMD(CSR_INT_MASK);
1597         IWL_CMD(CSR_FH_INT_STATUS);
1598         IWL_CMD(CSR_GPIO_IN);
1599         IWL_CMD(CSR_RESET);
1600         IWL_CMD(CSR_GP_CNTRL);
1601         IWL_CMD(CSR_HW_REV);
1602         IWL_CMD(CSR_EEPROM_REG);
1603         IWL_CMD(CSR_EEPROM_GP);
1604         IWL_CMD(CSR_OTP_GP_REG);
1605         IWL_CMD(CSR_GIO_REG);
1606         IWL_CMD(CSR_GP_UCODE_REG);
1607         IWL_CMD(CSR_GP_DRIVER_REG);
1608         IWL_CMD(CSR_UCODE_DRV_GP1);
1609         IWL_CMD(CSR_UCODE_DRV_GP2);
1610         IWL_CMD(CSR_LED_REG);
1611         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1612         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1613         IWL_CMD(CSR_ANA_PLL_CFG);
1614         IWL_CMD(CSR_HW_REV_WA_REG);
1615         IWL_CMD(CSR_MONITOR_STATUS_REG);
1616         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1617         default:
1618                 return "UNKNOWN";
1619         }
1620 #undef IWL_CMD
1621 }
1622
1623 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1624 {
1625         int i;
1626         static const u32 csr_tbl[] = {
1627                 CSR_HW_IF_CONFIG_REG,
1628                 CSR_INT_COALESCING,
1629                 CSR_INT,
1630                 CSR_INT_MASK,
1631                 CSR_FH_INT_STATUS,
1632                 CSR_GPIO_IN,
1633                 CSR_RESET,
1634                 CSR_GP_CNTRL,
1635                 CSR_HW_REV,
1636                 CSR_EEPROM_REG,
1637                 CSR_EEPROM_GP,
1638                 CSR_OTP_GP_REG,
1639                 CSR_GIO_REG,
1640                 CSR_GP_UCODE_REG,
1641                 CSR_GP_DRIVER_REG,
1642                 CSR_UCODE_DRV_GP1,
1643                 CSR_UCODE_DRV_GP2,
1644                 CSR_LED_REG,
1645                 CSR_DRAM_INT_TBL_REG,
1646                 CSR_GIO_CHICKEN_BITS,
1647                 CSR_ANA_PLL_CFG,
1648                 CSR_MONITOR_STATUS_REG,
1649                 CSR_HW_REV_WA_REG,
1650                 CSR_DBG_HPET_MEM_REG
1651         };
1652         IWL_ERR(trans, "CSR values:\n");
1653         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1654                 "CSR_INT_PERIODIC_REG)\n");
1655         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1656                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1657                         get_csr_string(csr_tbl[i]),
1658                         iwl_read32(trans, csr_tbl[i]));
1659         }
1660 }
1661
1662 #ifdef CONFIG_IWLWIFI_DEBUGFS
1663 /* create and remove of files */
1664 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1665         if (!debugfs_create_file(#name, mode, parent, trans,            \
1666                                  &iwl_dbgfs_##name##_ops))              \
1667                 goto err;                                               \
1668 } while (0)
1669
1670 /* file operation */
1671 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1672 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1673         .read = iwl_dbgfs_##name##_read,                                \
1674         .open = simple_open,                                            \
1675         .llseek = generic_file_llseek,                                  \
1676 };
1677
1678 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1679 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1680         .write = iwl_dbgfs_##name##_write,                              \
1681         .open = simple_open,                                            \
1682         .llseek = generic_file_llseek,                                  \
1683 };
1684
1685 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1686 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1687         .write = iwl_dbgfs_##name##_write,                              \
1688         .read = iwl_dbgfs_##name##_read,                                \
1689         .open = simple_open,                                            \
1690         .llseek = generic_file_llseek,                                  \
1691 };
1692
1693 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1694                                        char __user *user_buf,
1695                                        size_t count, loff_t *ppos)
1696 {
1697         struct iwl_trans *trans = file->private_data;
1698         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1699         struct iwl_txq *txq;
1700         struct iwl_queue *q;
1701         char *buf;
1702         int pos = 0;
1703         int cnt;
1704         int ret;
1705         size_t bufsz;
1706
1707         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1708
1709         if (!trans_pcie->txq)
1710                 return -EAGAIN;
1711
1712         buf = kzalloc(bufsz, GFP_KERNEL);
1713         if (!buf)
1714                 return -ENOMEM;
1715
1716         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1717                 txq = &trans_pcie->txq[cnt];
1718                 q = &txq->q;
1719                 pos += scnprintf(buf + pos, bufsz - pos,
1720                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1721                                 cnt, q->read_ptr, q->write_ptr,
1722                                 !!test_bit(cnt, trans_pcie->queue_used),
1723                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1724                                  txq->need_update,
1725                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1726         }
1727         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1728         kfree(buf);
1729         return ret;
1730 }
1731
1732 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1733                                        char __user *user_buf,
1734                                        size_t count, loff_t *ppos)
1735 {
1736         struct iwl_trans *trans = file->private_data;
1737         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1738         struct iwl_rxq *rxq = &trans_pcie->rxq;
1739         char buf[256];
1740         int pos = 0;
1741         const size_t bufsz = sizeof(buf);
1742
1743         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1744                                                 rxq->read);
1745         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1746                                                 rxq->write);
1747         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1748                                                 rxq->write_actual);
1749         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1750                                                 rxq->need_update);
1751         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1752                                                 rxq->free_count);
1753         if (rxq->rb_stts) {
1754                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1755                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1756         } else {
1757                 pos += scnprintf(buf + pos, bufsz - pos,
1758                                         "closed_rb_num: Not Allocated\n");
1759         }
1760         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1761 }
1762
1763 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1764                                         char __user *user_buf,
1765                                         size_t count, loff_t *ppos)
1766 {
1767         struct iwl_trans *trans = file->private_data;
1768         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1769         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1770
1771         int pos = 0;
1772         char *buf;
1773         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1774         ssize_t ret;
1775
1776         buf = kzalloc(bufsz, GFP_KERNEL);
1777         if (!buf)
1778                 return -ENOMEM;
1779
1780         pos += scnprintf(buf + pos, bufsz - pos,
1781                         "Interrupt Statistics Report:\n");
1782
1783         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1784                 isr_stats->hw);
1785         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1786                 isr_stats->sw);
1787         if (isr_stats->sw || isr_stats->hw) {
1788                 pos += scnprintf(buf + pos, bufsz - pos,
1789                         "\tLast Restarting Code:  0x%X\n",
1790                         isr_stats->err_code);
1791         }
1792 #ifdef CONFIG_IWLWIFI_DEBUG
1793         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1794                 isr_stats->sch);
1795         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1796                 isr_stats->alive);
1797 #endif
1798         pos += scnprintf(buf + pos, bufsz - pos,
1799                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1800
1801         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1802                 isr_stats->ctkill);
1803
1804         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1805                 isr_stats->wakeup);
1806
1807         pos += scnprintf(buf + pos, bufsz - pos,
1808                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1809
1810         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1811                 isr_stats->tx);
1812
1813         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1814                 isr_stats->unhandled);
1815
1816         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1817         kfree(buf);
1818         return ret;
1819 }
1820
1821 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1822                                          const char __user *user_buf,
1823                                          size_t count, loff_t *ppos)
1824 {
1825         struct iwl_trans *trans = file->private_data;
1826         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1827         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1828
1829         char buf[8];
1830         int buf_size;
1831         u32 reset_flag;
1832
1833         memset(buf, 0, sizeof(buf));
1834         buf_size = min(count, sizeof(buf) -  1);
1835         if (copy_from_user(buf, user_buf, buf_size))
1836                 return -EFAULT;
1837         if (sscanf(buf, "%x", &reset_flag) != 1)
1838                 return -EFAULT;
1839         if (reset_flag == 0)
1840                 memset(isr_stats, 0, sizeof(*isr_stats));
1841
1842         return count;
1843 }
1844
1845 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1846                                    const char __user *user_buf,
1847                                    size_t count, loff_t *ppos)
1848 {
1849         struct iwl_trans *trans = file->private_data;
1850         char buf[8];
1851         int buf_size;
1852         int csr;
1853
1854         memset(buf, 0, sizeof(buf));
1855         buf_size = min(count, sizeof(buf) -  1);
1856         if (copy_from_user(buf, user_buf, buf_size))
1857                 return -EFAULT;
1858         if (sscanf(buf, "%d", &csr) != 1)
1859                 return -EFAULT;
1860
1861         iwl_pcie_dump_csr(trans);
1862
1863         return count;
1864 }
1865
1866 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1867                                      char __user *user_buf,
1868                                      size_t count, loff_t *ppos)
1869 {
1870         struct iwl_trans *trans = file->private_data;
1871         char *buf = NULL;
1872         ssize_t ret;
1873
1874         ret = iwl_dump_fh(trans, &buf);
1875         if (ret < 0)
1876                 return ret;
1877         if (!buf)
1878                 return -EINVAL;
1879         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1880         kfree(buf);
1881         return ret;
1882 }
1883
1884 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1885 DEBUGFS_READ_FILE_OPS(fh_reg);
1886 DEBUGFS_READ_FILE_OPS(rx_queue);
1887 DEBUGFS_READ_FILE_OPS(tx_queue);
1888 DEBUGFS_WRITE_FILE_OPS(csr);
1889
1890 /*
1891  * Create the debugfs files and directories
1892  *
1893  */
1894 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1895                                          struct dentry *dir)
1896 {
1897         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1898         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1899         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1900         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1901         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1902         return 0;
1903
1904 err:
1905         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1906         return -ENOMEM;
1907 }
1908 #else
1909 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1910                                          struct dentry *dir)
1911 {
1912         return 0;
1913 }
1914 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1915
1916 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1917 {
1918         u32 cmdlen = 0;
1919         int i;
1920
1921         for (i = 0; i < IWL_NUM_OF_TBS; i++)
1922                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1923
1924         return cmdlen;
1925 }
1926
1927 static const struct {
1928         u32 start, end;
1929 } iwl_prph_dump_addr[] = {
1930         { .start = 0x00a00000, .end = 0x00a00000 },
1931         { .start = 0x00a0000c, .end = 0x00a00024 },
1932         { .start = 0x00a0002c, .end = 0x00a0003c },
1933         { .start = 0x00a00410, .end = 0x00a00418 },
1934         { .start = 0x00a00420, .end = 0x00a00420 },
1935         { .start = 0x00a00428, .end = 0x00a00428 },
1936         { .start = 0x00a00430, .end = 0x00a0043c },
1937         { .start = 0x00a00444, .end = 0x00a00444 },
1938         { .start = 0x00a004c0, .end = 0x00a004cc },
1939         { .start = 0x00a004d8, .end = 0x00a004d8 },
1940         { .start = 0x00a004e0, .end = 0x00a004f0 },
1941         { .start = 0x00a00840, .end = 0x00a00840 },
1942         { .start = 0x00a00850, .end = 0x00a00858 },
1943         { .start = 0x00a01004, .end = 0x00a01008 },
1944         { .start = 0x00a01010, .end = 0x00a01010 },
1945         { .start = 0x00a01018, .end = 0x00a01018 },
1946         { .start = 0x00a01024, .end = 0x00a01024 },
1947         { .start = 0x00a0102c, .end = 0x00a01034 },
1948         { .start = 0x00a0103c, .end = 0x00a01040 },
1949         { .start = 0x00a01048, .end = 0x00a01094 },
1950         { .start = 0x00a01c00, .end = 0x00a01c20 },
1951         { .start = 0x00a01c58, .end = 0x00a01c58 },
1952         { .start = 0x00a01c7c, .end = 0x00a01c7c },
1953         { .start = 0x00a01c28, .end = 0x00a01c54 },
1954         { .start = 0x00a01c5c, .end = 0x00a01c5c },
1955         { .start = 0x00a01c84, .end = 0x00a01c84 },
1956         { .start = 0x00a01ce0, .end = 0x00a01d0c },
1957         { .start = 0x00a01d18, .end = 0x00a01d20 },
1958         { .start = 0x00a01d2c, .end = 0x00a01d30 },
1959         { .start = 0x00a01d40, .end = 0x00a01d5c },
1960         { .start = 0x00a01d80, .end = 0x00a01d80 },
1961         { .start = 0x00a01d98, .end = 0x00a01d98 },
1962         { .start = 0x00a01dc0, .end = 0x00a01dfc },
1963         { .start = 0x00a01e00, .end = 0x00a01e2c },
1964         { .start = 0x00a01e40, .end = 0x00a01e60 },
1965         { .start = 0x00a01e84, .end = 0x00a01e90 },
1966         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1967         { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1968         { .start = 0x00a01f00, .end = 0x00a01f14 },
1969         { .start = 0x00a01f44, .end = 0x00a01f58 },
1970         { .start = 0x00a01f80, .end = 0x00a01fa8 },
1971         { .start = 0x00a01fb0, .end = 0x00a01fbc },
1972         { .start = 0x00a01ff8, .end = 0x00a01ffc },
1973         { .start = 0x00a02000, .end = 0x00a02048 },
1974         { .start = 0x00a02068, .end = 0x00a020f0 },
1975         { .start = 0x00a02100, .end = 0x00a02118 },
1976         { .start = 0x00a02140, .end = 0x00a0214c },
1977         { .start = 0x00a02168, .end = 0x00a0218c },
1978         { .start = 0x00a021c0, .end = 0x00a021c0 },
1979         { .start = 0x00a02400, .end = 0x00a02410 },
1980         { .start = 0x00a02418, .end = 0x00a02420 },
1981         { .start = 0x00a02428, .end = 0x00a0242c },
1982         { .start = 0x00a02434, .end = 0x00a02434 },
1983         { .start = 0x00a02440, .end = 0x00a02460 },
1984         { .start = 0x00a02468, .end = 0x00a024b0 },
1985         { .start = 0x00a024c8, .end = 0x00a024cc },
1986         { .start = 0x00a02500, .end = 0x00a02504 },
1987         { .start = 0x00a0250c, .end = 0x00a02510 },
1988         { .start = 0x00a02540, .end = 0x00a02554 },
1989         { .start = 0x00a02580, .end = 0x00a025f4 },
1990         { .start = 0x00a02600, .end = 0x00a0260c },
1991         { .start = 0x00a02648, .end = 0x00a02650 },
1992         { .start = 0x00a02680, .end = 0x00a02680 },
1993         { .start = 0x00a026c0, .end = 0x00a026d0 },
1994         { .start = 0x00a02700, .end = 0x00a0270c },
1995         { .start = 0x00a02804, .end = 0x00a02804 },
1996         { .start = 0x00a02818, .end = 0x00a0281c },
1997         { .start = 0x00a02c00, .end = 0x00a02db4 },
1998         { .start = 0x00a02df4, .end = 0x00a02fb0 },
1999         { .start = 0x00a03000, .end = 0x00a03014 },
2000         { .start = 0x00a0301c, .end = 0x00a0302c },
2001         { .start = 0x00a03034, .end = 0x00a03038 },
2002         { .start = 0x00a03040, .end = 0x00a03048 },
2003         { .start = 0x00a03060, .end = 0x00a03068 },
2004         { .start = 0x00a03070, .end = 0x00a03074 },
2005         { .start = 0x00a0307c, .end = 0x00a0307c },
2006         { .start = 0x00a03080, .end = 0x00a03084 },
2007         { .start = 0x00a0308c, .end = 0x00a03090 },
2008         { .start = 0x00a03098, .end = 0x00a03098 },
2009         { .start = 0x00a030a0, .end = 0x00a030a0 },
2010         { .start = 0x00a030a8, .end = 0x00a030b4 },
2011         { .start = 0x00a030bc, .end = 0x00a030bc },
2012         { .start = 0x00a030c0, .end = 0x00a0312c },
2013         { .start = 0x00a03c00, .end = 0x00a03c5c },
2014         { .start = 0x00a04400, .end = 0x00a04454 },
2015         { .start = 0x00a04460, .end = 0x00a04474 },
2016         { .start = 0x00a044c0, .end = 0x00a044ec },
2017         { .start = 0x00a04500, .end = 0x00a04504 },
2018         { .start = 0x00a04510, .end = 0x00a04538 },
2019         { .start = 0x00a04540, .end = 0x00a04548 },
2020         { .start = 0x00a04560, .end = 0x00a0457c },
2021         { .start = 0x00a04590, .end = 0x00a04598 },
2022         { .start = 0x00a045c0, .end = 0x00a045f4 },
2023 };
2024
2025 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2026                                     struct iwl_fw_error_dump_data **data)
2027 {
2028         struct iwl_fw_error_dump_prph *prph;
2029         unsigned long flags;
2030         u32 prph_len = 0, i;
2031
2032         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2033                 return 0;
2034
2035         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2036                 /* The range includes both boundaries */
2037                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2038                          iwl_prph_dump_addr[i].start + 4;
2039                 int reg;
2040                 __le32 *val;
2041
2042                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2043
2044                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2045                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2046                                         num_bytes_in_chunk);
2047                 prph = (void *)(*data)->data;
2048                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2049                 val = (void *)prph->data;
2050
2051                 for (reg = iwl_prph_dump_addr[i].start;
2052                      reg <= iwl_prph_dump_addr[i].end;
2053                      reg += 4)
2054                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2055                                                                       reg));
2056                 *data = iwl_fw_error_next_data(*data);
2057         }
2058
2059         iwl_trans_release_nic_access(trans, &flags);
2060
2061         return prph_len;
2062 }
2063
2064 #define IWL_CSR_TO_DUMP (0x250)
2065
2066 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2067                                    struct iwl_fw_error_dump_data **data)
2068 {
2069         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2070         __le32 *val;
2071         int i;
2072
2073         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2074         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2075         val = (void *)(*data)->data;
2076
2077         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2078                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2079
2080         *data = iwl_fw_error_next_data(*data);
2081
2082         return csr_len;
2083 }
2084
2085 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2086                                        struct iwl_fw_error_dump_data **data)
2087 {
2088         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2089         unsigned long flags;
2090         __le32 *val;
2091         int i;
2092
2093         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2094                 return 0;
2095
2096         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2097         (*data)->len = cpu_to_le32(fh_regs_len);
2098         val = (void *)(*data)->data;
2099
2100         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2101                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2102
2103         iwl_trans_release_nic_access(trans, &flags);
2104
2105         *data = iwl_fw_error_next_data(*data);
2106
2107         return sizeof(**data) + fh_regs_len;
2108 }
2109
2110 static
2111 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2112 {
2113         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2114         struct iwl_fw_error_dump_data *data;
2115         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2116         struct iwl_fw_error_dump_txcmd *txcmd;
2117         struct iwl_trans_dump_data *dump_data;
2118         u32 len;
2119         u32 monitor_len;
2120         int i, ptr;
2121
2122         /* transport dump header */
2123         len = sizeof(*dump_data);
2124
2125         /* host commands */
2126         len += sizeof(*data) +
2127                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2128
2129         /* CSR registers */
2130         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2131
2132         /* PRPH registers */
2133         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2134                 /* The range includes both boundaries */
2135                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2136                         iwl_prph_dump_addr[i].start + 4;
2137
2138                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2139                         num_bytes_in_chunk;
2140         }
2141
2142         /* FH registers */
2143         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2144
2145         /* FW monitor */
2146         if (trans_pcie->fw_mon_page) {
2147                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2148                        trans_pcie->fw_mon_size;
2149                 monitor_len = trans_pcie->fw_mon_size;
2150         } else if (trans->dbg_dest_tlv) {
2151                 u32 base, end;
2152
2153                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2154                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2155
2156                 base = iwl_read_prph(trans, base) <<
2157                        trans->dbg_dest_tlv->base_shift;
2158                 end = iwl_read_prph(trans, end) <<
2159                       trans->dbg_dest_tlv->end_shift;
2160
2161                 /* Make "end" point to the actual end */
2162                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2163                         end += (1 << trans->dbg_dest_tlv->end_shift);
2164                 monitor_len = end - base;
2165                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2166                        monitor_len;
2167         } else {
2168                 monitor_len = 0;
2169         }
2170
2171         dump_data = vzalloc(len);
2172         if (!dump_data)
2173                 return NULL;
2174
2175         len = 0;
2176         data = (void *)dump_data->data;
2177         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2178         txcmd = (void *)data->data;
2179         spin_lock_bh(&cmdq->lock);
2180         ptr = cmdq->q.write_ptr;
2181         for (i = 0; i < cmdq->q.n_window; i++) {
2182                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2183                 u32 caplen, cmdlen;
2184
2185                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2186                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2187
2188                 if (cmdlen) {
2189                         len += sizeof(*txcmd) + caplen;
2190                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2191                         txcmd->caplen = cpu_to_le32(caplen);
2192                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2193                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2194                 }
2195
2196                 ptr = iwl_queue_dec_wrap(ptr);
2197         }
2198         spin_unlock_bh(&cmdq->lock);
2199
2200         data->len = cpu_to_le32(len);
2201         len += sizeof(*data);
2202         data = iwl_fw_error_next_data(data);
2203
2204         len += iwl_trans_pcie_dump_prph(trans, &data);
2205         len += iwl_trans_pcie_dump_csr(trans, &data);
2206         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2207         /* data is already pointing to the next section */
2208
2209         if ((trans_pcie->fw_mon_page &&
2210              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2211             trans->dbg_dest_tlv) {
2212                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2213                 u32 base, write_ptr, wrap_cnt;
2214
2215                 /* If there was a dest TLV - use the values from there */
2216                 if (trans->dbg_dest_tlv) {
2217                         write_ptr =
2218                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2219                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2220                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2221                 } else {
2222                         base = MON_BUFF_BASE_ADDR;
2223                         write_ptr = MON_BUFF_WRPTR;
2224                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2225                 }
2226
2227                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2228                 fw_mon_data = (void *)data->data;
2229                 fw_mon_data->fw_mon_wr_ptr =
2230                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2231                 fw_mon_data->fw_mon_cycle_cnt =
2232                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2233                 fw_mon_data->fw_mon_base_ptr =
2234                         cpu_to_le32(iwl_read_prph(trans, base));
2235
2236                 len += sizeof(*data) + sizeof(*fw_mon_data);
2237                 if (trans_pcie->fw_mon_page) {
2238                         data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2239                                                 sizeof(*fw_mon_data));
2240
2241                         /*
2242                          * The firmware is now asserted, it won't write anything
2243                          * to the buffer. CPU can take ownership to fetch the
2244                          * data. The buffer will be handed back to the device
2245                          * before the firmware will be restarted.
2246                          */
2247                         dma_sync_single_for_cpu(trans->dev,
2248                                                 trans_pcie->fw_mon_phys,
2249                                                 trans_pcie->fw_mon_size,
2250                                                 DMA_FROM_DEVICE);
2251                         memcpy(fw_mon_data->data,
2252                                page_address(trans_pcie->fw_mon_page),
2253                                trans_pcie->fw_mon_size);
2254
2255                         len += trans_pcie->fw_mon_size;
2256                 } else {
2257                         /* If we are here then the buffer is internal */
2258
2259                         /*
2260                          * Update pointers to reflect actual values after
2261                          * shifting
2262                          */
2263                         base = iwl_read_prph(trans, base) <<
2264                                trans->dbg_dest_tlv->base_shift;
2265                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2266                                            monitor_len / sizeof(u32));
2267                         data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2268                                                 monitor_len);
2269                         len += monitor_len;
2270                 }
2271         }
2272
2273         dump_data->len = len;
2274
2275         return dump_data;
2276 }
2277
2278 static const struct iwl_trans_ops trans_ops_pcie = {
2279         .start_hw = iwl_trans_pcie_start_hw,
2280         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2281         .fw_alive = iwl_trans_pcie_fw_alive,
2282         .start_fw = iwl_trans_pcie_start_fw,
2283         .stop_device = iwl_trans_pcie_stop_device,
2284
2285         .d3_suspend = iwl_trans_pcie_d3_suspend,
2286         .d3_resume = iwl_trans_pcie_d3_resume,
2287
2288         .send_cmd = iwl_trans_pcie_send_hcmd,
2289
2290         .tx = iwl_trans_pcie_tx,
2291         .reclaim = iwl_trans_pcie_reclaim,
2292
2293         .txq_disable = iwl_trans_pcie_txq_disable,
2294         .txq_enable = iwl_trans_pcie_txq_enable,
2295
2296         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2297
2298         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2299
2300         .write8 = iwl_trans_pcie_write8,
2301         .write32 = iwl_trans_pcie_write32,
2302         .read32 = iwl_trans_pcie_read32,
2303         .read_prph = iwl_trans_pcie_read_prph,
2304         .write_prph = iwl_trans_pcie_write_prph,
2305         .read_mem = iwl_trans_pcie_read_mem,
2306         .write_mem = iwl_trans_pcie_write_mem,
2307         .configure = iwl_trans_pcie_configure,
2308         .set_pmi = iwl_trans_pcie_set_pmi,
2309         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2310         .release_nic_access = iwl_trans_pcie_release_nic_access,
2311         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2312
2313         .ref = iwl_trans_pcie_ref,
2314         .unref = iwl_trans_pcie_unref,
2315
2316         .dump_data = iwl_trans_pcie_dump_data,
2317 };
2318
2319 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2320                                        const struct pci_device_id *ent,
2321                                        const struct iwl_cfg *cfg)
2322 {
2323         struct iwl_trans_pcie *trans_pcie;
2324         struct iwl_trans *trans;
2325         u16 pci_cmd;
2326         int err;
2327
2328         trans = kzalloc(sizeof(struct iwl_trans) +
2329                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2330         if (!trans) {
2331                 err = -ENOMEM;
2332                 goto out;
2333         }
2334
2335         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2336
2337         trans->ops = &trans_ops_pcie;
2338         trans->cfg = cfg;
2339         trans_lockdep_init(trans);
2340         trans_pcie->trans = trans;
2341         spin_lock_init(&trans_pcie->irq_lock);
2342         spin_lock_init(&trans_pcie->reg_lock);
2343         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2344
2345         err = pci_enable_device(pdev);
2346         if (err)
2347                 goto out_no_pci;
2348
2349         if (!cfg->base_params->pcie_l1_allowed) {
2350                 /*
2351                  * W/A - seems to solve weird behavior. We need to remove this
2352                  * if we don't want to stay in L1 all the time. This wastes a
2353                  * lot of power.
2354                  */
2355                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2356                                        PCIE_LINK_STATE_L1 |
2357                                        PCIE_LINK_STATE_CLKPM);
2358         }
2359
2360         pci_set_master(pdev);
2361
2362         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2363         if (!err)
2364                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2365         if (err) {
2366                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2367                 if (!err)
2368                         err = pci_set_consistent_dma_mask(pdev,
2369                                                           DMA_BIT_MASK(32));
2370                 /* both attempts failed: */
2371                 if (err) {
2372                         dev_err(&pdev->dev, "No suitable DMA available\n");
2373                         goto out_pci_disable_device;
2374                 }
2375         }
2376
2377         err = pci_request_regions(pdev, DRV_NAME);
2378         if (err) {
2379                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2380                 goto out_pci_disable_device;
2381         }
2382
2383         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2384         if (!trans_pcie->hw_base) {
2385                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2386                 err = -ENODEV;
2387                 goto out_pci_release_regions;
2388         }
2389
2390         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2391          * PCI Tx retries from interfering with C3 CPU state */
2392         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2393
2394         trans->dev = &pdev->dev;
2395         trans_pcie->pci_dev = pdev;
2396         iwl_disable_interrupts(trans);
2397
2398         err = pci_enable_msi(pdev);
2399         if (err) {
2400                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2401                 /* enable rfkill interrupt: hw bug w/a */
2402                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2403                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2404                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2405                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2406                 }
2407         }
2408
2409         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2410         /*
2411          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2412          * changed, and now the revision step also includes bit 0-1 (no more
2413          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2414          * in the old format.
2415          */
2416         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2417                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2418                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2419
2420         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2421         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2422                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2423
2424         /* Initialize the wait queue for commands */
2425         init_waitqueue_head(&trans_pcie->wait_command_queue);
2426
2427         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2428                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2429
2430         trans->dev_cmd_headroom = 0;
2431         trans->dev_cmd_pool =
2432                 kmem_cache_create(trans->dev_cmd_pool_name,
2433                                   sizeof(struct iwl_device_cmd)
2434                                   + trans->dev_cmd_headroom,
2435                                   sizeof(void *),
2436                                   SLAB_HWCACHE_ALIGN,
2437                                   NULL);
2438
2439         if (!trans->dev_cmd_pool) {
2440                 err = -ENOMEM;
2441                 goto out_pci_disable_msi;
2442         }
2443
2444         if (iwl_pcie_alloc_ict(trans))
2445                 goto out_free_cmd_pool;
2446
2447         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2448                                    iwl_pcie_irq_handler,
2449                                    IRQF_SHARED, DRV_NAME, trans);
2450         if (err) {
2451                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2452                 goto out_free_ict;
2453         }
2454
2455         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2456         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2457
2458         return trans;
2459
2460 out_free_ict:
2461         iwl_pcie_free_ict(trans);
2462 out_free_cmd_pool:
2463         kmem_cache_destroy(trans->dev_cmd_pool);
2464 out_pci_disable_msi:
2465         pci_disable_msi(pdev);
2466 out_pci_release_regions:
2467         pci_release_regions(pdev);
2468 out_pci_disable_device:
2469         pci_disable_device(pdev);
2470 out_no_pci:
2471         kfree(trans);
2472 out:
2473         return ERR_PTR(err);
2474 }