drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  33  *
  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-agn-hw.h"
  79 #include "iwl-fw-error-dump.h"
  80 #include "internal.h"
  81 #include "iwl-fh.h"
  82
  83 /* extended range in FW SRAM */
  84 #define IWL_FW_MEM_EXTENDED_START       0x40000
  85 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  86
  87 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  88 {
  89         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  90
  91         if (!trans_pcie->fw_mon_page)
  92                 return;
  93
  94         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  95                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  96         __free_pages(trans_pcie->fw_mon_page,
  97                      get_order(trans_pcie->fw_mon_size));
  98         trans_pcie->fw_mon_page = NULL;
  99         trans_pcie->fw_mon_phys = 0;
 100         trans_pcie->fw_mon_size = 0;
 101 }
 102
 103 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
 104 {
 105         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 106         struct page *page;
 107         dma_addr_t phys;
 108         u32 size;
 109         u8 power;
 110
 111         if (trans_pcie->fw_mon_page) {
 112                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 113                                            trans_pcie->fw_mon_size,
 114                                            DMA_FROM_DEVICE);
 115                 return;
 116         }
 117
 118         phys = 0;
 119         for (power = 26; power >= 11; power--) {
 120                 int order;
 121
 122                 size = BIT(power);
 123                 order = get_order(size);
 124                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 125                                    order);
 126                 if (!page)
 127                         continue;
 128
 129                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 130                                     DMA_FROM_DEVICE);
 131                 if (dma_mapping_error(trans->dev, phys)) {
 132                         __free_pages(page, order);
 133                         continue;
 134                 }
 135                 IWL_INFO(trans,
 136                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 137                          size, order);
 138                 break;
 139         }
 140
 141         if (WARN_ON_ONCE(!page))
 142                 return;
 143
 144         trans_pcie->fw_mon_page = page;
 145         trans_pcie->fw_mon_phys = phys;
 146         trans_pcie->fw_mon_size = size;
 147 }
 148
 149 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 150 {
 151         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 152                     ((reg & 0x0000ffff) | (2 << 28)));
 153         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 154 }
 155
 156 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 157 {
 158         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 159         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 160                     ((reg & 0x0000ffff) | (3 << 28)));
 161 }
 162
 163 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 164 {
 165         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 166                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 167                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 168                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 169         else
 170                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 171                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 172                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 173 }
 174
 175 /* PCI registers */
 176 #define PCI_CFG_RETRY_TIMEOUT   0x041
 177
 178 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 179 {
 180         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 181         u16 lctl;
 182         u16 cap;
 183
 184         /*
 185          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 186          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 187          * If so (likely), disable L0S, so device moves directly L0->L1;
 188          *    costs negligible amount of power savings.
 189          * If not (unlikely), enable L0S, so there is at least some
 190          *    power savings, even without L1.
 191          */
 192         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 193         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 194                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 195         else
 196                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 197         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 198
 199         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 200         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 201         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 202                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 203                  trans->ltr_enabled ? "En" : "Dis");
 204 }
 205
 206 /*
 207  * Start up NIC's basic functionality after it has been reset
 208  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 209  * NOTE:  This does not load uCode nor start the embedded processor
 210  */
 211 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 212 {
 213         int ret = 0;
 214         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 215
 216         /*
 217          * Use "set_bit" below rather than "write", to preserve any hardware
 218          * bits already set by default after reset.
 219          */
 220
 221         /* Disable L0S exit timer (platform NMI Work/Around) */
 222         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 223                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 224                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 225
 226         /*
 227          * Disable L0s without affecting L1;
 228          *  don't wait for ICH L0s (ICH bug W/A)
 229          */
 230         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 231                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 232
 233         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 234         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 235
 236         /*
 237          * Enable HAP INTA (interrupt from management bus) to
 238          * wake device's PCI Express link L1a -> L0s
 239          */
 240         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 241                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 242
 243         iwl_pcie_apm_config(trans);
 244
 245         /* Configure analog phase-lock-loop before activating to D0A */
 246         if (trans->cfg->base_params->pll_cfg_val)
 247                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 248                             trans->cfg->base_params->pll_cfg_val);
 249
 250         /*
 251          * Set "initialization complete" bit to move adapter from
 252          * D0U* --> D0A* (powered-up active) state.
 253          */
 254         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 255
 256         /*
 257          * Wait for clock stabilization; once stabilized, access to
 258          * device-internal resources is supported, e.g. iwl_write_prph()
 259          * and accesses to uCode SRAM.
 260          */
 261         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 262                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 263                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 264         if (ret < 0) {
 265                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 266                 goto out;
 267         }
 268
 269         if (trans->cfg->host_interrupt_operation_mode) {
 270                 /*
 271                  * This is a bit of an abuse - This is needed for 7260 / 3160
 272                  * only check host_interrupt_operation_mode even if this is
 273                  * not related to host_interrupt_operation_mode.
 274                  *
 275                  * Enable the oscillator to count wake up time for L1 exit. This
 276                  * consumes slightly more power (100uA) - but allows to be sure
 277                  * that we wake up from L1 on time.
 278                  *
 279                  * This looks weird: read twice the same register, discard the
 280                  * value, set a bit, and yet again, read that same register
 281                  * just to discard the value. But that's the way the hardware
 282                  * seems to like it.
 283                  */
 284                 iwl_read_prph(trans, OSC_CLK);
 285                 iwl_read_prph(trans, OSC_CLK);
 286                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 287                 iwl_read_prph(trans, OSC_CLK);
 288                 iwl_read_prph(trans, OSC_CLK);
 289         }
 290
 291         /*
 292          * Enable DMA clock and wait for it to stabilize.
 293          *
 294          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 295          * bits do not disable clocks.  This preserves any hardware
 296          * bits already set by default in "CLK_CTRL_REG" after reset.
 297          */
 298         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 299                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 300                                APMG_CLK_VAL_DMA_CLK_RQT);
 301                 udelay(20);
 302
 303                 /* Disable L1-Active */
 304                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 305                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 306
 307                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 308                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 309                                APMG_RTC_INT_STT_RFKILL);
 310         }
 311
 312         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 313
 314 out:
 315         return ret;
 316 }
 317
 318 /*
 319  * Enable LP XTAL to avoid HW bug where device may consume much power if
 320  * FW is not loaded after device reset. LP XTAL is disabled by default
 321  * after device HW reset. Do it only if XTAL is fed by internal source.
 322  * Configure device's "persistence" mode to avoid resetting XTAL again when
 323  * SHRD_HW_RST occurs in S3.
 324  */
 325 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 326 {
 327         int ret;
 328         u32 apmg_gp1_reg;
 329         u32 apmg_xtal_cfg_reg;
 330         u32 dl_cfg_reg;
 331
 332         /* Force XTAL ON */
 333         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 334                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 335
 336         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 337         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 338
 339         udelay(10);
 340
 341         /*
 342          * Set "initialization complete" bit to move adapter from
 343          * D0U* --> D0A* (powered-up active) state.
 344          */
 345         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 346
 347         /*
 348          * Wait for clock stabilization; once stabilized, access to
 349          * device-internal resources is possible.
 350          */
 351         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 352                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 353                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 354                            25000);
 355         if (WARN_ON(ret < 0)) {
 356                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 357                 /* Release XTAL ON request */
 358                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 359                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360                 return;
 361         }
 362
 363         /*
 364          * Clear "disable persistence" to avoid LP XTAL resetting when
 365          * SHRD_HW_RST is applied in S3.
 366          */
 367         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 368                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 369
 370         /*
 371          * Force APMG XTAL to be active to prevent its disabling by HW
 372          * caused by APMG idle state.
 373          */
 374         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 375                                                     SHR_APMG_XTAL_CFG_REG);
 376         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 377                                  apmg_xtal_cfg_reg |
 378                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 379
 380         /*
 381          * Reset entire device again - do controller reset (results in
 382          * SHRD_HW_RST). Turn MAC off before proceeding.
 383          */
 384         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 385
 386         udelay(10);
 387
 388         /* Enable LP XTAL by indirect access through CSR */
 389         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 390         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 391                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 392                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 393
 394         /* Clear delay line clock power up */
 395         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 396         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 397                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 398
 399         /*
 400          * Enable persistence mode to avoid LP XTAL resetting when
 401          * SHRD_HW_RST is applied in S3.
 402          */
 403         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 404                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 405
 406         /*
 407          * Clear "initialization complete" bit to move adapter from
 408          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 409          */
 410         iwl_clear_bit(trans, CSR_GP_CNTRL,
 411                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 412
 413         /* Activates XTAL resources monitor */
 414         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 415                                  CSR_MONITOR_XTAL_RESOURCES);
 416
 417         /* Release XTAL ON request */
 418         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 419                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 420         udelay(10);
 421
 422         /* Release APMG XTAL */
 423         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 424                                  apmg_xtal_cfg_reg &
 425                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 426 }
 427
 428 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 429 {
 430         int ret = 0;
 431
 432         /* stop device's busmaster DMA activity */
 433         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 434
 435         ret = iwl_poll_bit(trans, CSR_RESET,
 436                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 437                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 438         if (ret < 0)
 439                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 440
 441         IWL_DEBUG_INFO(trans, "stop master\n");
 442
 443         return ret;
 444 }
 445
 446 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 447 {
 448         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 449
 450         if (op_mode_leave) {
 451                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 452                         iwl_pcie_apm_init(trans);
 453
 454                 /* inform ME that we are leaving */
 455                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 456                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 457                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 458                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 459                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 460                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 461                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 462                 mdelay(5);
 463         }
 464
 465         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 466
 467         /* Stop device's DMA activity */
 468         iwl_pcie_apm_stop_master(trans);
 469
 470         if (trans->cfg->lp_xtal_workaround) {
 471                 iwl_pcie_apm_lp_xtal_enable(trans);
 472                 return;
 473         }
 474
 475         /* Reset the entire device */
 476         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 477
 478         udelay(10);
 479
 480         /*
 481          * Clear "initialization complete" bit to move adapter from
 482          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 483          */
 484         iwl_clear_bit(trans, CSR_GP_CNTRL,
 485                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 486 }
 487
 488 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 489 {
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         /* nic_init */
 493         spin_lock(&trans_pcie->irq_lock);
 494         iwl_pcie_apm_init(trans);
 495
 496         spin_unlock(&trans_pcie->irq_lock);
 497
 498         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 499                 iwl_pcie_set_pwr(trans, false);
 500
 501         iwl_op_mode_nic_config(trans->op_mode);
 502
 503         /* Allocate the RX queue, or reset if it is already allocated */
 504         iwl_pcie_rx_init(trans);
 505
 506         /* Allocate or reset and init all Tx and Command queues */
 507         if (iwl_pcie_tx_init(trans))
 508                 return -ENOMEM;
 509
 510         if (trans->cfg->base_params->shadow_reg_enable) {
 511                 /* enable shadow regs in HW */
 512                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 513                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 514         }
 515
 516         return 0;
 517 }
 518
 519 #define HW_READY_TIMEOUT (50)
 520
 521 /* Note: returns poll_bit return value, which is >= 0 if success */
 522 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 523 {
 524         int ret;
 525
 526         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 527                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 528
 529         /* See if we got it */
 530         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 531                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 532                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 533                            HW_READY_TIMEOUT);
 534
 535         if (ret >= 0)
 536                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 537
 538         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 539         return ret;
 540 }
 541
 542 /* Note: returns standard 0/-ERROR code */
 543 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 544 {
 545         int ret;
 546         int t = 0;
 547         int iter;
 548
 549         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 550
 551         ret = iwl_pcie_set_hw_ready(trans);
 552         /* If the card is ready, exit 0 */
 553         if (ret >= 0)
 554                 return 0;
 555
 556         for (iter = 0; iter < 10; iter++) {
 557                 /* If HW is not ready, prepare the conditions to check again */
 558                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 559                             CSR_HW_IF_CONFIG_REG_PREPARE);
 560
 561                 do {
 562                         ret = iwl_pcie_set_hw_ready(trans);
 563                         if (ret >= 0)
 564                                 return 0;
 565
 566                         usleep_range(200, 1000);
 567                         t += 200;
 568                 } while (t < 150000);
 569                 msleep(25);
 570         }
 571
 572         IWL_ERR(trans, "Couldn't prepare the card\n");
 573
 574         return ret;
 575 }
 576
 577 /*
 578  * ucode
 579  */
 580 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 581                                    dma_addr_t phy_addr, u32 byte_cnt)
 582 {
 583         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 584         int ret;
 585
 586         trans_pcie->ucode_write_complete = false;
 587
 588         iwl_write_direct32(trans,
 589                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 590                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 591
 592         iwl_write_direct32(trans,
 593                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 594                            dst_addr);
 595
 596         iwl_write_direct32(trans,
 597                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 598                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 599
 600         iwl_write_direct32(trans,
 601                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 602                            (iwl_get_dma_hi_addr(phy_addr)
 603                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 604
 605         iwl_write_direct32(trans,
 606                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 607                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 608                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 609                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 610
 611         iwl_write_direct32(trans,
 612                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 613                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 614                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 615                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 616
 617         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 618                                  trans_pcie->ucode_write_complete, 5 * HZ);
 619         if (!ret) {
 620                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 621                 return -ETIMEDOUT;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 628                             const struct fw_desc *section)
 629 {
 630         u8 *v_addr;
 631         dma_addr_t p_addr;
 632         u32 offset, chunk_sz = section->len;
 633         int ret = 0;
 634
 635         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 636                      section_num);
 637
 638         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 639                                     GFP_KERNEL | __GFP_NOWARN);
 640         if (!v_addr) {
 641                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 642                 chunk_sz = PAGE_SIZE;
 643                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 644                                             &p_addr, GFP_KERNEL);
 645                 if (!v_addr)
 646                         return -ENOMEM;
 647         }
 648
 649         for (offset = 0; offset < section->len; offset += chunk_sz) {
 650                 u32 copy_size, dst_addr;
 651                 bool extended_addr = false;
 652
 653                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 654                 dst_addr = section->offset + offset;
 655
 656                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 657                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 658                         extended_addr = true;
 659
 660                 if (extended_addr)
 661                         iwl_set_bits_prph(trans, LMPM_CHICK,
 662                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 663
 664                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 665                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 666                                                    copy_size);
 667
 668                 if (extended_addr)
 669                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 670                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 671
 672                 if (ret) {
 673                         IWL_ERR(trans,
 674                                 "Could not load the [%d] uCode section\n",
 675                                 section_num);
 676                         break;
 677                 }
 678         }
 679
 680         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 681         return ret;
 682 }
 683
 684 static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
 685                                             const struct fw_img *image,
 686                                             int cpu,
 687                                             int *first_ucode_section)
 688 {
 689         int shift_param;
 690         int i, ret = 0, sec_num = 0x1;
 691         u32 val, last_read_idx = 0;
 692
 693         if (cpu == 1) {
 694                 shift_param = 0;
 695                 *first_ucode_section = 0;
 696         } else {
 697                 shift_param = 16;
 698                 (*first_ucode_section)++;
 699         }
 700
 701         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 702                 last_read_idx = i;
 703
 704                 if (!image->sec[i].data ||
 705                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 706                         IWL_DEBUG_FW(trans,
 707                                      "Break since Data not valid or Empty section, sec = %d\n",
 708                                      i);
 709                         break;
 710                 }
 711
 712                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 713                 if (ret)
 714                         return ret;
 715
 716                 /* Notify the ucode of the loaded section number and status */
 717                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 718                 val = val | (sec_num << shift_param);
 719                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 720                 sec_num = (sec_num << 1) | 0x1;
 721         }
 722
 723         *first_ucode_section = last_read_idx;
 724
 725         return 0;
 726 }
 727
 728 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 729                                       const struct fw_img *image,
 730                                       int cpu,
 731                                       int *first_ucode_section)
 732 {
 733         int shift_param;
 734         int i, ret = 0;
 735         u32 last_read_idx = 0;
 736
 737         if (cpu == 1) {
 738                 shift_param = 0;
 739                 *first_ucode_section = 0;
 740         } else {
 741                 shift_param = 16;
 742                 (*first_ucode_section)++;
 743         }
 744
 745         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 746                 last_read_idx = i;
 747
 748                 if (!image->sec[i].data ||
 749                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 750                         IWL_DEBUG_FW(trans,
 751                                      "Break since Data not valid or Empty section, sec = %d\n",
 752                                      i);
 753                         break;
 754                 }
 755
 756                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 757                 if (ret)
 758                         return ret;
 759         }
 760
 761         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 762                 iwl_set_bits_prph(trans,
 763                                   CSR_UCODE_LOAD_STATUS_ADDR,
 764                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 765                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 766                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 767                                         shift_param);
 768
 769         *first_ucode_section = last_read_idx;
 770
 771         return 0;
 772 }
 773
 774 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 775 {
 776         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 777         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 778         int i;
 779
 780         if (dest->version)
 781                 IWL_ERR(trans,
 782                         "DBG DEST version is %d - expect issues\n",
 783                         dest->version);
 784
 785         IWL_INFO(trans, "Applying debug destination %s\n",
 786                  get_fw_dbg_mode_string(dest->monitor_mode));
 787
 788         if (dest->monitor_mode == EXTERNAL_MODE)
 789                 iwl_pcie_alloc_fw_monitor(trans);
 790         else
 791                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 792
 793         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 794                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 795                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 796
 797                 switch (dest->reg_ops[i].op) {
 798                 case CSR_ASSIGN:
 799                         iwl_write32(trans, addr, val);
 800                         break;
 801                 case CSR_SETBIT:
 802                         iwl_set_bit(trans, addr, BIT(val));
 803                         break;
 804                 case CSR_CLEARBIT:
 805                         iwl_clear_bit(trans, addr, BIT(val));
 806                         break;
 807                 case PRPH_ASSIGN:
 808                         iwl_write_prph(trans, addr, val);
 809                         break;
 810                 case PRPH_SETBIT:
 811                         iwl_set_bits_prph(trans, addr, BIT(val));
 812                         break;
 813                 case PRPH_CLEARBIT:
 814                         iwl_clear_bits_prph(trans, addr, BIT(val));
 815                         break;
 816                 default:
 817                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 818                                 dest->reg_ops[i].op);
 819                         break;
 820                 }
 821         }
 822
 823         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 824                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 825                                trans_pcie->fw_mon_phys >> dest->base_shift);
 826                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 827                                (trans_pcie->fw_mon_phys +
 828                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 829         }
 830 }
 831
 832 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 833                                 const struct fw_img *image)
 834 {
 835         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 836         int ret = 0;
 837         int first_ucode_section;
 838
 839         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 840                      image->is_dual_cpus ? "Dual" : "Single");
 841
 842         /* load to FW the binary non secured sections of CPU1 */
 843         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 844         if (ret)
 845                 return ret;
 846
 847         if (image->is_dual_cpus) {
 848                 /* set CPU2 header address */
 849                 iwl_write_prph(trans,
 850                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 851                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 852
 853                 /* load to FW the binary sections of CPU2 */
 854                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 855                                                  &first_ucode_section);
 856                 if (ret)
 857                         return ret;
 858         }
 859
 860         /* supported for 7000 only for the moment */
 861         if (iwlwifi_mod_params.fw_monitor &&
 862             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 863                 iwl_pcie_alloc_fw_monitor(trans);
 864
 865                 if (trans_pcie->fw_mon_size) {
 866                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 867                                        trans_pcie->fw_mon_phys >> 4);
 868                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 869                                        (trans_pcie->fw_mon_phys +
 870                                         trans_pcie->fw_mon_size) >> 4);
 871                 }
 872         } else if (trans->dbg_dest_tlv) {
 873                 iwl_pcie_apply_destination(trans);
 874         }
 875
 876         /* release CPU reset */
 877         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 878                 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 879         else
 880                 iwl_write32(trans, CSR_RESET, 0);
 881
 882         return 0;
 883 }
 884
 885 static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
 886                                            const struct fw_img *image)
 887 {
 888         int ret = 0;
 889         int first_ucode_section;
 890         u32 reg;
 891
 892         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 893                      image->is_dual_cpus ? "Dual" : "Single");
 894
 895         /* configure the ucode to be ready to get the secured image */
 896         /* release CPU reset */
 897         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 898
 899         /* load to FW the binary Secured sections of CPU1 */
 900         ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
 901                                                &first_ucode_section);
 902         if (ret)
 903                 return ret;
 904
 905         /* load to FW the binary sections of CPU2 */
 906         ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
 907                                                &first_ucode_section);
 908         if (ret)
 909                 return ret;
 910
 911         /* Notify FW loading is done */
 912         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 913
 914         /* wait for image verification to complete  */
 915         ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
 916                                 LMPM_SECURE_BOOT_STATUS_SUCCESS,
 917                                 LMPM_SECURE_BOOT_STATUS_SUCCESS,
 918                                 LMPM_SECURE_TIME_OUT);
 919         if (ret < 0) {
 920                 reg = iwl_read_prph(trans,
 921                                     LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
 922
 923                 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
 924                         reg);
 925                 return ret;
 926         }
 927
 928         return 0;
 929 }
 930
 931 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 932                                    const struct fw_img *fw, bool run_in_rfkill)
 933 {
 934         int ret;
 935         bool hw_rfkill;
 936
 937         /* This may fail if AMT took ownership of the device */
 938         if (iwl_pcie_prepare_card_hw(trans)) {
 939                 IWL_WARN(trans, "Exit HW not ready\n");
 940                 return -EIO;
 941         }
 942
 943         iwl_enable_rfkill_int(trans);
 944
 945         /* If platform's RF_KILL switch is NOT set to KILL */
 946         hw_rfkill = iwl_is_rfkill_set(trans);
 947         if (hw_rfkill)
 948                 set_bit(STATUS_RFKILL, &trans->status);
 949         else
 950                 clear_bit(STATUS_RFKILL, &trans->status);
 951         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 952         if (hw_rfkill && !run_in_rfkill)
 953                 return -ERFKILL;
 954
 955         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 956
 957         ret = iwl_pcie_nic_init(trans);
 958         if (ret) {
 959                 IWL_ERR(trans, "Unable to init nic\n");
 960                 return ret;
 961         }
 962
 963         /* make sure rfkill handshake bits are cleared */
 964         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 965         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 966                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 967
 968         /* clear (again), then enable host interrupts */
 969         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 970         iwl_enable_interrupts(trans);
 971
 972         /* really make sure rfkill handshake bits are cleared */
 973         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 974         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 975
 976         /* Load the given image to the HW */
 977         if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
 978             (CSR_HW_REV_STEP(trans->hw_rev) == SILICON_B_STEP))
 979                 return iwl_pcie_load_given_ucode_8000b(trans, fw);
 980         else
 981                 return iwl_pcie_load_given_ucode(trans, fw);
 982 }
 983
 984 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 985 {
 986         iwl_pcie_reset_ict(trans);
 987         iwl_pcie_tx_start(trans, scd_addr);
 988 }
 989
 990 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 991 {
 992         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 993         bool hw_rfkill, was_hw_rfkill;
 994
 995         was_hw_rfkill = iwl_is_rfkill_set(trans);
 996
 997         /* tell the device to stop sending interrupts */
 998         spin_lock(&trans_pcie->irq_lock);
 999         iwl_disable_interrupts(trans);
1000         spin_unlock(&trans_pcie->irq_lock);
1001
1002         /* device going down, Stop using ICT table */
1003         iwl_pcie_disable_ict(trans);
1004
1005         /*
1006          * If a HW restart happens during firmware loading,
1007          * then the firmware loading might call this function
1008          * and later it might be called again due to the
1009          * restart. So don't process again if the device is
1010          * already dead.
1011          */
1012         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1013                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1014                 iwl_pcie_tx_stop(trans);
1015                 iwl_pcie_rx_stop(trans);
1016
1017                 /* Power-down device's busmaster DMA clocks */
1018                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1019                                APMG_CLK_VAL_DMA_CLK_RQT);
1020                 udelay(5);
1021         }
1022
1023         /* Make sure (redundant) we've released our request to stay awake */
1024         iwl_clear_bit(trans, CSR_GP_CNTRL,
1025                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1026
1027         /* Stop the device, and put it in low power state */
1028         iwl_pcie_apm_stop(trans, false);
1029
1030         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1031          * Clean again the interrupt here
1032          */
1033         spin_lock(&trans_pcie->irq_lock);
1034         iwl_disable_interrupts(trans);
1035         spin_unlock(&trans_pcie->irq_lock);
1036
1037         /* stop and reset the on-board processor */
1038         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1039         udelay(20);
1040
1041         /* clear all status bits */
1042         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1043         clear_bit(STATUS_INT_ENABLED, &trans->status);
1044         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1045         clear_bit(STATUS_RFKILL, &trans->status);
1046
1047         /*
1048          * Even if we stop the HW, we still want the RF kill
1049          * interrupt
1050          */
1051         iwl_enable_rfkill_int(trans);
1052
1053         /*
1054          * Check again since the RF kill state may have changed while
1055          * all the interrupts were disabled, in this case we couldn't
1056          * receive the RF kill interrupt and update the state in the
1057          * op_mode.
1058          * Don't call the op_mode if the rkfill state hasn't changed.
1059          * This allows the op_mode to call stop_device from the rfkill
1060          * notification without endless recursion. Under very rare
1061          * circumstances, we might have a small recursion if the rfkill
1062          * state changed exactly now while we were called from stop_device.
1063          * This is very unlikely but can happen and is supported.
1064          */
1065         hw_rfkill = iwl_is_rfkill_set(trans);
1066         if (hw_rfkill)
1067                 set_bit(STATUS_RFKILL, &trans->status);
1068         else
1069                 clear_bit(STATUS_RFKILL, &trans->status);
1070         if (hw_rfkill != was_hw_rfkill)
1071                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1072
1073         /* re-take ownership to prevent other users from stealing the deivce */
1074         iwl_pcie_prepare_card_hw(trans);
1075 }
1076
1077 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1078 {
1079         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1080                 iwl_trans_pcie_stop_device(trans);
1081 }
1082
1083 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1084 {
1085         iwl_disable_interrupts(trans);
1086
1087         /*
1088          * in testing mode, the host stays awake and the
1089          * hardware won't be reset (not even partially)
1090          */
1091         if (test)
1092                 return;
1093
1094         iwl_pcie_disable_ict(trans);
1095
1096         iwl_clear_bit(trans, CSR_GP_CNTRL,
1097                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1098         iwl_clear_bit(trans, CSR_GP_CNTRL,
1099                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1100
1101         /*
1102          * reset TX queues -- some of their registers reset during S3
1103          * so if we don't reset everything here the D3 image would try
1104          * to execute some invalid memory upon resume
1105          */
1106         iwl_trans_pcie_tx_reset(trans);
1107
1108         iwl_pcie_set_pwr(trans, true);
1109 }
1110
1111 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1112                                     enum iwl_d3_status *status,
1113                                     bool test)
1114 {
1115         u32 val;
1116         int ret;
1117
1118         if (test) {
1119                 iwl_enable_interrupts(trans);
1120                 *status = IWL_D3_STATUS_ALIVE;
1121                 return 0;
1122         }
1123
1124         /*
1125          * Also enables interrupts - none will happen as the device doesn't
1126          * know we're waking it up, only when the opmode actually tells it
1127          * after this call.
1128          */
1129         iwl_pcie_reset_ict(trans);
1130
1131         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1132         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1133
1134         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1135                 udelay(2);
1136
1137         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1138                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1139                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1140                            25000);
1141         if (ret < 0) {
1142                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1143                 return ret;
1144         }
1145
1146         iwl_pcie_set_pwr(trans, false);
1147
1148         iwl_trans_pcie_tx_reset(trans);
1149
1150         ret = iwl_pcie_rx_init(trans);
1151         if (ret) {
1152                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1153                 return ret;
1154         }
1155
1156         val = iwl_read32(trans, CSR_RESET);
1157         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1158                 *status = IWL_D3_STATUS_RESET;
1159         else
1160                 *status = IWL_D3_STATUS_ALIVE;
1161
1162         return 0;
1163 }
1164
1165 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1166 {
1167         bool hw_rfkill;
1168         int err;
1169
1170         err = iwl_pcie_prepare_card_hw(trans);
1171         if (err) {
1172                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1173                 return err;
1174         }
1175
1176         /* Reset the entire device */
1177         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1178
1179         usleep_range(10, 15);
1180
1181         iwl_pcie_apm_init(trans);
1182
1183         /* From now on, the op_mode will be kept updated about RF kill state */
1184         iwl_enable_rfkill_int(trans);
1185
1186         hw_rfkill = iwl_is_rfkill_set(trans);
1187         if (hw_rfkill)
1188                 set_bit(STATUS_RFKILL, &trans->status);
1189         else
1190                 clear_bit(STATUS_RFKILL, &trans->status);
1191         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1192
1193         return 0;
1194 }
1195
1196 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1197 {
1198         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1199
1200         /* disable interrupts - don't enable HW RF kill interrupt */
1201         spin_lock(&trans_pcie->irq_lock);
1202         iwl_disable_interrupts(trans);
1203         spin_unlock(&trans_pcie->irq_lock);
1204
1205         iwl_pcie_apm_stop(trans, true);
1206
1207         spin_lock(&trans_pcie->irq_lock);
1208         iwl_disable_interrupts(trans);
1209         spin_unlock(&trans_pcie->irq_lock);
1210
1211         iwl_pcie_disable_ict(trans);
1212 }
1213
1214 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1215 {
1216         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1217 }
1218
1219 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1220 {
1221         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1222 }
1223
1224 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1225 {
1226         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1227 }
1228
1229 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1230 {
1231         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1232                                ((reg & 0x000FFFFF) | (3 << 24)));
1233         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1234 }
1235
1236 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1237                                       u32 val)
1238 {
1239         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1240                                ((addr & 0x000FFFFF) | (3 << 24)));
1241         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1242 }
1243
1244 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1245 {
1246         WARN_ON(1);
1247         return 0;
1248 }
1249
1250 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1251                                      const struct iwl_trans_config *trans_cfg)
1252 {
1253         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1254
1255         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1256         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1257         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1258                 trans_pcie->n_no_reclaim_cmds = 0;
1259         else
1260                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1261         if (trans_pcie->n_no_reclaim_cmds)
1262                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1263                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1264
1265         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1266         if (trans_pcie->rx_buf_size_8k)
1267                 trans_pcie->rx_page_order = get_order(8 * 1024);
1268         else
1269                 trans_pcie->rx_page_order = get_order(4 * 1024);
1270
1271         trans_pcie->wd_timeout =
1272                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1273
1274         trans_pcie->command_names = trans_cfg->command_names;
1275         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1276         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1277
1278         /* Initialize NAPI here - it should be before registering to mac80211
1279          * in the opmode but after the HW struct is allocated.
1280          * As this function may be called again in some corner cases don't
1281          * do anything if NAPI was already initialized.
1282          */
1283         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1284                 init_dummy_netdev(&trans_pcie->napi_dev);
1285                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1286                                      &trans_pcie->napi_dev,
1287                                      iwl_pcie_dummy_napi_poll, 64);
1288         }
1289 }
1290
1291 void iwl_trans_pcie_free(struct iwl_trans *trans)
1292 {
1293         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1294
1295         synchronize_irq(trans_pcie->pci_dev->irq);
1296
1297         iwl_pcie_tx_free(trans);
1298         iwl_pcie_rx_free(trans);
1299
1300         free_irq(trans_pcie->pci_dev->irq, trans);
1301         iwl_pcie_free_ict(trans);
1302
1303         pci_disable_msi(trans_pcie->pci_dev);
1304         iounmap(trans_pcie->hw_base);
1305         pci_release_regions(trans_pcie->pci_dev);
1306         pci_disable_device(trans_pcie->pci_dev);
1307         kmem_cache_destroy(trans->dev_cmd_pool);
1308
1309         if (trans_pcie->napi.poll)
1310                 netif_napi_del(&trans_pcie->napi);
1311
1312         iwl_pcie_free_fw_monitor(trans);
1313
1314         kfree(trans);
1315 }
1316
1317 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1318 {
1319         if (state)
1320                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1321         else
1322                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1323 }
1324
1325 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1326                                                 unsigned long *flags)
1327 {
1328         int ret;
1329         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1330
1331         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1332
1333         if (trans_pcie->cmd_in_flight)
1334                 goto out;
1335
1336         /* this bit wakes up the NIC */
1337         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1338                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1339         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1340                 udelay(2);
1341
1342         /*
1343          * These bits say the device is running, and should keep running for
1344          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1345          * but they do not indicate that embedded SRAM is restored yet;
1346          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1347          * to/from host DRAM when sleeping/waking for power-saving.
1348          * Each direction takes approximately 1/4 millisecond; with this
1349          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1350          * series of register accesses are expected (e.g. reading Event Log),
1351          * to keep device from sleeping.
1352          *
1353          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1354          * SRAM is okay/restored.  We don't check that here because this call
1355          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1356          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1357          *
1358          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1359          * and do not save/restore SRAM when power cycling.
1360          */
1361         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1362                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1363                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1364                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1365         if (unlikely(ret < 0)) {
1366                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1367                 if (!silent) {
1368                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1369                         WARN_ONCE(1,
1370                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1371                                   val);
1372                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1373                         return false;
1374                 }
1375         }
1376
1377 out:
1378         /*
1379          * Fool sparse by faking we release the lock - sparse will
1380          * track nic_access anyway.
1381          */
1382         __release(&trans_pcie->reg_lock);
1383         return true;
1384 }
1385
1386 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1387                                               unsigned long *flags)
1388 {
1389         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1390
1391         lockdep_assert_held(&trans_pcie->reg_lock);
1392
1393         /*
1394          * Fool sparse by faking we acquiring the lock - sparse will
1395          * track nic_access anyway.
1396          */
1397         __acquire(&trans_pcie->reg_lock);
1398
1399         if (trans_pcie->cmd_in_flight)
1400                 goto out;
1401
1402         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1403                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1404         /*
1405          * Above we read the CSR_GP_CNTRL register, which will flush
1406          * any previous writes, but we need the write that clears the
1407          * MAC_ACCESS_REQ bit to be performed before any other writes
1408          * scheduled on different CPUs (after we drop reg_lock).
1409          */
1410         mmiowb();
1411 out:
1412         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1413 }
1414
1415 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1416                                    void *buf, int dwords)
1417 {
1418         unsigned long flags;
1419         int offs, ret = 0;
1420         u32 *vals = buf;
1421
1422         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1423                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1424                 for (offs = 0; offs < dwords; offs++)
1425                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1426                 iwl_trans_release_nic_access(trans, &flags);
1427         } else {
1428                 ret = -EBUSY;
1429         }
1430         return ret;
1431 }
1432
1433 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1434                                     const void *buf, int dwords)
1435 {
1436         unsigned long flags;
1437         int offs, ret = 0;
1438         const u32 *vals = buf;
1439
1440         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1441                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1442                 for (offs = 0; offs < dwords; offs++)
1443                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1444                                     vals ? vals[offs] : 0);
1445                 iwl_trans_release_nic_access(trans, &flags);
1446         } else {
1447                 ret = -EBUSY;
1448         }
1449         return ret;
1450 }
1451
1452 #define IWL_FLUSH_WAIT_MS       2000
1453
1454 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1455 {
1456         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1457         struct iwl_txq *txq;
1458         struct iwl_queue *q;
1459         int cnt;
1460         unsigned long now = jiffies;
1461         u32 scd_sram_addr;
1462         u8 buf[16];
1463         int ret = 0;
1464
1465         /* waiting for all the tx frames complete might take a while */
1466         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1467                 u8 wr_ptr;
1468
1469                 if (cnt == trans_pcie->cmd_queue)
1470                         continue;
1471                 if (!test_bit(cnt, trans_pcie->queue_used))
1472                         continue;
1473                 if (!(BIT(cnt) & txq_bm))
1474                         continue;
1475
1476                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1477                 txq = &trans_pcie->txq[cnt];
1478                 q = &txq->q;
1479                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1480
1481                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1482                        !time_after(jiffies,
1483                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1484                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1485
1486                         if (WARN_ONCE(wr_ptr != write_ptr,
1487                                       "WR pointer moved while flushing %d -> %d\n",
1488                                       wr_ptr, write_ptr))
1489                                 return -ETIMEDOUT;
1490                         msleep(1);
1491                 }
1492
1493                 if (q->read_ptr != q->write_ptr) {
1494                         IWL_ERR(trans,
1495                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1496                         ret = -ETIMEDOUT;
1497                         break;
1498                 }
1499                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1500         }
1501
1502         if (!ret)
1503                 return 0;
1504
1505         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1506                 txq->q.read_ptr, txq->q.write_ptr);
1507
1508         scd_sram_addr = trans_pcie->scd_base_addr +
1509                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1510         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1511
1512         iwl_print_hex_error(trans, buf, sizeof(buf));
1513
1514         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1515                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1516                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1517
1518         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1519                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1520                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1521                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1522                 u32 tbl_dw =
1523                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1524                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1525
1526                 if (cnt & 0x1)
1527                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1528                 else
1529                         tbl_dw = tbl_dw & 0x0000FFFF;
1530
1531                 IWL_ERR(trans,
1532                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1533                         cnt, active ? "" : "in", fifo, tbl_dw,
1534                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1535                                 (TFD_QUEUE_SIZE_MAX - 1),
1536                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1537         }
1538
1539         return ret;
1540 }
1541
1542 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1543                                          u32 mask, u32 value)
1544 {
1545         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1546         unsigned long flags;
1547
1548         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1549         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1550         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1551 }
1552
1553 static const char *get_csr_string(int cmd)
1554 {
1555 #define IWL_CMD(x) case x: return #x
1556         switch (cmd) {
1557         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1558         IWL_CMD(CSR_INT_COALESCING);
1559         IWL_CMD(CSR_INT);
1560         IWL_CMD(CSR_INT_MASK);
1561         IWL_CMD(CSR_FH_INT_STATUS);
1562         IWL_CMD(CSR_GPIO_IN);
1563         IWL_CMD(CSR_RESET);
1564         IWL_CMD(CSR_GP_CNTRL);
1565         IWL_CMD(CSR_HW_REV);
1566         IWL_CMD(CSR_EEPROM_REG);
1567         IWL_CMD(CSR_EEPROM_GP);
1568         IWL_CMD(CSR_OTP_GP_REG);
1569         IWL_CMD(CSR_GIO_REG);
1570         IWL_CMD(CSR_GP_UCODE_REG);
1571         IWL_CMD(CSR_GP_DRIVER_REG);
1572         IWL_CMD(CSR_UCODE_DRV_GP1);
1573         IWL_CMD(CSR_UCODE_DRV_GP2);
1574         IWL_CMD(CSR_LED_REG);
1575         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1576         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1577         IWL_CMD(CSR_ANA_PLL_CFG);
1578         IWL_CMD(CSR_HW_REV_WA_REG);
1579         IWL_CMD(CSR_MONITOR_STATUS_REG);
1580         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1581         default:
1582                 return "UNKNOWN";
1583         }
1584 #undef IWL_CMD
1585 }
1586
1587 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1588 {
1589         int i;
1590         static const u32 csr_tbl[] = {
1591                 CSR_HW_IF_CONFIG_REG,
1592                 CSR_INT_COALESCING,
1593                 CSR_INT,
1594                 CSR_INT_MASK,
1595                 CSR_FH_INT_STATUS,
1596                 CSR_GPIO_IN,
1597                 CSR_RESET,
1598                 CSR_GP_CNTRL,
1599                 CSR_HW_REV,
1600                 CSR_EEPROM_REG,
1601                 CSR_EEPROM_GP,
1602                 CSR_OTP_GP_REG,
1603                 CSR_GIO_REG,
1604                 CSR_GP_UCODE_REG,
1605                 CSR_GP_DRIVER_REG,
1606                 CSR_UCODE_DRV_GP1,
1607                 CSR_UCODE_DRV_GP2,
1608                 CSR_LED_REG,
1609                 CSR_DRAM_INT_TBL_REG,
1610                 CSR_GIO_CHICKEN_BITS,
1611                 CSR_ANA_PLL_CFG,
1612                 CSR_MONITOR_STATUS_REG,
1613                 CSR_HW_REV_WA_REG,
1614                 CSR_DBG_HPET_MEM_REG
1615         };
1616         IWL_ERR(trans, "CSR values:\n");
1617         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1618                 "CSR_INT_PERIODIC_REG)\n");
1619         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1620                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1621                         get_csr_string(csr_tbl[i]),
1622                         iwl_read32(trans, csr_tbl[i]));
1623         }
1624 }
1625
1626 #ifdef CONFIG_IWLWIFI_DEBUGFS
1627 /* create and remove of files */
1628 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1629         if (!debugfs_create_file(#name, mode, parent, trans,            \
1630                                  &iwl_dbgfs_##name##_ops))              \
1631                 goto err;                                               \
1632 } while (0)
1633
1634 /* file operation */
1635 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1636 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1637         .read = iwl_dbgfs_##name##_read,                                \
1638         .open = simple_open,                                            \
1639         .llseek = generic_file_llseek,                                  \
1640 };
1641
1642 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1643 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1644         .write = iwl_dbgfs_##name##_write,                              \
1645         .open = simple_open,                                            \
1646         .llseek = generic_file_llseek,                                  \
1647 };
1648
1649 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1650 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1651         .write = iwl_dbgfs_##name##_write,                              \
1652         .read = iwl_dbgfs_##name##_read,                                \
1653         .open = simple_open,                                            \
1654         .llseek = generic_file_llseek,                                  \
1655 };
1656
1657 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1658                                        char __user *user_buf,
1659                                        size_t count, loff_t *ppos)
1660 {
1661         struct iwl_trans *trans = file->private_data;
1662         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1663         struct iwl_txq *txq;
1664         struct iwl_queue *q;
1665         char *buf;
1666         int pos = 0;
1667         int cnt;
1668         int ret;
1669         size_t bufsz;
1670
1671         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1672
1673         if (!trans_pcie->txq)
1674                 return -EAGAIN;
1675
1676         buf = kzalloc(bufsz, GFP_KERNEL);
1677         if (!buf)
1678                 return -ENOMEM;
1679
1680         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1681                 txq = &trans_pcie->txq[cnt];
1682                 q = &txq->q;
1683                 pos += scnprintf(buf + pos, bufsz - pos,
1684                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1685                                 cnt, q->read_ptr, q->write_ptr,
1686                                 !!test_bit(cnt, trans_pcie->queue_used),
1687                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1688                                  txq->need_update,
1689                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1690         }
1691         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1692         kfree(buf);
1693         return ret;
1694 }
1695
1696 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1697                                        char __user *user_buf,
1698                                        size_t count, loff_t *ppos)
1699 {
1700         struct iwl_trans *trans = file->private_data;
1701         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1702         struct iwl_rxq *rxq = &trans_pcie->rxq;
1703         char buf[256];
1704         int pos = 0;
1705         const size_t bufsz = sizeof(buf);
1706
1707         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1708                                                 rxq->read);
1709         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1710                                                 rxq->write);
1711         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1712                                                 rxq->write_actual);
1713         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1714                                                 rxq->need_update);
1715         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1716                                                 rxq->free_count);
1717         if (rxq->rb_stts) {
1718                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1719                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1720         } else {
1721                 pos += scnprintf(buf + pos, bufsz - pos,
1722                                         "closed_rb_num: Not Allocated\n");
1723         }
1724         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1725 }
1726
1727 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1728                                         char __user *user_buf,
1729                                         size_t count, loff_t *ppos)
1730 {
1731         struct iwl_trans *trans = file->private_data;
1732         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1733         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1734
1735         int pos = 0;
1736         char *buf;
1737         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1738         ssize_t ret;
1739
1740         buf = kzalloc(bufsz, GFP_KERNEL);
1741         if (!buf)
1742                 return -ENOMEM;
1743
1744         pos += scnprintf(buf + pos, bufsz - pos,
1745                         "Interrupt Statistics Report:\n");
1746
1747         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1748                 isr_stats->hw);
1749         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1750                 isr_stats->sw);
1751         if (isr_stats->sw || isr_stats->hw) {
1752                 pos += scnprintf(buf + pos, bufsz - pos,
1753                         "\tLast Restarting Code:  0x%X\n",
1754                         isr_stats->err_code);
1755         }
1756 #ifdef CONFIG_IWLWIFI_DEBUG
1757         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1758                 isr_stats->sch);
1759         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1760                 isr_stats->alive);
1761 #endif
1762         pos += scnprintf(buf + pos, bufsz - pos,
1763                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1764
1765         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1766                 isr_stats->ctkill);
1767
1768         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1769                 isr_stats->wakeup);
1770
1771         pos += scnprintf(buf + pos, bufsz - pos,
1772                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1773
1774         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1775                 isr_stats->tx);
1776
1777         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1778                 isr_stats->unhandled);
1779
1780         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1781         kfree(buf);
1782         return ret;
1783 }
1784
1785 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1786                                          const char __user *user_buf,
1787                                          size_t count, loff_t *ppos)
1788 {
1789         struct iwl_trans *trans = file->private_data;
1790         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1791         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1792
1793         char buf[8];
1794         int buf_size;
1795         u32 reset_flag;
1796
1797         memset(buf, 0, sizeof(buf));
1798         buf_size = min(count, sizeof(buf) -  1);
1799         if (copy_from_user(buf, user_buf, buf_size))
1800                 return -EFAULT;
1801         if (sscanf(buf, "%x", &reset_flag) != 1)
1802                 return -EFAULT;
1803         if (reset_flag == 0)
1804                 memset(isr_stats, 0, sizeof(*isr_stats));
1805
1806         return count;
1807 }
1808
1809 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1810                                    const char __user *user_buf,
1811                                    size_t count, loff_t *ppos)
1812 {
1813         struct iwl_trans *trans = file->private_data;
1814         char buf[8];
1815         int buf_size;
1816         int csr;
1817
1818         memset(buf, 0, sizeof(buf));
1819         buf_size = min(count, sizeof(buf) -  1);
1820         if (copy_from_user(buf, user_buf, buf_size))
1821                 return -EFAULT;
1822         if (sscanf(buf, "%d", &csr) != 1)
1823                 return -EFAULT;
1824
1825         iwl_pcie_dump_csr(trans);
1826
1827         return count;
1828 }
1829
1830 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1831                                      char __user *user_buf,
1832                                      size_t count, loff_t *ppos)
1833 {
1834         struct iwl_trans *trans = file->private_data;
1835         char *buf = NULL;
1836         ssize_t ret;
1837
1838         ret = iwl_dump_fh(trans, &buf);
1839         if (ret < 0)
1840                 return ret;
1841         if (!buf)
1842                 return -EINVAL;
1843         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1844         kfree(buf);
1845         return ret;
1846 }
1847
1848 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1849 DEBUGFS_READ_FILE_OPS(fh_reg);
1850 DEBUGFS_READ_FILE_OPS(rx_queue);
1851 DEBUGFS_READ_FILE_OPS(tx_queue);
1852 DEBUGFS_WRITE_FILE_OPS(csr);
1853
1854 /*
1855  * Create the debugfs files and directories
1856  *
1857  */
1858 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1859                                          struct dentry *dir)
1860 {
1861         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1862         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1863         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1864         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1865         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1866         return 0;
1867
1868 err:
1869         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1870         return -ENOMEM;
1871 }
1872 #else
1873 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1874                                          struct dentry *dir)
1875 {
1876         return 0;
1877 }
1878 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1879
1880 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1881 {
1882         u32 cmdlen = 0;
1883         int i;
1884
1885         for (i = 0; i < IWL_NUM_OF_TBS; i++)
1886                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1887
1888         return cmdlen;
1889 }
1890
1891 static const struct {
1892         u32 start, end;
1893 } iwl_prph_dump_addr[] = {
1894         { .start = 0x00a00000, .end = 0x00a00000 },
1895         { .start = 0x00a0000c, .end = 0x00a00024 },
1896         { .start = 0x00a0002c, .end = 0x00a0003c },
1897         { .start = 0x00a00410, .end = 0x00a00418 },
1898         { .start = 0x00a00420, .end = 0x00a00420 },
1899         { .start = 0x00a00428, .end = 0x00a00428 },
1900         { .start = 0x00a00430, .end = 0x00a0043c },
1901         { .start = 0x00a00444, .end = 0x00a00444 },
1902         { .start = 0x00a004c0, .end = 0x00a004cc },
1903         { .start = 0x00a004d8, .end = 0x00a004d8 },
1904         { .start = 0x00a004e0, .end = 0x00a004f0 },
1905         { .start = 0x00a00840, .end = 0x00a00840 },
1906         { .start = 0x00a00850, .end = 0x00a00858 },
1907         { .start = 0x00a01004, .end = 0x00a01008 },
1908         { .start = 0x00a01010, .end = 0x00a01010 },
1909         { .start = 0x00a01018, .end = 0x00a01018 },
1910         { .start = 0x00a01024, .end = 0x00a01024 },
1911         { .start = 0x00a0102c, .end = 0x00a01034 },
1912         { .start = 0x00a0103c, .end = 0x00a01040 },
1913         { .start = 0x00a01048, .end = 0x00a01094 },
1914         { .start = 0x00a01c00, .end = 0x00a01c20 },
1915         { .start = 0x00a01c58, .end = 0x00a01c58 },
1916         { .start = 0x00a01c7c, .end = 0x00a01c7c },
1917         { .start = 0x00a01c28, .end = 0x00a01c54 },
1918         { .start = 0x00a01c5c, .end = 0x00a01c5c },
1919         { .start = 0x00a01c84, .end = 0x00a01c84 },
1920         { .start = 0x00a01ce0, .end = 0x00a01d0c },
1921         { .start = 0x00a01d18, .end = 0x00a01d20 },
1922         { .start = 0x00a01d2c, .end = 0x00a01d30 },
1923         { .start = 0x00a01d40, .end = 0x00a01d5c },
1924         { .start = 0x00a01d80, .end = 0x00a01d80 },
1925         { .start = 0x00a01d98, .end = 0x00a01d98 },
1926         { .start = 0x00a01dc0, .end = 0x00a01dfc },
1927         { .start = 0x00a01e00, .end = 0x00a01e2c },
1928         { .start = 0x00a01e40, .end = 0x00a01e60 },
1929         { .start = 0x00a01e84, .end = 0x00a01e90 },
1930         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1931         { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1932         { .start = 0x00a01f00, .end = 0x00a01f14 },
1933         { .start = 0x00a01f44, .end = 0x00a01f58 },
1934         { .start = 0x00a01f80, .end = 0x00a01fa8 },
1935         { .start = 0x00a01fb0, .end = 0x00a01fbc },
1936         { .start = 0x00a01ff8, .end = 0x00a01ffc },
1937         { .start = 0x00a02000, .end = 0x00a02048 },
1938         { .start = 0x00a02068, .end = 0x00a020f0 },
1939         { .start = 0x00a02100, .end = 0x00a02118 },
1940         { .start = 0x00a02140, .end = 0x00a0214c },
1941         { .start = 0x00a02168, .end = 0x00a0218c },
1942         { .start = 0x00a021c0, .end = 0x00a021c0 },
1943         { .start = 0x00a02400, .end = 0x00a02410 },
1944         { .start = 0x00a02418, .end = 0x00a02420 },
1945         { .start = 0x00a02428, .end = 0x00a0242c },
1946         { .start = 0x00a02434, .end = 0x00a02434 },
1947         { .start = 0x00a02440, .end = 0x00a02460 },
1948         { .start = 0x00a02468, .end = 0x00a024b0 },
1949         { .start = 0x00a024c8, .end = 0x00a024cc },
1950         { .start = 0x00a02500, .end = 0x00a02504 },
1951         { .start = 0x00a0250c, .end = 0x00a02510 },
1952         { .start = 0x00a02540, .end = 0x00a02554 },
1953         { .start = 0x00a02580, .end = 0x00a025f4 },
1954         { .start = 0x00a02600, .end = 0x00a0260c },
1955         { .start = 0x00a02648, .end = 0x00a02650 },
1956         { .start = 0x00a02680, .end = 0x00a02680 },
1957         { .start = 0x00a026c0, .end = 0x00a026d0 },
1958         { .start = 0x00a02700, .end = 0x00a0270c },
1959         { .start = 0x00a02804, .end = 0x00a02804 },
1960         { .start = 0x00a02818, .end = 0x00a0281c },
1961         { .start = 0x00a02c00, .end = 0x00a02db4 },
1962         { .start = 0x00a02df4, .end = 0x00a02fb0 },
1963         { .start = 0x00a03000, .end = 0x00a03014 },
1964         { .start = 0x00a0301c, .end = 0x00a0302c },
1965         { .start = 0x00a03034, .end = 0x00a03038 },
1966         { .start = 0x00a03040, .end = 0x00a03048 },
1967         { .start = 0x00a03060, .end = 0x00a03068 },
1968         { .start = 0x00a03070, .end = 0x00a03074 },
1969         { .start = 0x00a0307c, .end = 0x00a0307c },
1970         { .start = 0x00a03080, .end = 0x00a03084 },
1971         { .start = 0x00a0308c, .end = 0x00a03090 },
1972         { .start = 0x00a03098, .end = 0x00a03098 },
1973         { .start = 0x00a030a0, .end = 0x00a030a0 },
1974         { .start = 0x00a030a8, .end = 0x00a030b4 },
1975         { .start = 0x00a030bc, .end = 0x00a030bc },
1976         { .start = 0x00a030c0, .end = 0x00a0312c },
1977         { .start = 0x00a03c00, .end = 0x00a03c5c },
1978         { .start = 0x00a04400, .end = 0x00a04454 },
1979         { .start = 0x00a04460, .end = 0x00a04474 },
1980         { .start = 0x00a044c0, .end = 0x00a044ec },
1981         { .start = 0x00a04500, .end = 0x00a04504 },
1982         { .start = 0x00a04510, .end = 0x00a04538 },
1983         { .start = 0x00a04540, .end = 0x00a04548 },
1984         { .start = 0x00a04560, .end = 0x00a0457c },
1985         { .start = 0x00a04590, .end = 0x00a04598 },
1986         { .start = 0x00a045c0, .end = 0x00a045f4 },
1987 };
1988
1989 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1990                                     struct iwl_fw_error_dump_data **data)
1991 {
1992         struct iwl_fw_error_dump_prph *prph;
1993         unsigned long flags;
1994         u32 prph_len = 0, i;
1995
1996         if (!iwl_trans_grab_nic_access(trans, false, &flags))
1997                 return 0;
1998
1999         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2000                 /* The range includes both boundaries */
2001                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2002                          iwl_prph_dump_addr[i].start + 4;
2003                 int reg;
2004                 __le32 *val;
2005
2006                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2007
2008                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2009                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2010                                         num_bytes_in_chunk);
2011                 prph = (void *)(*data)->data;
2012                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2013                 val = (void *)prph->data;
2014
2015                 for (reg = iwl_prph_dump_addr[i].start;
2016                      reg <= iwl_prph_dump_addr[i].end;
2017                      reg += 4)
2018                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2019                                                                       reg));
2020                 *data = iwl_fw_error_next_data(*data);
2021         }
2022
2023         iwl_trans_release_nic_access(trans, &flags);
2024
2025         return prph_len;
2026 }
2027
2028 #define IWL_CSR_TO_DUMP (0x250)
2029
2030 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2031                                    struct iwl_fw_error_dump_data **data)
2032 {
2033         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2034         __le32 *val;
2035         int i;
2036
2037         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2038         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2039         val = (void *)(*data)->data;
2040
2041         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2042                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2043
2044         *data = iwl_fw_error_next_data(*data);
2045
2046         return csr_len;
2047 }
2048
2049 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2050                                        struct iwl_fw_error_dump_data **data)
2051 {
2052         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2053         unsigned long flags;
2054         __le32 *val;
2055         int i;
2056
2057         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2058                 return 0;
2059
2060         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2061         (*data)->len = cpu_to_le32(fh_regs_len);
2062         val = (void *)(*data)->data;
2063
2064         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2065                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2066
2067         iwl_trans_release_nic_access(trans, &flags);
2068
2069         *data = iwl_fw_error_next_data(*data);
2070
2071         return sizeof(**data) + fh_regs_len;
2072 }
2073
2074 static
2075 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2076 {
2077         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2078         struct iwl_fw_error_dump_data *data;
2079         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2080         struct iwl_fw_error_dump_txcmd *txcmd;
2081         struct iwl_trans_dump_data *dump_data;
2082         u32 len;
2083         u32 monitor_len;
2084         int i, ptr;
2085
2086         /* transport dump header */
2087         len = sizeof(*dump_data);
2088
2089         /* host commands */
2090         len += sizeof(*data) +
2091                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2092
2093         /* CSR registers */
2094         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2095
2096         /* PRPH registers */
2097         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2098                 /* The range includes both boundaries */
2099                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2100                         iwl_prph_dump_addr[i].start + 4;
2101
2102                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2103                         num_bytes_in_chunk;
2104         }
2105
2106         /* FH registers */
2107         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2108
2109         /* FW monitor */
2110         if (trans_pcie->fw_mon_page) {
2111                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2112                        trans_pcie->fw_mon_size;
2113                 monitor_len = trans_pcie->fw_mon_size;
2114         } else if (trans->dbg_dest_tlv) {
2115                 u32 base, end;
2116
2117                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2118                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2119
2120                 base = iwl_read_prph(trans, base) <<
2121                        trans->dbg_dest_tlv->base_shift;
2122                 end = iwl_read_prph(trans, end) <<
2123                       trans->dbg_dest_tlv->end_shift;
2124
2125                 /* Make "end" point to the actual end */
2126                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2127                         end += (1 << trans->dbg_dest_tlv->end_shift);
2128                 monitor_len = end - base;
2129                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2130                        monitor_len;
2131         } else {
2132                 monitor_len = 0;
2133         }
2134
2135         dump_data = vzalloc(len);
2136         if (!dump_data)
2137                 return NULL;
2138
2139         len = 0;
2140         data = (void *)dump_data->data;
2141         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2142         txcmd = (void *)data->data;
2143         spin_lock_bh(&cmdq->lock);
2144         ptr = cmdq->q.write_ptr;
2145         for (i = 0; i < cmdq->q.n_window; i++) {
2146                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2147                 u32 caplen, cmdlen;
2148
2149                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2150                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2151
2152                 if (cmdlen) {
2153                         len += sizeof(*txcmd) + caplen;
2154                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2155                         txcmd->caplen = cpu_to_le32(caplen);
2156                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2157                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2158                 }
2159
2160                 ptr = iwl_queue_dec_wrap(ptr);
2161         }
2162         spin_unlock_bh(&cmdq->lock);
2163
2164         data->len = cpu_to_le32(len);
2165         len += sizeof(*data);
2166         data = iwl_fw_error_next_data(data);
2167
2168         len += iwl_trans_pcie_dump_prph(trans, &data);
2169         len += iwl_trans_pcie_dump_csr(trans, &data);
2170         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2171         /* data is already pointing to the next section */
2172
2173         if ((trans_pcie->fw_mon_page &&
2174              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2175             trans->dbg_dest_tlv) {
2176                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2177                 u32 base, write_ptr, wrap_cnt;
2178
2179                 /* If there was a dest TLV - use the values from there */
2180                 if (trans->dbg_dest_tlv) {
2181                         write_ptr =
2182                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2183                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2184                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2185                 } else {
2186                         base = MON_BUFF_BASE_ADDR;
2187                         write_ptr = MON_BUFF_WRPTR;
2188                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2189                 }
2190
2191                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2192                 fw_mon_data = (void *)data->data;
2193                 fw_mon_data->fw_mon_wr_ptr =
2194                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2195                 fw_mon_data->fw_mon_cycle_cnt =
2196                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2197                 fw_mon_data->fw_mon_base_ptr =
2198                         cpu_to_le32(iwl_read_prph(trans, base));
2199
2200                 len += sizeof(*data) + sizeof(*fw_mon_data);
2201                 if (trans_pcie->fw_mon_page) {
2202                         data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2203                                                 sizeof(*fw_mon_data));
2204
2205                         /*
2206                          * The firmware is now asserted, it won't write anything
2207                          * to the buffer. CPU can take ownership to fetch the
2208                          * data. The buffer will be handed back to the device
2209                          * before the firmware will be restarted.
2210                          */
2211                         dma_sync_single_for_cpu(trans->dev,
2212                                                 trans_pcie->fw_mon_phys,
2213                                                 trans_pcie->fw_mon_size,
2214                                                 DMA_FROM_DEVICE);
2215                         memcpy(fw_mon_data->data,
2216                                page_address(trans_pcie->fw_mon_page),
2217                                trans_pcie->fw_mon_size);
2218
2219                         len += trans_pcie->fw_mon_size;
2220                 } else {
2221                         /* If we are here then the buffer is internal */
2222
2223                         /*
2224                          * Update pointers to reflect actual values after
2225                          * shifting
2226                          */
2227                         base = iwl_read_prph(trans, base) <<
2228                                trans->dbg_dest_tlv->base_shift;
2229                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2230                                            monitor_len / sizeof(u32));
2231                         data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2232                                                 monitor_len);
2233                         len += monitor_len;
2234                 }
2235         }
2236
2237         dump_data->len = len;
2238
2239         return dump_data;
2240 }
2241
2242 static const struct iwl_trans_ops trans_ops_pcie = {
2243         .start_hw = iwl_trans_pcie_start_hw,
2244         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2245         .fw_alive = iwl_trans_pcie_fw_alive,
2246         .start_fw = iwl_trans_pcie_start_fw,
2247         .stop_device = iwl_trans_pcie_stop_device,
2248
2249         .d3_suspend = iwl_trans_pcie_d3_suspend,
2250         .d3_resume = iwl_trans_pcie_d3_resume,
2251
2252         .send_cmd = iwl_trans_pcie_send_hcmd,
2253
2254         .tx = iwl_trans_pcie_tx,
2255         .reclaim = iwl_trans_pcie_reclaim,
2256
2257         .txq_disable = iwl_trans_pcie_txq_disable,
2258         .txq_enable = iwl_trans_pcie_txq_enable,
2259
2260         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2261
2262         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2263
2264         .write8 = iwl_trans_pcie_write8,
2265         .write32 = iwl_trans_pcie_write32,
2266         .read32 = iwl_trans_pcie_read32,
2267         .read_prph = iwl_trans_pcie_read_prph,
2268         .write_prph = iwl_trans_pcie_write_prph,
2269         .read_mem = iwl_trans_pcie_read_mem,
2270         .write_mem = iwl_trans_pcie_write_mem,
2271         .configure = iwl_trans_pcie_configure,
2272         .set_pmi = iwl_trans_pcie_set_pmi,
2273         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2274         .release_nic_access = iwl_trans_pcie_release_nic_access,
2275         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2276
2277         .dump_data = iwl_trans_pcie_dump_data,
2278 };
2279
2280 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2281                                        const struct pci_device_id *ent,
2282                                        const struct iwl_cfg *cfg)
2283 {
2284         struct iwl_trans_pcie *trans_pcie;
2285         struct iwl_trans *trans;
2286         u16 pci_cmd;
2287         int err;
2288
2289         trans = kzalloc(sizeof(struct iwl_trans) +
2290                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2291         if (!trans) {
2292                 err = -ENOMEM;
2293                 goto out;
2294         }
2295
2296         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2297
2298         trans->ops = &trans_ops_pcie;
2299         trans->cfg = cfg;
2300         trans_lockdep_init(trans);
2301         trans_pcie->trans = trans;
2302         spin_lock_init(&trans_pcie->irq_lock);
2303         spin_lock_init(&trans_pcie->reg_lock);
2304         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2305
2306         err = pci_enable_device(pdev);
2307         if (err)
2308                 goto out_no_pci;
2309
2310         if (!cfg->base_params->pcie_l1_allowed) {
2311                 /*
2312                  * W/A - seems to solve weird behavior. We need to remove this
2313                  * if we don't want to stay in L1 all the time. This wastes a
2314                  * lot of power.
2315                  */
2316                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2317                                        PCIE_LINK_STATE_L1 |
2318                                        PCIE_LINK_STATE_CLKPM);
2319         }
2320
2321         pci_set_master(pdev);
2322
2323         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2324         if (!err)
2325                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2326         if (err) {
2327                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2328                 if (!err)
2329                         err = pci_set_consistent_dma_mask(pdev,
2330                                                           DMA_BIT_MASK(32));
2331                 /* both attempts failed: */
2332                 if (err) {
2333                         dev_err(&pdev->dev, "No suitable DMA available\n");
2334                         goto out_pci_disable_device;
2335                 }
2336         }
2337
2338         err = pci_request_regions(pdev, DRV_NAME);
2339         if (err) {
2340                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2341                 goto out_pci_disable_device;
2342         }
2343
2344         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2345         if (!trans_pcie->hw_base) {
2346                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2347                 err = -ENODEV;
2348                 goto out_pci_release_regions;
2349         }
2350
2351         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2352          * PCI Tx retries from interfering with C3 CPU state */
2353         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2354
2355         trans->dev = &pdev->dev;
2356         trans_pcie->pci_dev = pdev;
2357         iwl_disable_interrupts(trans);
2358
2359         err = pci_enable_msi(pdev);
2360         if (err) {
2361                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2362                 /* enable rfkill interrupt: hw bug w/a */
2363                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2364                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2365                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2366                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2367                 }
2368         }
2369
2370         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2371         /*
2372          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2373          * changed, and now the revision step also includes bit 0-1 (no more
2374          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2375          * in the old format.
2376          */
2377         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2378                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2379                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2380
2381         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2382         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2383                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2384
2385         /* Initialize the wait queue for commands */
2386         init_waitqueue_head(&trans_pcie->wait_command_queue);
2387
2388         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2389                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2390
2391         trans->dev_cmd_headroom = 0;
2392         trans->dev_cmd_pool =
2393                 kmem_cache_create(trans->dev_cmd_pool_name,
2394                                   sizeof(struct iwl_device_cmd)
2395                                   + trans->dev_cmd_headroom,
2396                                   sizeof(void *),
2397                                   SLAB_HWCACHE_ALIGN,
2398                                   NULL);
2399
2400         if (!trans->dev_cmd_pool) {
2401                 err = -ENOMEM;
2402                 goto out_pci_disable_msi;
2403         }
2404
2405         if (iwl_pcie_alloc_ict(trans))
2406                 goto out_free_cmd_pool;
2407
2408         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2409                                    iwl_pcie_irq_handler,
2410                                    IRQF_SHARED, DRV_NAME, trans);
2411         if (err) {
2412                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2413                 goto out_free_ict;
2414         }
2415
2416         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2417
2418         return trans;
2419
2420 out_free_ict:
2421         iwl_pcie_free_ict(trans);
2422 out_free_cmd_pool:
2423         kmem_cache_destroy(trans->dev_cmd_pool);
2424 out_pci_disable_msi:
2425         pci_disable_msi(pdev);
2426 out_pci_release_regions:
2427         pci_release_regions(pdev);
2428 out_pci_disable_device:
2429         pci_disable_device(pdev);
2430 out_no_pci:
2431         kfree(trans);
2432 out:
2433         return ERR_PTR(err);
2434 }