Merge branch 'pm-cpufreq'

[cascardo/linux.git] / Documentation / devicetree / bindings / mtd / nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 3733300..b056016 100644 (file)
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -35,6 +35,15 @@ Optional NAND chip properties:
 - nand-ecc-step-size: integer representing the number of data bytes
                      that are covered by a single ECC step.
 
+- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
+                    strength. The maximum ECC strength is both controller and
+                    chip dependent. The controller side has to select the ECC
+                    config providing the best strength and taking the OOB area
+                    size constraint into account.
+                    This is particularly useful when only the in-band area is
+                    used by the upper layers, and you want to make your NAND
+                    as reliable as possible.
+
 The ECC strength and ECC step size properties define the correction capability
 of a controller. Together, they say a controller can correct "{strength} bit
 errors per {size} bytes".