#include <linux/irqchip.h>
#include <asm/irq.h>
+#define TIMER0_IRQ 3 /* Fixed by ISA */
+
/*
* Early Hardware specific Interrupt setup
* -Platform independent, needed for each CPU (not foldable into init_IRQ)
static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
- switch (irq) {
+ switch (hw) {
case TIMER0_IRQ:
+ irq_set_percpu_devid(irq);
irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
break;
default:
.map = arc_intc_domain_map,
};
-static struct irq_domain *root_domain;
-
static int __init
init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
{
+ struct irq_domain *root_domain;
+
if (parent)
panic("DeviceTree incore intc not a root irq controller\n");
- root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
+ root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
&arc_intc_domain_ops, NULL);
-
if (!root_domain)
panic("root irq domain not avail\n");
- /* with this we don't need to export root_domain */
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
irq_set_default_host(root_domain);
return 0;