Merge branch 'work.splice_read' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / arm / boot / dts / imx6qdl-gw52xx.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 7191b84..a7100f9 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -315,6 +315,8 @@
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
+       uart-has-rtscts;
+       rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };
 
@@ -353,6 +355,12 @@
        status = "okay";
 };
 
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+};
+
 &iomuxc {
        imx6qdl-gw52xx {
                pinctrl_audmux: audmuxgrp {
@@ -376,18 +384,18 @@
 
                pinctrl_enet: enetgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
-                               MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
-                               MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
-                               MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
-                               MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
-                               MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
-                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
-                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                               MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
+                               MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
+                               MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
+                               MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
+                               MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
+                               MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
+                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
+                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
+                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
+                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
+                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
+                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
@@ -487,6 +495,7 @@
                        fsl,pins = <
                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                               MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
                        >;
                };
 
@@ -549,5 +558,11 @@
                                MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
                        >;
                };
+
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
+                       >;
+               };
        };
 };