Merge tag 'ceph-for-4.9-rc1' of git://github.com/ceph/ceph-client

[cascardo/linux.git] / arch / arm / boot / dts / imx6ul.dtsi

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 7177899..c5c05fd 100644 (file)
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -36,6 +36,9 @@
                serial5 = &uart6;
                serial6 = &uart7;
                serial7 = &uart8;
+               sai1 = &sai1;
+               sai2 = &sai2;
+               sai3 = &sai3;
                spi0 = &ecspi1;
                spi1 = &ecspi2;
                spi2 = &ecspi3;
@@ -55,15 +58,15 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        operating-points = <
                                /* kHz  uV */
-                               528000  1250000
-                               396000  1150000
-                               198000  1150000
+                               528000  1175000
+                               396000  1025000
+                               198000  950000
                        >;
                        fsl,soc-operating-points = <
                                /* KHz  uV */
-                               528000  1250000
-                               396000  1150000
-                               198000  1150000
+                               528000  1175000
+                               396000  1175000
+                               198000  1175000
                        >;
                        clocks = <&clks IMX6UL_CLK_ARM>,
                                 <&clks IMX6UL_CLK_PLL2_BUS>,
@@ -408,6 +411,8 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
+                               gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
+                                             <&iomuxc 16 33 16>;
                        };
 
                        gpio2: gpio@020a0000 {
@@ -419,6 +424,7 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
+                               gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
                        };
 
                        gpio3: gpio@020a4000 {
@@ -430,6 +436,7 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
+                               gpio-ranges = <&iomuxc 0 65 29>;
                        };
 
                        gpio4: gpio@020a8000 {
@@ -441,6 +448,7 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
+                               gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
                        };
 
                        gpio5: gpio@020ac000 {
@@ -452,6 +460,7 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
+                               gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
                        };
 
                        fec2: ethernet@020b4000 {
@@ -512,7 +521,7 @@
                                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 
-                               reg_3p0: regulator-3p0@120 {
+                               reg_3p0: regulator-3p0 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2625000>;
@@ -526,7 +535,7 @@
                                        anatop-enable-bit = <0>;
                                };
 
-                               reg_arm: regulator-vddcore@140 {
+                               reg_arm: regulator-vddcore {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "cpu";
                                        regulator-min-microvolt = <725000>;
@@ -543,7 +552,7 @@
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_soc: regulator-vddsoc@140 {
+                               reg_soc: regulator-vddsoc {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;
@@ -641,7 +650,8 @@
                        };
 
                        gpr: iomuxc-gpr@020e4000 {
-                               compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
+                               compatible = "fsl,imx6ul-iomuxc-gpr",
+                                            "fsl,imx6q-iomuxc-gpr", "syscon";
                                reg = <0x020e4000 0x4000>;
                        };