Merge tag 'ceph-for-4.9-rc1' of git://github.com/ceph/ceph-client

[cascardo/linux.git] / arch / arm / boot / dts / r7s72100.dtsi

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 89e46eb..fb9ef9c 100644 (file)
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -37,46 +37,41 @@
                #size-cells = <1>;
 
                /* External clocks */
-               extal_clk: extal_clk {
+               extal_clk: extal {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        /* If clk present, value must be set by board */
                        clock-frequency = <0>;
-                       clock-output-names = "extal";
                };
 
-               usb_x1_clk: usb_x1_clk {
+               usb_x1_clk: usb_x1 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        /* If clk present, value must be set by board */
                        clock-frequency = <0>;
-                       clock-output-names = "usb_x1";
                };
 
                /* Fixed factor clocks */
-               b_clk: b_clk {
+               b_clk: b {
                        #clock-cells = <0>;
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R7S72100_CLK_PLL>;
                        clock-mult = <1>;
                        clock-div = <3>;
-                       clock-output-names = "b";
                };
-               p1_clk: p1_clk {
+               p1_clk: p1 {
                        #clock-cells = <0>;
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R7S72100_CLK_PLL>;
                        clock-mult = <1>;
                        clock-div = <6>;
-                       clock-output-names = "p1";
                };
-               p0_clk: p0_clk {
+               p0_clk: p0 {
                        #clock-cells = <0>;
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R7S72100_CLK_PLL>;
                        clock-mult = <1>;
                        clock-div = <12>;
-                       clock-output-names = "p0";
                };
 
                /* Special CPG clocks */
@@ -113,6 +108,15 @@
                        clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
                };
 
+               mstp7_clks: mstp7_clks@fcfe0430 {
+                       #clock-cells = <1>;
+                       compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                       reg = <0xfcfe0430 4>;
+                       clocks = <&p0_clk>;
+                       clock-indices = <R7S72100_CLK_ETHER>;
+                       clock-output-names = "ether";
+               };
+
                mstp9_clks: mstp9_clks@fcfe0438 {
                        #clock-cells = <1>;
                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -424,4 +428,17 @@
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
+
+       ether: ethernet@e8203000 {
+               compatible = "renesas,ether-r7s72100";
+               reg = <0xe8203000 0x800>,
+                     <0xe8204800 0x200>;
+               interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
+               power-domains = <&cpg_clocks>;
+               phy-mode = "mii";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
 };