Merge branch 'work.splice_read' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / arm / boot / dts / r8a7792.dtsi

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 9763289..713141d 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -25,6 +25,7 @@
                i2c3 = &i2c3;
                i2c4 = &i2c4;
                i2c5 = &i2c5;
+               spi0 = &qspi;
                vin0 = &vin0;
                vin1 = &vin1;
                vin2 = &vin2;
@@ -556,6 +557,21 @@
                        status = "disabled";
                };
 
+               qspi: spi@e6b10000 {
+                       compatible = "renesas,qspi-r8a7792", "renesas,qspi";
+                       reg = <0 0xe6b10000 0 0x2c>;
+                       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
+                       dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                              <&dmac1 0x17>, <&dmac1 0x18>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                du: display@feb00000 {
                        compatible = "renesas,du-r8a7792";
                        reg = <0 0xfeb00000 0 0x40000>;
@@ -668,6 +684,30 @@
                        status = "disabled";
                };
 
+               vsp1@fe928000 {
+                       compatible = "renesas,vsp1";
+                       reg = <0 0xfe928000 0 0x8000>;
+                       interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+               };
+
+               vsp1@fe930000 {
+                       compatible = "renesas,vsp1";
+                       reg = <0 0xfe930000 0 0x8000>;
+                       interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+               };
+
+               vsp1@fe938000 {
+                       compatible = "renesas,vsp1";
+                       reg = <0 0xfe938000 0 0x8000>;
+                       interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+               };
+
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@e6150000 {
                        compatible = "renesas,r8a7792-cpg-clocks",
@@ -757,10 +797,15 @@
                        compatible = "renesas,r8a7792-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                       clocks = <&m2_clk>;
+                       clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
-                       clock-indices = <R8A7792_CLK_JPU>;
-                       clock-output-names = "jpu";
+                       clock-indices = <
+                               R8A7792_CLK_JPU
+                               R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
+                               R8A7792_CLK_VSP1_SY
+                       >;
+                       clock-output-names = "jpu", "vsp1du1", "vsp1du0",
+                                            "vsp1-sy";
                };
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7792-mstp-clocks",
@@ -831,6 +876,7 @@
                        clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
                                 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
                                 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
+                                <&cpg_clocks R8A7792_CLK_QSPI>,
                                 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
                                 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
@@ -841,6 +887,7 @@
                                R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
                                R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
                                R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
+                               R8A7792_CLK_QSPI_MOD
                                R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
                                R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
                                R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
@@ -850,8 +897,9 @@
                                "gpio7", "gpio6", "gpio5", "gpio4",
                                "gpio3", "gpio2", "gpio1", "gpio0",
                                "gpio11", "gpio10", "can1", "can0",
-                               "gpio9", "gpio8", "i2c5", "i2c4",
-                               "i2c3", "i2c2", "i2c1", "i2c0";
+                               "qspi_mod", "gpio9", "gpio8",
+                               "i2c5", "i2c4", "i2c3", "i2c2",
+                               "i2c1", "i2c0";
                };
        };