Merge tag 'iwlwifi-next-for-kalle-2014-12-30' of https://git.kernel.org/pub/scm/linux...

[cascardo/linux.git] / arch / arm / boot / dts / rk3288.dtsi

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ebcd2d2..910dcad 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "skeleton.dtsi"
 
 / {
@@ -46,6 +47,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "rockchip,rk3066-smp";
                rockchip,pmu = <&pmu>;
 
                cpu0: cpu@500 {
@@ -68,6 +70,7 @@
                                 216000  900000
                                 126000  900000
                        >;
+                       #cooling-cells = <2>; /* min followed by max */
                        clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
                };
@@ -138,6 +141,7 @@
 
        timer {
                compatible = "arm,armv7-timer";
+               arm,cpu-registers-not-fw-configured;
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -357,6 +361,41 @@
                status = "disabled";
        };
 
+       thermal-zones {
+               #include "rk3288-thermal.dtsi"
+       };
+
+       tsadc: tsadc@ff280000 {
+               compatible = "rockchip,rk3288-tsadc";
+               reg = <0xff280000 0x100>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+               clock-names = "tsadc", "apb_pclk";
+               resets = <&cru SRST_TSADC>;
+               reset-names = "tsadc-apb";
+               pinctrl-names = "default";
+               pinctrl-0 = <&otp_out>;
+               #thermal-sensor-cells = <1>;
+               rockchip,hw-tshut-temp = <95000>;
+               status = "disabled";
+       };
+
+       gmac: ethernet@ff290000 {
+               compatible = "rockchip,rk3288-gmac";
+               reg = <0xff290000 0x10000>;
+               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "macirq";
+               rockchip,grf = <&grf>;
+               clocks = <&cru SCLK_MAC>,
+                       <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+                       <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
+                       <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+               clock-names = "stmmaceth",
+                       "mac_clk_rx", "mac_clk_tx",
+                       "clk_mac_ref", "clk_mac_refout",
+                       "aclk_mac", "pclk_mac";
+       };
+
        usb_host0_ehci: usb@ff500000 {
                compatible = "generic-ehci";
                reg = <0xff500000 0x100>;
@@ -702,6 +741,11 @@
                        bias-disable;
                };
 
+               pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+                       bias-disable;
+                       drive-strength = <12>;
+               };
+
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
                                rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
@@ -1016,6 +1060,12 @@
                        };
                };
 
+               tsadc {
+                       otp_out: otp-out {
+                               rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
                pwm0 {
                        pwm0_pin: pwm0-pin {
                                rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
@@ -1039,5 +1089,38 @@
                                rockchip,pins = <7 23 3 &pcfg_pull_none>;
                        };
                };
+
+               gmac {
+                       rgmii_pins: rgmii-pins {
+                               rockchip,pins = <3 30 3 &pcfg_pull_none>,
+                                               <3 31 3 &pcfg_pull_none>,
+                                               <3 26 3 &pcfg_pull_none>,
+                                               <3 27 3 &pcfg_pull_none>,
+                                               <3 28 3 &pcfg_pull_none_12ma>,
+                                               <3 29 3 &pcfg_pull_none_12ma>,
+                                               <3 24 3 &pcfg_pull_none_12ma>,
+                                               <3 25 3 &pcfg_pull_none_12ma>,
+                                               <4 0 3 &pcfg_pull_none>,
+                                               <4 5 3 &pcfg_pull_none>,
+                                               <4 6 3 &pcfg_pull_none>,
+                                               <4 9 3 &pcfg_pull_none_12ma>,
+                                               <4 4 3 &pcfg_pull_none_12ma>,
+                                               <4 1 3 &pcfg_pull_none>,
+                                               <4 3 3 &pcfg_pull_none>;
+                       };
+
+                       rmii_pins: rmii-pins {
+                               rockchip,pins = <3 30 3 &pcfg_pull_none>,
+                                               <3 31 3 &pcfg_pull_none>,
+                                               <3 28 3 &pcfg_pull_none>,
+                                               <3 29 3 &pcfg_pull_none>,
+                                               <4 0 3 &pcfg_pull_none>,
+                                               <4 5 3 &pcfg_pull_none>,
+                                               <4 4 3 &pcfg_pull_none>,
+                                               <4 1 3 &pcfg_pull_none>,
+                                               <4 2 3 &pcfg_pull_none>,
+                                               <4 3 3 &pcfg_pull_none>;
+                       };
+               };
        };
 };