Merge tag 'ceph-for-4.9-rc1' of git://github.com/ceph/ceph-client

[cascardo/linux.git] / arch / arm / boot / dts / sun8i-h3.dtsi

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 2c958c4..75a8654 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -150,7 +150,7 @@
                };
 
                mmc0: mmc@01c0f000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c0f000 0x1000>;
                        clocks = <&ccu CLK_BUS_MMC0>,
                                 <&ccu CLK_MMC0>,
@@ -169,7 +169,7 @@
                };
 
                mmc1: mmc@01c10000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c10000 0x1000>;
                        clocks = <&ccu CLK_BUS_MMC1>,
                                 <&ccu CLK_MMC1>,
@@ -188,7 +188,7 @@
                };
 
                mmc2: mmc@01c11000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c11000 0x1000>;
                        clocks = <&ccu CLK_BUS_MMC2>,
                                 <&ccu CLK_MMC2>,
@@ -491,6 +491,45 @@
                        status = "disabled";
                };
 
+               i2c0: i2c@01c2ac00 {
+                       compatible = "allwinner,sun6i-a31-i2c";
+                       reg = <0x01c2ac00 0x400>;
+                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2C0>;
+                       resets = <&ccu RST_BUS_I2C0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c1: i2c@01c2b000 {
+                       compatible = "allwinner,sun6i-a31-i2c";
+                       reg = <0x01c2b000 0x400>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2C1>;
+                       resets = <&ccu RST_BUS_I2C1>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c1_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c2: i2c@01c2b400 {
+                       compatible = "allwinner,sun6i-a31-i2c";
+                       reg = <0x01c2b000 0x400>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2C2>;
+                       resets = <&ccu RST_BUS_I2C2>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c2_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                gic: interrupt-controller@01c81000 {
                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
                        reg = <0x01c81000 0x1000>,