Merge branch 'work.splice_read' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / arm / include / asm / cputype.h

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index e2d94c1..522b5fe 100644 (file)
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -61,6 +61,7 @@
        ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
 
 #define ARM_CPU_IMP_ARM                        0x41
+#define ARM_CPU_IMP_DEC                        0x44
 #define ARM_CPU_IMP_INTEL              0x69
 
 /* ARM implemented processors */
@@ -77,6 +78,17 @@
 #define ARM_CPU_PART_CORTEX_A15                0x4100c0f0
 #define ARM_CPU_PART_MASK              0xff00fff0
 
+/* DEC implemented cores */
+#define ARM_CPU_PART_SA1100            0x4400a110
+
+/* Intel implemented cores */
+#define ARM_CPU_PART_SA1110            0x6900b110
+#define ARM_CPU_REV_SA1110_A0          0
+#define ARM_CPU_REV_SA1110_B0          4
+#define ARM_CPU_REV_SA1110_B1          5
+#define ARM_CPU_REV_SA1110_B2          6
+#define ARM_CPU_REV_SA1110_B4          8
+
 #define ARM_CPU_XSCALE_ARCH_MASK       0xe000
 #define ARM_CPU_XSCALE_ARCH_V1         0x2000
 #define ARM_CPU_XSCALE_ARCH_V2         0x4000
@@ -153,6 +165,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
        return read_cpuid(CPUID_ID);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+       return read_cpuid(CPUID_CACHETYPE);
+}
+
 #elif defined(CONFIG_CPU_V7M)
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
@@ -160,6 +177,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
        return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+       return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
+}
+
 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
@@ -174,6 +196,11 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
        return (read_cpuid_id() & 0xFF000000) >> 24;
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_revision(void)
+{
+       return read_cpuid_id() & 0x0000000f;
+}
+
 /*
  * The CPU part number is meaningless without referring to the CPU
  * implementer: implementers are free to define their own part numbers
@@ -194,11 +221,6 @@ static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
        return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 }
 
-static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
-{
-       return read_cpuid(CPUID_CACHETYPE);
-}
-
 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 {
        return read_cpuid(CPUID_TCM);
@@ -209,6 +231,10 @@ static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
        return read_cpuid(CPUID_MPIDR);
 }
 
+/* StrongARM-11x0 CPUs */
+#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
+#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
+
 /*
  * Intel's XScale3 core supports some v6 features (supersections, L2)
  * but advertises itself as v5 as it does not support the v6 ISA.  For